diff --git a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h index 4f62732c7d..9b8aead77b 100644 --- a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h @@ -120,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -139,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h index 6f6340f257..8c99c7dfb1 100644 --- a/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h +++ b/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_eco5_struct.h new file mode 100644 index 0000000000..1c4ade584f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_eco5_struct.h @@ -0,0 +1,1883 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of version register + * NA + */ +typedef union { + struct { + /** version : RO; bitpos: [31:0]; default: 825569322; + * NA + */ + uint32_t version:32; + }; + uint32_t val; +} csi_host_version_reg_t; + + +/** Group: Configuration Registers */ +/** Type of n_lanes register + * NA + */ +typedef union { + struct { + /** n_lanes : R/W; bitpos: [2:0]; default: 1; + * NA + */ + uint32_t n_lanes:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} csi_host_n_lanes_reg_t; + +/** Type of csi2_resetn register + * NA + */ +typedef union { + struct { + /** csi2_resetn : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t csi2_resetn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_csi2_resetn_reg_t; + +/** Type of phy_shutdownz register + * NA + */ +typedef union { + struct { + /** phy_shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_shutdownz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_phy_shutdownz_reg_t; + +/** Type of dphy_rstz register + * NA + */ +typedef union { + struct { + /** dphy_rstz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t dphy_rstz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_dphy_rstz_reg_t; + +/** Type of phy_rx register + * NA + */ +typedef union { + struct { + /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_rxulpsesc_0:1; + /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_rxulpsesc_1:1; + uint32_t reserved_2:14; + /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t phy_rxulpsclknot:1; + /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t phy_rxclkactivehs:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_phy_rx_reg_t; + +/** Type of phy_test_ctrl0 register + * NA + */ +typedef union { + struct { + /** phy_testclr : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t phy_testclr:1; + /** phy_testclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_testclk:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_phy_test_ctrl0_reg_t; + +/** Type of phy_test_ctrl1 register + * NA + */ +typedef union { + struct { + /** phy_testdin : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t phy_testdin:8; + /** phy_testdout : RO; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t phy_testdout:8; + /** phy_testen : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_testen:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_phy_test_ctrl1_reg_t; + +/** Type of vc_extension register + * NA + */ +typedef union { + struct { + /** vcx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t vcx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_vc_extension_reg_t; + +/** Type of phy_cal register + * NA + */ +typedef union { + struct { + /** rxskewcalhs : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t rxskewcalhs:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_phy_cal_reg_t; + +/** Type of scrambling register + * NA + */ +typedef union { + struct { + /** scramble_enable : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t scramble_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_scrambling_reg_t; + +/** Type of scrambling_seed1 register + * NA + */ +typedef union { + struct { + /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104; + * NA + */ + uint32_t scramble_seed_lane1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_scrambling_seed1_reg_t; + +/** Type of scrambling_seed2 register + * NA + */ +typedef union { + struct { + /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488; + * NA + */ + uint32_t scramble_seed_lane2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_scrambling_seed2_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_st_main register + * NA + */ +typedef union { + struct { + /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_status_int_phy_fatal:1; + /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_status_int_pkt_fatal:1; + /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_status_int_bndry_frame_fatal:1; + /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_status_int_seq_frame_fatal:1; + /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_status_int_crc_frame_fatal:1; + /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_status_int_pld_crc_fatal:1; + /** st_status_int_data_id : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_status_int_data_id:1; + /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_status_int_ecc_corrected:1; + uint32_t reserved_8:8; + /** st_status_int_phy : RC; bitpos: [16]; default: 0; + * NA + */ + uint32_t st_status_int_phy:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_int_st_main_reg_t; + +/** Type of int_st_phy_fatal register + * NA + */ +typedef union { + struct { + /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_phy_errsotsynchs_0:1; + /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_st_phy_fatal_reg_t; + +/** Type of int_msk_phy_fatal register + * NA + */ +typedef union { + struct { + /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_phy_errsotsynchs_0:1; + /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_msk_phy_fatal_reg_t; + +/** Type of int_force_phy_fatal register + * NA + */ +typedef union { + struct { + /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_phy_errsotsynchs_0:1; + /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_force_phy_fatal_reg_t; + +/** Type of int_st_pkt_fatal register + * NA + */ +typedef union { + struct { + /** st_err_ecc_double : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_ecc_double:1; + /** st_shorter_payload : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_st_pkt_fatal_reg_t; + +/** Type of int_msk_pkt_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_ecc_double:1; + /** mask_shorter_payload : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_msk_pkt_fatal_reg_t; + +/** Type of int_force_pkt_fatal register + * NA + */ +typedef union { + struct { + /** force_err_ecc_double : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_ecc_double:1; + /** force_shorter_payload : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_force_pkt_fatal_reg_t; + +/** Type of int_st_phy register + * NA + */ +typedef union { + struct { + /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_phy_errsoths_0:1; + /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0; + * NA + */ + uint32_t st_phy_erresc_0:1; + /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0; + * NA + */ + uint32_t st_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_st_phy_reg_t; + +/** Type of int_msk_phy register + * NA + */ +typedef union { + struct { + /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_phy_errsoths_0:1; + /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t mask_phy_erresc_0:1; + /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t mask_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_msk_phy_reg_t; + +/** Type of int_force_phy register + * NA + */ +typedef union { + struct { + /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_phy_errsoths_0:1; + /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t force_phy_erresc_0:1; + /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t force_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_force_phy_reg_t; + +/** Type of int_st_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc0:1; + /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc1:1; + /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc2:1; + /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc3:1; + /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc4:1; + /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc5:1; + /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc6:1; + /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc7:1; + /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc8:1; + /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc9:1; + /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc10:1; + /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc11:1; + /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc12:1; + /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc13:1; + /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc14:1; + /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_bndry_frame_fatal_reg_t; + +/** Type of int_msk_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc0:1; + /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc1:1; + /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc2:1; + /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc3:1; + /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc4:1; + /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc5:1; + /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc6:1; + /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc7:1; + /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc8:1; + /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc9:1; + /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc10:1; + /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc11:1; + /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc12:1; + /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc13:1; + /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc14:1; + /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_bndry_frame_fatal_reg_t; + +/** Type of int_force_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc0:1; + /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc1:1; + /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc2:1; + /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc3:1; + /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc4:1; + /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc5:1; + /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc6:1; + /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc7:1; + /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc8:1; + /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc9:1; + /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc10:1; + /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc11:1; + /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc12:1; + /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc13:1; + /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc14:1; + /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_bndry_frame_fatal_reg_t; + +/** Type of int_st_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc0:1; + /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc1:1; + /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc2:1; + /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc3:1; + /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc4:1; + /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc5:1; + /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc6:1; + /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc7:1; + /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc8:1; + /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc9:1; + /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc10:1; + /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc11:1; + /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc12:1; + /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc13:1; + /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc14:1; + /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_seq_frame_fatal_reg_t; + +/** Type of int_msk_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc0:1; + /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc1:1; + /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc2:1; + /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc3:1; + /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc4:1; + /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc5:1; + /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc6:1; + /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc7:1; + /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc8:1; + /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc9:1; + /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc10:1; + /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc11:1; + /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc12:1; + /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc13:1; + /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc14:1; + /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_seq_frame_fatal_reg_t; + +/** Type of int_force_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc0:1; + /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc1:1; + /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc2:1; + /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc3:1; + /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc4:1; + /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc5:1; + /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc6:1; + /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc7:1; + /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc8:1; + /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc9:1; + /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc10:1; + /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc11:1; + /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc12:1; + /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc13:1; + /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc14:1; + /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_seq_frame_fatal_reg_t; + +/** Type of int_st_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc0:1; + /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc1:1; + /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc2:1; + /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc3:1; + /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc4:1; + /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc5:1; + /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc6:1; + /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc7:1; + /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc8:1; + /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc9:1; + /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc10:1; + /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc11:1; + /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc12:1; + /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc13:1; + /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc14:1; + /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_crc_frame_fatal_reg_t; + +/** Type of int_msk_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc0:1; + /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc1:1; + /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc2:1; + /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc3:1; + /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc4:1; + /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc5:1; + /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc6:1; + /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc7:1; + /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc8:1; + /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc9:1; + /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc10:1; + /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc11:1; + /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc12:1; + /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc13:1; + /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc14:1; + /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_crc_frame_fatal_reg_t; + +/** Type of int_force_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc0:1; + /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc1:1; + /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc2:1; + /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc3:1; + /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc4:1; + /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc5:1; + /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc6:1; + /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc7:1; + /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc8:1; + /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc9:1; + /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc10:1; + /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc11:1; + /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc12:1; + /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc13:1; + /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc14:1; + /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_crc_frame_fatal_reg_t; + +/** Type of int_st_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_crc_vc0:1; + /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_crc_vc1:1; + /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_crc_vc2:1; + /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_crc_vc3:1; + /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_crc_vc4:1; + /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_crc_vc5:1; + /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_crc_vc6:1; + /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_crc_vc7:1; + /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_crc_vc8:1; + /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_crc_vc9:1; + /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_crc_vc10:1; + /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_crc_vc11:1; + /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_crc_vc12:1; + /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_crc_vc13:1; + /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_crc_vc14:1; + /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_pld_crc_fatal_reg_t; + +/** Type of int_msk_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc0:1; + /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc1:1; + /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc2:1; + /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc3:1; + /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc4:1; + /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc5:1; + /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc6:1; + /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc7:1; + /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc8:1; + /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc9:1; + /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc10:1; + /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc11:1; + /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc12:1; + /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc13:1; + /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc14:1; + /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_pld_crc_fatal_reg_t; + +/** Type of int_force_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_crc_vc0:1; + /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_crc_vc1:1; + /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_crc_vc2:1; + /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_crc_vc3:1; + /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_crc_vc4:1; + /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_crc_vc5:1; + /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_crc_vc6:1; + /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_crc_vc7:1; + /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_crc_vc8:1; + /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_crc_vc9:1; + /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_crc_vc10:1; + /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_crc_vc11:1; + /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_crc_vc12:1; + /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_crc_vc13:1; + /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_crc_vc14:1; + /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_pld_crc_fatal_reg_t; + +/** Type of int_st_data_id register + * NA + */ +typedef union { + struct { + /** st_err_id_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_id_vc0:1; + /** st_err_id_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_id_vc1:1; + /** st_err_id_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_id_vc2:1; + /** st_err_id_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_id_vc3:1; + /** st_err_id_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_id_vc4:1; + /** st_err_id_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_id_vc5:1; + /** st_err_id_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_id_vc6:1; + /** st_err_id_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_id_vc7:1; + /** st_err_id_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_id_vc8:1; + /** st_err_id_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_id_vc9:1; + /** st_err_id_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_id_vc10:1; + /** st_err_id_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_id_vc11:1; + /** st_err_id_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_id_vc12:1; + /** st_err_id_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_id_vc13:1; + /** st_err_id_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_id_vc14:1; + /** st_err_id_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_data_id_reg_t; + +/** Type of int_msk_data_id register + * NA + */ +typedef union { + struct { + /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_id_vc0:1; + /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_id_vc1:1; + /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_id_vc2:1; + /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_id_vc3:1; + /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_id_vc4:1; + /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_id_vc5:1; + /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_id_vc6:1; + /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_id_vc7:1; + /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_id_vc8:1; + /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_id_vc9:1; + /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_id_vc10:1; + /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_id_vc11:1; + /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_id_vc12:1; + /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_id_vc13:1; + /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_id_vc14:1; + /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_data_id_reg_t; + +/** Type of int_force_data_id register + * NA + */ +typedef union { + struct { + /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_id_vc0:1; + /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_id_vc1:1; + /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_id_vc2:1; + /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_id_vc3:1; + /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_id_vc4:1; + /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_id_vc5:1; + /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_id_vc6:1; + /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_id_vc7:1; + /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_id_vc8:1; + /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_id_vc9:1; + /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_id_vc10:1; + /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_id_vc11:1; + /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_id_vc12:1; + /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_id_vc13:1; + /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_id_vc14:1; + /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_data_id_reg_t; + +/** Type of int_st_ecc_corrected register + * NA + */ +typedef union { + struct { + /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc0:1; + /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc1:1; + /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc2:1; + /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc3:1; + /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc4:1; + /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc5:1; + /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc6:1; + /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc7:1; + /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc8:1; + /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc9:1; + /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc10:1; + /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc11:1; + /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc12:1; + /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc13:1; + /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc14:1; + /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_ecc_corrected_reg_t; + +/** Type of int_msk_ecc_corrected register + * NA + */ +typedef union { + struct { + /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc0:1; + /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc1:1; + /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc2:1; + /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc3:1; + /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc4:1; + /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc5:1; + /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc6:1; + /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc7:1; + /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc8:1; + /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc9:1; + /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc10:1; + /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc11:1; + /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc12:1; + /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc13:1; + /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc14:1; + /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_ecc_corrected_reg_t; + +/** Type of int_force_ecc_corrected register + * NA + */ +typedef union { + struct { + /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc0:1; + /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc1:1; + /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc2:1; + /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc3:1; + /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc4:1; + /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc5:1; + /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc6:1; + /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc7:1; + /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc8:1; + /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc9:1; + /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc10:1; + /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc11:1; + /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc12:1; + /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc13:1; + /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc14:1; + /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_ecc_corrected_reg_t; + + +/** Group: Status Registers */ +/** Type of phy_stopstate register + * NA + */ +typedef union { + struct { + /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_stopstatedata_0:1; + /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_stopstatedata_1:1; + uint32_t reserved_2:14; + /** phy_stopstateclk : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_stopstateclk:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_phy_stopstate_reg_t; + + +typedef struct { + volatile csi_host_version_reg_t version; + volatile csi_host_n_lanes_reg_t n_lanes; + volatile csi_host_csi2_resetn_reg_t csi2_resetn; + volatile csi_host_int_st_main_reg_t int_st_main; + uint32_t reserved_010[12]; + volatile csi_host_phy_shutdownz_reg_t phy_shutdownz; + volatile csi_host_dphy_rstz_reg_t dphy_rstz; + volatile csi_host_phy_rx_reg_t phy_rx; + volatile csi_host_phy_stopstate_reg_t phy_stopstate; + volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0; + volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1; + uint32_t reserved_058[28]; + volatile csi_host_vc_extension_reg_t vc_extension; + volatile csi_host_phy_cal_reg_t phy_cal; + uint32_t reserved_0d0[4]; + volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal; + volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal; + volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal; + uint32_t reserved_0ec; + volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal; + volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal; + volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal; + uint32_t reserved_0fc[5]; + volatile csi_host_int_st_phy_reg_t int_st_phy; + volatile csi_host_int_msk_phy_reg_t int_msk_phy; + volatile csi_host_int_force_phy_reg_t int_force_phy; + uint32_t reserved_11c[89]; + volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal; + volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal; + volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal; + uint32_t reserved_28c; + volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal; + volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal; + volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal; + uint32_t reserved_29c; + volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal; + volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal; + volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal; + uint32_t reserved_2ac; + volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal; + volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal; + volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal; + uint32_t reserved_2bc; + volatile csi_host_int_st_data_id_reg_t int_st_data_id; + volatile csi_host_int_msk_data_id_reg_t int_msk_data_id; + volatile csi_host_int_force_data_id_reg_t int_force_data_id; + uint32_t reserved_2cc; + volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected; + volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected; + volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected; + uint32_t reserved_2dc[9]; + volatile csi_host_scrambling_reg_t scrambling; + volatile csi_host_scrambling_seed1_reg_t scrambling_seed1; + volatile csi_host_scrambling_seed2_reg_t scrambling_seed2; +} csi_host_dev_t; + +extern csi_host_dev_t MIPI_CSI_HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_reg.h new file mode 100644 index 0000000000..2527e2c67e --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_reg.h @@ -0,0 +1,2627 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CSI_HOST_VERSION_REG register + * NA + */ +#define CSI_HOST_VERSION_REG (DR_REG_CSI_HOST_BASE + 0x0) +/** CSI_HOST_VERSION : RO; bitpos: [31:0]; default: 825569322; + * NA + */ +#define CSI_HOST_VERSION 0xFFFFFFFFU +#define CSI_HOST_VERSION_M (CSI_HOST_VERSION_V << CSI_HOST_VERSION_S) +#define CSI_HOST_VERSION_V 0xFFFFFFFFU +#define CSI_HOST_VERSION_S 0 + +/** CSI_HOST_N_LANES_REG register + * NA + */ +#define CSI_HOST_N_LANES_REG (DR_REG_CSI_HOST_BASE + 0x4) +/** CSI_HOST_N_LANES : R/W; bitpos: [2:0]; default: 1; + * NA + */ +#define CSI_HOST_N_LANES 0x00000007U +#define CSI_HOST_N_LANES_M (CSI_HOST_N_LANES_V << CSI_HOST_N_LANES_S) +#define CSI_HOST_N_LANES_V 0x00000007U +#define CSI_HOST_N_LANES_S 0 + +/** CSI_HOST_CSI2_RESETN_REG register + * NA + */ +#define CSI_HOST_CSI2_RESETN_REG (DR_REG_CSI_HOST_BASE + 0x8) +/** CSI_HOST_CSI2_RESETN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_CSI2_RESETN (BIT(0)) +#define CSI_HOST_CSI2_RESETN_M (CSI_HOST_CSI2_RESETN_V << CSI_HOST_CSI2_RESETN_S) +#define CSI_HOST_CSI2_RESETN_V 0x00000001U +#define CSI_HOST_CSI2_RESETN_S 0 + +/** CSI_HOST_INT_ST_MAIN_REG register + * NA + */ +#define CSI_HOST_INT_ST_MAIN_REG (DR_REG_CSI_HOST_BASE + 0xc) +/** CSI_HOST_ST_STATUS_INT_PHY_FATAL : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_PHY_FATAL (BIT(0)) +#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_M (CSI_HOST_ST_STATUS_INT_PHY_FATAL_V << CSI_HOST_ST_STATUS_INT_PHY_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_PHY_FATAL_S 0 +/** CSI_HOST_ST_STATUS_INT_PKT_FATAL : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_PKT_FATAL (BIT(1)) +#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_M (CSI_HOST_ST_STATUS_INT_PKT_FATAL_V << CSI_HOST_ST_STATUS_INT_PKT_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_PKT_FATAL_S 1 +/** CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL (BIT(2)) +#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_M (CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_BNDRY_FRAME_FATAL_S 2 +/** CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL (BIT(3)) +#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_M (CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_SEQ_FRAME_FATAL_S 3 +/** CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL (BIT(4)) +#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_M (CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_V << CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_CRC_FRAME_FATAL_S 4 +/** CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL (BIT(5)) +#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_M (CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_V << CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_S) +#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_PLD_CRC_FATAL_S 5 +/** CSI_HOST_ST_STATUS_INT_DATA_ID : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_DATA_ID (BIT(6)) +#define CSI_HOST_ST_STATUS_INT_DATA_ID_M (CSI_HOST_ST_STATUS_INT_DATA_ID_V << CSI_HOST_ST_STATUS_INT_DATA_ID_S) +#define CSI_HOST_ST_STATUS_INT_DATA_ID_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_DATA_ID_S 6 +/** CSI_HOST_ST_STATUS_INT_ECC_CORRECTED : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED (BIT(7)) +#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_M (CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_V << CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_S) +#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_ECC_CORRECTED_S 7 +/** CSI_HOST_ST_STATUS_INT_PHY : RC; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_ST_STATUS_INT_PHY (BIT(16)) +#define CSI_HOST_ST_STATUS_INT_PHY_M (CSI_HOST_ST_STATUS_INT_PHY_V << CSI_HOST_ST_STATUS_INT_PHY_S) +#define CSI_HOST_ST_STATUS_INT_PHY_V 0x00000001U +#define CSI_HOST_ST_STATUS_INT_PHY_S 16 + +/** CSI_HOST_PHY_SHUTDOWNZ_REG register + * NA + */ +#define CSI_HOST_PHY_SHUTDOWNZ_REG (DR_REG_CSI_HOST_BASE + 0x40) +/** CSI_HOST_PHY_SHUTDOWNZ : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_PHY_SHUTDOWNZ (BIT(0)) +#define CSI_HOST_PHY_SHUTDOWNZ_M (CSI_HOST_PHY_SHUTDOWNZ_V << CSI_HOST_PHY_SHUTDOWNZ_S) +#define CSI_HOST_PHY_SHUTDOWNZ_V 0x00000001U +#define CSI_HOST_PHY_SHUTDOWNZ_S 0 + +/** CSI_HOST_DPHY_RSTZ_REG register + * NA + */ +#define CSI_HOST_DPHY_RSTZ_REG (DR_REG_CSI_HOST_BASE + 0x44) +/** CSI_HOST_DPHY_RSTZ : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_DPHY_RSTZ (BIT(0)) +#define CSI_HOST_DPHY_RSTZ_M (CSI_HOST_DPHY_RSTZ_V << CSI_HOST_DPHY_RSTZ_S) +#define CSI_HOST_DPHY_RSTZ_V 0x00000001U +#define CSI_HOST_DPHY_RSTZ_S 0 + +/** CSI_HOST_PHY_RX_REG register + * NA + */ +#define CSI_HOST_PHY_RX_REG (DR_REG_CSI_HOST_BASE + 0x48) +/** CSI_HOST_PHY_RXULPSESC_0 : RO; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_PHY_RXULPSESC_0 (BIT(0)) +#define CSI_HOST_PHY_RXULPSESC_0_M (CSI_HOST_PHY_RXULPSESC_0_V << CSI_HOST_PHY_RXULPSESC_0_S) +#define CSI_HOST_PHY_RXULPSESC_0_V 0x00000001U +#define CSI_HOST_PHY_RXULPSESC_0_S 0 +/** CSI_HOST_PHY_RXULPSESC_1 : RO; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_PHY_RXULPSESC_1 (BIT(1)) +#define CSI_HOST_PHY_RXULPSESC_1_M (CSI_HOST_PHY_RXULPSESC_1_V << CSI_HOST_PHY_RXULPSESC_1_S) +#define CSI_HOST_PHY_RXULPSESC_1_V 0x00000001U +#define CSI_HOST_PHY_RXULPSESC_1_S 1 +/** CSI_HOST_PHY_RXULPSCLKNOT : RO; bitpos: [16]; default: 1; + * NA + */ +#define CSI_HOST_PHY_RXULPSCLKNOT (BIT(16)) +#define CSI_HOST_PHY_RXULPSCLKNOT_M (CSI_HOST_PHY_RXULPSCLKNOT_V << CSI_HOST_PHY_RXULPSCLKNOT_S) +#define CSI_HOST_PHY_RXULPSCLKNOT_V 0x00000001U +#define CSI_HOST_PHY_RXULPSCLKNOT_S 16 +/** CSI_HOST_PHY_RXCLKACTIVEHS : RO; bitpos: [17]; default: 0; + * NA + */ +#define CSI_HOST_PHY_RXCLKACTIVEHS (BIT(17)) +#define CSI_HOST_PHY_RXCLKACTIVEHS_M (CSI_HOST_PHY_RXCLKACTIVEHS_V << CSI_HOST_PHY_RXCLKACTIVEHS_S) +#define CSI_HOST_PHY_RXCLKACTIVEHS_V 0x00000001U +#define CSI_HOST_PHY_RXCLKACTIVEHS_S 17 + +/** CSI_HOST_PHY_STOPSTATE_REG register + * NA + */ +#define CSI_HOST_PHY_STOPSTATE_REG (DR_REG_CSI_HOST_BASE + 0x4c) +/** CSI_HOST_PHY_STOPSTATEDATA_0 : RO; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_PHY_STOPSTATEDATA_0 (BIT(0)) +#define CSI_HOST_PHY_STOPSTATEDATA_0_M (CSI_HOST_PHY_STOPSTATEDATA_0_V << CSI_HOST_PHY_STOPSTATEDATA_0_S) +#define CSI_HOST_PHY_STOPSTATEDATA_0_V 0x00000001U +#define CSI_HOST_PHY_STOPSTATEDATA_0_S 0 +/** CSI_HOST_PHY_STOPSTATEDATA_1 : RO; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_PHY_STOPSTATEDATA_1 (BIT(1)) +#define CSI_HOST_PHY_STOPSTATEDATA_1_M (CSI_HOST_PHY_STOPSTATEDATA_1_V << CSI_HOST_PHY_STOPSTATEDATA_1_S) +#define CSI_HOST_PHY_STOPSTATEDATA_1_V 0x00000001U +#define CSI_HOST_PHY_STOPSTATEDATA_1_S 1 +/** CSI_HOST_PHY_STOPSTATECLK : RO; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_PHY_STOPSTATECLK (BIT(16)) +#define CSI_HOST_PHY_STOPSTATECLK_M (CSI_HOST_PHY_STOPSTATECLK_V << CSI_HOST_PHY_STOPSTATECLK_S) +#define CSI_HOST_PHY_STOPSTATECLK_V 0x00000001U +#define CSI_HOST_PHY_STOPSTATECLK_S 16 + +/** CSI_HOST_PHY_TEST_CTRL0_REG register + * NA + */ +#define CSI_HOST_PHY_TEST_CTRL0_REG (DR_REG_CSI_HOST_BASE + 0x50) +/** CSI_HOST_PHY_TESTCLR : R/W; bitpos: [0]; default: 1; + * NA + */ +#define CSI_HOST_PHY_TESTCLR (BIT(0)) +#define CSI_HOST_PHY_TESTCLR_M (CSI_HOST_PHY_TESTCLR_V << CSI_HOST_PHY_TESTCLR_S) +#define CSI_HOST_PHY_TESTCLR_V 0x00000001U +#define CSI_HOST_PHY_TESTCLR_S 0 +/** CSI_HOST_PHY_TESTCLK : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_PHY_TESTCLK (BIT(1)) +#define CSI_HOST_PHY_TESTCLK_M (CSI_HOST_PHY_TESTCLK_V << CSI_HOST_PHY_TESTCLK_S) +#define CSI_HOST_PHY_TESTCLK_V 0x00000001U +#define CSI_HOST_PHY_TESTCLK_S 1 + +/** CSI_HOST_PHY_TEST_CTRL1_REG register + * NA + */ +#define CSI_HOST_PHY_TEST_CTRL1_REG (DR_REG_CSI_HOST_BASE + 0x54) +/** CSI_HOST_PHY_TESTDIN : R/W; bitpos: [7:0]; default: 0; + * NA + */ +#define CSI_HOST_PHY_TESTDIN 0x000000FFU +#define CSI_HOST_PHY_TESTDIN_M (CSI_HOST_PHY_TESTDIN_V << CSI_HOST_PHY_TESTDIN_S) +#define CSI_HOST_PHY_TESTDIN_V 0x000000FFU +#define CSI_HOST_PHY_TESTDIN_S 0 +/** CSI_HOST_PHY_TESTDOUT : RO; bitpos: [15:8]; default: 0; + * NA + */ +#define CSI_HOST_PHY_TESTDOUT 0x000000FFU +#define CSI_HOST_PHY_TESTDOUT_M (CSI_HOST_PHY_TESTDOUT_V << CSI_HOST_PHY_TESTDOUT_S) +#define CSI_HOST_PHY_TESTDOUT_V 0x000000FFU +#define CSI_HOST_PHY_TESTDOUT_S 8 +/** CSI_HOST_PHY_TESTEN : R/W; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_PHY_TESTEN (BIT(16)) +#define CSI_HOST_PHY_TESTEN_M (CSI_HOST_PHY_TESTEN_V << CSI_HOST_PHY_TESTEN_S) +#define CSI_HOST_PHY_TESTEN_V 0x00000001U +#define CSI_HOST_PHY_TESTEN_S 16 + +/** CSI_HOST_VC_EXTENSION_REG register + * NA + */ +#define CSI_HOST_VC_EXTENSION_REG (DR_REG_CSI_HOST_BASE + 0xc8) +/** CSI_HOST_VCX : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_VCX (BIT(0)) +#define CSI_HOST_VCX_M (CSI_HOST_VCX_V << CSI_HOST_VCX_S) +#define CSI_HOST_VCX_V 0x00000001U +#define CSI_HOST_VCX_S 0 + +/** CSI_HOST_PHY_CAL_REG register + * NA + */ +#define CSI_HOST_PHY_CAL_REG (DR_REG_CSI_HOST_BASE + 0xcc) +/** CSI_HOST_RXSKEWCALHS : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_RXSKEWCALHS (BIT(0)) +#define CSI_HOST_RXSKEWCALHS_M (CSI_HOST_RXSKEWCALHS_V << CSI_HOST_RXSKEWCALHS_S) +#define CSI_HOST_RXSKEWCALHS_V 0x00000001U +#define CSI_HOST_RXSKEWCALHS_S 0 + +/** CSI_HOST_INT_ST_PHY_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe0) +/** CSI_HOST_ST_PHY_ERRSOTSYNCHS_0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0 (BIT(0)) +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_M (CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_S) +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_0_S 0 +/** CSI_HOST_ST_PHY_ERRSOTSYNCHS_1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1 (BIT(1)) +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_M (CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_S) +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRSOTSYNCHS_1_S 1 + +/** CSI_HOST_INT_MSK_PHY_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe4) +/** CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0 (BIT(0)) +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_M (CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_S) +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_0_S 0 +/** CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1 (BIT(1)) +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_M (CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_S) +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRSOTSYNCHS_1_S 1 + +/** CSI_HOST_INT_FORCE_PHY_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_PHY_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xe8) +/** CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0 (BIT(0)) +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_M (CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_V << CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_S) +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_0_S 0 +/** CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1 (BIT(1)) +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_M (CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_V << CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_S) +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRSOTSYNCHS_1_S 1 + +/** CSI_HOST_INT_ST_PKT_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf0) +/** CSI_HOST_ST_ERR_ECC_DOUBLE : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_DOUBLE (BIT(0)) +#define CSI_HOST_ST_ERR_ECC_DOUBLE_M (CSI_HOST_ST_ERR_ECC_DOUBLE_V << CSI_HOST_ST_ERR_ECC_DOUBLE_S) +#define CSI_HOST_ST_ERR_ECC_DOUBLE_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_DOUBLE_S 0 +/** CSI_HOST_ST_SHORTER_PAYLOAD : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_SHORTER_PAYLOAD (BIT(1)) +#define CSI_HOST_ST_SHORTER_PAYLOAD_M (CSI_HOST_ST_SHORTER_PAYLOAD_V << CSI_HOST_ST_SHORTER_PAYLOAD_S) +#define CSI_HOST_ST_SHORTER_PAYLOAD_V 0x00000001U +#define CSI_HOST_ST_SHORTER_PAYLOAD_S 1 + +/** CSI_HOST_INT_MSK_PKT_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf4) +/** CSI_HOST_MASK_ERR_ECC_DOUBLE : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_DOUBLE (BIT(0)) +#define CSI_HOST_MASK_ERR_ECC_DOUBLE_M (CSI_HOST_MASK_ERR_ECC_DOUBLE_V << CSI_HOST_MASK_ERR_ECC_DOUBLE_S) +#define CSI_HOST_MASK_ERR_ECC_DOUBLE_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_DOUBLE_S 0 +/** CSI_HOST_MASK_SHORTER_PAYLOAD : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_SHORTER_PAYLOAD (BIT(1)) +#define CSI_HOST_MASK_SHORTER_PAYLOAD_M (CSI_HOST_MASK_SHORTER_PAYLOAD_V << CSI_HOST_MASK_SHORTER_PAYLOAD_S) +#define CSI_HOST_MASK_SHORTER_PAYLOAD_V 0x00000001U +#define CSI_HOST_MASK_SHORTER_PAYLOAD_S 1 + +/** CSI_HOST_INT_FORCE_PKT_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_PKT_FATAL_REG (DR_REG_CSI_HOST_BASE + 0xf8) +/** CSI_HOST_FORCE_ERR_ECC_DOUBLE : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_DOUBLE (BIT(0)) +#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_M (CSI_HOST_FORCE_ERR_ECC_DOUBLE_V << CSI_HOST_FORCE_ERR_ECC_DOUBLE_S) +#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_DOUBLE_S 0 +/** CSI_HOST_FORCE_SHORTER_PAYLOAD : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_SHORTER_PAYLOAD (BIT(1)) +#define CSI_HOST_FORCE_SHORTER_PAYLOAD_M (CSI_HOST_FORCE_SHORTER_PAYLOAD_V << CSI_HOST_FORCE_SHORTER_PAYLOAD_S) +#define CSI_HOST_FORCE_SHORTER_PAYLOAD_V 0x00000001U +#define CSI_HOST_FORCE_SHORTER_PAYLOAD_S 1 + +/** CSI_HOST_INT_ST_PHY_REG register + * NA + */ +#define CSI_HOST_INT_ST_PHY_REG (DR_REG_CSI_HOST_BASE + 0x110) +/** CSI_HOST_ST_PHY_ERRSOTHS_0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRSOTHS_0 (BIT(0)) +#define CSI_HOST_ST_PHY_ERRSOTHS_0_M (CSI_HOST_ST_PHY_ERRSOTHS_0_V << CSI_HOST_ST_PHY_ERRSOTHS_0_S) +#define CSI_HOST_ST_PHY_ERRSOTHS_0_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRSOTHS_0_S 0 +/** CSI_HOST_ST_PHY_ERRSOTHS_1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRSOTHS_1 (BIT(1)) +#define CSI_HOST_ST_PHY_ERRSOTHS_1_M (CSI_HOST_ST_PHY_ERRSOTHS_1_V << CSI_HOST_ST_PHY_ERRSOTHS_1_S) +#define CSI_HOST_ST_PHY_ERRSOTHS_1_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRSOTHS_1_S 1 +/** CSI_HOST_ST_PHY_ERRESC_0 : RC; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRESC_0 (BIT(16)) +#define CSI_HOST_ST_PHY_ERRESC_0_M (CSI_HOST_ST_PHY_ERRESC_0_V << CSI_HOST_ST_PHY_ERRESC_0_S) +#define CSI_HOST_ST_PHY_ERRESC_0_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRESC_0_S 16 +/** CSI_HOST_ST_PHY_ERRESC_1 : RC; bitpos: [17]; default: 0; + * NA + */ +#define CSI_HOST_ST_PHY_ERRESC_1 (BIT(17)) +#define CSI_HOST_ST_PHY_ERRESC_1_M (CSI_HOST_ST_PHY_ERRESC_1_V << CSI_HOST_ST_PHY_ERRESC_1_S) +#define CSI_HOST_ST_PHY_ERRESC_1_V 0x00000001U +#define CSI_HOST_ST_PHY_ERRESC_1_S 17 + +/** CSI_HOST_INT_MSK_PHY_REG register + * NA + */ +#define CSI_HOST_INT_MSK_PHY_REG (DR_REG_CSI_HOST_BASE + 0x114) +/** CSI_HOST_MASK_PHY_ERRSOTHS_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRSOTHS_0 (BIT(0)) +#define CSI_HOST_MASK_PHY_ERRSOTHS_0_M (CSI_HOST_MASK_PHY_ERRSOTHS_0_V << CSI_HOST_MASK_PHY_ERRSOTHS_0_S) +#define CSI_HOST_MASK_PHY_ERRSOTHS_0_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRSOTHS_0_S 0 +/** CSI_HOST_MASK_PHY_ERRSOTHS_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRSOTHS_1 (BIT(1)) +#define CSI_HOST_MASK_PHY_ERRSOTHS_1_M (CSI_HOST_MASK_PHY_ERRSOTHS_1_V << CSI_HOST_MASK_PHY_ERRSOTHS_1_S) +#define CSI_HOST_MASK_PHY_ERRSOTHS_1_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRSOTHS_1_S 1 +/** CSI_HOST_MASK_PHY_ERRESC_0 : R/W; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRESC_0 (BIT(16)) +#define CSI_HOST_MASK_PHY_ERRESC_0_M (CSI_HOST_MASK_PHY_ERRESC_0_V << CSI_HOST_MASK_PHY_ERRESC_0_S) +#define CSI_HOST_MASK_PHY_ERRESC_0_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRESC_0_S 16 +/** CSI_HOST_MASK_PHY_ERRESC_1 : R/W; bitpos: [17]; default: 0; + * NA + */ +#define CSI_HOST_MASK_PHY_ERRESC_1 (BIT(17)) +#define CSI_HOST_MASK_PHY_ERRESC_1_M (CSI_HOST_MASK_PHY_ERRESC_1_V << CSI_HOST_MASK_PHY_ERRESC_1_S) +#define CSI_HOST_MASK_PHY_ERRESC_1_V 0x00000001U +#define CSI_HOST_MASK_PHY_ERRESC_1_S 17 + +/** CSI_HOST_INT_FORCE_PHY_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_PHY_REG (DR_REG_CSI_HOST_BASE + 0x118) +/** CSI_HOST_FORCE_PHY_ERRSOTHS_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRSOTHS_0 (BIT(0)) +#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_M (CSI_HOST_FORCE_PHY_ERRSOTHS_0_V << CSI_HOST_FORCE_PHY_ERRSOTHS_0_S) +#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRSOTHS_0_S 0 +/** CSI_HOST_FORCE_PHY_ERRSOTHS_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRSOTHS_1 (BIT(1)) +#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_M (CSI_HOST_FORCE_PHY_ERRSOTHS_1_V << CSI_HOST_FORCE_PHY_ERRSOTHS_1_S) +#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRSOTHS_1_S 1 +/** CSI_HOST_FORCE_PHY_ERRESC_0 : R/W; bitpos: [16]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRESC_0 (BIT(16)) +#define CSI_HOST_FORCE_PHY_ERRESC_0_M (CSI_HOST_FORCE_PHY_ERRESC_0_V << CSI_HOST_FORCE_PHY_ERRESC_0_S) +#define CSI_HOST_FORCE_PHY_ERRESC_0_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRESC_0_S 16 +/** CSI_HOST_FORCE_PHY_ERRESC_1 : R/W; bitpos: [17]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_PHY_ERRESC_1 (BIT(17)) +#define CSI_HOST_FORCE_PHY_ERRESC_1_M (CSI_HOST_FORCE_PHY_ERRESC_1_V << CSI_HOST_FORCE_PHY_ERRESC_1_S) +#define CSI_HOST_FORCE_PHY_ERRESC_1_V 0x00000001U +#define CSI_HOST_FORCE_PHY_ERRESC_1_S 17 + +/** CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x280) +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC0_S 0 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC1_S 1 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC2_S 2 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC3_S 3 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC4_S 4 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC5_S 5 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC6_S 6 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC7_S 7 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC8_S 8 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC9_S 9 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC10_S 10 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC11_S 11 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC12_S 12 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC13_S 13 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC14_S 14 +/** CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_M (CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_S) +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_F_BNDRY_MATCH_VC15_S 15 + +/** CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x284) +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC0_S 0 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC1_S 1 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC2_S 2 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC3_S 3 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC4_S 4 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC5_S 5 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC6_S 6 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC7_S 7 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC8_S 8 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC9_S 9 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC10_S 10 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC11_S 11 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC12_S 12 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC13_S 13 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC14_S 14 +/** CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_M (CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_S) +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_BNDRY_MATCH_VC15_S 15 + +/** CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x288) +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC0_S 0 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC1_S 1 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC2_S 2 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC3_S 3 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC4_S 4 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC5_S 5 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC6_S 6 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC7_S 7 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC8_S 8 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC9_S 9 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC10_S 10 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC11_S 11 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC12_S 12 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC13_S 13 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC14_S 14 +/** CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_M (CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_V << CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_S) +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_BNDRY_MATCH_VC15_S 15 + +/** CSI_HOST_INT_ST_SEQ_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x290) +/** CSI_HOST_ST_ERR_F_SEQ_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_F_SEQ_VC0_M (CSI_HOST_ST_ERR_F_SEQ_VC0_V << CSI_HOST_ST_ERR_F_SEQ_VC0_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC0_S 0 +/** CSI_HOST_ST_ERR_F_SEQ_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_F_SEQ_VC1_M (CSI_HOST_ST_ERR_F_SEQ_VC1_V << CSI_HOST_ST_ERR_F_SEQ_VC1_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC1_S 1 +/** CSI_HOST_ST_ERR_F_SEQ_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_F_SEQ_VC2_M (CSI_HOST_ST_ERR_F_SEQ_VC2_V << CSI_HOST_ST_ERR_F_SEQ_VC2_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC2_S 2 +/** CSI_HOST_ST_ERR_F_SEQ_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_F_SEQ_VC3_M (CSI_HOST_ST_ERR_F_SEQ_VC3_V << CSI_HOST_ST_ERR_F_SEQ_VC3_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC3_S 3 +/** CSI_HOST_ST_ERR_F_SEQ_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_F_SEQ_VC4_M (CSI_HOST_ST_ERR_F_SEQ_VC4_V << CSI_HOST_ST_ERR_F_SEQ_VC4_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC4_S 4 +/** CSI_HOST_ST_ERR_F_SEQ_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_F_SEQ_VC5_M (CSI_HOST_ST_ERR_F_SEQ_VC5_V << CSI_HOST_ST_ERR_F_SEQ_VC5_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC5_S 5 +/** CSI_HOST_ST_ERR_F_SEQ_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_F_SEQ_VC6_M (CSI_HOST_ST_ERR_F_SEQ_VC6_V << CSI_HOST_ST_ERR_F_SEQ_VC6_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC6_S 6 +/** CSI_HOST_ST_ERR_F_SEQ_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_F_SEQ_VC7_M (CSI_HOST_ST_ERR_F_SEQ_VC7_V << CSI_HOST_ST_ERR_F_SEQ_VC7_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC7_S 7 +/** CSI_HOST_ST_ERR_F_SEQ_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_F_SEQ_VC8_M (CSI_HOST_ST_ERR_F_SEQ_VC8_V << CSI_HOST_ST_ERR_F_SEQ_VC8_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC8_S 8 +/** CSI_HOST_ST_ERR_F_SEQ_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_F_SEQ_VC9_M (CSI_HOST_ST_ERR_F_SEQ_VC9_V << CSI_HOST_ST_ERR_F_SEQ_VC9_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC9_S 9 +/** CSI_HOST_ST_ERR_F_SEQ_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_F_SEQ_VC10_M (CSI_HOST_ST_ERR_F_SEQ_VC10_V << CSI_HOST_ST_ERR_F_SEQ_VC10_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC10_S 10 +/** CSI_HOST_ST_ERR_F_SEQ_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_F_SEQ_VC11_M (CSI_HOST_ST_ERR_F_SEQ_VC11_V << CSI_HOST_ST_ERR_F_SEQ_VC11_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC11_S 11 +/** CSI_HOST_ST_ERR_F_SEQ_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_F_SEQ_VC12_M (CSI_HOST_ST_ERR_F_SEQ_VC12_V << CSI_HOST_ST_ERR_F_SEQ_VC12_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC12_S 12 +/** CSI_HOST_ST_ERR_F_SEQ_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_F_SEQ_VC13_M (CSI_HOST_ST_ERR_F_SEQ_VC13_V << CSI_HOST_ST_ERR_F_SEQ_VC13_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC13_S 13 +/** CSI_HOST_ST_ERR_F_SEQ_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_F_SEQ_VC14_M (CSI_HOST_ST_ERR_F_SEQ_VC14_V << CSI_HOST_ST_ERR_F_SEQ_VC14_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC14_S 14 +/** CSI_HOST_ST_ERR_F_SEQ_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_F_SEQ_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_F_SEQ_VC15_M (CSI_HOST_ST_ERR_F_SEQ_VC15_V << CSI_HOST_ST_ERR_F_SEQ_VC15_S) +#define CSI_HOST_ST_ERR_F_SEQ_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_F_SEQ_VC15_S 15 + +/** CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x294) +/** CSI_HOST_MASK_ERR_F_SEQ_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC0_M (CSI_HOST_MASK_ERR_F_SEQ_VC0_V << CSI_HOST_MASK_ERR_F_SEQ_VC0_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC0_S 0 +/** CSI_HOST_MASK_ERR_F_SEQ_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC1_M (CSI_HOST_MASK_ERR_F_SEQ_VC1_V << CSI_HOST_MASK_ERR_F_SEQ_VC1_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC1_S 1 +/** CSI_HOST_MASK_ERR_F_SEQ_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC2_M (CSI_HOST_MASK_ERR_F_SEQ_VC2_V << CSI_HOST_MASK_ERR_F_SEQ_VC2_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC2_S 2 +/** CSI_HOST_MASK_ERR_F_SEQ_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC3_M (CSI_HOST_MASK_ERR_F_SEQ_VC3_V << CSI_HOST_MASK_ERR_F_SEQ_VC3_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC3_S 3 +/** CSI_HOST_MASK_ERR_F_SEQ_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC4_M (CSI_HOST_MASK_ERR_F_SEQ_VC4_V << CSI_HOST_MASK_ERR_F_SEQ_VC4_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC4_S 4 +/** CSI_HOST_MASK_ERR_F_SEQ_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC5_M (CSI_HOST_MASK_ERR_F_SEQ_VC5_V << CSI_HOST_MASK_ERR_F_SEQ_VC5_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC5_S 5 +/** CSI_HOST_MASK_ERR_F_SEQ_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC6_M (CSI_HOST_MASK_ERR_F_SEQ_VC6_V << CSI_HOST_MASK_ERR_F_SEQ_VC6_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC6_S 6 +/** CSI_HOST_MASK_ERR_F_SEQ_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC7_M (CSI_HOST_MASK_ERR_F_SEQ_VC7_V << CSI_HOST_MASK_ERR_F_SEQ_VC7_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC7_S 7 +/** CSI_HOST_MASK_ERR_F_SEQ_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC8_M (CSI_HOST_MASK_ERR_F_SEQ_VC8_V << CSI_HOST_MASK_ERR_F_SEQ_VC8_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC8_S 8 +/** CSI_HOST_MASK_ERR_F_SEQ_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC9_M (CSI_HOST_MASK_ERR_F_SEQ_VC9_V << CSI_HOST_MASK_ERR_F_SEQ_VC9_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC9_S 9 +/** CSI_HOST_MASK_ERR_F_SEQ_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC10_M (CSI_HOST_MASK_ERR_F_SEQ_VC10_V << CSI_HOST_MASK_ERR_F_SEQ_VC10_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC10_S 10 +/** CSI_HOST_MASK_ERR_F_SEQ_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC11_M (CSI_HOST_MASK_ERR_F_SEQ_VC11_V << CSI_HOST_MASK_ERR_F_SEQ_VC11_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC11_S 11 +/** CSI_HOST_MASK_ERR_F_SEQ_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC12_M (CSI_HOST_MASK_ERR_F_SEQ_VC12_V << CSI_HOST_MASK_ERR_F_SEQ_VC12_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC12_S 12 +/** CSI_HOST_MASK_ERR_F_SEQ_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC13_M (CSI_HOST_MASK_ERR_F_SEQ_VC13_V << CSI_HOST_MASK_ERR_F_SEQ_VC13_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC13_S 13 +/** CSI_HOST_MASK_ERR_F_SEQ_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC14_M (CSI_HOST_MASK_ERR_F_SEQ_VC14_V << CSI_HOST_MASK_ERR_F_SEQ_VC14_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC14_S 14 +/** CSI_HOST_MASK_ERR_F_SEQ_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_F_SEQ_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_F_SEQ_VC15_M (CSI_HOST_MASK_ERR_F_SEQ_VC15_V << CSI_HOST_MASK_ERR_F_SEQ_VC15_S) +#define CSI_HOST_MASK_ERR_F_SEQ_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_F_SEQ_VC15_S 15 + +/** CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x298) +/** CSI_HOST_FORCE_ERR_F_SEQ_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_M (CSI_HOST_FORCE_ERR_F_SEQ_VC0_V << CSI_HOST_FORCE_ERR_F_SEQ_VC0_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC0_S 0 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_M (CSI_HOST_FORCE_ERR_F_SEQ_VC1_V << CSI_HOST_FORCE_ERR_F_SEQ_VC1_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC1_S 1 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_M (CSI_HOST_FORCE_ERR_F_SEQ_VC2_V << CSI_HOST_FORCE_ERR_F_SEQ_VC2_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC2_S 2 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_M (CSI_HOST_FORCE_ERR_F_SEQ_VC3_V << CSI_HOST_FORCE_ERR_F_SEQ_VC3_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC3_S 3 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_M (CSI_HOST_FORCE_ERR_F_SEQ_VC4_V << CSI_HOST_FORCE_ERR_F_SEQ_VC4_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC4_S 4 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_M (CSI_HOST_FORCE_ERR_F_SEQ_VC5_V << CSI_HOST_FORCE_ERR_F_SEQ_VC5_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC5_S 5 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_M (CSI_HOST_FORCE_ERR_F_SEQ_VC6_V << CSI_HOST_FORCE_ERR_F_SEQ_VC6_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC6_S 6 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_M (CSI_HOST_FORCE_ERR_F_SEQ_VC7_V << CSI_HOST_FORCE_ERR_F_SEQ_VC7_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC7_S 7 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_M (CSI_HOST_FORCE_ERR_F_SEQ_VC8_V << CSI_HOST_FORCE_ERR_F_SEQ_VC8_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC8_S 8 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_M (CSI_HOST_FORCE_ERR_F_SEQ_VC9_V << CSI_HOST_FORCE_ERR_F_SEQ_VC9_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC9_S 9 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_M (CSI_HOST_FORCE_ERR_F_SEQ_VC10_V << CSI_HOST_FORCE_ERR_F_SEQ_VC10_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC10_S 10 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_M (CSI_HOST_FORCE_ERR_F_SEQ_VC11_V << CSI_HOST_FORCE_ERR_F_SEQ_VC11_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC11_S 11 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_M (CSI_HOST_FORCE_ERR_F_SEQ_VC12_V << CSI_HOST_FORCE_ERR_F_SEQ_VC12_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC12_S 12 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_M (CSI_HOST_FORCE_ERR_F_SEQ_VC13_V << CSI_HOST_FORCE_ERR_F_SEQ_VC13_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC13_S 13 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_M (CSI_HOST_FORCE_ERR_F_SEQ_VC14_V << CSI_HOST_FORCE_ERR_F_SEQ_VC14_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC14_S 14 +/** CSI_HOST_FORCE_ERR_F_SEQ_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_F_SEQ_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_M (CSI_HOST_FORCE_ERR_F_SEQ_VC15_V << CSI_HOST_FORCE_ERR_F_SEQ_VC15_S) +#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_F_SEQ_VC15_S 15 + +/** CSI_HOST_INT_ST_CRC_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a0) +/** CSI_HOST_ST_ERR_FRAME_DATA_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_M (CSI_HOST_ST_ERR_FRAME_DATA_VC0_V << CSI_HOST_ST_ERR_FRAME_DATA_VC0_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC0_S 0 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_M (CSI_HOST_ST_ERR_FRAME_DATA_VC1_V << CSI_HOST_ST_ERR_FRAME_DATA_VC1_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC1_S 1 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_M (CSI_HOST_ST_ERR_FRAME_DATA_VC2_V << CSI_HOST_ST_ERR_FRAME_DATA_VC2_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC2_S 2 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_M (CSI_HOST_ST_ERR_FRAME_DATA_VC3_V << CSI_HOST_ST_ERR_FRAME_DATA_VC3_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC3_S 3 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_M (CSI_HOST_ST_ERR_FRAME_DATA_VC4_V << CSI_HOST_ST_ERR_FRAME_DATA_VC4_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC4_S 4 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_M (CSI_HOST_ST_ERR_FRAME_DATA_VC5_V << CSI_HOST_ST_ERR_FRAME_DATA_VC5_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC5_S 5 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_M (CSI_HOST_ST_ERR_FRAME_DATA_VC6_V << CSI_HOST_ST_ERR_FRAME_DATA_VC6_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC6_S 6 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_M (CSI_HOST_ST_ERR_FRAME_DATA_VC7_V << CSI_HOST_ST_ERR_FRAME_DATA_VC7_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC7_S 7 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_M (CSI_HOST_ST_ERR_FRAME_DATA_VC8_V << CSI_HOST_ST_ERR_FRAME_DATA_VC8_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC8_S 8 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_M (CSI_HOST_ST_ERR_FRAME_DATA_VC9_V << CSI_HOST_ST_ERR_FRAME_DATA_VC9_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC9_S 9 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_M (CSI_HOST_ST_ERR_FRAME_DATA_VC10_V << CSI_HOST_ST_ERR_FRAME_DATA_VC10_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC10_S 10 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_M (CSI_HOST_ST_ERR_FRAME_DATA_VC11_V << CSI_HOST_ST_ERR_FRAME_DATA_VC11_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC11_S 11 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_M (CSI_HOST_ST_ERR_FRAME_DATA_VC12_V << CSI_HOST_ST_ERR_FRAME_DATA_VC12_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC12_S 12 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_M (CSI_HOST_ST_ERR_FRAME_DATA_VC13_V << CSI_HOST_ST_ERR_FRAME_DATA_VC13_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC13_S 13 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_M (CSI_HOST_ST_ERR_FRAME_DATA_VC14_V << CSI_HOST_ST_ERR_FRAME_DATA_VC14_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC14_S 14 +/** CSI_HOST_ST_ERR_FRAME_DATA_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_FRAME_DATA_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_M (CSI_HOST_ST_ERR_FRAME_DATA_VC15_V << CSI_HOST_ST_ERR_FRAME_DATA_VC15_S) +#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_FRAME_DATA_VC15_S 15 + +/** CSI_HOST_INT_MSK_CRC_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a4) +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC0_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC0_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC0_S 0 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC1_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC1_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC1_S 1 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC2_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC2_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC2_S 2 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC3_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC3_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC3_S 3 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC4_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC4_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC4_S 4 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC5_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC5_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC5_S 5 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC6_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC6_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC6_S 6 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC7_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC7_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC7_S 7 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC8_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC8_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC8_S 8 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC9_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC9_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC9_S 9 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC10_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC10_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC10_S 10 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC11_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC11_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC11_S 11 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC12_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC12_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC12_S 12 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC13_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC13_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC13_S 13 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC14_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC14_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC14_S 14 +/** CSI_HOST_MASK_ERR_FRAME_DATA_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_M (CSI_HOST_MASK_ERR_FRAME_DATA_VC15_V << CSI_HOST_MASK_ERR_FRAME_DATA_VC15_S) +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_FRAME_DATA_VC15_S 15 + +/** CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2a8) +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC0_S 0 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC1_S 1 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC2_S 2 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC3_S 3 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC4_S 4 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC5_S 5 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC6_S 6 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC7_S 7 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC8_S 8 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC9_S 9 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC10_S 10 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC11_S 11 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC12_S 12 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC13_S 13 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC14_S 14 +/** CSI_HOST_FORCE_ERR_FRAME_DATA_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_M (CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_V << CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_S) +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_FRAME_DATA_VC15_S 15 + +/** CSI_HOST_INT_ST_PLD_CRC_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_ST_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b0) +/** CSI_HOST_ST_ERR_CRC_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_CRC_VC0_M (CSI_HOST_ST_ERR_CRC_VC0_V << CSI_HOST_ST_ERR_CRC_VC0_S) +#define CSI_HOST_ST_ERR_CRC_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC0_S 0 +/** CSI_HOST_ST_ERR_CRC_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_CRC_VC1_M (CSI_HOST_ST_ERR_CRC_VC1_V << CSI_HOST_ST_ERR_CRC_VC1_S) +#define CSI_HOST_ST_ERR_CRC_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC1_S 1 +/** CSI_HOST_ST_ERR_CRC_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_CRC_VC2_M (CSI_HOST_ST_ERR_CRC_VC2_V << CSI_HOST_ST_ERR_CRC_VC2_S) +#define CSI_HOST_ST_ERR_CRC_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC2_S 2 +/** CSI_HOST_ST_ERR_CRC_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_CRC_VC3_M (CSI_HOST_ST_ERR_CRC_VC3_V << CSI_HOST_ST_ERR_CRC_VC3_S) +#define CSI_HOST_ST_ERR_CRC_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC3_S 3 +/** CSI_HOST_ST_ERR_CRC_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_CRC_VC4_M (CSI_HOST_ST_ERR_CRC_VC4_V << CSI_HOST_ST_ERR_CRC_VC4_S) +#define CSI_HOST_ST_ERR_CRC_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC4_S 4 +/** CSI_HOST_ST_ERR_CRC_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_CRC_VC5_M (CSI_HOST_ST_ERR_CRC_VC5_V << CSI_HOST_ST_ERR_CRC_VC5_S) +#define CSI_HOST_ST_ERR_CRC_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC5_S 5 +/** CSI_HOST_ST_ERR_CRC_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_CRC_VC6_M (CSI_HOST_ST_ERR_CRC_VC6_V << CSI_HOST_ST_ERR_CRC_VC6_S) +#define CSI_HOST_ST_ERR_CRC_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC6_S 6 +/** CSI_HOST_ST_ERR_CRC_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_CRC_VC7_M (CSI_HOST_ST_ERR_CRC_VC7_V << CSI_HOST_ST_ERR_CRC_VC7_S) +#define CSI_HOST_ST_ERR_CRC_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC7_S 7 +/** CSI_HOST_ST_ERR_CRC_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_CRC_VC8_M (CSI_HOST_ST_ERR_CRC_VC8_V << CSI_HOST_ST_ERR_CRC_VC8_S) +#define CSI_HOST_ST_ERR_CRC_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC8_S 8 +/** CSI_HOST_ST_ERR_CRC_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_CRC_VC9_M (CSI_HOST_ST_ERR_CRC_VC9_V << CSI_HOST_ST_ERR_CRC_VC9_S) +#define CSI_HOST_ST_ERR_CRC_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC9_S 9 +/** CSI_HOST_ST_ERR_CRC_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_CRC_VC10_M (CSI_HOST_ST_ERR_CRC_VC10_V << CSI_HOST_ST_ERR_CRC_VC10_S) +#define CSI_HOST_ST_ERR_CRC_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC10_S 10 +/** CSI_HOST_ST_ERR_CRC_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_CRC_VC11_M (CSI_HOST_ST_ERR_CRC_VC11_V << CSI_HOST_ST_ERR_CRC_VC11_S) +#define CSI_HOST_ST_ERR_CRC_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC11_S 11 +/** CSI_HOST_ST_ERR_CRC_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_CRC_VC12_M (CSI_HOST_ST_ERR_CRC_VC12_V << CSI_HOST_ST_ERR_CRC_VC12_S) +#define CSI_HOST_ST_ERR_CRC_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC12_S 12 +/** CSI_HOST_ST_ERR_CRC_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_CRC_VC13_M (CSI_HOST_ST_ERR_CRC_VC13_V << CSI_HOST_ST_ERR_CRC_VC13_S) +#define CSI_HOST_ST_ERR_CRC_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC13_S 13 +/** CSI_HOST_ST_ERR_CRC_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_CRC_VC14_M (CSI_HOST_ST_ERR_CRC_VC14_V << CSI_HOST_ST_ERR_CRC_VC14_S) +#define CSI_HOST_ST_ERR_CRC_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC14_S 14 +/** CSI_HOST_ST_ERR_CRC_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_CRC_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_CRC_VC15_M (CSI_HOST_ST_ERR_CRC_VC15_V << CSI_HOST_ST_ERR_CRC_VC15_S) +#define CSI_HOST_ST_ERR_CRC_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_CRC_VC15_S 15 + +/** CSI_HOST_INT_MSK_PLD_CRC_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_MSK_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b4) +/** CSI_HOST_MASK_ERR_CRC_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_CRC_VC0_M (CSI_HOST_MASK_ERR_CRC_VC0_V << CSI_HOST_MASK_ERR_CRC_VC0_S) +#define CSI_HOST_MASK_ERR_CRC_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC0_S 0 +/** CSI_HOST_MASK_ERR_CRC_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_CRC_VC1_M (CSI_HOST_MASK_ERR_CRC_VC1_V << CSI_HOST_MASK_ERR_CRC_VC1_S) +#define CSI_HOST_MASK_ERR_CRC_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC1_S 1 +/** CSI_HOST_MASK_ERR_CRC_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_CRC_VC2_M (CSI_HOST_MASK_ERR_CRC_VC2_V << CSI_HOST_MASK_ERR_CRC_VC2_S) +#define CSI_HOST_MASK_ERR_CRC_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC2_S 2 +/** CSI_HOST_MASK_ERR_CRC_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_CRC_VC3_M (CSI_HOST_MASK_ERR_CRC_VC3_V << CSI_HOST_MASK_ERR_CRC_VC3_S) +#define CSI_HOST_MASK_ERR_CRC_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC3_S 3 +/** CSI_HOST_MASK_ERR_CRC_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_CRC_VC4_M (CSI_HOST_MASK_ERR_CRC_VC4_V << CSI_HOST_MASK_ERR_CRC_VC4_S) +#define CSI_HOST_MASK_ERR_CRC_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC4_S 4 +/** CSI_HOST_MASK_ERR_CRC_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_CRC_VC5_M (CSI_HOST_MASK_ERR_CRC_VC5_V << CSI_HOST_MASK_ERR_CRC_VC5_S) +#define CSI_HOST_MASK_ERR_CRC_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC5_S 5 +/** CSI_HOST_MASK_ERR_CRC_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_CRC_VC6_M (CSI_HOST_MASK_ERR_CRC_VC6_V << CSI_HOST_MASK_ERR_CRC_VC6_S) +#define CSI_HOST_MASK_ERR_CRC_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC6_S 6 +/** CSI_HOST_MASK_ERR_CRC_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_CRC_VC7_M (CSI_HOST_MASK_ERR_CRC_VC7_V << CSI_HOST_MASK_ERR_CRC_VC7_S) +#define CSI_HOST_MASK_ERR_CRC_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC7_S 7 +/** CSI_HOST_MASK_ERR_CRC_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_CRC_VC8_M (CSI_HOST_MASK_ERR_CRC_VC8_V << CSI_HOST_MASK_ERR_CRC_VC8_S) +#define CSI_HOST_MASK_ERR_CRC_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC8_S 8 +/** CSI_HOST_MASK_ERR_CRC_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_CRC_VC9_M (CSI_HOST_MASK_ERR_CRC_VC9_V << CSI_HOST_MASK_ERR_CRC_VC9_S) +#define CSI_HOST_MASK_ERR_CRC_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC9_S 9 +/** CSI_HOST_MASK_ERR_CRC_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_CRC_VC10_M (CSI_HOST_MASK_ERR_CRC_VC10_V << CSI_HOST_MASK_ERR_CRC_VC10_S) +#define CSI_HOST_MASK_ERR_CRC_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC10_S 10 +/** CSI_HOST_MASK_ERR_CRC_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_CRC_VC11_M (CSI_HOST_MASK_ERR_CRC_VC11_V << CSI_HOST_MASK_ERR_CRC_VC11_S) +#define CSI_HOST_MASK_ERR_CRC_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC11_S 11 +/** CSI_HOST_MASK_ERR_CRC_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_CRC_VC12_M (CSI_HOST_MASK_ERR_CRC_VC12_V << CSI_HOST_MASK_ERR_CRC_VC12_S) +#define CSI_HOST_MASK_ERR_CRC_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC12_S 12 +/** CSI_HOST_MASK_ERR_CRC_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_CRC_VC13_M (CSI_HOST_MASK_ERR_CRC_VC13_V << CSI_HOST_MASK_ERR_CRC_VC13_S) +#define CSI_HOST_MASK_ERR_CRC_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC13_S 13 +/** CSI_HOST_MASK_ERR_CRC_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_CRC_VC14_M (CSI_HOST_MASK_ERR_CRC_VC14_V << CSI_HOST_MASK_ERR_CRC_VC14_S) +#define CSI_HOST_MASK_ERR_CRC_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC14_S 14 +/** CSI_HOST_MASK_ERR_CRC_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_CRC_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_CRC_VC15_M (CSI_HOST_MASK_ERR_CRC_VC15_V << CSI_HOST_MASK_ERR_CRC_VC15_S) +#define CSI_HOST_MASK_ERR_CRC_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_CRC_VC15_S 15 + +/** CSI_HOST_INT_FORCE_PLD_CRC_FATAL_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_PLD_CRC_FATAL_REG (DR_REG_CSI_HOST_BASE + 0x2b8) +/** CSI_HOST_FORCE_ERR_CRC_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_CRC_VC0_M (CSI_HOST_FORCE_ERR_CRC_VC0_V << CSI_HOST_FORCE_ERR_CRC_VC0_S) +#define CSI_HOST_FORCE_ERR_CRC_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC0_S 0 +/** CSI_HOST_FORCE_ERR_CRC_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_CRC_VC1_M (CSI_HOST_FORCE_ERR_CRC_VC1_V << CSI_HOST_FORCE_ERR_CRC_VC1_S) +#define CSI_HOST_FORCE_ERR_CRC_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC1_S 1 +/** CSI_HOST_FORCE_ERR_CRC_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_CRC_VC2_M (CSI_HOST_FORCE_ERR_CRC_VC2_V << CSI_HOST_FORCE_ERR_CRC_VC2_S) +#define CSI_HOST_FORCE_ERR_CRC_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC2_S 2 +/** CSI_HOST_FORCE_ERR_CRC_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_CRC_VC3_M (CSI_HOST_FORCE_ERR_CRC_VC3_V << CSI_HOST_FORCE_ERR_CRC_VC3_S) +#define CSI_HOST_FORCE_ERR_CRC_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC3_S 3 +/** CSI_HOST_FORCE_ERR_CRC_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_CRC_VC4_M (CSI_HOST_FORCE_ERR_CRC_VC4_V << CSI_HOST_FORCE_ERR_CRC_VC4_S) +#define CSI_HOST_FORCE_ERR_CRC_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC4_S 4 +/** CSI_HOST_FORCE_ERR_CRC_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_CRC_VC5_M (CSI_HOST_FORCE_ERR_CRC_VC5_V << CSI_HOST_FORCE_ERR_CRC_VC5_S) +#define CSI_HOST_FORCE_ERR_CRC_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC5_S 5 +/** CSI_HOST_FORCE_ERR_CRC_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_CRC_VC6_M (CSI_HOST_FORCE_ERR_CRC_VC6_V << CSI_HOST_FORCE_ERR_CRC_VC6_S) +#define CSI_HOST_FORCE_ERR_CRC_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC6_S 6 +/** CSI_HOST_FORCE_ERR_CRC_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_CRC_VC7_M (CSI_HOST_FORCE_ERR_CRC_VC7_V << CSI_HOST_FORCE_ERR_CRC_VC7_S) +#define CSI_HOST_FORCE_ERR_CRC_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC7_S 7 +/** CSI_HOST_FORCE_ERR_CRC_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_CRC_VC8_M (CSI_HOST_FORCE_ERR_CRC_VC8_V << CSI_HOST_FORCE_ERR_CRC_VC8_S) +#define CSI_HOST_FORCE_ERR_CRC_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC8_S 8 +/** CSI_HOST_FORCE_ERR_CRC_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_CRC_VC9_M (CSI_HOST_FORCE_ERR_CRC_VC9_V << CSI_HOST_FORCE_ERR_CRC_VC9_S) +#define CSI_HOST_FORCE_ERR_CRC_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC9_S 9 +/** CSI_HOST_FORCE_ERR_CRC_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_CRC_VC10_M (CSI_HOST_FORCE_ERR_CRC_VC10_V << CSI_HOST_FORCE_ERR_CRC_VC10_S) +#define CSI_HOST_FORCE_ERR_CRC_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC10_S 10 +/** CSI_HOST_FORCE_ERR_CRC_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_CRC_VC11_M (CSI_HOST_FORCE_ERR_CRC_VC11_V << CSI_HOST_FORCE_ERR_CRC_VC11_S) +#define CSI_HOST_FORCE_ERR_CRC_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC11_S 11 +/** CSI_HOST_FORCE_ERR_CRC_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_CRC_VC12_M (CSI_HOST_FORCE_ERR_CRC_VC12_V << CSI_HOST_FORCE_ERR_CRC_VC12_S) +#define CSI_HOST_FORCE_ERR_CRC_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC12_S 12 +/** CSI_HOST_FORCE_ERR_CRC_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_CRC_VC13_M (CSI_HOST_FORCE_ERR_CRC_VC13_V << CSI_HOST_FORCE_ERR_CRC_VC13_S) +#define CSI_HOST_FORCE_ERR_CRC_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC13_S 13 +/** CSI_HOST_FORCE_ERR_CRC_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_CRC_VC14_M (CSI_HOST_FORCE_ERR_CRC_VC14_V << CSI_HOST_FORCE_ERR_CRC_VC14_S) +#define CSI_HOST_FORCE_ERR_CRC_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC14_S 14 +/** CSI_HOST_FORCE_ERR_CRC_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_CRC_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_CRC_VC15_M (CSI_HOST_FORCE_ERR_CRC_VC15_V << CSI_HOST_FORCE_ERR_CRC_VC15_S) +#define CSI_HOST_FORCE_ERR_CRC_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_CRC_VC15_S 15 + +/** CSI_HOST_INT_ST_DATA_ID_REG register + * NA + */ +#define CSI_HOST_INT_ST_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c0) +/** CSI_HOST_ST_ERR_ID_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_ID_VC0_M (CSI_HOST_ST_ERR_ID_VC0_V << CSI_HOST_ST_ERR_ID_VC0_S) +#define CSI_HOST_ST_ERR_ID_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC0_S 0 +/** CSI_HOST_ST_ERR_ID_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_ID_VC1_M (CSI_HOST_ST_ERR_ID_VC1_V << CSI_HOST_ST_ERR_ID_VC1_S) +#define CSI_HOST_ST_ERR_ID_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC1_S 1 +/** CSI_HOST_ST_ERR_ID_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_ID_VC2_M (CSI_HOST_ST_ERR_ID_VC2_V << CSI_HOST_ST_ERR_ID_VC2_S) +#define CSI_HOST_ST_ERR_ID_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC2_S 2 +/** CSI_HOST_ST_ERR_ID_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_ID_VC3_M (CSI_HOST_ST_ERR_ID_VC3_V << CSI_HOST_ST_ERR_ID_VC3_S) +#define CSI_HOST_ST_ERR_ID_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC3_S 3 +/** CSI_HOST_ST_ERR_ID_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_ID_VC4_M (CSI_HOST_ST_ERR_ID_VC4_V << CSI_HOST_ST_ERR_ID_VC4_S) +#define CSI_HOST_ST_ERR_ID_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC4_S 4 +/** CSI_HOST_ST_ERR_ID_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_ID_VC5_M (CSI_HOST_ST_ERR_ID_VC5_V << CSI_HOST_ST_ERR_ID_VC5_S) +#define CSI_HOST_ST_ERR_ID_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC5_S 5 +/** CSI_HOST_ST_ERR_ID_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_ID_VC6_M (CSI_HOST_ST_ERR_ID_VC6_V << CSI_HOST_ST_ERR_ID_VC6_S) +#define CSI_HOST_ST_ERR_ID_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC6_S 6 +/** CSI_HOST_ST_ERR_ID_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_ID_VC7_M (CSI_HOST_ST_ERR_ID_VC7_V << CSI_HOST_ST_ERR_ID_VC7_S) +#define CSI_HOST_ST_ERR_ID_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC7_S 7 +/** CSI_HOST_ST_ERR_ID_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_ID_VC8_M (CSI_HOST_ST_ERR_ID_VC8_V << CSI_HOST_ST_ERR_ID_VC8_S) +#define CSI_HOST_ST_ERR_ID_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC8_S 8 +/** CSI_HOST_ST_ERR_ID_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_ID_VC9_M (CSI_HOST_ST_ERR_ID_VC9_V << CSI_HOST_ST_ERR_ID_VC9_S) +#define CSI_HOST_ST_ERR_ID_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC9_S 9 +/** CSI_HOST_ST_ERR_ID_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_ID_VC10_M (CSI_HOST_ST_ERR_ID_VC10_V << CSI_HOST_ST_ERR_ID_VC10_S) +#define CSI_HOST_ST_ERR_ID_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC10_S 10 +/** CSI_HOST_ST_ERR_ID_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_ID_VC11_M (CSI_HOST_ST_ERR_ID_VC11_V << CSI_HOST_ST_ERR_ID_VC11_S) +#define CSI_HOST_ST_ERR_ID_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC11_S 11 +/** CSI_HOST_ST_ERR_ID_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_ID_VC12_M (CSI_HOST_ST_ERR_ID_VC12_V << CSI_HOST_ST_ERR_ID_VC12_S) +#define CSI_HOST_ST_ERR_ID_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC12_S 12 +/** CSI_HOST_ST_ERR_ID_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_ID_VC13_M (CSI_HOST_ST_ERR_ID_VC13_V << CSI_HOST_ST_ERR_ID_VC13_S) +#define CSI_HOST_ST_ERR_ID_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC13_S 13 +/** CSI_HOST_ST_ERR_ID_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_ID_VC14_M (CSI_HOST_ST_ERR_ID_VC14_V << CSI_HOST_ST_ERR_ID_VC14_S) +#define CSI_HOST_ST_ERR_ID_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC14_S 14 +/** CSI_HOST_ST_ERR_ID_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ID_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_ID_VC15_M (CSI_HOST_ST_ERR_ID_VC15_V << CSI_HOST_ST_ERR_ID_VC15_S) +#define CSI_HOST_ST_ERR_ID_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_ID_VC15_S 15 + +/** CSI_HOST_INT_MSK_DATA_ID_REG register + * NA + */ +#define CSI_HOST_INT_MSK_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c4) +/** CSI_HOST_MASK_ERR_ID_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_ID_VC0_M (CSI_HOST_MASK_ERR_ID_VC0_V << CSI_HOST_MASK_ERR_ID_VC0_S) +#define CSI_HOST_MASK_ERR_ID_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC0_S 0 +/** CSI_HOST_MASK_ERR_ID_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_ID_VC1_M (CSI_HOST_MASK_ERR_ID_VC1_V << CSI_HOST_MASK_ERR_ID_VC1_S) +#define CSI_HOST_MASK_ERR_ID_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC1_S 1 +/** CSI_HOST_MASK_ERR_ID_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_ID_VC2_M (CSI_HOST_MASK_ERR_ID_VC2_V << CSI_HOST_MASK_ERR_ID_VC2_S) +#define CSI_HOST_MASK_ERR_ID_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC2_S 2 +/** CSI_HOST_MASK_ERR_ID_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_ID_VC3_M (CSI_HOST_MASK_ERR_ID_VC3_V << CSI_HOST_MASK_ERR_ID_VC3_S) +#define CSI_HOST_MASK_ERR_ID_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC3_S 3 +/** CSI_HOST_MASK_ERR_ID_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_ID_VC4_M (CSI_HOST_MASK_ERR_ID_VC4_V << CSI_HOST_MASK_ERR_ID_VC4_S) +#define CSI_HOST_MASK_ERR_ID_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC4_S 4 +/** CSI_HOST_MASK_ERR_ID_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_ID_VC5_M (CSI_HOST_MASK_ERR_ID_VC5_V << CSI_HOST_MASK_ERR_ID_VC5_S) +#define CSI_HOST_MASK_ERR_ID_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC5_S 5 +/** CSI_HOST_MASK_ERR_ID_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_ID_VC6_M (CSI_HOST_MASK_ERR_ID_VC6_V << CSI_HOST_MASK_ERR_ID_VC6_S) +#define CSI_HOST_MASK_ERR_ID_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC6_S 6 +/** CSI_HOST_MASK_ERR_ID_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_ID_VC7_M (CSI_HOST_MASK_ERR_ID_VC7_V << CSI_HOST_MASK_ERR_ID_VC7_S) +#define CSI_HOST_MASK_ERR_ID_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC7_S 7 +/** CSI_HOST_MASK_ERR_ID_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_ID_VC8_M (CSI_HOST_MASK_ERR_ID_VC8_V << CSI_HOST_MASK_ERR_ID_VC8_S) +#define CSI_HOST_MASK_ERR_ID_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC8_S 8 +/** CSI_HOST_MASK_ERR_ID_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_ID_VC9_M (CSI_HOST_MASK_ERR_ID_VC9_V << CSI_HOST_MASK_ERR_ID_VC9_S) +#define CSI_HOST_MASK_ERR_ID_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC9_S 9 +/** CSI_HOST_MASK_ERR_ID_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_ID_VC10_M (CSI_HOST_MASK_ERR_ID_VC10_V << CSI_HOST_MASK_ERR_ID_VC10_S) +#define CSI_HOST_MASK_ERR_ID_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC10_S 10 +/** CSI_HOST_MASK_ERR_ID_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_ID_VC11_M (CSI_HOST_MASK_ERR_ID_VC11_V << CSI_HOST_MASK_ERR_ID_VC11_S) +#define CSI_HOST_MASK_ERR_ID_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC11_S 11 +/** CSI_HOST_MASK_ERR_ID_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_ID_VC12_M (CSI_HOST_MASK_ERR_ID_VC12_V << CSI_HOST_MASK_ERR_ID_VC12_S) +#define CSI_HOST_MASK_ERR_ID_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC12_S 12 +/** CSI_HOST_MASK_ERR_ID_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_ID_VC13_M (CSI_HOST_MASK_ERR_ID_VC13_V << CSI_HOST_MASK_ERR_ID_VC13_S) +#define CSI_HOST_MASK_ERR_ID_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC13_S 13 +/** CSI_HOST_MASK_ERR_ID_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_ID_VC14_M (CSI_HOST_MASK_ERR_ID_VC14_V << CSI_HOST_MASK_ERR_ID_VC14_S) +#define CSI_HOST_MASK_ERR_ID_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC14_S 14 +/** CSI_HOST_MASK_ERR_ID_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ID_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_ID_VC15_M (CSI_HOST_MASK_ERR_ID_VC15_V << CSI_HOST_MASK_ERR_ID_VC15_S) +#define CSI_HOST_MASK_ERR_ID_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_ID_VC15_S 15 + +/** CSI_HOST_INT_FORCE_DATA_ID_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_DATA_ID_REG (DR_REG_CSI_HOST_BASE + 0x2c8) +/** CSI_HOST_FORCE_ERR_ID_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_ID_VC0_M (CSI_HOST_FORCE_ERR_ID_VC0_V << CSI_HOST_FORCE_ERR_ID_VC0_S) +#define CSI_HOST_FORCE_ERR_ID_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC0_S 0 +/** CSI_HOST_FORCE_ERR_ID_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_ID_VC1_M (CSI_HOST_FORCE_ERR_ID_VC1_V << CSI_HOST_FORCE_ERR_ID_VC1_S) +#define CSI_HOST_FORCE_ERR_ID_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC1_S 1 +/** CSI_HOST_FORCE_ERR_ID_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_ID_VC2_M (CSI_HOST_FORCE_ERR_ID_VC2_V << CSI_HOST_FORCE_ERR_ID_VC2_S) +#define CSI_HOST_FORCE_ERR_ID_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC2_S 2 +/** CSI_HOST_FORCE_ERR_ID_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_ID_VC3_M (CSI_HOST_FORCE_ERR_ID_VC3_V << CSI_HOST_FORCE_ERR_ID_VC3_S) +#define CSI_HOST_FORCE_ERR_ID_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC3_S 3 +/** CSI_HOST_FORCE_ERR_ID_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_ID_VC4_M (CSI_HOST_FORCE_ERR_ID_VC4_V << CSI_HOST_FORCE_ERR_ID_VC4_S) +#define CSI_HOST_FORCE_ERR_ID_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC4_S 4 +/** CSI_HOST_FORCE_ERR_ID_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_ID_VC5_M (CSI_HOST_FORCE_ERR_ID_VC5_V << CSI_HOST_FORCE_ERR_ID_VC5_S) +#define CSI_HOST_FORCE_ERR_ID_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC5_S 5 +/** CSI_HOST_FORCE_ERR_ID_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_ID_VC6_M (CSI_HOST_FORCE_ERR_ID_VC6_V << CSI_HOST_FORCE_ERR_ID_VC6_S) +#define CSI_HOST_FORCE_ERR_ID_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC6_S 6 +/** CSI_HOST_FORCE_ERR_ID_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_ID_VC7_M (CSI_HOST_FORCE_ERR_ID_VC7_V << CSI_HOST_FORCE_ERR_ID_VC7_S) +#define CSI_HOST_FORCE_ERR_ID_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC7_S 7 +/** CSI_HOST_FORCE_ERR_ID_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_ID_VC8_M (CSI_HOST_FORCE_ERR_ID_VC8_V << CSI_HOST_FORCE_ERR_ID_VC8_S) +#define CSI_HOST_FORCE_ERR_ID_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC8_S 8 +/** CSI_HOST_FORCE_ERR_ID_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_ID_VC9_M (CSI_HOST_FORCE_ERR_ID_VC9_V << CSI_HOST_FORCE_ERR_ID_VC9_S) +#define CSI_HOST_FORCE_ERR_ID_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC9_S 9 +/** CSI_HOST_FORCE_ERR_ID_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_ID_VC10_M (CSI_HOST_FORCE_ERR_ID_VC10_V << CSI_HOST_FORCE_ERR_ID_VC10_S) +#define CSI_HOST_FORCE_ERR_ID_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC10_S 10 +/** CSI_HOST_FORCE_ERR_ID_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_ID_VC11_M (CSI_HOST_FORCE_ERR_ID_VC11_V << CSI_HOST_FORCE_ERR_ID_VC11_S) +#define CSI_HOST_FORCE_ERR_ID_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC11_S 11 +/** CSI_HOST_FORCE_ERR_ID_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_ID_VC12_M (CSI_HOST_FORCE_ERR_ID_VC12_V << CSI_HOST_FORCE_ERR_ID_VC12_S) +#define CSI_HOST_FORCE_ERR_ID_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC12_S 12 +/** CSI_HOST_FORCE_ERR_ID_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_ID_VC13_M (CSI_HOST_FORCE_ERR_ID_VC13_V << CSI_HOST_FORCE_ERR_ID_VC13_S) +#define CSI_HOST_FORCE_ERR_ID_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC13_S 13 +/** CSI_HOST_FORCE_ERR_ID_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_ID_VC14_M (CSI_HOST_FORCE_ERR_ID_VC14_V << CSI_HOST_FORCE_ERR_ID_VC14_S) +#define CSI_HOST_FORCE_ERR_ID_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC14_S 14 +/** CSI_HOST_FORCE_ERR_ID_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ID_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_ID_VC15_M (CSI_HOST_FORCE_ERR_ID_VC15_V << CSI_HOST_FORCE_ERR_ID_VC15_S) +#define CSI_HOST_FORCE_ERR_ID_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ID_VC15_S 15 + +/** CSI_HOST_INT_ST_ECC_CORRECTED_REG register + * NA + */ +#define CSI_HOST_INT_ST_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d0) +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC0 : RC; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0 (BIT(0)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC0_S 0 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC1 : RC; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1 (BIT(1)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC1_S 1 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC2 : RC; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2 (BIT(2)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC2_S 2 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC3 : RC; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3 (BIT(3)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC3_S 3 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC4 : RC; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4 (BIT(4)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC4_S 4 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC5 : RC; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5 (BIT(5)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC5_S 5 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC6 : RC; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6 (BIT(6)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC6_S 6 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC7 : RC; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7 (BIT(7)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC7_S 7 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC8 : RC; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8 (BIT(8)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC8_S 8 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC9 : RC; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9 (BIT(9)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC9_S 9 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC10 : RC; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10 (BIT(10)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC10_S 10 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC11 : RC; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11 (BIT(11)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC11_S 11 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC12 : RC; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12 (BIT(12)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC12_S 12 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC13 : RC; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13 (BIT(13)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC13_S 13 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC14 : RC; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14 (BIT(14)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC14_S 14 +/** CSI_HOST_ST_ERR_ECC_CORRECTED_VC15 : RC; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15 (BIT(15)) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_M (CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_S) +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_V 0x00000001U +#define CSI_HOST_ST_ERR_ECC_CORRECTED_VC15_S 15 + +/** CSI_HOST_INT_MSK_ECC_CORRECTED_REG register + * NA + */ +#define CSI_HOST_INT_MSK_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d4) +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0 (BIT(0)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC0_S 0 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1 (BIT(1)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC1_S 1 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2 (BIT(2)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC2_S 2 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3 (BIT(3)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC3_S 3 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4 (BIT(4)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC4_S 4 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5 (BIT(5)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC5_S 5 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6 (BIT(6)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC6_S 6 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7 (BIT(7)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC7_S 7 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8 (BIT(8)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC8_S 8 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9 (BIT(9)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC9_S 9 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10 (BIT(10)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC10_S 10 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11 (BIT(11)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC11_S 11 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12 (BIT(12)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC12_S 12 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13 (BIT(13)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC13_S 13 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14 (BIT(14)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC14_S 14 +/** CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15 (BIT(15)) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_M (CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_S) +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_V 0x00000001U +#define CSI_HOST_MASK_ERR_ECC_CORRECTED_VC15_S 15 + +/** CSI_HOST_INT_FORCE_ECC_CORRECTED_REG register + * NA + */ +#define CSI_HOST_INT_FORCE_ECC_CORRECTED_REG (DR_REG_CSI_HOST_BASE + 0x2d8) +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0 (BIT(0)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC0_S 0 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1 (BIT(1)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC1_S 1 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2 (BIT(2)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC2_S 2 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3 (BIT(3)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC3_S 3 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4 (BIT(4)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC4_S 4 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5 (BIT(5)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC5_S 5 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6 (BIT(6)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC6_S 6 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7 (BIT(7)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC7_S 7 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8 (BIT(8)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC8_S 8 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9 (BIT(9)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC9_S 9 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10 (BIT(10)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC10_S 10 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11 (BIT(11)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC11_S 11 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12 (BIT(12)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC12_S 12 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13 (BIT(13)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC13_S 13 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14 (BIT(14)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC14_S 14 +/** CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15 (BIT(15)) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_M (CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_V << CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_S) +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_V 0x00000001U +#define CSI_HOST_FORCE_ERR_ECC_CORRECTED_VC15_S 15 + +/** CSI_HOST_SCRAMBLING_REG register + * NA + */ +#define CSI_HOST_SCRAMBLING_REG (DR_REG_CSI_HOST_BASE + 0x300) +/** CSI_HOST_SCRAMBLE_ENABLE : R/W; bitpos: [0]; default: 0; + * NA + */ +#define CSI_HOST_SCRAMBLE_ENABLE (BIT(0)) +#define CSI_HOST_SCRAMBLE_ENABLE_M (CSI_HOST_SCRAMBLE_ENABLE_V << CSI_HOST_SCRAMBLE_ENABLE_S) +#define CSI_HOST_SCRAMBLE_ENABLE_V 0x00000001U +#define CSI_HOST_SCRAMBLE_ENABLE_S 0 + +/** CSI_HOST_SCRAMBLING_SEED1_REG register + * NA + */ +#define CSI_HOST_SCRAMBLING_SEED1_REG (DR_REG_CSI_HOST_BASE + 0x304) +/** CSI_HOST_SCRAMBLE_SEED_LANE1 : R/W; bitpos: [15:0]; default: 4104; + * NA + */ +#define CSI_HOST_SCRAMBLE_SEED_LANE1 0x0000FFFFU +#define CSI_HOST_SCRAMBLE_SEED_LANE1_M (CSI_HOST_SCRAMBLE_SEED_LANE1_V << CSI_HOST_SCRAMBLE_SEED_LANE1_S) +#define CSI_HOST_SCRAMBLE_SEED_LANE1_V 0x0000FFFFU +#define CSI_HOST_SCRAMBLE_SEED_LANE1_S 0 + +/** CSI_HOST_SCRAMBLING_SEED2_REG register + * NA + */ +#define CSI_HOST_SCRAMBLING_SEED2_REG (DR_REG_CSI_HOST_BASE + 0x308) +/** CSI_HOST_SCRAMBLE_SEED_LANE2 : R/W; bitpos: [15:0]; default: 4488; + * NA + */ +#define CSI_HOST_SCRAMBLE_SEED_LANE2 0x0000FFFFU +#define CSI_HOST_SCRAMBLE_SEED_LANE2_M (CSI_HOST_SCRAMBLE_SEED_LANE2_V << CSI_HOST_SCRAMBLE_SEED_LANE2_S) +#define CSI_HOST_SCRAMBLE_SEED_LANE2_V 0x0000FFFFU +#define CSI_HOST_SCRAMBLE_SEED_LANE2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_struct.h new file mode 100644 index 0000000000..bf5bfc43d9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_host_struct.h @@ -0,0 +1,1883 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of version register + * NA + */ +typedef union { + struct { + /** version : RO; bitpos: [31:0]; default: 825569322; + * NA + */ + uint32_t version:32; + }; + uint32_t val; +} csi_host_version_reg_t; + + +/** Group: Configuration Registers */ +/** Type of n_lanes register + * NA + */ +typedef union { + struct { + /** n_lanes : R/W; bitpos: [2:0]; default: 1; + * NA + */ + uint32_t n_lanes:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} csi_host_n_lanes_reg_t; + +/** Type of csi2_resetn register + * NA + */ +typedef union { + struct { + /** csi2_resetn : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t csi2_resetn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_csi2_resetn_reg_t; + +/** Type of phy_shutdownz register + * NA + */ +typedef union { + struct { + /** phy_shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_shutdownz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_phy_shutdownz_reg_t; + +/** Type of dphy_rstz register + * NA + */ +typedef union { + struct { + /** dphy_rstz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t dphy_rstz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_dphy_rstz_reg_t; + +/** Type of phy_rx register + * NA + */ +typedef union { + struct { + /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_rxulpsesc_0:1; + /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_rxulpsesc_1:1; + uint32_t reserved_2:14; + /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t phy_rxulpsclknot:1; + /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t phy_rxclkactivehs:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_phy_rx_reg_t; + +/** Type of phy_test_ctrl0 register + * NA + */ +typedef union { + struct { + /** phy_testclr : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t phy_testclr:1; + /** phy_testclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_testclk:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_phy_test_ctrl0_reg_t; + +/** Type of phy_test_ctrl1 register + * NA + */ +typedef union { + struct { + /** phy_testdin : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t phy_testdin:8; + /** phy_testdout : RO; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t phy_testdout:8; + /** phy_testen : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_testen:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_phy_test_ctrl1_reg_t; + +/** Type of vc_extension register + * NA + */ +typedef union { + struct { + /** vcx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t vcx:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_vc_extension_reg_t; + +/** Type of phy_cal register + * NA + */ +typedef union { + struct { + /** rxskewcalhs : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t rxskewcalhs:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_phy_cal_reg_t; + +/** Type of scrambling register + * NA + */ +typedef union { + struct { + /** scramble_enable : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t scramble_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_host_scrambling_reg_t; + +/** Type of scrambling_seed1 register + * NA + */ +typedef union { + struct { + /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104; + * NA + */ + uint32_t scramble_seed_lane1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_scrambling_seed1_reg_t; + +/** Type of scrambling_seed2 register + * NA + */ +typedef union { + struct { + /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488; + * NA + */ + uint32_t scramble_seed_lane2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_scrambling_seed2_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_st_main register + * NA + */ +typedef union { + struct { + /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_status_int_phy_fatal:1; + /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_status_int_pkt_fatal:1; + /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_status_int_bndry_frame_fatal:1; + /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_status_int_seq_frame_fatal:1; + /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_status_int_crc_frame_fatal:1; + /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_status_int_pld_crc_fatal:1; + /** st_status_int_data_id : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_status_int_data_id:1; + /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_status_int_ecc_corrected:1; + uint32_t reserved_8:8; + /** st_status_int_phy : RC; bitpos: [16]; default: 0; + * NA + */ + uint32_t st_status_int_phy:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_int_st_main_reg_t; + +/** Type of int_st_phy_fatal register + * NA + */ +typedef union { + struct { + /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_phy_errsotsynchs_0:1; + /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_st_phy_fatal_reg_t; + +/** Type of int_msk_phy_fatal register + * NA + */ +typedef union { + struct { + /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_phy_errsotsynchs_0:1; + /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_msk_phy_fatal_reg_t; + +/** Type of int_force_phy_fatal register + * NA + */ +typedef union { + struct { + /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_phy_errsotsynchs_0:1; + /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_phy_errsotsynchs_1:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_force_phy_fatal_reg_t; + +/** Type of int_st_pkt_fatal register + * NA + */ +typedef union { + struct { + /** st_err_ecc_double : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_ecc_double:1; + /** st_shorter_payload : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_st_pkt_fatal_reg_t; + +/** Type of int_msk_pkt_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_ecc_double:1; + /** mask_shorter_payload : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_msk_pkt_fatal_reg_t; + +/** Type of int_force_pkt_fatal register + * NA + */ +typedef union { + struct { + /** force_err_ecc_double : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_ecc_double:1; + /** force_shorter_payload : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_shorter_payload:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_host_int_force_pkt_fatal_reg_t; + +/** Type of int_st_phy register + * NA + */ +typedef union { + struct { + /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_phy_errsoths_0:1; + /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0; + * NA + */ + uint32_t st_phy_erresc_0:1; + /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0; + * NA + */ + uint32_t st_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_st_phy_reg_t; + +/** Type of int_msk_phy register + * NA + */ +typedef union { + struct { + /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_phy_errsoths_0:1; + /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t mask_phy_erresc_0:1; + /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t mask_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_msk_phy_reg_t; + +/** Type of int_force_phy register + * NA + */ +typedef union { + struct { + /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_phy_errsoths_0:1; + /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_phy_errsoths_1:1; + uint32_t reserved_2:14; + /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t force_phy_erresc_0:1; + /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t force_phy_erresc_1:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_host_int_force_phy_reg_t; + +/** Type of int_st_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc0:1; + /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc1:1; + /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc2:1; + /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc3:1; + /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc4:1; + /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc5:1; + /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc6:1; + /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc7:1; + /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc8:1; + /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc9:1; + /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc10:1; + /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc11:1; + /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc12:1; + /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc13:1; + /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc14:1; + /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_bndry_frame_fatal_reg_t; + +/** Type of int_msk_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc0:1; + /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc1:1; + /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc2:1; + /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc3:1; + /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc4:1; + /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc5:1; + /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc6:1; + /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc7:1; + /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc8:1; + /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc9:1; + /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc10:1; + /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc11:1; + /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc12:1; + /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc13:1; + /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc14:1; + /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_bndry_frame_fatal_reg_t; + +/** Type of int_force_bndry_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc0:1; + /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc1:1; + /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc2:1; + /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc3:1; + /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc4:1; + /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc5:1; + /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc6:1; + /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc7:1; + /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc8:1; + /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc9:1; + /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc10:1; + /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc11:1; + /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc12:1; + /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc13:1; + /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc14:1; + /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_f_bndry_match_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_bndry_frame_fatal_reg_t; + +/** Type of int_st_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc0:1; + /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc1:1; + /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc2:1; + /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc3:1; + /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc4:1; + /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc5:1; + /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc6:1; + /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc7:1; + /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc8:1; + /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc9:1; + /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc10:1; + /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc11:1; + /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc12:1; + /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc13:1; + /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc14:1; + /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_seq_frame_fatal_reg_t; + +/** Type of int_msk_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc0:1; + /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc1:1; + /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc2:1; + /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc3:1; + /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc4:1; + /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc5:1; + /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc6:1; + /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc7:1; + /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc8:1; + /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc9:1; + /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc10:1; + /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc11:1; + /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc12:1; + /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc13:1; + /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc14:1; + /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_seq_frame_fatal_reg_t; + +/** Type of int_force_seq_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc0:1; + /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc1:1; + /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc2:1; + /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc3:1; + /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc4:1; + /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc5:1; + /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc6:1; + /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc7:1; + /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc8:1; + /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc9:1; + /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc10:1; + /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc11:1; + /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc12:1; + /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc13:1; + /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc14:1; + /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_f_seq_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_seq_frame_fatal_reg_t; + +/** Type of int_st_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc0:1; + /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc1:1; + /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc2:1; + /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc3:1; + /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc4:1; + /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc5:1; + /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc6:1; + /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc7:1; + /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc8:1; + /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc9:1; + /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc10:1; + /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc11:1; + /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc12:1; + /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc13:1; + /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc14:1; + /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_crc_frame_fatal_reg_t; + +/** Type of int_msk_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc0:1; + /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc1:1; + /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc2:1; + /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc3:1; + /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc4:1; + /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc5:1; + /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc6:1; + /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc7:1; + /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc8:1; + /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc9:1; + /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc10:1; + /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc11:1; + /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc12:1; + /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc13:1; + /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc14:1; + /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_crc_frame_fatal_reg_t; + +/** Type of int_force_crc_frame_fatal register + * NA + */ +typedef union { + struct { + /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc0:1; + /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc1:1; + /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc2:1; + /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc3:1; + /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc4:1; + /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc5:1; + /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc6:1; + /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc7:1; + /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc8:1; + /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc9:1; + /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc10:1; + /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc11:1; + /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc12:1; + /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc13:1; + /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc14:1; + /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_frame_data_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_crc_frame_fatal_reg_t; + +/** Type of int_st_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_crc_vc0:1; + /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_crc_vc1:1; + /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_crc_vc2:1; + /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_crc_vc3:1; + /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_crc_vc4:1; + /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_crc_vc5:1; + /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_crc_vc6:1; + /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_crc_vc7:1; + /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_crc_vc8:1; + /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_crc_vc9:1; + /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_crc_vc10:1; + /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_crc_vc11:1; + /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_crc_vc12:1; + /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_crc_vc13:1; + /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_crc_vc14:1; + /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_pld_crc_fatal_reg_t; + +/** Type of int_msk_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc0:1; + /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc1:1; + /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc2:1; + /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc3:1; + /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc4:1; + /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc5:1; + /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc6:1; + /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc7:1; + /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc8:1; + /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc9:1; + /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc10:1; + /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc11:1; + /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc12:1; + /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc13:1; + /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc14:1; + /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_pld_crc_fatal_reg_t; + +/** Type of int_force_pld_crc_fatal register + * NA + */ +typedef union { + struct { + /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_crc_vc0:1; + /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_crc_vc1:1; + /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_crc_vc2:1; + /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_crc_vc3:1; + /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_crc_vc4:1; + /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_crc_vc5:1; + /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_crc_vc6:1; + /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_crc_vc7:1; + /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_crc_vc8:1; + /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_crc_vc9:1; + /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_crc_vc10:1; + /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_crc_vc11:1; + /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_crc_vc12:1; + /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_crc_vc13:1; + /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_crc_vc14:1; + /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_crc_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_pld_crc_fatal_reg_t; + +/** Type of int_st_data_id register + * NA + */ +typedef union { + struct { + /** st_err_id_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_id_vc0:1; + /** st_err_id_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_id_vc1:1; + /** st_err_id_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_id_vc2:1; + /** st_err_id_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_id_vc3:1; + /** st_err_id_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_id_vc4:1; + /** st_err_id_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_id_vc5:1; + /** st_err_id_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_id_vc6:1; + /** st_err_id_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_id_vc7:1; + /** st_err_id_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_id_vc8:1; + /** st_err_id_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_id_vc9:1; + /** st_err_id_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_id_vc10:1; + /** st_err_id_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_id_vc11:1; + /** st_err_id_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_id_vc12:1; + /** st_err_id_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_id_vc13:1; + /** st_err_id_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_id_vc14:1; + /** st_err_id_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_data_id_reg_t; + +/** Type of int_msk_data_id register + * NA + */ +typedef union { + struct { + /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_id_vc0:1; + /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_id_vc1:1; + /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_id_vc2:1; + /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_id_vc3:1; + /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_id_vc4:1; + /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_id_vc5:1; + /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_id_vc6:1; + /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_id_vc7:1; + /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_id_vc8:1; + /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_id_vc9:1; + /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_id_vc10:1; + /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_id_vc11:1; + /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_id_vc12:1; + /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_id_vc13:1; + /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_id_vc14:1; + /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_data_id_reg_t; + +/** Type of int_force_data_id register + * NA + */ +typedef union { + struct { + /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_id_vc0:1; + /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_id_vc1:1; + /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_id_vc2:1; + /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_id_vc3:1; + /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_id_vc4:1; + /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_id_vc5:1; + /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_id_vc6:1; + /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_id_vc7:1; + /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_id_vc8:1; + /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_id_vc9:1; + /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_id_vc10:1; + /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_id_vc11:1; + /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_id_vc12:1; + /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_id_vc13:1; + /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_id_vc14:1; + /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_id_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_data_id_reg_t; + +/** Type of int_st_ecc_corrected register + * NA + */ +typedef union { + struct { + /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc0:1; + /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc1:1; + /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc2:1; + /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc3:1; + /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc4:1; + /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc5:1; + /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc6:1; + /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc7:1; + /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc8:1; + /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc9:1; + /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc10:1; + /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc11:1; + /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc12:1; + /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc13:1; + /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc14:1; + /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0; + * NA + */ + uint32_t st_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_st_ecc_corrected_reg_t; + +/** Type of int_msk_ecc_corrected register + * NA + */ +typedef union { + struct { + /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc0:1; + /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc1:1; + /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc2:1; + /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc3:1; + /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc4:1; + /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc5:1; + /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc6:1; + /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc7:1; + /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc8:1; + /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc9:1; + /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc10:1; + /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc11:1; + /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc12:1; + /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc13:1; + /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc14:1; + /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_msk_ecc_corrected_reg_t; + +/** Type of int_force_ecc_corrected register + * NA + */ +typedef union { + struct { + /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc0:1; + /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc1:1; + /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc2:1; + /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc3:1; + /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc4:1; + /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc5:1; + /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc6:1; + /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc7:1; + /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc8:1; + /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc9:1; + /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc10:1; + /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc11:1; + /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc12:1; + /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc13:1; + /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc14:1; + /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_err_ecc_corrected_vc15:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_host_int_force_ecc_corrected_reg_t; + + +/** Group: Status Registers */ +/** Type of phy_stopstate register + * NA + */ +typedef union { + struct { + /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_stopstatedata_0:1; + /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_stopstatedata_1:1; + uint32_t reserved_2:14; + /** phy_stopstateclk : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_stopstateclk:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_host_phy_stopstate_reg_t; + + +typedef struct csi_host_dev_t { + volatile csi_host_version_reg_t version; + volatile csi_host_n_lanes_reg_t n_lanes; + volatile csi_host_csi2_resetn_reg_t csi2_resetn; + volatile csi_host_int_st_main_reg_t int_st_main; + uint32_t reserved_010[12]; + volatile csi_host_phy_shutdownz_reg_t phy_shutdownz; + volatile csi_host_dphy_rstz_reg_t dphy_rstz; + volatile csi_host_phy_rx_reg_t phy_rx; + volatile csi_host_phy_stopstate_reg_t phy_stopstate; + volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0; + volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1; + uint32_t reserved_058[28]; + volatile csi_host_vc_extension_reg_t vc_extension; + volatile csi_host_phy_cal_reg_t phy_cal; + uint32_t reserved_0d0[4]; + volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal; + volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal; + volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal; + uint32_t reserved_0ec; + volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal; + volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal; + volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal; + uint32_t reserved_0fc[5]; + volatile csi_host_int_st_phy_reg_t int_st_phy; + volatile csi_host_int_msk_phy_reg_t int_msk_phy; + volatile csi_host_int_force_phy_reg_t int_force_phy; + uint32_t reserved_11c[89]; + volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal; + volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal; + volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal; + uint32_t reserved_28c; + volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal; + volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal; + volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal; + uint32_t reserved_29c; + volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal; + volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal; + volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal; + uint32_t reserved_2ac; + volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal; + volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal; + volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal; + uint32_t reserved_2bc; + volatile csi_host_int_st_data_id_reg_t int_st_data_id; + volatile csi_host_int_msk_data_id_reg_t int_msk_data_id; + volatile csi_host_int_force_data_id_reg_t int_force_data_id; + uint32_t reserved_2cc; + volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected; + volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected; + volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected; + uint32_t reserved_2dc[9]; + volatile csi_host_scrambling_reg_t scrambling; + volatile csi_host_scrambling_seed1_reg_t scrambling_seed1; + volatile csi_host_scrambling_seed2_reg_t scrambling_seed2; +} csi_host_dev_t; + +extern csi_host_dev_t MIPI_CSI_HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h new file mode 100644 index 0000000000..f2f78f4ec9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h @@ -0,0 +1,868 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of clk_en register + * dsi bridge clk control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * this bit configures force_on of dsi_bridge register clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_clk_en_reg_t; + +/** Type of en register + * dsi bridge en register + */ +typedef union { + struct { + /** dsi_en : R/W; bitpos: [0]; default: 0; + * this bit configures module enable of dsi_bridge. 0: disable, 1: enable + */ + uint32_t dsi_en:1; + /** dsi_brig_rst : R/W; bitpos: [1]; default: 0; + * Configures software reset of dsi_bridge. 0: release reset, 1: reset + */ + uint32_t dsi_brig_rst:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_en_reg_t; + +/** Type of dma_req_cfg register + * dsi bridge dma burst len register + */ +typedef union { + struct { + /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; + * this field configures the num of 64-bit in one dma burst transfer, valid only when + * dsi_bridge as flow controller + */ + uint32_t dma_burst_len:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_brg_dma_req_cfg_reg_t; + +/** Type of raw_num_cfg register + * dsi bridge raw number control register + */ +typedef union { + struct { + /** raw_num_total : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total pix bits/64 + */ + uint32_t raw_num_total:22; + /** unalign_64bit_en : R/W; bitpos: [22]; default: 0; + * this field configures whether the total pix bits is a multiple of 64bits. 0: align + * to 64-bit, 1: unalign to 64-bit + */ + uint32_t unalign_64bit_en:1; + uint32_t reserved_23:8; + /** raw_num_total_set : WT; bitpos: [31]; default: 0; + * this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, + * 1: enable. valid only when dsi_bridge as flow controller + */ + uint32_t raw_num_total_set:1; + }; + uint32_t val; +} dsi_brg_raw_num_cfg_reg_t; + +/** Type of raw_buf_credit_ctl register + * dsi bridge credit register + */ +typedef union { + struct { + /** credit_thrd : R/W; bitpos: [14:0]; default: 1024; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * 64-bit, valid only when dsi_bridge as flow controller + */ + uint32_t credit_thrd:15; + uint32_t reserved_15:1; + /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * dma burst, valid only when dsi_bridge as flow controller + */ + uint32_t credit_burst_thrd:15; + /** credit_reset : R/W; bitpos: [31]; default: 0; + * this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when + * dsi_bridge as flow controller + */ + uint32_t credit_reset:1; + }; + uint32_t val; +} dsi_brg_raw_buf_credit_ctl_reg_t; + +/** Type of pixel_type register + * dsi bridge dpi type control register + */ +typedef union { + struct { + /** raw_type : R/W; bitpos: [3:0]; default: 0; + * this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444, + * 9:yuv422, 10:yuv420, 12:gray + */ + uint32_t raw_type:4; + /** dpi_config : R/W; bitpos: [5:4]; default: 0; + * this field configures the pixel arrange type of dpi interface + */ + uint32_t dpi_config:2; + /** data_in_type : R/W; bitpos: [6]; default: 0; + * input data type, 0: not yuv, 1: yuv + */ + uint32_t data_in_type:1; + /** dpi_type : R/W; bitpos: [10:7]; default: 0; + * this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + */ + uint32_t dpi_type:4; + uint32_t reserved_11:21; + }; + uint32_t val; +} dsi_brg_pixel_type_reg_t; + +/** Type of dma_block_interval register + * dsi bridge dma block interval control register + */ +typedef union { + struct { + /** dma_block_slot : R/W; bitpos: [9:0]; default: 9; + * this field configures the max block_slot_cnt + */ + uint32_t dma_block_slot:10; + /** dma_block_interval : R/W; bitpos: [27:10]; default: 9; + * this field configures the max block_interval_cnt, block_interval_cnt increased by 1 + * when block_slot_cnt if full + */ + uint32_t dma_block_interval:18; + /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1; + * this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + */ + uint32_t raw_num_total_auto_reload:1; + /** dma_block_interval_en : R/W; bitpos: [29]; default: 1; + * this bit configures enable of interval between dma block transfer, 0: disable, 1: + * enable + */ + uint32_t dma_block_interval_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} dsi_brg_dma_block_interval_reg_t; + +/** Type of dma_req_interval register + * dsi bridge dma req interval control register + */ +typedef union { + struct { + /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; + * this field configures the interval between dma req events + */ + uint32_t dma_req_interval:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_brg_dma_req_interval_reg_t; + +/** Type of dpi_lcd_ctl register + * dsi bridge dpi signal control register + */ +typedef union { + struct { + /** dpishutdn : R/W; bitpos: [0]; default: 0; + * this bit configures dpishutdn signal in dpi interface + */ + uint32_t dpishutdn:1; + /** dpicolorm : R/W; bitpos: [1]; default: 0; + * this bit configures dpicolorm signal in dpi interface + */ + uint32_t dpicolorm:1; + /** dpiupdatecfg : R/W; bitpos: [2]; default: 0; + * this bit configures dpiupdatecfg signal in dpi interface + */ + uint32_t dpiupdatecfg:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} dsi_brg_dpi_lcd_ctl_reg_t; + +/** Type of dpi_rsv_dpi_data register + * dsi bridge dpi reserved data register + */ +typedef union { + struct { + /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383; + * this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + */ + uint32_t dpi_rsv_data:30; + /** dpi_dbg_en : R/W; bitpos: [30]; default: 0; + * Configures data debug feature enable. 0: disable, 1: enable + */ + uint32_t dpi_dbg_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} dsi_brg_dpi_rsv_dpi_data_reg_t; + +/** Type of dpi_v_cfg0 register + * dsi bridge dpi v config register 0 + */ +typedef union { + struct { + /** vtotal : R/W; bitpos: [11:0]; default: 525; + * this field configures the total length of one frame (by line) for dpi output, must + * meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + */ + uint32_t vtotal:12; + uint32_t reserved_12:4; + /** vdisp : R/W; bitpos: [27:16]; default: 480; + * this field configures the length of valid line (by line) for dpi output + */ + uint32_t vdisp:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_v_cfg0_reg_t; + +/** Type of dpi_v_cfg1 register + * dsi bridge dpi v config register 1 + */ +typedef union { + struct { + /** vbank : R/W; bitpos: [11:0]; default: 33; + * this field configures the length between vsync and valid line (by line) for dpi + * output + */ + uint32_t vbank:12; + uint32_t reserved_12:4; + /** vsync : R/W; bitpos: [27:16]; default: 2; + * this field configures the length of vsync (by line) for dpi output + */ + uint32_t vsync:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_v_cfg1_reg_t; + +/** Type of dpi_h_cfg0 register + * dsi bridge dpi h config register 0 + */ +typedef union { + struct { + /** htotal : R/W; bitpos: [11:0]; default: 800; + * this field configures the total length of one line (by pixel num) for dpi output, + * must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + */ + uint32_t htotal:12; + uint32_t reserved_12:4; + /** hdisp : R/W; bitpos: [27:16]; default: 640; + * this field configures the length of valid pixel data (by pixel num) for dpi output + */ + uint32_t hdisp:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_h_cfg0_reg_t; + +/** Type of dpi_h_cfg1 register + * dsi bridge dpi h config register 1 + */ +typedef union { + struct { + /** hbank : R/W; bitpos: [11:0]; default: 48; + * this field configures the length between hsync and pixel data valid (by pixel num) + * for dpi output + */ + uint32_t hbank:12; + uint32_t reserved_12:4; + /** hsync : R/W; bitpos: [27:16]; default: 96; + * this field configures the length of hsync (by pixel num) for dpi output + */ + uint32_t hsync:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_h_cfg1_reg_t; + +/** Type of dpi_misc_config register + * dsi_bridge dpi misc config register + */ +typedef union { + struct { + /** dpi_en : R/W; bitpos: [0]; default: 0; + * this bit configures enable of dpi output, 0: disable, 1: enable + */ + uint32_t dpi_en:1; + uint32_t reserved_1:3; + /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413; + * this field configures the underrun interrupt musk, when underrun occurs and line + * cnt is less then this field + */ + uint32_t fifo_underrun_discard_vcnt:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_brg_dpi_misc_config_reg_t; + +/** Type of dpi_config_update register + * dsi_bridge dpi config update register + */ +typedef union { + struct { + /** dpi_config_update : WT; bitpos: [0]; default: 0; + * write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + */ + uint32_t dpi_config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_dpi_config_update_reg_t; + +/** Type of host_trigger_rev register + * dsi_bridge host trigger reverse control register + */ +typedef union { + struct { + /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0; + * tx_trigger reverse. 0: disable, 1: enable + */ + uint32_t tx_trigger_rev_en:1; + /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0; + * rx_trigger reverse. 0: disable, 1: enable + */ + uint32_t rx_trigger_rev_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_host_trigger_rev_reg_t; + +/** Type of blk_raw_num_cfg register + * dsi_bridge block raw number control register + */ +typedef union { + struct { + /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total block pix bits/64 + */ + uint32_t blk_raw_num_total:22; + uint32_t reserved_22:9; + /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0; + * write 1 to reload reg_blk_raw_num_total to internal cnt + */ + uint32_t blk_raw_num_total_set:1; + }; + uint32_t val; +} dsi_brg_blk_raw_num_cfg_reg_t; + +/** Type of dma_frame_interval register + * dsi_bridge dam frame interval control register + */ +typedef union { + struct { + /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9; + * this field configures the max frame_slot_cnt + */ + uint32_t dma_frame_slot:10; + /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9; + * this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 + * when frame_slot_cnt if full + */ + uint32_t dma_frame_interval:18; + /** dma_multiblk_en : R/W; bitpos: [28]; default: 0; + * this bit configures enable multi-blk transfer, 0: disable, 1: enable + */ + uint32_t dma_multiblk_en:1; + /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1; + * this bit configures enable interval between frame transfer, 0: disable, 1: enable + */ + uint32_t dma_frame_interval_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} dsi_brg_dma_frame_interval_reg_t; + +/** Type of mem_aux_ctrl register + * dsi_bridge mem aux control register + */ +typedef union { + struct { + /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures dsi_bridge fifo memory aux ctrl + */ + uint32_t dsi_mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_brg_mem_aux_ctrl_reg_t; + +/** Type of rdn_eco_low register + * dsi_bridge rdn eco all low register + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} dsi_brg_rdn_eco_low_reg_t; + +/** Type of rdn_eco_high register + * dsi_bridge rdn eco all high register + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} dsi_brg_rdn_eco_high_reg_t; + +/** Type of host_ctrl register + * dsi_bridge host control register + */ +typedef union { + struct { + /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1; + * this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: + * enable + */ + uint32_t dsi_cfg_ref_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_host_ctrl_reg_t; + +/** Type of mem_clk_ctrl register + * dsi_bridge mem force on control register + */ +typedef union { + struct { + /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0; + * this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: + * force on + */ + uint32_t dsi_bridge_mem_clk_force_on:1; + /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + */ + uint32_t dsi_mem_clk_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_mem_clk_ctrl_reg_t; + +/** Type of dma_flow_ctrl register + * dsi_bridge dma flow controller register + */ +typedef union { + struct { + /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1; + * this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge + * as flow controller + */ + uint32_t dsi_dma_flow_controller:1; + uint32_t reserved_1:3; + /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1; + * this field configures the num of blocks when multi-blk is enable and dmac as flow + * controller + */ + uint32_t dma_flow_multiblk_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} dsi_brg_dma_flow_ctrl_reg_t; + +/** Type of raw_buf_almost_empty_thrd register + * dsi_bridge buffer empty threshold register + */ +typedef union { + struct { + /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512; + * this field configures the fifo almost empty threshold, is valid only when dmac as + * flow controller + */ + uint32_t dsi_raw_buf_almost_empty_thrd:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} dsi_brg_raw_buf_almost_empty_thrd_reg_t; + +/** Type of yuv_cfg register + * dsi_bridge yuv format config register + */ +typedef union { + struct { + /** protocol : R/W; bitpos: [0]; default: 0; + * this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + */ + uint32_t protocol:1; + /** yuv_pix_endian : R/W; bitpos: [1]; default: 0; + * this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + */ + uint32_t yuv_pix_endian:1; + /** yuv422_format : R/W; bitpos: [3:2]; default: 0; + * this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + */ + uint32_t yuv422_format:2; + /** yuv_range : R/W; bitpos: [4]; default: 0; + * Configures yuv pixel range, 0: limit range, 1: full range + */ + uint32_t yuv_range:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} dsi_brg_yuv_cfg_reg_t; + +/** Type of phy_lp_loopback_ctrl register + * dsi phy lp_loopback test ctrl + */ +typedef union { + struct { + /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0; + * txdataesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txdataesc_1:8; + /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0; + * txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txrequestesc_1:1; + /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0; + * txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txvalidesc_1:1; + /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0; + * txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txlpdtesc_1:1; + /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0; + * basedir_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_basedir_1:1; + uint32_t reserved_12:4; + /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0; + * txdataesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txdataesc_0:8; + /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0; + * txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txrequestesc_0:1; + /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0; + * txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txvalidesc_0:1; + /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0; + * txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txlpdtesc_0:1; + /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0; + * basedir_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_basedir_0:1; + /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0; + * dsi phy lp_loopback test start check + */ + uint32_t phy_lp_loopback_check:1; + /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0; + * dsi phy lp_loopback test check done + */ + uint32_t phy_lp_loopback_check_done:1; + /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0; + * dsi phy lp_loopback ctrl en + */ + uint32_t phy_lp_loopback_en:1; + /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0; + * result of dsi phy lp_loopback test + */ + uint32_t phy_lp_loopback_ok:1; + }; + uint32_t val; +} dsi_brg_phy_lp_loopback_ctrl_reg_t; + +/** Type of phy_hs_loopback_ctrl register + * dsi phy hp_loopback test ctrl + */ +typedef union { + struct { + /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0; + * txdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txdatahs_1:8; + /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0; + * txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequestdatahs_1:1; + /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1; + * basedir_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_basedir_1:1; + uint32_t reserved_10:6; + /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0; + * txdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txdatahs_0:8; + /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0; + * txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequestdatahs_0:1; + /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0; + * basedir_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_basedir_0:1; + uint32_t reserved_26:1; + /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0; + * txrequesthsclk when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequesthsclk:1; + /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0; + * dsi phy hs_loopback test start check + */ + uint32_t phy_hs_loopback_check:1; + /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0; + * dsi phy hs_loopback test check done + */ + uint32_t phy_hs_loopback_check_done:1; + /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0; + * dsi phy hs_loopback ctrl en + */ + uint32_t phy_hs_loopback_en:1; + /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0; + * result of dsi phy hs_loopback test + */ + uint32_t phy_hs_loopback_ok:1; + }; + uint32_t val; +} dsi_brg_phy_hs_loopback_ctrl_reg_t; + +/** Type of phy_loopback_cnt register + * loopback test cnt + */ +typedef union { + struct { + /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64; + * hs_loopback test check cnt + */ + uint32_t phy_hs_check_cnt_th:8; + uint32_t reserved_8:8; + /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64; + * lp_loopback test check cnt + */ + uint32_t phy_lp_check_cnt_th:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_brg_phy_loopback_cnt_reg_t; + + +/** Group: Status Registers */ +/** Type of fifo_flow_status register + * dsi bridge raw buffer depth register + */ +typedef union { + struct { + /** raw_buf_depth : RO; bitpos: [13:0]; default: 0; + * this field configures the depth of dsi_bridge fifo depth + */ + uint32_t raw_buf_depth:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_brg_fifo_flow_status_reg_t; + +/** Type of host_bist_ctl register + * dsi_bridge host bist control register + */ +typedef union { + struct { + /** bistok : RO; bitpos: [0]; default: 0; + * bistok + */ + uint32_t bistok:1; + /** biston : R/W; bitpos: [1]; default: 0; + * biston + */ + uint32_t biston:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_host_bist_ctl_reg_t; + +/** Type of rdn_eco_cs register + * dsi_bridge rdn eco cs register + */ +typedef union { + struct { + /** rdn_eco_en : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ + uint32_t rdn_eco_en:1; + /** rdn_eco_result : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ + uint32_t rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_rdn_eco_cs_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_ena register + * dsi_bridge interrupt enable register + */ +typedef union { + struct { + /** underrun_int_ena : R/W; bitpos: [0]; default: 0; + * write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled + * by dpi_underrun interrupt signal + */ + uint32_t underrun_int_ena:1; + /** vsync_int_ena : R/W; bitpos: [1]; default: 0; + * write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by + * dpi_vsync interrupt signal + */ + uint32_t vsync_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_int_ena_reg_t; + +/** Type of int_clr register + * dsi_bridge interrupt clear register + */ +typedef union { + struct { + /** underrun_int_clr : WT; bitpos: [0]; default: 0; + * write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ + uint32_t underrun_int_clr:1; + /** vsync_int_clr : WT; bitpos: [1]; default: 0; + * write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ + uint32_t vsync_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_int_clr_reg_t; + +/** Type of int_raw register + * dsi_bridge raw interrupt register + */ +typedef union { + struct { + /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * the raw interrupt status of dpi_underrun + */ + uint32_t underrun_int_raw:1; + /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * the raw interrupt status of dpi_vsync + */ + uint32_t vsync_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_int_raw_reg_t; + +/** Type of int_st register + * dsi_bridge masked interrupt register + */ +typedef union { + struct { + /** underrun_int_st : RO; bitpos: [0]; default: 0; + * the masked interrupt status of dpi_underrun + */ + uint32_t underrun_int_st:1; + /** vsync_int_st : RO; bitpos: [1]; default: 0; + * the masked interrupt status of dpi_vsync + */ + uint32_t vsync_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of ver_date register + * version control register + */ +typedef union { + struct { + /** ver_data : R/W; bitpos: [31:0]; default: 539296009; + * Represents csv version + */ + uint32_t ver_data:32; + }; + uint32_t val; +} dsi_brg_ver_date_reg_t; + + +typedef struct { + volatile dsi_brg_clk_en_reg_t clk_en; + volatile dsi_brg_en_reg_t en; + volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg; + volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg; + volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl; + volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status; + volatile dsi_brg_pixel_type_reg_t pixel_type; + volatile dsi_brg_dma_block_interval_reg_t dma_block_interval; + volatile dsi_brg_dma_req_interval_reg_t dma_req_interval; + volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl; + volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data; + uint32_t reserved_02c; + volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0; + volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1; + volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0; + volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1; + volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config; + volatile dsi_brg_dpi_config_update_reg_t dpi_config_update; + uint32_t reserved_048[2]; + volatile dsi_brg_int_ena_reg_t int_ena; + volatile dsi_brg_int_clr_reg_t int_clr; + volatile dsi_brg_int_raw_reg_t int_raw; + volatile dsi_brg_int_st_reg_t int_st; + volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl; + volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev; + volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg; + volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval; + volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl; + volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs; + volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low; + volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high; + volatile dsi_brg_host_ctrl_reg_t host_ctrl; + volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl; + volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl; + volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd; + volatile dsi_brg_yuv_cfg_reg_t yuv_cfg; + volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl; + volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl; + volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt; + uint32_t reserved_0a0[24]; + volatile dsi_brg_ver_date_reg_t ver_date; +} dsi_brg_dev_t; + +extern dsi_brg_dev_t MIPI_DSI_BRIDGE; + +#ifndef __cplusplus +_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_reg.h new file mode 100644 index 0000000000..b63d11181d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_reg.h @@ -0,0 +1,907 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DSI_BRG_CLK_EN_REG register + * dsi bridge clk control register + */ +#define DSI_BRG_CLK_EN_REG (DR_REG_DSI_BRG_BASE + 0x0) +/** DSI_BRG_CLK_EN : R/W; bitpos: [0]; default: 0; + * this bit configures force_on of dsi_bridge register clock gate + */ +#define DSI_BRG_CLK_EN (BIT(0)) +#define DSI_BRG_CLK_EN_M (DSI_BRG_CLK_EN_V << DSI_BRG_CLK_EN_S) +#define DSI_BRG_CLK_EN_V 0x00000001U +#define DSI_BRG_CLK_EN_S 0 + +/** DSI_BRG_EN_REG register + * dsi bridge en register + */ +#define DSI_BRG_EN_REG (DR_REG_DSI_BRG_BASE + 0x4) +/** DSI_BRG_DSI_EN : R/W; bitpos: [0]; default: 0; + * this bit configures module enable of dsi_bridge. 0: disable, 1: enable + */ +#define DSI_BRG_DSI_EN (BIT(0)) +#define DSI_BRG_DSI_EN_M (DSI_BRG_DSI_EN_V << DSI_BRG_DSI_EN_S) +#define DSI_BRG_DSI_EN_V 0x00000001U +#define DSI_BRG_DSI_EN_S 0 +/** DSI_BRG_DSI_BRIG_RST : R/W; bitpos: [1]; default: 0; + * Configures software reset of dsi_bridge. 0: release reset, 1: reset + */ +#define DSI_BRG_DSI_BRIG_RST (BIT(1)) +#define DSI_BRG_DSI_BRIG_RST_M (DSI_BRG_DSI_BRIG_RST_V << DSI_BRG_DSI_BRIG_RST_S) +#define DSI_BRG_DSI_BRIG_RST_V 0x00000001U +#define DSI_BRG_DSI_BRIG_RST_S 1 + +/** DSI_BRG_DMA_REQ_CFG_REG register + * dsi bridge dma burst len register + */ +#define DSI_BRG_DMA_REQ_CFG_REG (DR_REG_DSI_BRG_BASE + 0x8) +/** DSI_BRG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128; + * this field configures the num of 64-bit in one dma burst transfer, valid only when + * dsi_bridge as flow controller + */ +#define DSI_BRG_DMA_BURST_LEN 0x00000FFFU +#define DSI_BRG_DMA_BURST_LEN_M (DSI_BRG_DMA_BURST_LEN_V << DSI_BRG_DMA_BURST_LEN_S) +#define DSI_BRG_DMA_BURST_LEN_V 0x00000FFFU +#define DSI_BRG_DMA_BURST_LEN_S 0 + +/** DSI_BRG_RAW_NUM_CFG_REG register + * dsi bridge raw number control register + */ +#define DSI_BRG_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0xc) +/** DSI_BRG_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total pix bits/64 + */ +#define DSI_BRG_RAW_NUM_TOTAL 0x003FFFFFU +#define DSI_BRG_RAW_NUM_TOTAL_M (DSI_BRG_RAW_NUM_TOTAL_V << DSI_BRG_RAW_NUM_TOTAL_S) +#define DSI_BRG_RAW_NUM_TOTAL_V 0x003FFFFFU +#define DSI_BRG_RAW_NUM_TOTAL_S 0 +/** DSI_BRG_UNALIGN_64BIT_EN : R/W; bitpos: [22]; default: 0; + * this field configures whether the total pix bits is a multiple of 64bits. 0: align + * to 64-bit, 1: unalign to 64-bit + */ +#define DSI_BRG_UNALIGN_64BIT_EN (BIT(22)) +#define DSI_BRG_UNALIGN_64BIT_EN_M (DSI_BRG_UNALIGN_64BIT_EN_V << DSI_BRG_UNALIGN_64BIT_EN_S) +#define DSI_BRG_UNALIGN_64BIT_EN_V 0x00000001U +#define DSI_BRG_UNALIGN_64BIT_EN_S 22 +/** DSI_BRG_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0; + * this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, + * 1: enable. valid only when dsi_bridge as flow controller + */ +#define DSI_BRG_RAW_NUM_TOTAL_SET (BIT(31)) +#define DSI_BRG_RAW_NUM_TOTAL_SET_M (DSI_BRG_RAW_NUM_TOTAL_SET_V << DSI_BRG_RAW_NUM_TOTAL_SET_S) +#define DSI_BRG_RAW_NUM_TOTAL_SET_V 0x00000001U +#define DSI_BRG_RAW_NUM_TOTAL_SET_S 31 + +/** DSI_BRG_RAW_BUF_CREDIT_CTL_REG register + * dsi bridge credit register + */ +#define DSI_BRG_RAW_BUF_CREDIT_CTL_REG (DR_REG_DSI_BRG_BASE + 0x10) +/** DSI_BRG_CREDIT_THRD : R/W; bitpos: [14:0]; default: 1024; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * 64-bit, valid only when dsi_bridge as flow controller + */ +#define DSI_BRG_CREDIT_THRD 0x00007FFFU +#define DSI_BRG_CREDIT_THRD_M (DSI_BRG_CREDIT_THRD_V << DSI_BRG_CREDIT_THRD_S) +#define DSI_BRG_CREDIT_THRD_V 0x00007FFFU +#define DSI_BRG_CREDIT_THRD_S 0 +/** DSI_BRG_CREDIT_BURST_THRD : R/W; bitpos: [30:16]; default: 800; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * dma burst, valid only when dsi_bridge as flow controller + */ +#define DSI_BRG_CREDIT_BURST_THRD 0x00007FFFU +#define DSI_BRG_CREDIT_BURST_THRD_M (DSI_BRG_CREDIT_BURST_THRD_V << DSI_BRG_CREDIT_BURST_THRD_S) +#define DSI_BRG_CREDIT_BURST_THRD_V 0x00007FFFU +#define DSI_BRG_CREDIT_BURST_THRD_S 16 +/** DSI_BRG_CREDIT_RESET : R/W; bitpos: [31]; default: 0; + * this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when + * dsi_bridge as flow controller + */ +#define DSI_BRG_CREDIT_RESET (BIT(31)) +#define DSI_BRG_CREDIT_RESET_M (DSI_BRG_CREDIT_RESET_V << DSI_BRG_CREDIT_RESET_S) +#define DSI_BRG_CREDIT_RESET_V 0x00000001U +#define DSI_BRG_CREDIT_RESET_S 31 + +/** DSI_BRG_FIFO_FLOW_STATUS_REG register + * dsi bridge raw buffer depth register + */ +#define DSI_BRG_FIFO_FLOW_STATUS_REG (DR_REG_DSI_BRG_BASE + 0x14) +/** DSI_BRG_RAW_BUF_DEPTH : RO; bitpos: [13:0]; default: 0; + * this field configures the depth of dsi_bridge fifo depth + */ +#define DSI_BRG_RAW_BUF_DEPTH 0x00003FFFU +#define DSI_BRG_RAW_BUF_DEPTH_M (DSI_BRG_RAW_BUF_DEPTH_V << DSI_BRG_RAW_BUF_DEPTH_S) +#define DSI_BRG_RAW_BUF_DEPTH_V 0x00003FFFU +#define DSI_BRG_RAW_BUF_DEPTH_S 0 + +/** DSI_BRG_PIXEL_TYPE_REG register + * dsi bridge dpi type control register + */ +#define DSI_BRG_PIXEL_TYPE_REG (DR_REG_DSI_BRG_BASE + 0x18) +/** DSI_BRG_RAW_TYPE : R/W; bitpos: [3:0]; default: 0; + * this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444, + * 9:yuv422, 10:yuv420, 12:gray + */ +#define DSI_BRG_RAW_TYPE 0x0000000FU +#define DSI_BRG_RAW_TYPE_M (DSI_BRG_RAW_TYPE_V << DSI_BRG_RAW_TYPE_S) +#define DSI_BRG_RAW_TYPE_V 0x0000000FU +#define DSI_BRG_RAW_TYPE_S 0 +/** DSI_BRG_DPI_CONFIG : R/W; bitpos: [5:4]; default: 0; + * this field configures the pixel arrange type of dpi interface + */ +#define DSI_BRG_DPI_CONFIG 0x00000003U +#define DSI_BRG_DPI_CONFIG_M (DSI_BRG_DPI_CONFIG_V << DSI_BRG_DPI_CONFIG_S) +#define DSI_BRG_DPI_CONFIG_V 0x00000003U +#define DSI_BRG_DPI_CONFIG_S 4 +/** DSI_BRG_DATA_IN_TYPE : R/W; bitpos: [6]; default: 0; + * input data type, 0: not yuv, 1: yuv + */ +#define DSI_BRG_DATA_IN_TYPE (BIT(6)) +#define DSI_BRG_DATA_IN_TYPE_M (DSI_BRG_DATA_IN_TYPE_V << DSI_BRG_DATA_IN_TYPE_S) +#define DSI_BRG_DATA_IN_TYPE_V 0x00000001U +#define DSI_BRG_DATA_IN_TYPE_S 6 +/** DSI_BRG_DPI_TYPE : R/W; bitpos: [10:7]; default: 0; + * this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + */ +#define DSI_BRG_DPI_TYPE 0x0000000FU +#define DSI_BRG_DPI_TYPE_M (DSI_BRG_DPI_TYPE_V << DSI_BRG_DPI_TYPE_S) +#define DSI_BRG_DPI_TYPE_V 0x0000000FU +#define DSI_BRG_DPI_TYPE_S 7 + +/** DSI_BRG_DMA_BLOCK_INTERVAL_REG register + * dsi bridge dma block interval control register + */ +#define DSI_BRG_DMA_BLOCK_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x1c) +/** DSI_BRG_DMA_BLOCK_SLOT : R/W; bitpos: [9:0]; default: 9; + * this field configures the max block_slot_cnt + */ +#define DSI_BRG_DMA_BLOCK_SLOT 0x000003FFU +#define DSI_BRG_DMA_BLOCK_SLOT_M (DSI_BRG_DMA_BLOCK_SLOT_V << DSI_BRG_DMA_BLOCK_SLOT_S) +#define DSI_BRG_DMA_BLOCK_SLOT_V 0x000003FFU +#define DSI_BRG_DMA_BLOCK_SLOT_S 0 +/** DSI_BRG_DMA_BLOCK_INTERVAL : R/W; bitpos: [27:10]; default: 9; + * this field configures the max block_interval_cnt, block_interval_cnt increased by 1 + * when block_slot_cnt if full + */ +#define DSI_BRG_DMA_BLOCK_INTERVAL 0x0003FFFFU +#define DSI_BRG_DMA_BLOCK_INTERVAL_M (DSI_BRG_DMA_BLOCK_INTERVAL_V << DSI_BRG_DMA_BLOCK_INTERVAL_S) +#define DSI_BRG_DMA_BLOCK_INTERVAL_V 0x0003FFFFU +#define DSI_BRG_DMA_BLOCK_INTERVAL_S 10 +/** DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD : R/W; bitpos: [28]; default: 1; + * this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + */ +#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD (BIT(28)) +#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_M (DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V << DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S) +#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V 0x00000001U +#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S 28 +/** DSI_BRG_DMA_BLOCK_INTERVAL_EN : R/W; bitpos: [29]; default: 1; + * this bit configures enable of interval between dma block transfer, 0: disable, 1: + * enable + */ +#define DSI_BRG_DMA_BLOCK_INTERVAL_EN (BIT(29)) +#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_M (DSI_BRG_DMA_BLOCK_INTERVAL_EN_V << DSI_BRG_DMA_BLOCK_INTERVAL_EN_S) +#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_V 0x00000001U +#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_S 29 + +/** DSI_BRG_DMA_REQ_INTERVAL_REG register + * dsi bridge dma req interval control register + */ +#define DSI_BRG_DMA_REQ_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x20) +/** DSI_BRG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1; + * this field configures the interval between dma req events + */ +#define DSI_BRG_DMA_REQ_INTERVAL 0x0000FFFFU +#define DSI_BRG_DMA_REQ_INTERVAL_M (DSI_BRG_DMA_REQ_INTERVAL_V << DSI_BRG_DMA_REQ_INTERVAL_S) +#define DSI_BRG_DMA_REQ_INTERVAL_V 0x0000FFFFU +#define DSI_BRG_DMA_REQ_INTERVAL_S 0 + +/** DSI_BRG_DPI_LCD_CTL_REG register + * dsi bridge dpi signal control register + */ +#define DSI_BRG_DPI_LCD_CTL_REG (DR_REG_DSI_BRG_BASE + 0x24) +/** DSI_BRG_DPISHUTDN : R/W; bitpos: [0]; default: 0; + * this bit configures dpishutdn signal in dpi interface + */ +#define DSI_BRG_DPISHUTDN (BIT(0)) +#define DSI_BRG_DPISHUTDN_M (DSI_BRG_DPISHUTDN_V << DSI_BRG_DPISHUTDN_S) +#define DSI_BRG_DPISHUTDN_V 0x00000001U +#define DSI_BRG_DPISHUTDN_S 0 +/** DSI_BRG_DPICOLORM : R/W; bitpos: [1]; default: 0; + * this bit configures dpicolorm signal in dpi interface + */ +#define DSI_BRG_DPICOLORM (BIT(1)) +#define DSI_BRG_DPICOLORM_M (DSI_BRG_DPICOLORM_V << DSI_BRG_DPICOLORM_S) +#define DSI_BRG_DPICOLORM_V 0x00000001U +#define DSI_BRG_DPICOLORM_S 1 +/** DSI_BRG_DPIUPDATECFG : R/W; bitpos: [2]; default: 0; + * this bit configures dpiupdatecfg signal in dpi interface + */ +#define DSI_BRG_DPIUPDATECFG (BIT(2)) +#define DSI_BRG_DPIUPDATECFG_M (DSI_BRG_DPIUPDATECFG_V << DSI_BRG_DPIUPDATECFG_S) +#define DSI_BRG_DPIUPDATECFG_V 0x00000001U +#define DSI_BRG_DPIUPDATECFG_S 2 + +/** DSI_BRG_DPI_RSV_DPI_DATA_REG register + * dsi bridge dpi reserved data register + */ +#define DSI_BRG_DPI_RSV_DPI_DATA_REG (DR_REG_DSI_BRG_BASE + 0x28) +/** DSI_BRG_DPI_RSV_DATA : R/W; bitpos: [29:0]; default: 16383; + * this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + */ +#define DSI_BRG_DPI_RSV_DATA 0x3FFFFFFFU +#define DSI_BRG_DPI_RSV_DATA_M (DSI_BRG_DPI_RSV_DATA_V << DSI_BRG_DPI_RSV_DATA_S) +#define DSI_BRG_DPI_RSV_DATA_V 0x3FFFFFFFU +#define DSI_BRG_DPI_RSV_DATA_S 0 +/** DSI_BRG_DPI_DBG_EN : R/W; bitpos: [30]; default: 0; + * Configures data debug feature enable. 0: disable, 1: enable + */ +#define DSI_BRG_DPI_DBG_EN (BIT(30)) +#define DSI_BRG_DPI_DBG_EN_M (DSI_BRG_DPI_DBG_EN_V << DSI_BRG_DPI_DBG_EN_S) +#define DSI_BRG_DPI_DBG_EN_V 0x00000001U +#define DSI_BRG_DPI_DBG_EN_S 30 + +/** DSI_BRG_DPI_V_CFG0_REG register + * dsi bridge dpi v config register 0 + */ +#define DSI_BRG_DPI_V_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x30) +/** DSI_BRG_VTOTAL : R/W; bitpos: [11:0]; default: 525; + * this field configures the total length of one frame (by line) for dpi output, must + * meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + */ +#define DSI_BRG_VTOTAL 0x00000FFFU +#define DSI_BRG_VTOTAL_M (DSI_BRG_VTOTAL_V << DSI_BRG_VTOTAL_S) +#define DSI_BRG_VTOTAL_V 0x00000FFFU +#define DSI_BRG_VTOTAL_S 0 +/** DSI_BRG_VDISP : R/W; bitpos: [27:16]; default: 480; + * this field configures the length of valid line (by line) for dpi output + */ +#define DSI_BRG_VDISP 0x00000FFFU +#define DSI_BRG_VDISP_M (DSI_BRG_VDISP_V << DSI_BRG_VDISP_S) +#define DSI_BRG_VDISP_V 0x00000FFFU +#define DSI_BRG_VDISP_S 16 + +/** DSI_BRG_DPI_V_CFG1_REG register + * dsi bridge dpi v config register 1 + */ +#define DSI_BRG_DPI_V_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x34) +/** DSI_BRG_VBANK : R/W; bitpos: [11:0]; default: 33; + * this field configures the length between vsync and valid line (by line) for dpi + * output + */ +#define DSI_BRG_VBANK 0x00000FFFU +#define DSI_BRG_VBANK_M (DSI_BRG_VBANK_V << DSI_BRG_VBANK_S) +#define DSI_BRG_VBANK_V 0x00000FFFU +#define DSI_BRG_VBANK_S 0 +/** DSI_BRG_VSYNC : R/W; bitpos: [27:16]; default: 2; + * this field configures the length of vsync (by line) for dpi output + */ +#define DSI_BRG_VSYNC 0x00000FFFU +#define DSI_BRG_VSYNC_M (DSI_BRG_VSYNC_V << DSI_BRG_VSYNC_S) +#define DSI_BRG_VSYNC_V 0x00000FFFU +#define DSI_BRG_VSYNC_S 16 + +/** DSI_BRG_DPI_H_CFG0_REG register + * dsi bridge dpi h config register 0 + */ +#define DSI_BRG_DPI_H_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x38) +/** DSI_BRG_HTOTAL : R/W; bitpos: [11:0]; default: 800; + * this field configures the total length of one line (by pixel num) for dpi output, + * must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + */ +#define DSI_BRG_HTOTAL 0x00000FFFU +#define DSI_BRG_HTOTAL_M (DSI_BRG_HTOTAL_V << DSI_BRG_HTOTAL_S) +#define DSI_BRG_HTOTAL_V 0x00000FFFU +#define DSI_BRG_HTOTAL_S 0 +/** DSI_BRG_HDISP : R/W; bitpos: [27:16]; default: 640; + * this field configures the length of valid pixel data (by pixel num) for dpi output + */ +#define DSI_BRG_HDISP 0x00000FFFU +#define DSI_BRG_HDISP_M (DSI_BRG_HDISP_V << DSI_BRG_HDISP_S) +#define DSI_BRG_HDISP_V 0x00000FFFU +#define DSI_BRG_HDISP_S 16 + +/** DSI_BRG_DPI_H_CFG1_REG register + * dsi bridge dpi h config register 1 + */ +#define DSI_BRG_DPI_H_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x3c) +/** DSI_BRG_HBANK : R/W; bitpos: [11:0]; default: 48; + * this field configures the length between hsync and pixel data valid (by pixel num) + * for dpi output + */ +#define DSI_BRG_HBANK 0x00000FFFU +#define DSI_BRG_HBANK_M (DSI_BRG_HBANK_V << DSI_BRG_HBANK_S) +#define DSI_BRG_HBANK_V 0x00000FFFU +#define DSI_BRG_HBANK_S 0 +/** DSI_BRG_HSYNC : R/W; bitpos: [27:16]; default: 96; + * this field configures the length of hsync (by pixel num) for dpi output + */ +#define DSI_BRG_HSYNC 0x00000FFFU +#define DSI_BRG_HSYNC_M (DSI_BRG_HSYNC_V << DSI_BRG_HSYNC_S) +#define DSI_BRG_HSYNC_V 0x00000FFFU +#define DSI_BRG_HSYNC_S 16 + +/** DSI_BRG_DPI_MISC_CONFIG_REG register + * dsi_bridge dpi misc config register + */ +#define DSI_BRG_DPI_MISC_CONFIG_REG (DR_REG_DSI_BRG_BASE + 0x40) +/** DSI_BRG_DPI_EN : R/W; bitpos: [0]; default: 0; + * this bit configures enable of dpi output, 0: disable, 1: enable + */ +#define DSI_BRG_DPI_EN (BIT(0)) +#define DSI_BRG_DPI_EN_M (DSI_BRG_DPI_EN_V << DSI_BRG_DPI_EN_S) +#define DSI_BRG_DPI_EN_V 0x00000001U +#define DSI_BRG_DPI_EN_S 0 +/** DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT : R/W; bitpos: [15:4]; default: 413; + * this field configures the underrun interrupt musk, when underrun occurs and line + * cnt is less then this field + */ +#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT 0x00000FFFU +#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_M (DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V << DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S) +#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V 0x00000FFFU +#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S 4 + +/** DSI_BRG_DPI_CONFIG_UPDATE_REG register + * dsi_bridge dpi config update register + */ +#define DSI_BRG_DPI_CONFIG_UPDATE_REG (DR_REG_DSI_BRG_BASE + 0x44) +/** DSI_BRG_DPI_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + */ +#define DSI_BRG_DPI_CONFIG_UPDATE (BIT(0)) +#define DSI_BRG_DPI_CONFIG_UPDATE_M (DSI_BRG_DPI_CONFIG_UPDATE_V << DSI_BRG_DPI_CONFIG_UPDATE_S) +#define DSI_BRG_DPI_CONFIG_UPDATE_V 0x00000001U +#define DSI_BRG_DPI_CONFIG_UPDATE_S 0 + +/** DSI_BRG_INT_ENA_REG register + * dsi_bridge interrupt enable register + */ +#define DSI_BRG_INT_ENA_REG (DR_REG_DSI_BRG_BASE + 0x50) +/** DSI_BRG_UNDERRUN_INT_ENA : R/W; bitpos: [0]; default: 0; + * write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled + * by dpi_underrun interrupt signal + */ +#define DSI_BRG_UNDERRUN_INT_ENA (BIT(0)) +#define DSI_BRG_UNDERRUN_INT_ENA_M (DSI_BRG_UNDERRUN_INT_ENA_V << DSI_BRG_UNDERRUN_INT_ENA_S) +#define DSI_BRG_UNDERRUN_INT_ENA_V 0x00000001U +#define DSI_BRG_UNDERRUN_INT_ENA_S 0 +/** DSI_BRG_VSYNC_INT_ENA : R/W; bitpos: [1]; default: 0; + * write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by + * dpi_vsync interrupt signal + */ +#define DSI_BRG_VSYNC_INT_ENA (BIT(1)) +#define DSI_BRG_VSYNC_INT_ENA_M (DSI_BRG_VSYNC_INT_ENA_V << DSI_BRG_VSYNC_INT_ENA_S) +#define DSI_BRG_VSYNC_INT_ENA_V 0x00000001U +#define DSI_BRG_VSYNC_INT_ENA_S 1 + +/** DSI_BRG_INT_CLR_REG register + * dsi_bridge interrupt clear register + */ +#define DSI_BRG_INT_CLR_REG (DR_REG_DSI_BRG_BASE + 0x54) +/** DSI_BRG_UNDERRUN_INT_CLR : WT; bitpos: [0]; default: 0; + * write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ +#define DSI_BRG_UNDERRUN_INT_CLR (BIT(0)) +#define DSI_BRG_UNDERRUN_INT_CLR_M (DSI_BRG_UNDERRUN_INT_CLR_V << DSI_BRG_UNDERRUN_INT_CLR_S) +#define DSI_BRG_UNDERRUN_INT_CLR_V 0x00000001U +#define DSI_BRG_UNDERRUN_INT_CLR_S 0 +/** DSI_BRG_VSYNC_INT_CLR : WT; bitpos: [1]; default: 0; + * write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ +#define DSI_BRG_VSYNC_INT_CLR (BIT(1)) +#define DSI_BRG_VSYNC_INT_CLR_M (DSI_BRG_VSYNC_INT_CLR_V << DSI_BRG_VSYNC_INT_CLR_S) +#define DSI_BRG_VSYNC_INT_CLR_V 0x00000001U +#define DSI_BRG_VSYNC_INT_CLR_S 1 + +/** DSI_BRG_INT_RAW_REG register + * dsi_bridge raw interrupt register + */ +#define DSI_BRG_INT_RAW_REG (DR_REG_DSI_BRG_BASE + 0x58) +/** DSI_BRG_UNDERRUN_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * the raw interrupt status of dpi_underrun + */ +#define DSI_BRG_UNDERRUN_INT_RAW (BIT(0)) +#define DSI_BRG_UNDERRUN_INT_RAW_M (DSI_BRG_UNDERRUN_INT_RAW_V << DSI_BRG_UNDERRUN_INT_RAW_S) +#define DSI_BRG_UNDERRUN_INT_RAW_V 0x00000001U +#define DSI_BRG_UNDERRUN_INT_RAW_S 0 +/** DSI_BRG_VSYNC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * the raw interrupt status of dpi_vsync + */ +#define DSI_BRG_VSYNC_INT_RAW (BIT(1)) +#define DSI_BRG_VSYNC_INT_RAW_M (DSI_BRG_VSYNC_INT_RAW_V << DSI_BRG_VSYNC_INT_RAW_S) +#define DSI_BRG_VSYNC_INT_RAW_V 0x00000001U +#define DSI_BRG_VSYNC_INT_RAW_S 1 + +/** DSI_BRG_INT_ST_REG register + * dsi_bridge masked interrupt register + */ +#define DSI_BRG_INT_ST_REG (DR_REG_DSI_BRG_BASE + 0x5c) +/** DSI_BRG_UNDERRUN_INT_ST : RO; bitpos: [0]; default: 0; + * the masked interrupt status of dpi_underrun + */ +#define DSI_BRG_UNDERRUN_INT_ST (BIT(0)) +#define DSI_BRG_UNDERRUN_INT_ST_M (DSI_BRG_UNDERRUN_INT_ST_V << DSI_BRG_UNDERRUN_INT_ST_S) +#define DSI_BRG_UNDERRUN_INT_ST_V 0x00000001U +#define DSI_BRG_UNDERRUN_INT_ST_S 0 +/** DSI_BRG_VSYNC_INT_ST : RO; bitpos: [1]; default: 0; + * the masked interrupt status of dpi_vsync + */ +#define DSI_BRG_VSYNC_INT_ST (BIT(1)) +#define DSI_BRG_VSYNC_INT_ST_M (DSI_BRG_VSYNC_INT_ST_V << DSI_BRG_VSYNC_INT_ST_S) +#define DSI_BRG_VSYNC_INT_ST_V 0x00000001U +#define DSI_BRG_VSYNC_INT_ST_S 1 + +/** DSI_BRG_HOST_BIST_CTL_REG register + * dsi_bridge host bist control register + */ +#define DSI_BRG_HOST_BIST_CTL_REG (DR_REG_DSI_BRG_BASE + 0x60) +/** DSI_BRG_BISTOK : RO; bitpos: [0]; default: 0; + * bistok + */ +#define DSI_BRG_BISTOK (BIT(0)) +#define DSI_BRG_BISTOK_M (DSI_BRG_BISTOK_V << DSI_BRG_BISTOK_S) +#define DSI_BRG_BISTOK_V 0x00000001U +#define DSI_BRG_BISTOK_S 0 +/** DSI_BRG_BISTON : R/W; bitpos: [1]; default: 0; + * biston + */ +#define DSI_BRG_BISTON (BIT(1)) +#define DSI_BRG_BISTON_M (DSI_BRG_BISTON_V << DSI_BRG_BISTON_S) +#define DSI_BRG_BISTON_V 0x00000001U +#define DSI_BRG_BISTON_S 1 + +/** DSI_BRG_HOST_TRIGGER_REV_REG register + * dsi_bridge host trigger reverse control register + */ +#define DSI_BRG_HOST_TRIGGER_REV_REG (DR_REG_DSI_BRG_BASE + 0x64) +/** DSI_BRG_TX_TRIGGER_REV_EN : R/W; bitpos: [0]; default: 0; + * tx_trigger reverse. 0: disable, 1: enable + */ +#define DSI_BRG_TX_TRIGGER_REV_EN (BIT(0)) +#define DSI_BRG_TX_TRIGGER_REV_EN_M (DSI_BRG_TX_TRIGGER_REV_EN_V << DSI_BRG_TX_TRIGGER_REV_EN_S) +#define DSI_BRG_TX_TRIGGER_REV_EN_V 0x00000001U +#define DSI_BRG_TX_TRIGGER_REV_EN_S 0 +/** DSI_BRG_RX_TRIGGER_REV_EN : R/W; bitpos: [1]; default: 0; + * rx_trigger reverse. 0: disable, 1: enable + */ +#define DSI_BRG_RX_TRIGGER_REV_EN (BIT(1)) +#define DSI_BRG_RX_TRIGGER_REV_EN_M (DSI_BRG_RX_TRIGGER_REV_EN_V << DSI_BRG_RX_TRIGGER_REV_EN_S) +#define DSI_BRG_RX_TRIGGER_REV_EN_V 0x00000001U +#define DSI_BRG_RX_TRIGGER_REV_EN_S 1 + +/** DSI_BRG_BLK_RAW_NUM_CFG_REG register + * dsi_bridge block raw number control register + */ +#define DSI_BRG_BLK_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0x68) +/** DSI_BRG_BLK_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total block pix bits/64 + */ +#define DSI_BRG_BLK_RAW_NUM_TOTAL 0x003FFFFFU +#define DSI_BRG_BLK_RAW_NUM_TOTAL_M (DSI_BRG_BLK_RAW_NUM_TOTAL_V << DSI_BRG_BLK_RAW_NUM_TOTAL_S) +#define DSI_BRG_BLK_RAW_NUM_TOTAL_V 0x003FFFFFU +#define DSI_BRG_BLK_RAW_NUM_TOTAL_S 0 +/** DSI_BRG_BLK_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0; + * write 1 to reload reg_blk_raw_num_total to internal cnt + */ +#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET (BIT(31)) +#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_M (DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V << DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S) +#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V 0x00000001U +#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S 31 + +/** DSI_BRG_DMA_FRAME_INTERVAL_REG register + * dsi_bridge dam frame interval control register + */ +#define DSI_BRG_DMA_FRAME_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x6c) +/** DSI_BRG_DMA_FRAME_SLOT : R/W; bitpos: [9:0]; default: 9; + * this field configures the max frame_slot_cnt + */ +#define DSI_BRG_DMA_FRAME_SLOT 0x000003FFU +#define DSI_BRG_DMA_FRAME_SLOT_M (DSI_BRG_DMA_FRAME_SLOT_V << DSI_BRG_DMA_FRAME_SLOT_S) +#define DSI_BRG_DMA_FRAME_SLOT_V 0x000003FFU +#define DSI_BRG_DMA_FRAME_SLOT_S 0 +/** DSI_BRG_DMA_FRAME_INTERVAL : R/W; bitpos: [27:10]; default: 9; + * this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 + * when frame_slot_cnt if full + */ +#define DSI_BRG_DMA_FRAME_INTERVAL 0x0003FFFFU +#define DSI_BRG_DMA_FRAME_INTERVAL_M (DSI_BRG_DMA_FRAME_INTERVAL_V << DSI_BRG_DMA_FRAME_INTERVAL_S) +#define DSI_BRG_DMA_FRAME_INTERVAL_V 0x0003FFFFU +#define DSI_BRG_DMA_FRAME_INTERVAL_S 10 +/** DSI_BRG_DMA_MULTIBLK_EN : R/W; bitpos: [28]; default: 0; + * this bit configures enable multi-blk transfer, 0: disable, 1: enable + */ +#define DSI_BRG_DMA_MULTIBLK_EN (BIT(28)) +#define DSI_BRG_DMA_MULTIBLK_EN_M (DSI_BRG_DMA_MULTIBLK_EN_V << DSI_BRG_DMA_MULTIBLK_EN_S) +#define DSI_BRG_DMA_MULTIBLK_EN_V 0x00000001U +#define DSI_BRG_DMA_MULTIBLK_EN_S 28 +/** DSI_BRG_DMA_FRAME_INTERVAL_EN : R/W; bitpos: [29]; default: 1; + * this bit configures enable interval between frame transfer, 0: disable, 1: enable + */ +#define DSI_BRG_DMA_FRAME_INTERVAL_EN (BIT(29)) +#define DSI_BRG_DMA_FRAME_INTERVAL_EN_M (DSI_BRG_DMA_FRAME_INTERVAL_EN_V << DSI_BRG_DMA_FRAME_INTERVAL_EN_S) +#define DSI_BRG_DMA_FRAME_INTERVAL_EN_V 0x00000001U +#define DSI_BRG_DMA_FRAME_INTERVAL_EN_S 29 + +/** DSI_BRG_MEM_AUX_CTRL_REG register + * dsi_bridge mem aux control register + */ +#define DSI_BRG_MEM_AUX_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x70) +/** DSI_BRG_DSI_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures dsi_bridge fifo memory aux ctrl + */ +#define DSI_BRG_DSI_MEM_AUX_CTRL 0x00003FFFU +#define DSI_BRG_DSI_MEM_AUX_CTRL_M (DSI_BRG_DSI_MEM_AUX_CTRL_V << DSI_BRG_DSI_MEM_AUX_CTRL_S) +#define DSI_BRG_DSI_MEM_AUX_CTRL_V 0x00003FFFU +#define DSI_BRG_DSI_MEM_AUX_CTRL_S 0 + +/** DSI_BRG_RDN_ECO_CS_REG register + * dsi_bridge rdn eco cs register + */ +#define DSI_BRG_RDN_ECO_CS_REG (DR_REG_DSI_BRG_BASE + 0x74) +/** DSI_BRG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ +#define DSI_BRG_RDN_ECO_EN (BIT(0)) +#define DSI_BRG_RDN_ECO_EN_M (DSI_BRG_RDN_ECO_EN_V << DSI_BRG_RDN_ECO_EN_S) +#define DSI_BRG_RDN_ECO_EN_V 0x00000001U +#define DSI_BRG_RDN_ECO_EN_S 0 +/** DSI_BRG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ +#define DSI_BRG_RDN_ECO_RESULT (BIT(1)) +#define DSI_BRG_RDN_ECO_RESULT_M (DSI_BRG_RDN_ECO_RESULT_V << DSI_BRG_RDN_ECO_RESULT_S) +#define DSI_BRG_RDN_ECO_RESULT_V 0x00000001U +#define DSI_BRG_RDN_ECO_RESULT_S 1 + +/** DSI_BRG_RDN_ECO_LOW_REG register + * dsi_bridge rdn eco all low register + */ +#define DSI_BRG_RDN_ECO_LOW_REG (DR_REG_DSI_BRG_BASE + 0x78) +/** DSI_BRG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ +#define DSI_BRG_RDN_ECO_LOW 0xFFFFFFFFU +#define DSI_BRG_RDN_ECO_LOW_M (DSI_BRG_RDN_ECO_LOW_V << DSI_BRG_RDN_ECO_LOW_S) +#define DSI_BRG_RDN_ECO_LOW_V 0xFFFFFFFFU +#define DSI_BRG_RDN_ECO_LOW_S 0 + +/** DSI_BRG_RDN_ECO_HIGH_REG register + * dsi_bridge rdn eco all high register + */ +#define DSI_BRG_RDN_ECO_HIGH_REG (DR_REG_DSI_BRG_BASE + 0x7c) +/** DSI_BRG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ +#define DSI_BRG_RDN_ECO_HIGH 0xFFFFFFFFU +#define DSI_BRG_RDN_ECO_HIGH_M (DSI_BRG_RDN_ECO_HIGH_V << DSI_BRG_RDN_ECO_HIGH_S) +#define DSI_BRG_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define DSI_BRG_RDN_ECO_HIGH_S 0 + +/** DSI_BRG_HOST_CTRL_REG register + * dsi_bridge host control register + */ +#define DSI_BRG_HOST_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x80) +/** DSI_BRG_DSI_CFG_REF_CLK_EN : R/W; bitpos: [0]; default: 1; + * this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: + * enable + */ +#define DSI_BRG_DSI_CFG_REF_CLK_EN (BIT(0)) +#define DSI_BRG_DSI_CFG_REF_CLK_EN_M (DSI_BRG_DSI_CFG_REF_CLK_EN_V << DSI_BRG_DSI_CFG_REF_CLK_EN_S) +#define DSI_BRG_DSI_CFG_REF_CLK_EN_V 0x00000001U +#define DSI_BRG_DSI_CFG_REF_CLK_EN_S 0 + +/** DSI_BRG_MEM_CLK_CTRL_REG register + * dsi_bridge mem force on control register + */ +#define DSI_BRG_MEM_CLK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x84) +/** DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0; + * this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: + * force on + */ +#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON (BIT(0)) +#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_M (DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S) +#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V 0x00000001U +#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S 0 +/** DSI_BRG_DSI_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + */ +#define DSI_BRG_DSI_MEM_CLK_FORCE_ON (BIT(1)) +#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_M (DSI_BRG_DSI_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_MEM_CLK_FORCE_ON_S) +#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_V 0x00000001U +#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_S 1 + +/** DSI_BRG_DMA_FLOW_CTRL_REG register + * dsi_bridge dma flow controller register + */ +#define DSI_BRG_DMA_FLOW_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x88) +/** DSI_BRG_DSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [0]; default: 1; + * this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge + * as flow controller + */ +#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER (BIT(0)) +#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_M (DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V << DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S) +#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V 0x00000001U +#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S 0 +/** DSI_BRG_DMA_FLOW_MULTIBLK_NUM : R/W; bitpos: [7:4]; default: 1; + * this field configures the num of blocks when multi-blk is enable and dmac as flow + * controller + */ +#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM 0x0000000FU +#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_M (DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V << DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S) +#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V 0x0000000FU +#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S 4 + +/** DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG register + * dsi_bridge buffer empty threshold register + */ +#define DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG (DR_REG_DSI_BRG_BASE + 0x8c) +/** DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD : R/W; bitpos: [10:0]; default: 512; + * this field configures the fifo almost empty threshold, is valid only when dmac as + * flow controller + */ +#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD 0x000007FFU +#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_M (DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V << DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S) +#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V 0x000007FFU +#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S 0 + +/** DSI_BRG_YUV_CFG_REG register + * dsi_bridge yuv format config register + */ +#define DSI_BRG_YUV_CFG_REG (DR_REG_DSI_BRG_BASE + 0x90) +/** DSI_BRG_PROTOCAL : R/W; bitpos: [0]; default: 0; + * this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + */ +#define DSI_BRG_PROTOCAL (BIT(0)) +#define DSI_BRG_PROTOCAL_M (DSI_BRG_PROTOCAL_V << DSI_BRG_PROTOCAL_S) +#define DSI_BRG_PROTOCAL_V 0x00000001U +#define DSI_BRG_PROTOCAL_S 0 +/** DSI_BRG_YUV_PIX_ENDIAN : R/W; bitpos: [1]; default: 0; + * this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + */ +#define DSI_BRG_YUV_PIX_ENDIAN (BIT(1)) +#define DSI_BRG_YUV_PIX_ENDIAN_M (DSI_BRG_YUV_PIX_ENDIAN_V << DSI_BRG_YUV_PIX_ENDIAN_S) +#define DSI_BRG_YUV_PIX_ENDIAN_V 0x00000001U +#define DSI_BRG_YUV_PIX_ENDIAN_S 1 +/** DSI_BRG_YUV422_FORMAT : R/W; bitpos: [3:2]; default: 0; + * this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + */ +#define DSI_BRG_YUV422_FORMAT 0x00000003U +#define DSI_BRG_YUV422_FORMAT_M (DSI_BRG_YUV422_FORMAT_V << DSI_BRG_YUV422_FORMAT_S) +#define DSI_BRG_YUV422_FORMAT_V 0x00000003U +#define DSI_BRG_YUV422_FORMAT_S 2 +/** DSI_BRG_YUV_RANGE : R/W; bitpos: [4]; default: 0; + * Configures yuv pixel range, 0: limit range, 1: full range + */ +#define DSI_BRG_YUV_RANGE (BIT(4)) +#define DSI_BRG_YUV_RANGE_M (DSI_BRG_YUV_RANGE_V << DSI_BRG_YUV_RANGE_S) +#define DSI_BRG_YUV_RANGE_V 0x00000001U +#define DSI_BRG_YUV_RANGE_S 4 + +/** DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG register + * dsi phy lp_loopback test ctrl + */ +#define DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x94) +/** DSI_BRG_PHY_LP_TXDATAESC_1 : R/W; bitpos: [7:0]; default: 0; + * txdataesc_1 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXDATAESC_1 0x000000FFU +#define DSI_BRG_PHY_LP_TXDATAESC_1_M (DSI_BRG_PHY_LP_TXDATAESC_1_V << DSI_BRG_PHY_LP_TXDATAESC_1_S) +#define DSI_BRG_PHY_LP_TXDATAESC_1_V 0x000000FFU +#define DSI_BRG_PHY_LP_TXDATAESC_1_S 0 +/** DSI_BRG_PHY_LP_TXREQUESTESC_1 : R/W; bitpos: [8]; default: 0; + * txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXREQUESTESC_1 (BIT(8)) +#define DSI_BRG_PHY_LP_TXREQUESTESC_1_M (DSI_BRG_PHY_LP_TXREQUESTESC_1_V << DSI_BRG_PHY_LP_TXREQUESTESC_1_S) +#define DSI_BRG_PHY_LP_TXREQUESTESC_1_V 0x00000001U +#define DSI_BRG_PHY_LP_TXREQUESTESC_1_S 8 +/** DSI_BRG_PHY_LP_TXVALIDESC_1 : R/W; bitpos: [9]; default: 0; + * txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXVALIDESC_1 (BIT(9)) +#define DSI_BRG_PHY_LP_TXVALIDESC_1_M (DSI_BRG_PHY_LP_TXVALIDESC_1_V << DSI_BRG_PHY_LP_TXVALIDESC_1_S) +#define DSI_BRG_PHY_LP_TXVALIDESC_1_V 0x00000001U +#define DSI_BRG_PHY_LP_TXVALIDESC_1_S 9 +/** DSI_BRG_PHY_LP_TXLPDTESC_1 : R/W; bitpos: [10]; default: 0; + * txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXLPDTESC_1 (BIT(10)) +#define DSI_BRG_PHY_LP_TXLPDTESC_1_M (DSI_BRG_PHY_LP_TXLPDTESC_1_V << DSI_BRG_PHY_LP_TXLPDTESC_1_S) +#define DSI_BRG_PHY_LP_TXLPDTESC_1_V 0x00000001U +#define DSI_BRG_PHY_LP_TXLPDTESC_1_S 10 +/** DSI_BRG_PHY_LP_BASEDIR_1 : R/W; bitpos: [11]; default: 0; + * basedir_1 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_BASEDIR_1 (BIT(11)) +#define DSI_BRG_PHY_LP_BASEDIR_1_M (DSI_BRG_PHY_LP_BASEDIR_1_V << DSI_BRG_PHY_LP_BASEDIR_1_S) +#define DSI_BRG_PHY_LP_BASEDIR_1_V 0x00000001U +#define DSI_BRG_PHY_LP_BASEDIR_1_S 11 +/** DSI_BRG_PHY_LP_TXDATAESC_0 : R/W; bitpos: [23:16]; default: 0; + * txdataesc_0 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXDATAESC_0 0x000000FFU +#define DSI_BRG_PHY_LP_TXDATAESC_0_M (DSI_BRG_PHY_LP_TXDATAESC_0_V << DSI_BRG_PHY_LP_TXDATAESC_0_S) +#define DSI_BRG_PHY_LP_TXDATAESC_0_V 0x000000FFU +#define DSI_BRG_PHY_LP_TXDATAESC_0_S 16 +/** DSI_BRG_PHY_LP_TXREQUESTESC_0 : R/W; bitpos: [24]; default: 0; + * txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXREQUESTESC_0 (BIT(24)) +#define DSI_BRG_PHY_LP_TXREQUESTESC_0_M (DSI_BRG_PHY_LP_TXREQUESTESC_0_V << DSI_BRG_PHY_LP_TXREQUESTESC_0_S) +#define DSI_BRG_PHY_LP_TXREQUESTESC_0_V 0x00000001U +#define DSI_BRG_PHY_LP_TXREQUESTESC_0_S 24 +/** DSI_BRG_PHY_LP_TXVALIDESC_0 : R/W; bitpos: [25]; default: 0; + * txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXVALIDESC_0 (BIT(25)) +#define DSI_BRG_PHY_LP_TXVALIDESC_0_M (DSI_BRG_PHY_LP_TXVALIDESC_0_V << DSI_BRG_PHY_LP_TXVALIDESC_0_S) +#define DSI_BRG_PHY_LP_TXVALIDESC_0_V 0x00000001U +#define DSI_BRG_PHY_LP_TXVALIDESC_0_S 25 +/** DSI_BRG_PHY_LP_TXLPDTESC_0 : R/W; bitpos: [26]; default: 0; + * txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_TXLPDTESC_0 (BIT(26)) +#define DSI_BRG_PHY_LP_TXLPDTESC_0_M (DSI_BRG_PHY_LP_TXLPDTESC_0_V << DSI_BRG_PHY_LP_TXLPDTESC_0_S) +#define DSI_BRG_PHY_LP_TXLPDTESC_0_V 0x00000001U +#define DSI_BRG_PHY_LP_TXLPDTESC_0_S 26 +/** DSI_BRG_PHY_LP_BASEDIR_0 : R/W; bitpos: [27]; default: 0; + * basedir_0 ctrl when enable dsi phy lp_loopback_test + */ +#define DSI_BRG_PHY_LP_BASEDIR_0 (BIT(27)) +#define DSI_BRG_PHY_LP_BASEDIR_0_M (DSI_BRG_PHY_LP_BASEDIR_0_V << DSI_BRG_PHY_LP_BASEDIR_0_S) +#define DSI_BRG_PHY_LP_BASEDIR_0_V 0x00000001U +#define DSI_BRG_PHY_LP_BASEDIR_0_S 27 +/** DSI_BRG_PHY_LP_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0; + * dsi phy lp_loopback test start check + */ +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK (BIT(28)) +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_M (DSI_BRG_PHY_LP_LOOPBACK_CHECK_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_S) +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_V 0x00000001U +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_S 28 +/** DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0; + * dsi phy lp_loopback test check done + */ +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE (BIT(29)) +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_M (DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S) +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V 0x00000001U +#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S 29 +/** DSI_BRG_PHY_LP_LOOPBACK_EN : R/W; bitpos: [30]; default: 0; + * dsi phy lp_loopback ctrl en + */ +#define DSI_BRG_PHY_LP_LOOPBACK_EN (BIT(30)) +#define DSI_BRG_PHY_LP_LOOPBACK_EN_M (DSI_BRG_PHY_LP_LOOPBACK_EN_V << DSI_BRG_PHY_LP_LOOPBACK_EN_S) +#define DSI_BRG_PHY_LP_LOOPBACK_EN_V 0x00000001U +#define DSI_BRG_PHY_LP_LOOPBACK_EN_S 30 +/** DSI_BRG_PHY_LP_LOOPBACK_OK : RO; bitpos: [31]; default: 0; + * result of dsi phy lp_loopback test + */ +#define DSI_BRG_PHY_LP_LOOPBACK_OK (BIT(31)) +#define DSI_BRG_PHY_LP_LOOPBACK_OK_M (DSI_BRG_PHY_LP_LOOPBACK_OK_V << DSI_BRG_PHY_LP_LOOPBACK_OK_S) +#define DSI_BRG_PHY_LP_LOOPBACK_OK_V 0x00000001U +#define DSI_BRG_PHY_LP_LOOPBACK_OK_S 31 + +/** DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG register + * dsi phy hp_loopback test ctrl + */ +#define DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x98) +/** DSI_BRG_PHY_HS_TXDATAHS_1 : R/W; bitpos: [7:0]; default: 0; + * txdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_TXDATAHS_1 0x000000FFU +#define DSI_BRG_PHY_HS_TXDATAHS_1_M (DSI_BRG_PHY_HS_TXDATAHS_1_V << DSI_BRG_PHY_HS_TXDATAHS_1_S) +#define DSI_BRG_PHY_HS_TXDATAHS_1_V 0x000000FFU +#define DSI_BRG_PHY_HS_TXDATAHS_1_S 0 +/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 : R/W; bitpos: [8]; default: 0; + * txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 (BIT(8)) +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_M (DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S) +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V 0x00000001U +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S 8 +/** DSI_BRG_PHY_HS_BASEDIR_1 : R/W; bitpos: [9]; default: 1; + * basedir_1 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_BASEDIR_1 (BIT(9)) +#define DSI_BRG_PHY_HS_BASEDIR_1_M (DSI_BRG_PHY_HS_BASEDIR_1_V << DSI_BRG_PHY_HS_BASEDIR_1_S) +#define DSI_BRG_PHY_HS_BASEDIR_1_V 0x00000001U +#define DSI_BRG_PHY_HS_BASEDIR_1_S 9 +/** DSI_BRG_PHY_HS_TXDATAHS_0 : R/W; bitpos: [23:16]; default: 0; + * txdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_TXDATAHS_0 0x000000FFU +#define DSI_BRG_PHY_HS_TXDATAHS_0_M (DSI_BRG_PHY_HS_TXDATAHS_0_V << DSI_BRG_PHY_HS_TXDATAHS_0_S) +#define DSI_BRG_PHY_HS_TXDATAHS_0_V 0x000000FFU +#define DSI_BRG_PHY_HS_TXDATAHS_0_S 16 +/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 : R/W; bitpos: [24]; default: 0; + * txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 (BIT(24)) +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_M (DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S) +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V 0x00000001U +#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S 24 +/** DSI_BRG_PHY_HS_BASEDIR_0 : R/W; bitpos: [25]; default: 0; + * basedir_0 ctrl when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_BASEDIR_0 (BIT(25)) +#define DSI_BRG_PHY_HS_BASEDIR_0_M (DSI_BRG_PHY_HS_BASEDIR_0_V << DSI_BRG_PHY_HS_BASEDIR_0_S) +#define DSI_BRG_PHY_HS_BASEDIR_0_V 0x00000001U +#define DSI_BRG_PHY_HS_BASEDIR_0_S 25 +/** DSI_BRG_PHY_HS_TXREQUESTHSCLK : R/W; bitpos: [27]; default: 0; + * txrequesthsclk when enable dsi phy hs_loopback_test + */ +#define DSI_BRG_PHY_HS_TXREQUESTHSCLK (BIT(27)) +#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_M (DSI_BRG_PHY_HS_TXREQUESTHSCLK_V << DSI_BRG_PHY_HS_TXREQUESTHSCLK_S) +#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_V 0x00000001U +#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_S 27 +/** DSI_BRG_PHY_HS_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0; + * dsi phy hs_loopback test start check + */ +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK (BIT(28)) +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_M (DSI_BRG_PHY_HS_LOOPBACK_CHECK_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_S) +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_V 0x00000001U +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_S 28 +/** DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0; + * dsi phy hs_loopback test check done + */ +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE (BIT(29)) +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_M (DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S) +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V 0x00000001U +#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S 29 +/** DSI_BRG_PHY_HS_LOOPBACK_EN : R/W; bitpos: [30]; default: 0; + * dsi phy hs_loopback ctrl en + */ +#define DSI_BRG_PHY_HS_LOOPBACK_EN (BIT(30)) +#define DSI_BRG_PHY_HS_LOOPBACK_EN_M (DSI_BRG_PHY_HS_LOOPBACK_EN_V << DSI_BRG_PHY_HS_LOOPBACK_EN_S) +#define DSI_BRG_PHY_HS_LOOPBACK_EN_V 0x00000001U +#define DSI_BRG_PHY_HS_LOOPBACK_EN_S 30 +/** DSI_BRG_PHY_HS_LOOPBACK_OK : RO; bitpos: [31]; default: 0; + * result of dsi phy hs_loopback test + */ +#define DSI_BRG_PHY_HS_LOOPBACK_OK (BIT(31)) +#define DSI_BRG_PHY_HS_LOOPBACK_OK_M (DSI_BRG_PHY_HS_LOOPBACK_OK_V << DSI_BRG_PHY_HS_LOOPBACK_OK_S) +#define DSI_BRG_PHY_HS_LOOPBACK_OK_V 0x00000001U +#define DSI_BRG_PHY_HS_LOOPBACK_OK_S 31 + +/** DSI_BRG_PHY_LOOPBACK_CNT_REG register + * loopback test cnt + */ +#define DSI_BRG_PHY_LOOPBACK_CNT_REG (DR_REG_DSI_BRG_BASE + 0x9c) +/** DSI_BRG_PHY_HS_CHECK_CNT_TH : R/W; bitpos: [7:0]; default: 64; + * hs_loopback test check cnt + */ +#define DSI_BRG_PHY_HS_CHECK_CNT_TH 0x000000FFU +#define DSI_BRG_PHY_HS_CHECK_CNT_TH_M (DSI_BRG_PHY_HS_CHECK_CNT_TH_V << DSI_BRG_PHY_HS_CHECK_CNT_TH_S) +#define DSI_BRG_PHY_HS_CHECK_CNT_TH_V 0x000000FFU +#define DSI_BRG_PHY_HS_CHECK_CNT_TH_S 0 +/** DSI_BRG_PHY_LP_CHECK_CNT_TH : R/W; bitpos: [23:16]; default: 64; + * lp_loopback test check cnt + */ +#define DSI_BRG_PHY_LP_CHECK_CNT_TH 0x000000FFU +#define DSI_BRG_PHY_LP_CHECK_CNT_TH_M (DSI_BRG_PHY_LP_CHECK_CNT_TH_V << DSI_BRG_PHY_LP_CHECK_CNT_TH_S) +#define DSI_BRG_PHY_LP_CHECK_CNT_TH_V 0x000000FFU +#define DSI_BRG_PHY_LP_CHECK_CNT_TH_S 16 + +/** DSI_BRG_VER_DATE_REG register + * version control register + */ +#define DSI_BRG_VER_DATE_REG (DR_REG_DSI_BRG_BASE + 0x100) +/** DSI_BRG_VER_DATA : R/W; bitpos: [31:0]; default: 539296009; + * Represents csv version + */ +#define DSI_BRG_VER_DATA 0xFFFFFFFFU +#define DSI_BRG_VER_DATA_M (DSI_BRG_VER_DATA_V << DSI_BRG_VER_DATA_S) +#define DSI_BRG_VER_DATA_V 0xFFFFFFFFU +#define DSI_BRG_VER_DATA_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h new file mode 100644 index 0000000000..3da6f91b24 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h @@ -0,0 +1,818 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of clk_en register + * dsi bridge clk control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * this bit configures force_on of dsi_bridge register clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_clk_en_reg_t; + +/** Type of en register + * dsi bridge en register + */ +typedef union { + struct { + /** dsi_en : R/W; bitpos: [0]; default: 0; + * this bit configures module enable of dsi_bridge. 0: disable, 1: enable + */ + uint32_t dsi_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_en_reg_t; + +/** Type of dma_req_cfg register + * dsi bridge dma burst len register + */ +typedef union { + struct { + /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; + * this field configures the num of 64-bit in one dma burst transfer, valid only when + * dsi_bridge as flow controller + */ + uint32_t dma_burst_len:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_brg_dma_req_cfg_reg_t; + +/** Type of raw_num_cfg register + * dsi bridge raw number control register + */ +typedef union { + struct { + /** raw_num_total : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total pix bits/64 + */ + uint32_t raw_num_total:22; + /** unalign_64bit_en : R/W; bitpos: [22]; default: 0; + * this field configures whether the total pix bits is a multiple of 64bits. 0: align + * to 64-bit, 1: unalign to 64-bit + */ + uint32_t unalign_64bit_en:1; + uint32_t reserved_23:8; + /** raw_num_total_set : WT; bitpos: [31]; default: 0; + * this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, + * 1: enable. valid only when dsi_bridge as flow controller + */ + uint32_t raw_num_total_set:1; + }; + uint32_t val; +} dsi_brg_raw_num_cfg_reg_t; + +/** Type of raw_buf_credit_ctl register + * dsi bridge credit register + */ +typedef union { + struct { + /** credit_thrd : R/W; bitpos: [14:0]; default: 1024; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * 64-bit, valid only when dsi_bridge as flow controller + */ + uint32_t credit_thrd:15; + uint32_t reserved_15:1; + /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800; + * this field configures the threshold whether dsi_bridge fifo can receive one more + * dma burst, valid only when dsi_bridge as flow controller + */ + uint32_t credit_burst_thrd:15; + /** credit_reset : R/W; bitpos: [31]; default: 0; + * this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when + * dsi_bridge as flow controller + */ + uint32_t credit_reset:1; + }; + uint32_t val; +} dsi_brg_raw_buf_credit_ctl_reg_t; + +/** Type of pixel_type register + * dsi bridge dpi type control register + */ +typedef union { + struct { + /** raw_type : R/W; bitpos: [3:0]; default: 0; + * this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + */ + uint32_t raw_type:4; + /** dpi_config : R/W; bitpos: [5:4]; default: 0; + * this field configures the pixel arrange type of dpi interface + */ + uint32_t dpi_config:2; + /** data_in_type : R/W; bitpos: [6]; default: 0; + * input data type, 0: rgb, 1: yuv + */ + uint32_t data_in_type:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} dsi_brg_pixel_type_reg_t; + +/** Type of dma_block_interval register + * dsi bridge dma block interval control register + */ +typedef union { + struct { + /** dma_block_slot : R/W; bitpos: [9:0]; default: 9; + * this field configures the max block_slot_cnt + */ + uint32_t dma_block_slot:10; + /** dma_block_interval : R/W; bitpos: [27:10]; default: 9; + * this field configures the max block_interval_cnt, block_interval_cnt increased by 1 + * when block_slot_cnt if full + */ + uint32_t dma_block_interval:18; + /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1; + * this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + */ + uint32_t raw_num_total_auto_reload:1; + /** dma_block_interval_en : R/W; bitpos: [29]; default: 1; + * this bit configures enable of interval between dma block transfer, 0: disable, 1: + * enable + */ + uint32_t dma_block_interval_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} dsi_brg_dma_block_interval_reg_t; + +/** Type of dma_req_interval register + * dsi bridge dma req interval control register + */ +typedef union { + struct { + /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; + * this field configures the interval between dma req events + */ + uint32_t dma_req_interval:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_brg_dma_req_interval_reg_t; + +/** Type of dpi_lcd_ctl register + * dsi bridge dpi signal control register + */ +typedef union { + struct { + /** dpishutdn : R/W; bitpos: [0]; default: 0; + * this bit configures dpishutdn signal in dpi interface + */ + uint32_t dpishutdn:1; + /** dpicolorm : R/W; bitpos: [1]; default: 0; + * this bit configures dpicolorm signal in dpi interface + */ + uint32_t dpicolorm:1; + /** dpiupdatecfg : R/W; bitpos: [2]; default: 0; + * this bit configures dpiupdatecfg signal in dpi interface + */ + uint32_t dpiupdatecfg:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} dsi_brg_dpi_lcd_ctl_reg_t; + +/** Type of dpi_rsv_dpi_data register + * dsi bridge dpi reserved data register + */ +typedef union { + struct { + /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383; + * this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + */ + uint32_t dpi_rsv_data:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} dsi_brg_dpi_rsv_dpi_data_reg_t; + +/** Type of dpi_v_cfg0 register + * dsi bridge dpi v config register 0 + */ +typedef union { + struct { + /** vtotal : R/W; bitpos: [11:0]; default: 525; + * this field configures the total length of one frame (by line) for dpi output, must + * meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + */ + uint32_t vtotal:12; + uint32_t reserved_12:4; + /** vdisp : R/W; bitpos: [27:16]; default: 480; + * this field configures the length of valid line (by line) for dpi output + */ + uint32_t vdisp:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_v_cfg0_reg_t; + +/** Type of dpi_v_cfg1 register + * dsi bridge dpi v config register 1 + */ +typedef union { + struct { + /** vbank : R/W; bitpos: [11:0]; default: 33; + * this field configures the length between vsync and valid line (by line) for dpi + * output + */ + uint32_t vbank:12; + uint32_t reserved_12:4; + /** vsync : R/W; bitpos: [27:16]; default: 2; + * this field configures the length of vsync (by line) for dpi output + */ + uint32_t vsync:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_v_cfg1_reg_t; + +/** Type of dpi_h_cfg0 register + * dsi bridge dpi h config register 0 + */ +typedef union { + struct { + /** htotal : R/W; bitpos: [11:0]; default: 800; + * this field configures the total length of one line (by pixel num) for dpi output, + * must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + */ + uint32_t htotal:12; + uint32_t reserved_12:4; + /** hdisp : R/W; bitpos: [27:16]; default: 640; + * this field configures the length of valid pixel data (by pixel num) for dpi output + */ + uint32_t hdisp:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_h_cfg0_reg_t; + +/** Type of dpi_h_cfg1 register + * dsi bridge dpi h config register 1 + */ +typedef union { + struct { + /** hbank : R/W; bitpos: [11:0]; default: 48; + * this field configures the length between hsync and pixel data valid (by pixel num) + * for dpi output + */ + uint32_t hbank:12; + uint32_t reserved_12:4; + /** hsync : R/W; bitpos: [27:16]; default: 96; + * this field configures the length of hsync (by pixel num) for dpi output + */ + uint32_t hsync:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} dsi_brg_dpi_h_cfg1_reg_t; + +/** Type of dpi_misc_config register + * dsi_bridge dpi misc config register + */ +typedef union { + struct { + /** dpi_en : R/W; bitpos: [0]; default: 0; + * this bit configures enable of dpi output, 0: disable, 1: enable + */ + uint32_t dpi_en:1; + uint32_t reserved_1:3; + /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413; + * this field configures the underrun interrupt musk, when underrun occurs and line + * cnt is less then this field + */ + uint32_t fifo_underrun_discard_vcnt:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_brg_dpi_misc_config_reg_t; + +/** Type of dpi_config_update register + * dsi_bridge dpi config update register + */ +typedef union { + struct { + /** dpi_config_update : WT; bitpos: [0]; default: 0; + * write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + */ + uint32_t dpi_config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_dpi_config_update_reg_t; + +/** Type of host_trigger_rev register + * dsi_bridge host trigger reverse control register + */ +typedef union { + struct { + /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0; + * tx_trigger reverse. 0: disable, 1: enable + */ + uint32_t tx_trigger_rev_en:1; + /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0; + * rx_trigger reverse. 0: disable, 1: enable + */ + uint32_t rx_trigger_rev_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_host_trigger_rev_reg_t; + +/** Type of blk_raw_num_cfg register + * dsi_bridge block raw number control register + */ +typedef union { + struct { + /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400; + * this field configures number of total block pix bits/64 + */ + uint32_t blk_raw_num_total:22; + uint32_t reserved_22:9; + /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0; + * write 1 to reload reg_blk_raw_num_total to internal cnt + */ + uint32_t blk_raw_num_total_set:1; + }; + uint32_t val; +} dsi_brg_blk_raw_num_cfg_reg_t; + +/** Type of dma_frame_interval register + * dsi_bridge dam frame interval control register + */ +typedef union { + struct { + /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9; + * this field configures the max frame_slot_cnt + */ + uint32_t dma_frame_slot:10; + /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9; + * this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 + * when frame_slot_cnt if full + */ + uint32_t dma_frame_interval:18; + /** dma_multiblk_en : R/W; bitpos: [28]; default: 0; + * this bit configures enable multi-blk transfer, 0: disable, 1: enable + */ + uint32_t dma_multiblk_en:1; + /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1; + * this bit configures enable interval between frame transfer, 0: disable, 1: enable + */ + uint32_t dma_frame_interval_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} dsi_brg_dma_frame_interval_reg_t; + +/** Type of mem_aux_ctrl register + * dsi_bridge mem aux control register + */ +typedef union { + struct { + /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures dsi_bridge fifo memory aux ctrl + */ + uint32_t dsi_mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_brg_mem_aux_ctrl_reg_t; + +/** Type of rdn_eco_low register + * dsi_bridge rdn eco all low register + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} dsi_brg_rdn_eco_low_reg_t; + +/** Type of rdn_eco_high register + * dsi_bridge rdn eco all high register + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} dsi_brg_rdn_eco_high_reg_t; + +/** Type of host_ctrl register + * dsi_bridge host control register + */ +typedef union { + struct { + /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1; + * this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: + * enable + */ + uint32_t dsi_cfg_ref_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_host_ctrl_reg_t; + +/** Type of mem_clk_ctrl register + * dsi_bridge mem force on control register + */ +typedef union { + struct { + /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0; + * this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: + * force on + */ + uint32_t dsi_bridge_mem_clk_force_on:1; + /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + */ + uint32_t dsi_mem_clk_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_mem_clk_ctrl_reg_t; + +/** Type of dma_flow_ctrl register + * dsi_bridge dma flow controller register + */ +typedef union { + struct { + /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1; + * this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge + * as flow controller + */ + uint32_t dsi_dma_flow_controller:1; + uint32_t reserved_1:3; + /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1; + * this field configures the num of blocks when multi-blk is enable and dmac as flow + * controller + */ + uint32_t dma_flow_multiblk_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} dsi_brg_dma_flow_ctrl_reg_t; + +/** Type of raw_buf_almost_empty_thrd register + * dsi_bridge buffer empty threshold register + */ +typedef union { + struct { + /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512; + * this field configures the fifo almost empty threshold, is valid only when dmac as + * flow controller + */ + uint32_t dsi_raw_buf_almost_empty_thrd:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} dsi_brg_raw_buf_almost_empty_thrd_reg_t; + +/** Type of yuv_cfg register + * dsi_bridge yuv format config register + */ +typedef union { + struct { + /** protocol : R/W; bitpos: [0]; default: 0; + * this bit configures yuv protocol, 0: bt.601, 1: bt.709 + */ + uint32_t protocol:1; + /** yuv_pix_endian : R/W; bitpos: [1]; default: 0; + * this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + */ + uint32_t yuv_pix_endian:1; + /** yuv422_format : R/W; bitpos: [3:2]; default: 0; + * this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + */ + uint32_t yuv422_format:2; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_brg_yuv_cfg_reg_t; + +/** Type of phy_lp_loopback_ctrl register + * dsi phy lp_loopback test ctrl + */ +typedef union { + struct { + /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0; + * txdataesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txdataesc_1:8; + /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0; + * txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txrequestesc_1:1; + /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0; + * txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txvalidesc_1:1; + /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0; + * txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txlpdtesc_1:1; + /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0; + * basedir_1 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_basedir_1:1; + uint32_t reserved_12:4; + /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0; + * txdataesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txdataesc_0:8; + /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0; + * txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txrequestesc_0:1; + /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0; + * txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txvalidesc_0:1; + /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0; + * txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_txlpdtesc_0:1; + /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0; + * basedir_0 ctrl when enable dsi phy lp_loopback_test + */ + uint32_t phy_lp_basedir_0:1; + /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0; + * dsi phy lp_loopback test start check + */ + uint32_t phy_lp_loopback_check:1; + /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0; + * dsi phy lp_loopback test check done + */ + uint32_t phy_lp_loopback_check_done:1; + /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0; + * dsi phy lp_loopback ctrl en + */ + uint32_t phy_lp_loopback_en:1; + /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0; + * result of dsi phy lp_loopback test + */ + uint32_t phy_lp_loopback_ok:1; + }; + uint32_t val; +} dsi_brg_phy_lp_loopback_ctrl_reg_t; + +/** Type of phy_hs_loopback_ctrl register + * dsi phy hp_loopback test ctrl + */ +typedef union { + struct { + /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0; + * txdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txdatahs_1:8; + /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0; + * txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequestdatahs_1:1; + /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1; + * basedir_1 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_basedir_1:1; + uint32_t reserved_10:6; + /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0; + * txdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txdatahs_0:8; + /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0; + * txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequestdatahs_0:1; + /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0; + * basedir_0 ctrl when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_basedir_0:1; + uint32_t reserved_26:1; + /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0; + * txrequesthsclk when enable dsi phy hs_loopback_test + */ + uint32_t phy_hs_txrequesthsclk:1; + /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0; + * dsi phy hs_loopback test start check + */ + uint32_t phy_hs_loopback_check:1; + /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0; + * dsi phy hs_loopback test check done + */ + uint32_t phy_hs_loopback_check_done:1; + /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0; + * dsi phy hs_loopback ctrl en + */ + uint32_t phy_hs_loopback_en:1; + /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0; + * result of dsi phy hs_loopback test + */ + uint32_t phy_hs_loopback_ok:1; + }; + uint32_t val; +} dsi_brg_phy_hs_loopback_ctrl_reg_t; + +/** Type of phy_loopback_cnt register + * loopback test cnt + */ +typedef union { + struct { + /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64; + * hs_loopback test check cnt + */ + uint32_t phy_hs_check_cnt_th:8; + uint32_t reserved_8:8; + /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64; + * lp_loopback test check cnt + */ + uint32_t phy_lp_check_cnt_th:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_brg_phy_loopback_cnt_reg_t; + + +/** Group: Status Registers */ +/** Type of fifo_flow_status register + * dsi bridge raw buffer depth register + */ +typedef union { + struct { + /** raw_buf_depth : RO; bitpos: [13:0]; default: 0; + * this field configures the depth of dsi_bridge fifo depth + */ + uint32_t raw_buf_depth:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_brg_fifo_flow_status_reg_t; + +/** Type of host_bist_ctl register + * dsi_bridge host bist control register + */ +typedef union { + struct { + /** bistok : RO; bitpos: [0]; default: 0; + * bistok + */ + uint32_t bistok:1; + /** biston : R/W; bitpos: [1]; default: 0; + * biston + */ + uint32_t biston:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_host_bist_ctl_reg_t; + +/** Type of rdn_eco_cs register + * dsi_bridge rdn eco cs register + */ +typedef union { + struct { + /** rdn_eco_en : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ + uint32_t rdn_eco_en:1; + /** rdn_eco_result : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ + uint32_t rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_brg_rdn_eco_cs_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_ena register + * dsi_bridge interrupt enable register + */ +typedef union { + struct { + /** underrun_int_ena : R/W; bitpos: [0]; default: 0; + * write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled + * by dpi_underrun interrupt signal + */ + uint32_t underrun_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_int_ena_reg_t; + +/** Type of int_clr register + * dsi_bridge interrupt clear register + */ +typedef union { + struct { + /** underrun_int_clr : WT; bitpos: [0]; default: 0; + * write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ + uint32_t underrun_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_int_clr_reg_t; + +/** Type of int_raw register + * dsi_bridge raw interrupt register + */ +typedef union { + struct { + /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * the raw interrupt status of dpi_underrun + */ + uint32_t underrun_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_int_raw_reg_t; + +/** Type of int_st register + * dsi_bridge masked interrupt register + */ +typedef union { + struct { + /** underrun_int_st : RO; bitpos: [0]; default: 0; + * the masked interrupt status of dpi_underrun + */ + uint32_t underrun_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_brg_int_st_reg_t; + + +typedef struct dsi_brg_dev_t { + volatile dsi_brg_clk_en_reg_t clk_en; + volatile dsi_brg_en_reg_t en; + volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg; + volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg; + volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl; + volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status; + volatile dsi_brg_pixel_type_reg_t pixel_type; + volatile dsi_brg_dma_block_interval_reg_t dma_block_interval; + volatile dsi_brg_dma_req_interval_reg_t dma_req_interval; + volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl; + volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data; + uint32_t reserved_02c; + volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0; + volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1; + volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0; + volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1; + volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config; + volatile dsi_brg_dpi_config_update_reg_t dpi_config_update; + uint32_t reserved_048[2]; + volatile dsi_brg_int_ena_reg_t int_ena; + volatile dsi_brg_int_clr_reg_t int_clr; + volatile dsi_brg_int_raw_reg_t int_raw; + volatile dsi_brg_int_st_reg_t int_st; + volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl; + volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev; + volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg; + volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval; + volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl; + volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs; + volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low; + volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high; + volatile dsi_brg_host_ctrl_reg_t host_ctrl; + volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl; + volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl; + volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd; + volatile dsi_brg_yuv_cfg_reg_t yuv_cfg; + volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl; + volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl; + volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt; +} dsi_brg_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure"); +#endif + +extern dsi_brg_dev_t MIPI_DSI_BRIDGE; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h new file mode 100644 index 0000000000..496ea0095f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h @@ -0,0 +1,2007 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of version register + * NA + */ +typedef union { + struct { + /** version : RO; bitpos: [31:0]; default: 825504042; + * NA + */ + uint32_t version:32; + }; + uint32_t val; +} dsi_host_version_reg_t; + + +/** Group: Configuration Registers */ +/** Type of pwr_up register + * NA + */ +typedef union { + struct { + /** shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t shutdownz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_pwr_up_reg_t; + +/** Type of clkmgr_cfg register + * NA + */ +typedef union { + struct { + /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t tx_esc_clk_division:8; + /** to_clk_division : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t to_clk_division:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_clkmgr_cfg_reg_t; + +/** Type of dpi_vcid register + * NA + */ +typedef union { + struct { + /** dpi_vcid : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dpi_vcid:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dpi_vcid_reg_t; + +/** Type of dpi_color_coding register + * NA + */ +typedef union { + struct { + /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t dpi_color_coding:4; + uint32_t reserved_4:4; + /** loosely18_en : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t loosely18_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_dpi_color_coding_reg_t; + +/** Type of dpi_cfg_pol register + * NA + */ +typedef union { + struct { + /** dataen_active_low : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t dataen_active_low:1; + /** vsync_active_low : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t vsync_active_low:1; + /** hsync_active_low : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t hsync_active_low:1; + /** shutd_active_low : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t shutd_active_low:1; + /** colorm_active_low : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t colorm_active_low:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} dsi_host_dpi_cfg_pol_reg_t; + +/** Type of dpi_lp_cmd_tim register + * NA + */ +typedef union { + struct { + /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t invact_lpcmd_time:8; + uint32_t reserved_8:8; + /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t outvact_lpcmd_time:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_dpi_lp_cmd_tim_reg_t; + +/** Type of dbi_vcid register + * NA + */ +typedef union { + struct { + /** dbi_vcid : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dbi_vcid:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dbi_vcid_reg_t; + +/** Type of dbi_cfg register + * NA + */ +typedef union { + struct { + /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t in_dbi_conf:4; + uint32_t reserved_4:4; + /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0; + * NA + */ + uint32_t out_dbi_conf:4; + uint32_t reserved_12:4; + /** lut_size_conf : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t lut_size_conf:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_dbi_cfg_reg_t; + +/** Type of dbi_partitioning_en register + * NA + */ +typedef union { + struct { + /** partitioning_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t partitioning_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_dbi_partitioning_en_reg_t; + +/** Type of dbi_cmdsize register + * NA + */ +typedef union { + struct { + /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t wr_cmd_size:16; + /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t allowed_cmd_size:16; + }; + uint32_t val; +} dsi_host_dbi_cmdsize_reg_t; + +/** Type of pckhdl_cfg register + * NA + */ +typedef union { + struct { + /** eotp_tx_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t eotp_tx_en:1; + /** eotp_rx_en : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t eotp_rx_en:1; + /** bta_en : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t bta_en:1; + /** ecc_rx_en : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t ecc_rx_en:1; + /** crc_rx_en : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t crc_rx_en:1; + /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t eotp_tx_lp_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} dsi_host_pckhdl_cfg_reg_t; + +/** Type of gen_vcid register + * NA + */ +typedef union { + struct { + /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t gen_vcid_rx:2; + uint32_t reserved_2:6; + /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0; + * NA + */ + uint32_t gen_vcid_tear_auto:2; + uint32_t reserved_10:6; + /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t gen_vcid_tx_auto:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_gen_vcid_reg_t; + +/** Type of mode_cfg register + * NA + */ +typedef union { + struct { + /** cmd_video_mode : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t cmd_video_mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_mode_cfg_reg_t; + +/** Type of vid_mode_cfg register + * NA + */ +typedef union { + struct { + /** vid_mode_type : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t vid_mode_type:2; + uint32_t reserved_2:6; + /** lp_vsa_en : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t lp_vsa_en:1; + /** lp_vbp_en : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t lp_vbp_en:1; + /** lp_vfp_en : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t lp_vfp_en:1; + /** lp_vact_en : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t lp_vact_en:1; + /** lp_hbp_en : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t lp_hbp_en:1; + /** lp_hfp_en : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t lp_hfp_en:1; + /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t frame_bta_ack_en:1; + /** lp_cmd_en : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t lp_cmd_en:1; + /** vpg_en : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t vpg_en:1; + uint32_t reserved_17:3; + /** vpg_mode : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t vpg_mode:1; + uint32_t reserved_21:3; + /** vpg_orientation : R/W; bitpos: [24]; default: 0; + * NA + */ + uint32_t vpg_orientation:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} dsi_host_vid_mode_cfg_reg_t; + +/** Type of vid_pkt_size register + * NA + */ +typedef union { + struct { + /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t vid_pkt_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_pkt_size_reg_t; + +/** Type of vid_num_chunks register + * NA + */ +typedef union { + struct { + /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_num_chunks:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_num_chunks_reg_t; + +/** Type of vid_null_size register + * NA + */ +typedef union { + struct { + /** vid_null_size : R/W; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_null_size:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_null_size_reg_t; + +/** Type of vid_hsa_time register + * NA + */ +typedef union { + struct { + /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hsa_time:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hsa_time_reg_t; + +/** Type of vid_hbp_time register + * NA + */ +typedef union { + struct { + /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hbp_time:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hbp_time_reg_t; + +/** Type of vid_hline_time register + * NA + */ +typedef union { + struct { + /** vid_hline_time : R/W; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t vid_hline_time:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_vid_hline_time_reg_t; + +/** Type of vid_vsa_lines register + * NA + */ +typedef union { + struct { + /** vsa_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vsa_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vsa_lines_reg_t; + +/** Type of vid_vbp_lines register + * NA + */ +typedef union { + struct { + /** vbp_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vbp_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vbp_lines_reg_t; + +/** Type of vid_vfp_lines register + * NA + */ +typedef union { + struct { + /** vfp_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vfp_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vfp_lines_reg_t; + +/** Type of vid_vactive_lines register + * NA + */ +typedef union { + struct { + /** v_active_lines : R/W; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t v_active_lines:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_vactive_lines_reg_t; + +/** Type of edpi_cmd_size register + * NA + */ +typedef union { + struct { + /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t edpi_allowed_cmd_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_edpi_cmd_size_reg_t; + +/** Type of cmd_mode_cfg register + * NA + */ +typedef union { + struct { + /** tear_fx_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t tear_fx_en:1; + /** ack_rqst_en : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t ack_rqst_en:1; + uint32_t reserved_2:6; + /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t gen_sw_0p_tx:1; + /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t gen_sw_1p_tx:1; + /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t gen_sw_2p_tx:1; + /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t gen_sr_0p_tx:1; + /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t gen_sr_1p_tx:1; + /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t gen_sr_2p_tx:1; + /** gen_lw_tx : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t gen_lw_tx:1; + uint32_t reserved_15:1; + /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t dcs_sw_0p_tx:1; + /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t dcs_sw_1p_tx:1; + /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t dcs_sr_0p_tx:1; + /** dcs_lw_tx : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t dcs_lw_tx:1; + uint32_t reserved_20:4; + /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0; + * NA + */ + uint32_t max_rd_pkt_size:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} dsi_host_cmd_mode_cfg_reg_t; + +/** Type of gen_hdr register + * NA + */ +typedef union { + struct { + /** gen_dt : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t gen_dt:6; + /** gen_vc : R/W; bitpos: [7:6]; default: 0; + * NA + */ + uint32_t gen_vc:2; + /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t gen_wc_lsbyte:8; + /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t gen_wc_msbyte:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_gen_hdr_reg_t; + +/** Type of gen_pld_data register + * NA + */ +typedef union { + struct { + /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t gen_pld_b1:8; + /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t gen_pld_b2:8; + /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t gen_pld_b3:8; + /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0; + * NA + */ + uint32_t gen_pld_b4:8; + }; + uint32_t val; +} dsi_host_gen_pld_data_reg_t; + +/** Type of to_cnt_cfg register + * NA + */ +typedef union { + struct { + /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lprx_to_cnt:16; + /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t hstx_to_cnt:16; + }; + uint32_t val; +} dsi_host_to_cnt_cfg_reg_t; + +/** Type of hs_rd_to_cnt register + * NA + */ +typedef union { + struct { + /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t hs_rd_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_hs_rd_to_cnt_reg_t; + +/** Type of lp_rd_to_cnt register + * NA + */ +typedef union { + struct { + /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lp_rd_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_lp_rd_to_cnt_reg_t; + +/** Type of hs_wr_to_cnt register + * NA + */ +typedef union { + struct { + /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t hs_wr_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_hs_wr_to_cnt_reg_t; + +/** Type of lp_wr_to_cnt register + * NA + */ +typedef union { + struct { + /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lp_wr_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_lp_wr_to_cnt_reg_t; + +/** Type of bta_to_cnt register + * NA + */ +typedef union { + struct { + /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t bta_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_bta_to_cnt_reg_t; + +/** Type of sdf_3d register + * NA + */ +typedef union { + struct { + /** mode_3d : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t mode_3d:2; + /** format_3d : R/W; bitpos: [3:2]; default: 0; + * NA + */ + uint32_t format_3d:2; + /** second_vsync : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t second_vsync:1; + /** right_first : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t right_first:1; + uint32_t reserved_6:10; + /** send_3d_cfg : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t send_3d_cfg:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_sdf_3d_reg_t; + +/** Type of lpclk_ctrl register + * NA + */ +typedef union { + struct { + /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_txrequestclkhs:1; + /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t auto_clklane_ctrl:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_lpclk_ctrl_reg_t; + +/** Type of phy_tmr_lpclk_cfg register + * NA + */ +typedef union { + struct { + /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t phy_clklp2hs_time:10; + uint32_t reserved_10:6; + /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0; + * NA + */ + uint32_t phy_clkhs2lp_time:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} dsi_host_phy_tmr_lpclk_cfg_reg_t; + +/** Type of phy_tmr_cfg register + * NA + */ +typedef union { + struct { + /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t phy_lp2hs_time:10; + uint32_t reserved_10:6; + /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0; + * NA + */ + uint32_t phy_hs2lp_time:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} dsi_host_phy_tmr_cfg_reg_t; + +/** Type of phy_rstz register + * NA + */ +typedef union { + struct { + /** phy_shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_shutdownz:1; + /** phy_rstz : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_rstz:1; + /** phy_enableclk : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_enableclk:1; + /** phy_forcepll : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_forcepll:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_rstz_reg_t; + +/** Type of phy_if_cfg register + * NA + */ +typedef union { + struct { + /** n_lanes : R/W; bitpos: [1:0]; default: 1; + * NA + */ + uint32_t n_lanes:2; + uint32_t reserved_2:6; + /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t phy_stop_wait_time:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_phy_if_cfg_reg_t; + +/** Type of phy_ulps_ctrl register + * NA + */ +typedef union { + struct { + /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_txrequlpsclk:1; + /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_txexitulpsclk:1; + /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_txrequlpslan:1; + /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_txexitulpslan:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_ulps_ctrl_reg_t; + +/** Type of phy_tx_triggers register + * NA + */ +typedef union { + struct { + /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t phy_tx_triggers:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_tx_triggers_reg_t; + +/** Type of phy_tst_ctrl0 register + * NA + */ +typedef union { + struct { + /** phy_testclr : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t phy_testclr:1; + /** phy_testclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_testclk:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_phy_tst_ctrl0_reg_t; + +/** Type of phy_tst_ctrl1 register + * NA + */ +typedef union { + struct { + /** phy_testdin : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t phy_testdin:8; + /** pht_testdout : RO; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t pht_testdout:8; + /** phy_testen : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_testen:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_phy_tst_ctrl1_reg_t; + +/** Type of phy_cal register + * NA + */ +typedef union { + struct { + /** txskewcalhs : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t txskewcalhs:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_phy_cal_reg_t; + +/** Type of dsc_parameter register + * NA + */ +typedef union { + struct { + /** compression_mode : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t compression_mode:1; + uint32_t reserved_1:7; + /** compress_algo : R/W; bitpos: [9:8]; default: 0; + * NA + */ + uint32_t compress_algo:2; + uint32_t reserved_10:6; + /** pps_sel : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t pps_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_dsc_parameter_reg_t; + +/** Type of phy_tmr_rd_cfg register + * NA + */ +typedef union { + struct { + /** max_rd_time : R/W; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t max_rd_time:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_phy_tmr_rd_cfg_reg_t; + +/** Type of vid_shadow_ctrl register + * NA + */ +typedef union { + struct { + /** vid_shadow_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t vid_shadow_en:1; + uint32_t reserved_1:7; + /** vid_shadow_req : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t vid_shadow_req:1; + uint32_t reserved_9:7; + /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t vid_shadow_pin_req:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_vid_shadow_ctrl_reg_t; + +/** Type of edpi_te_hw_cfg register + * NA + */ +typedef union { + struct { + /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t hw_tear_effect_on:1; + /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t hw_tear_effect_gen:1; + uint32_t reserved_2:2; + /** hw_set_scan_line : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t hw_set_scan_line:1; + uint32_t reserved_5:11; + /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t scan_line_parameter:16; + }; + uint32_t val; +} dsi_host_edpi_te_hw_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of cmd_pkt_status register + * NA + */ +typedef union { + struct { + /** gen_cmd_empty : RO; bitpos: [0]; default: 1; + * NA + */ + uint32_t gen_cmd_empty:1; + /** gen_cmd_full : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t gen_cmd_full:1; + /** gen_pld_w_empty : RO; bitpos: [2]; default: 1; + * NA + */ + uint32_t gen_pld_w_empty:1; + /** gen_pld_w_full : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t gen_pld_w_full:1; + /** gen_pld_r_empty : RO; bitpos: [4]; default: 1; + * NA + */ + uint32_t gen_pld_r_empty:1; + /** gen_pld_r_full : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t gen_pld_r_full:1; + /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t gen_rd_cmd_busy:1; + uint32_t reserved_7:9; + /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t gen_buff_cmd_empty:1; + /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t gen_buff_cmd_full:1; + /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1; + * NA + */ + uint32_t gen_buff_pld_empty:1; + /** gen_buff_pld_full : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t gen_buff_pld_full:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_cmd_pkt_status_reg_t; + +/** Type of phy_status register + * NA + */ +typedef union { + struct { + /** phy_lock : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_lock:1; + /** phy_direction : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_direction:1; + /** phy_stopstateclklane : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_stopstateclklane:1; + /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_ulpsactivenotclk:1; + /** phy_stopstate0lane : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t phy_stopstate0lane:1; + /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t phy_ulpsactivenot0lane:1; + /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1; + * NA + */ + uint32_t phy_rxulpsesc0lane:1; + /** phy_stopstate1lane : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t phy_stopstate1lane:1; + /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1; + * NA + */ + uint32_t phy_ulpsactivenot1lane:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_phy_status_reg_t; + +/** Type of dpi_vcid_act register + * NA + */ +typedef union { + struct { + /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dpi_vcid_act:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dpi_vcid_act_reg_t; + +/** Type of dpi_color_coding_act register + * NA + */ +typedef union { + struct { + /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t dpi_color_coding_act:4; + uint32_t reserved_4:4; + /** loosely18_en_act : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t loosely18_en_act:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_dpi_color_coding_act_reg_t; + +/** Type of dpi_lp_cmd_tim_act register + * NA + */ +typedef union { + struct { + /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t invact_lpcmd_time_act:8; + uint32_t reserved_8:8; + /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t outvact_lpcmd_time_act:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_dpi_lp_cmd_tim_act_reg_t; + +/** Type of vid_mode_cfg_act register + * NA + */ +typedef union { + struct { + /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t vid_mode_type_act:2; + /** lp_vsa_en_act : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t lp_vsa_en_act:1; + /** lp_vbp_en_act : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t lp_vbp_en_act:1; + /** lp_vfp_en_act : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t lp_vfp_en_act:1; + /** lp_vact_en_act : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t lp_vact_en_act:1; + /** lp_hbp_en_act : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t lp_hbp_en_act:1; + /** lp_hfp_en_act : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t lp_hfp_en_act:1; + /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t frame_bta_ack_en_act:1; + /** lp_cmd_en_act : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t lp_cmd_en_act:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_mode_cfg_act_reg_t; + +/** Type of vid_pkt_size_act register + * NA + */ +typedef union { + struct { + /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t vid_pkt_size_act:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_pkt_size_act_reg_t; + +/** Type of vid_num_chunks_act register + * NA + */ +typedef union { + struct { + /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_num_chunks_act:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_num_chunks_act_reg_t; + +/** Type of vid_null_size_act register + * NA + */ +typedef union { + struct { + /** vid_null_size_act : RO; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_null_size_act:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_null_size_act_reg_t; + +/** Type of vid_hsa_time_act register + * NA + */ +typedef union { + struct { + /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hsa_time_act:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hsa_time_act_reg_t; + +/** Type of vid_hbp_time_act register + * NA + */ +typedef union { + struct { + /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hbp_time_act:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hbp_time_act_reg_t; + +/** Type of vid_hline_time_act register + * NA + */ +typedef union { + struct { + /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t vid_hline_time_act:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_vid_hline_time_act_reg_t; + +/** Type of vid_vsa_lines_act register + * NA + */ +typedef union { + struct { + /** vsa_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vsa_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vsa_lines_act_reg_t; + +/** Type of vid_vbp_lines_act register + * NA + */ +typedef union { + struct { + /** vbp_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vbp_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vbp_lines_act_reg_t; + +/** Type of vid_vfp_lines_act register + * NA + */ +typedef union { + struct { + /** vfp_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vfp_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vfp_lines_act_reg_t; + +/** Type of vid_vactive_lines_act register + * NA + */ +typedef union { + struct { + /** v_active_lines_act : RO; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t v_active_lines_act:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_vactive_lines_act_reg_t; + +/** Type of vid_pkt_status register + * NA + */ +typedef union { + struct { + /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1; + * NA + */ + uint32_t dpi_cmd_w_empty:1; + /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t dpi_cmd_w_full:1; + /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1; + * NA + */ + uint32_t dpi_pld_w_empty:1; + /** dpi_pld_w_full : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t dpi_pld_w_full:1; + uint32_t reserved_4:12; + /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t dpi_buff_pld_empty:1; + /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t dpi_buff_pld_full:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_vid_pkt_status_reg_t; + +/** Type of sdf_3d_act register + * NA + */ +typedef union { + struct { + /** mode_3d_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t mode_3d_act:2; + /** format_3d_act : RO; bitpos: [3:2]; default: 0; + * NA + */ + uint32_t format_3d_act:2; + /** second_vsync_act : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t second_vsync_act:1; + /** right_first_act : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t right_first_act:1; + uint32_t reserved_6:10; + /** send_3d_cfg_act : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t send_3d_cfg_act:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_sdf_3d_act_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_st0 register + * NA + */ +typedef union { + struct { + /** ack_with_err_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t ack_with_err_0:1; + /** ack_with_err_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t ack_with_err_1:1; + /** ack_with_err_2 : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t ack_with_err_2:1; + /** ack_with_err_3 : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t ack_with_err_3:1; + /** ack_with_err_4 : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t ack_with_err_4:1; + /** ack_with_err_5 : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t ack_with_err_5:1; + /** ack_with_err_6 : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t ack_with_err_6:1; + /** ack_with_err_7 : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t ack_with_err_7:1; + /** ack_with_err_8 : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t ack_with_err_8:1; + /** ack_with_err_9 : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t ack_with_err_9:1; + /** ack_with_err_10 : RO; bitpos: [10]; default: 0; + * NA + */ + uint32_t ack_with_err_10:1; + /** ack_with_err_11 : RO; bitpos: [11]; default: 0; + * NA + */ + uint32_t ack_with_err_11:1; + /** ack_with_err_12 : RO; bitpos: [12]; default: 0; + * NA + */ + uint32_t ack_with_err_12:1; + /** ack_with_err_13 : RO; bitpos: [13]; default: 0; + * NA + */ + uint32_t ack_with_err_13:1; + /** ack_with_err_14 : RO; bitpos: [14]; default: 0; + * NA + */ + uint32_t ack_with_err_14:1; + /** ack_with_err_15 : RO; bitpos: [15]; default: 0; + * NA + */ + uint32_t ack_with_err_15:1; + /** dphy_errors_0 : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t dphy_errors_0:1; + /** dphy_errors_1 : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t dphy_errors_1:1; + /** dphy_errors_2 : RO; bitpos: [18]; default: 0; + * NA + */ + uint32_t dphy_errors_2:1; + /** dphy_errors_3 : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t dphy_errors_3:1; + /** dphy_errors_4 : RO; bitpos: [20]; default: 0; + * NA + */ + uint32_t dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_st0_reg_t; + +/** Type of int_st1 register + * NA + */ +typedef union { + struct { + /** to_hs_tx : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t to_hs_tx:1; + /** to_lp_rx : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t to_lp_rx:1; + /** ecc_single_err : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t ecc_single_err:1; + /** ecc_milti_err : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t ecc_milti_err:1; + /** crc_err : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t crc_err:1; + /** pkt_size_err : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t pkt_size_err:1; + /** eopt_err : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t eopt_err:1; + /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t dpi_pld_wr_err:1; + /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t gen_cmd_wr_err:1; + /** gen_pld_wr_err : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t gen_pld_wr_err:1; + /** gen_pld_send_err : RO; bitpos: [10]; default: 0; + * NA + */ + uint32_t gen_pld_send_err:1; + /** gen_pld_rd_err : RO; bitpos: [11]; default: 0; + * NA + */ + uint32_t gen_pld_rd_err:1; + /** gen_pld_recev_err : RO; bitpos: [12]; default: 0; + * NA + */ + uint32_t gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_st1_reg_t; + +/** Type of int_msk0 register + * NA + */ +typedef union { + struct { + /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_0:1; + /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_1:1; + /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_2:1; + /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_3:1; + /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_4:1; + /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_5:1; + /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_6:1; + /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_7:1; + /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_8:1; + /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_9:1; + /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_10:1; + /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_11:1; + /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_12:1; + /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_13:1; + /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_14:1; + /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_15:1; + /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_0:1; + /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_1:1; + /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_2:1; + /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_3:1; + /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_msk0_reg_t; + +/** Type of int_msk1 register + * NA + */ +typedef union { + struct { + /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_to_hs_tx:1; + /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_to_lp_rx:1; + /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_ecc_single_err:1; + /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_ecc_milti_err:1; + /** mask_crc_err : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_crc_err:1; + /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_pkt_size_err:1; + /** mask_eopt_err : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_eopt_err:1; + /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_dpi_pld_wr_err:1; + /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_gen_cmd_wr_err:1; + /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_gen_pld_wr_err:1; + /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_gen_pld_send_err:1; + /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_gen_pld_rd_err:1; + /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t mask_dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_msk1_reg_t; + +/** Type of int_force0 register + * NA + */ +typedef union { + struct { + /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_ack_with_err_0:1; + /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_ack_with_err_1:1; + /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_ack_with_err_2:1; + /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_ack_with_err_3:1; + /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_ack_with_err_4:1; + /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_ack_with_err_5:1; + /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_ack_with_err_6:1; + /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_ack_with_err_7:1; + /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_ack_with_err_8:1; + /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_ack_with_err_9:1; + /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_ack_with_err_10:1; + /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_ack_with_err_11:1; + /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_ack_with_err_12:1; + /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_ack_with_err_13:1; + /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_ack_with_err_14:1; + /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_ack_with_err_15:1; + /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t force_dphy_errors_0:1; + /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t force_dphy_errors_1:1; + /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t force_dphy_errors_2:1; + /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t force_dphy_errors_3:1; + /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t force_dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_force0_reg_t; + +/** Type of int_force1 register + * NA + */ +typedef union { + struct { + /** force_to_hs_tx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_to_hs_tx:1; + /** force_to_lp_rx : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_to_lp_rx:1; + /** force_ecc_single_err : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_ecc_single_err:1; + /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_ecc_milti_err:1; + /** force_crc_err : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_crc_err:1; + /** force_pkt_size_err : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_pkt_size_err:1; + /** force_eopt_err : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_eopt_err:1; + /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_dpi_pld_wr_err:1; + /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_gen_cmd_wr_err:1; + /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_gen_pld_wr_err:1; + /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_gen_pld_send_err:1; + /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_gen_pld_rd_err:1; + /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t force_dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_force1_reg_t; + + +typedef struct { + volatile dsi_host_version_reg_t version; + volatile dsi_host_pwr_up_reg_t pwr_up; + volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg; + volatile dsi_host_dpi_vcid_reg_t dpi_vcid; + volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding; + volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol; + volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim; + volatile dsi_host_dbi_vcid_reg_t dbi_vcid; + volatile dsi_host_dbi_cfg_reg_t dbi_cfg; + volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en; + volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize; + volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg; + volatile dsi_host_gen_vcid_reg_t gen_vcid; + volatile dsi_host_mode_cfg_reg_t mode_cfg; + volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg; + volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size; + volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks; + volatile dsi_host_vid_null_size_reg_t vid_null_size; + volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time; + volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time; + volatile dsi_host_vid_hline_time_reg_t vid_hline_time; + volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines; + volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines; + volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines; + volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines; + volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size; + volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg; + volatile dsi_host_gen_hdr_reg_t gen_hdr; + volatile dsi_host_gen_pld_data_reg_t gen_pld_data; + volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status; + volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg; + volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt; + volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt; + volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt; + volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt; + volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt; + volatile dsi_host_sdf_3d_reg_t sdf_3d; + volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl; + volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg; + volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg; + volatile dsi_host_phy_rstz_reg_t phy_rstz; + volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg; + volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl; + volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers; + volatile dsi_host_phy_status_reg_t phy_status; + volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0; + volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1; + volatile dsi_host_int_st0_reg_t int_st0; + volatile dsi_host_int_st1_reg_t int_st1; + volatile dsi_host_int_msk0_reg_t int_msk0; + volatile dsi_host_int_msk1_reg_t int_msk1; + volatile dsi_host_phy_cal_reg_t phy_cal; + uint32_t reserved_0d0[2]; + volatile dsi_host_int_force0_reg_t int_force0; + volatile dsi_host_int_force1_reg_t int_force1; + uint32_t reserved_0e0[4]; + volatile dsi_host_dsc_parameter_reg_t dsc_parameter; + volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg; + uint32_t reserved_0f8[2]; + volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl; + uint32_t reserved_104[2]; + volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act; + volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act; + uint32_t reserved_114; + volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act; + volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg; + uint32_t reserved_120[6]; + volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act; + volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act; + volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act; + volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act; + volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act; + volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act; + volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act; + volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act; + volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act; + volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act; + volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act; + uint32_t reserved_164; + volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status; + uint32_t reserved_16c[9]; + volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act; +} dsi_host_dev_t; + +extern dsi_host_dev_t MIPI_DSI_HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_reg.h new file mode 100644 index 0000000000..424140762b --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_reg.h @@ -0,0 +1,2360 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DSI_HOST_VERSION_REG register + * NA + */ +#define DSI_HOST_VERSION_REG (DR_REG_DSI_HOST_BASE + 0x0) +/** DSI_HOST_VERSION : RO; bitpos: [31:0]; default: 825504042; + * NA + */ +#define DSI_HOST_VERSION 0xFFFFFFFFU +#define DSI_HOST_VERSION_M (DSI_HOST_VERSION_V << DSI_HOST_VERSION_S) +#define DSI_HOST_VERSION_V 0xFFFFFFFFU +#define DSI_HOST_VERSION_S 0 + +/** DSI_HOST_PWR_UP_REG register + * NA + */ +#define DSI_HOST_PWR_UP_REG (DR_REG_DSI_HOST_BASE + 0x4) +/** DSI_HOST_SHUTDOWNZ : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_SHUTDOWNZ (BIT(0)) +#define DSI_HOST_SHUTDOWNZ_M (DSI_HOST_SHUTDOWNZ_V << DSI_HOST_SHUTDOWNZ_S) +#define DSI_HOST_SHUTDOWNZ_V 0x00000001U +#define DSI_HOST_SHUTDOWNZ_S 0 + +/** DSI_HOST_CLKMGR_CFG_REG register + * NA + */ +#define DSI_HOST_CLKMGR_CFG_REG (DR_REG_DSI_HOST_BASE + 0x8) +/** DSI_HOST_TX_ESC_CLK_DIVISION : R/W; bitpos: [7:0]; default: 0; + * NA + */ +#define DSI_HOST_TX_ESC_CLK_DIVISION 0x000000FFU +#define DSI_HOST_TX_ESC_CLK_DIVISION_M (DSI_HOST_TX_ESC_CLK_DIVISION_V << DSI_HOST_TX_ESC_CLK_DIVISION_S) +#define DSI_HOST_TX_ESC_CLK_DIVISION_V 0x000000FFU +#define DSI_HOST_TX_ESC_CLK_DIVISION_S 0 +/** DSI_HOST_TO_CLK_DIVISION : R/W; bitpos: [15:8]; default: 0; + * NA + */ +#define DSI_HOST_TO_CLK_DIVISION 0x000000FFU +#define DSI_HOST_TO_CLK_DIVISION_M (DSI_HOST_TO_CLK_DIVISION_V << DSI_HOST_TO_CLK_DIVISION_S) +#define DSI_HOST_TO_CLK_DIVISION_V 0x000000FFU +#define DSI_HOST_TO_CLK_DIVISION_S 8 + +/** DSI_HOST_DPI_VCID_REG register + * NA + */ +#define DSI_HOST_DPI_VCID_REG (DR_REG_DSI_HOST_BASE + 0xc) +/** DSI_HOST_DPI_VCID : R/W; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_DPI_VCID 0x00000003U +#define DSI_HOST_DPI_VCID_M (DSI_HOST_DPI_VCID_V << DSI_HOST_DPI_VCID_S) +#define DSI_HOST_DPI_VCID_V 0x00000003U +#define DSI_HOST_DPI_VCID_S 0 + +/** DSI_HOST_DPI_COLOR_CODING_REG register + * NA + */ +#define DSI_HOST_DPI_COLOR_CODING_REG (DR_REG_DSI_HOST_BASE + 0x10) +/** DSI_HOST_DPI_COLOR_CODING : R/W; bitpos: [3:0]; default: 0; + * NA + */ +#define DSI_HOST_DPI_COLOR_CODING 0x0000000FU +#define DSI_HOST_DPI_COLOR_CODING_M (DSI_HOST_DPI_COLOR_CODING_V << DSI_HOST_DPI_COLOR_CODING_S) +#define DSI_HOST_DPI_COLOR_CODING_V 0x0000000FU +#define DSI_HOST_DPI_COLOR_CODING_S 0 +/** DSI_HOST_LOOSELY18_EN : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_LOOSELY18_EN (BIT(8)) +#define DSI_HOST_LOOSELY18_EN_M (DSI_HOST_LOOSELY18_EN_V << DSI_HOST_LOOSELY18_EN_S) +#define DSI_HOST_LOOSELY18_EN_V 0x00000001U +#define DSI_HOST_LOOSELY18_EN_S 8 + +/** DSI_HOST_DPI_CFG_POL_REG register + * NA + */ +#define DSI_HOST_DPI_CFG_POL_REG (DR_REG_DSI_HOST_BASE + 0x14) +/** DSI_HOST_DATAEN_ACTIVE_LOW : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_DATAEN_ACTIVE_LOW (BIT(0)) +#define DSI_HOST_DATAEN_ACTIVE_LOW_M (DSI_HOST_DATAEN_ACTIVE_LOW_V << DSI_HOST_DATAEN_ACTIVE_LOW_S) +#define DSI_HOST_DATAEN_ACTIVE_LOW_V 0x00000001U +#define DSI_HOST_DATAEN_ACTIVE_LOW_S 0 +/** DSI_HOST_VSYNC_ACTIVE_LOW : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_VSYNC_ACTIVE_LOW (BIT(1)) +#define DSI_HOST_VSYNC_ACTIVE_LOW_M (DSI_HOST_VSYNC_ACTIVE_LOW_V << DSI_HOST_VSYNC_ACTIVE_LOW_S) +#define DSI_HOST_VSYNC_ACTIVE_LOW_V 0x00000001U +#define DSI_HOST_VSYNC_ACTIVE_LOW_S 1 +/** DSI_HOST_HSYNC_ACTIVE_LOW : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_HSYNC_ACTIVE_LOW (BIT(2)) +#define DSI_HOST_HSYNC_ACTIVE_LOW_M (DSI_HOST_HSYNC_ACTIVE_LOW_V << DSI_HOST_HSYNC_ACTIVE_LOW_S) +#define DSI_HOST_HSYNC_ACTIVE_LOW_V 0x00000001U +#define DSI_HOST_HSYNC_ACTIVE_LOW_S 2 +/** DSI_HOST_SHUTD_ACTIVE_LOW : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_SHUTD_ACTIVE_LOW (BIT(3)) +#define DSI_HOST_SHUTD_ACTIVE_LOW_M (DSI_HOST_SHUTD_ACTIVE_LOW_V << DSI_HOST_SHUTD_ACTIVE_LOW_S) +#define DSI_HOST_SHUTD_ACTIVE_LOW_V 0x00000001U +#define DSI_HOST_SHUTD_ACTIVE_LOW_S 3 +/** DSI_HOST_COLORM_ACTIVE_LOW : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_COLORM_ACTIVE_LOW (BIT(4)) +#define DSI_HOST_COLORM_ACTIVE_LOW_M (DSI_HOST_COLORM_ACTIVE_LOW_V << DSI_HOST_COLORM_ACTIVE_LOW_S) +#define DSI_HOST_COLORM_ACTIVE_LOW_V 0x00000001U +#define DSI_HOST_COLORM_ACTIVE_LOW_S 4 + +/** DSI_HOST_DPI_LP_CMD_TIM_REG register + * NA + */ +#define DSI_HOST_DPI_LP_CMD_TIM_REG (DR_REG_DSI_HOST_BASE + 0x18) +/** DSI_HOST_INVACT_LPCMD_TIME : R/W; bitpos: [7:0]; default: 0; + * NA + */ +#define DSI_HOST_INVACT_LPCMD_TIME 0x000000FFU +#define DSI_HOST_INVACT_LPCMD_TIME_M (DSI_HOST_INVACT_LPCMD_TIME_V << DSI_HOST_INVACT_LPCMD_TIME_S) +#define DSI_HOST_INVACT_LPCMD_TIME_V 0x000000FFU +#define DSI_HOST_INVACT_LPCMD_TIME_S 0 +/** DSI_HOST_OUTVACT_LPCMD_TIME : R/W; bitpos: [23:16]; default: 0; + * NA + */ +#define DSI_HOST_OUTVACT_LPCMD_TIME 0x000000FFU +#define DSI_HOST_OUTVACT_LPCMD_TIME_M (DSI_HOST_OUTVACT_LPCMD_TIME_V << DSI_HOST_OUTVACT_LPCMD_TIME_S) +#define DSI_HOST_OUTVACT_LPCMD_TIME_V 0x000000FFU +#define DSI_HOST_OUTVACT_LPCMD_TIME_S 16 + +/** DSI_HOST_DBI_VCID_REG register + * NA + */ +#define DSI_HOST_DBI_VCID_REG (DR_REG_DSI_HOST_BASE + 0x1c) +/** DSI_HOST_DBI_VCID : R/W; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_DBI_VCID 0x00000003U +#define DSI_HOST_DBI_VCID_M (DSI_HOST_DBI_VCID_V << DSI_HOST_DBI_VCID_S) +#define DSI_HOST_DBI_VCID_V 0x00000003U +#define DSI_HOST_DBI_VCID_S 0 + +/** DSI_HOST_DBI_CFG_REG register + * NA + */ +#define DSI_HOST_DBI_CFG_REG (DR_REG_DSI_HOST_BASE + 0x20) +/** DSI_HOST_IN_DBI_CONF : R/W; bitpos: [3:0]; default: 0; + * NA + */ +#define DSI_HOST_IN_DBI_CONF 0x0000000FU +#define DSI_HOST_IN_DBI_CONF_M (DSI_HOST_IN_DBI_CONF_V << DSI_HOST_IN_DBI_CONF_S) +#define DSI_HOST_IN_DBI_CONF_V 0x0000000FU +#define DSI_HOST_IN_DBI_CONF_S 0 +/** DSI_HOST_OUT_DBI_CONF : R/W; bitpos: [11:8]; default: 0; + * NA + */ +#define DSI_HOST_OUT_DBI_CONF 0x0000000FU +#define DSI_HOST_OUT_DBI_CONF_M (DSI_HOST_OUT_DBI_CONF_V << DSI_HOST_OUT_DBI_CONF_S) +#define DSI_HOST_OUT_DBI_CONF_V 0x0000000FU +#define DSI_HOST_OUT_DBI_CONF_S 8 +/** DSI_HOST_LUT_SIZE_CONF : R/W; bitpos: [17:16]; default: 0; + * NA + */ +#define DSI_HOST_LUT_SIZE_CONF 0x00000003U +#define DSI_HOST_LUT_SIZE_CONF_M (DSI_HOST_LUT_SIZE_CONF_V << DSI_HOST_LUT_SIZE_CONF_S) +#define DSI_HOST_LUT_SIZE_CONF_V 0x00000003U +#define DSI_HOST_LUT_SIZE_CONF_S 16 + +/** DSI_HOST_DBI_PARTITIONING_EN_REG register + * NA + */ +#define DSI_HOST_DBI_PARTITIONING_EN_REG (DR_REG_DSI_HOST_BASE + 0x24) +/** DSI_HOST_PARTITIONING_EN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_PARTITIONING_EN (BIT(0)) +#define DSI_HOST_PARTITIONING_EN_M (DSI_HOST_PARTITIONING_EN_V << DSI_HOST_PARTITIONING_EN_S) +#define DSI_HOST_PARTITIONING_EN_V 0x00000001U +#define DSI_HOST_PARTITIONING_EN_S 0 + +/** DSI_HOST_DBI_CMDSIZE_REG register + * NA + */ +#define DSI_HOST_DBI_CMDSIZE_REG (DR_REG_DSI_HOST_BASE + 0x28) +/** DSI_HOST_WR_CMD_SIZE : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_WR_CMD_SIZE 0x0000FFFFU +#define DSI_HOST_WR_CMD_SIZE_M (DSI_HOST_WR_CMD_SIZE_V << DSI_HOST_WR_CMD_SIZE_S) +#define DSI_HOST_WR_CMD_SIZE_V 0x0000FFFFU +#define DSI_HOST_WR_CMD_SIZE_S 0 +/** DSI_HOST_ALLOWED_CMD_SIZE : R/W; bitpos: [31:16]; default: 0; + * NA + */ +#define DSI_HOST_ALLOWED_CMD_SIZE 0x0000FFFFU +#define DSI_HOST_ALLOWED_CMD_SIZE_M (DSI_HOST_ALLOWED_CMD_SIZE_V << DSI_HOST_ALLOWED_CMD_SIZE_S) +#define DSI_HOST_ALLOWED_CMD_SIZE_V 0x0000FFFFU +#define DSI_HOST_ALLOWED_CMD_SIZE_S 16 + +/** DSI_HOST_PCKHDL_CFG_REG register + * NA + */ +#define DSI_HOST_PCKHDL_CFG_REG (DR_REG_DSI_HOST_BASE + 0x2c) +/** DSI_HOST_EOTP_TX_EN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_EOTP_TX_EN (BIT(0)) +#define DSI_HOST_EOTP_TX_EN_M (DSI_HOST_EOTP_TX_EN_V << DSI_HOST_EOTP_TX_EN_S) +#define DSI_HOST_EOTP_TX_EN_V 0x00000001U +#define DSI_HOST_EOTP_TX_EN_S 0 +/** DSI_HOST_EOTP_RX_EN : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_EOTP_RX_EN (BIT(1)) +#define DSI_HOST_EOTP_RX_EN_M (DSI_HOST_EOTP_RX_EN_V << DSI_HOST_EOTP_RX_EN_S) +#define DSI_HOST_EOTP_RX_EN_V 0x00000001U +#define DSI_HOST_EOTP_RX_EN_S 1 +/** DSI_HOST_BTA_EN : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_BTA_EN (BIT(2)) +#define DSI_HOST_BTA_EN_M (DSI_HOST_BTA_EN_V << DSI_HOST_BTA_EN_S) +#define DSI_HOST_BTA_EN_V 0x00000001U +#define DSI_HOST_BTA_EN_S 2 +/** DSI_HOST_ECC_RX_EN : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_ECC_RX_EN (BIT(3)) +#define DSI_HOST_ECC_RX_EN_M (DSI_HOST_ECC_RX_EN_V << DSI_HOST_ECC_RX_EN_S) +#define DSI_HOST_ECC_RX_EN_V 0x00000001U +#define DSI_HOST_ECC_RX_EN_S 3 +/** DSI_HOST_CRC_RX_EN : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_CRC_RX_EN (BIT(4)) +#define DSI_HOST_CRC_RX_EN_M (DSI_HOST_CRC_RX_EN_V << DSI_HOST_CRC_RX_EN_S) +#define DSI_HOST_CRC_RX_EN_V 0x00000001U +#define DSI_HOST_CRC_RX_EN_S 4 +/** DSI_HOST_EOTP_TX_LP_EN : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_EOTP_TX_LP_EN (BIT(5)) +#define DSI_HOST_EOTP_TX_LP_EN_M (DSI_HOST_EOTP_TX_LP_EN_V << DSI_HOST_EOTP_TX_LP_EN_S) +#define DSI_HOST_EOTP_TX_LP_EN_V 0x00000001U +#define DSI_HOST_EOTP_TX_LP_EN_S 5 + +/** DSI_HOST_GEN_VCID_REG register + * NA + */ +#define DSI_HOST_GEN_VCID_REG (DR_REG_DSI_HOST_BASE + 0x30) +/** DSI_HOST_GEN_VCID_RX : R/W; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_GEN_VCID_RX 0x00000003U +#define DSI_HOST_GEN_VCID_RX_M (DSI_HOST_GEN_VCID_RX_V << DSI_HOST_GEN_VCID_RX_S) +#define DSI_HOST_GEN_VCID_RX_V 0x00000003U +#define DSI_HOST_GEN_VCID_RX_S 0 +/** DSI_HOST_GEN_VCID_TEAR_AUTO : R/W; bitpos: [9:8]; default: 0; + * NA + */ +#define DSI_HOST_GEN_VCID_TEAR_AUTO 0x00000003U +#define DSI_HOST_GEN_VCID_TEAR_AUTO_M (DSI_HOST_GEN_VCID_TEAR_AUTO_V << DSI_HOST_GEN_VCID_TEAR_AUTO_S) +#define DSI_HOST_GEN_VCID_TEAR_AUTO_V 0x00000003U +#define DSI_HOST_GEN_VCID_TEAR_AUTO_S 8 +/** DSI_HOST_GEN_VCID_TX_AUTO : R/W; bitpos: [17:16]; default: 0; + * NA + */ +#define DSI_HOST_GEN_VCID_TX_AUTO 0x00000003U +#define DSI_HOST_GEN_VCID_TX_AUTO_M (DSI_HOST_GEN_VCID_TX_AUTO_V << DSI_HOST_GEN_VCID_TX_AUTO_S) +#define DSI_HOST_GEN_VCID_TX_AUTO_V 0x00000003U +#define DSI_HOST_GEN_VCID_TX_AUTO_S 16 + +/** DSI_HOST_MODE_CFG_REG register + * NA + */ +#define DSI_HOST_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x34) +/** DSI_HOST_CMD_VIDEO_MODE : R/W; bitpos: [0]; default: 1; + * NA + */ +#define DSI_HOST_CMD_VIDEO_MODE (BIT(0)) +#define DSI_HOST_CMD_VIDEO_MODE_M (DSI_HOST_CMD_VIDEO_MODE_V << DSI_HOST_CMD_VIDEO_MODE_S) +#define DSI_HOST_CMD_VIDEO_MODE_V 0x00000001U +#define DSI_HOST_CMD_VIDEO_MODE_S 0 + +/** DSI_HOST_VID_MODE_CFG_REG register + * NA + */ +#define DSI_HOST_VID_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x38) +/** DSI_HOST_VID_MODE_TYPE : R/W; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_MODE_TYPE 0x00000003U +#define DSI_HOST_VID_MODE_TYPE_M (DSI_HOST_VID_MODE_TYPE_V << DSI_HOST_VID_MODE_TYPE_S) +#define DSI_HOST_VID_MODE_TYPE_V 0x00000003U +#define DSI_HOST_VID_MODE_TYPE_S 0 +/** DSI_HOST_LP_VSA_EN : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_LP_VSA_EN (BIT(8)) +#define DSI_HOST_LP_VSA_EN_M (DSI_HOST_LP_VSA_EN_V << DSI_HOST_LP_VSA_EN_S) +#define DSI_HOST_LP_VSA_EN_V 0x00000001U +#define DSI_HOST_LP_VSA_EN_S 8 +/** DSI_HOST_LP_VBP_EN : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_LP_VBP_EN (BIT(9)) +#define DSI_HOST_LP_VBP_EN_M (DSI_HOST_LP_VBP_EN_V << DSI_HOST_LP_VBP_EN_S) +#define DSI_HOST_LP_VBP_EN_V 0x00000001U +#define DSI_HOST_LP_VBP_EN_S 9 +/** DSI_HOST_LP_VFP_EN : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_LP_VFP_EN (BIT(10)) +#define DSI_HOST_LP_VFP_EN_M (DSI_HOST_LP_VFP_EN_V << DSI_HOST_LP_VFP_EN_S) +#define DSI_HOST_LP_VFP_EN_V 0x00000001U +#define DSI_HOST_LP_VFP_EN_S 10 +/** DSI_HOST_LP_VACT_EN : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_LP_VACT_EN (BIT(11)) +#define DSI_HOST_LP_VACT_EN_M (DSI_HOST_LP_VACT_EN_V << DSI_HOST_LP_VACT_EN_S) +#define DSI_HOST_LP_VACT_EN_V 0x00000001U +#define DSI_HOST_LP_VACT_EN_S 11 +/** DSI_HOST_LP_HBP_EN : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_LP_HBP_EN (BIT(12)) +#define DSI_HOST_LP_HBP_EN_M (DSI_HOST_LP_HBP_EN_V << DSI_HOST_LP_HBP_EN_S) +#define DSI_HOST_LP_HBP_EN_V 0x00000001U +#define DSI_HOST_LP_HBP_EN_S 12 +/** DSI_HOST_LP_HFP_EN : R/W; bitpos: [13]; default: 0; + * NA + */ +#define DSI_HOST_LP_HFP_EN (BIT(13)) +#define DSI_HOST_LP_HFP_EN_M (DSI_HOST_LP_HFP_EN_V << DSI_HOST_LP_HFP_EN_S) +#define DSI_HOST_LP_HFP_EN_V 0x00000001U +#define DSI_HOST_LP_HFP_EN_S 13 +/** DSI_HOST_FRAME_BTA_ACK_EN : R/W; bitpos: [14]; default: 0; + * NA + */ +#define DSI_HOST_FRAME_BTA_ACK_EN (BIT(14)) +#define DSI_HOST_FRAME_BTA_ACK_EN_M (DSI_HOST_FRAME_BTA_ACK_EN_V << DSI_HOST_FRAME_BTA_ACK_EN_S) +#define DSI_HOST_FRAME_BTA_ACK_EN_V 0x00000001U +#define DSI_HOST_FRAME_BTA_ACK_EN_S 14 +/** DSI_HOST_LP_CMD_EN : R/W; bitpos: [15]; default: 0; + * NA + */ +#define DSI_HOST_LP_CMD_EN (BIT(15)) +#define DSI_HOST_LP_CMD_EN_M (DSI_HOST_LP_CMD_EN_V << DSI_HOST_LP_CMD_EN_S) +#define DSI_HOST_LP_CMD_EN_V 0x00000001U +#define DSI_HOST_LP_CMD_EN_S 15 +/** DSI_HOST_VPG_EN : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_VPG_EN (BIT(16)) +#define DSI_HOST_VPG_EN_M (DSI_HOST_VPG_EN_V << DSI_HOST_VPG_EN_S) +#define DSI_HOST_VPG_EN_V 0x00000001U +#define DSI_HOST_VPG_EN_S 16 +/** DSI_HOST_VPG_MODE : R/W; bitpos: [20]; default: 0; + * NA + */ +#define DSI_HOST_VPG_MODE (BIT(20)) +#define DSI_HOST_VPG_MODE_M (DSI_HOST_VPG_MODE_V << DSI_HOST_VPG_MODE_S) +#define DSI_HOST_VPG_MODE_V 0x00000001U +#define DSI_HOST_VPG_MODE_S 20 +/** DSI_HOST_VPG_ORIENTATION : R/W; bitpos: [24]; default: 0; + * NA + */ +#define DSI_HOST_VPG_ORIENTATION (BIT(24)) +#define DSI_HOST_VPG_ORIENTATION_M (DSI_HOST_VPG_ORIENTATION_V << DSI_HOST_VPG_ORIENTATION_S) +#define DSI_HOST_VPG_ORIENTATION_V 0x00000001U +#define DSI_HOST_VPG_ORIENTATION_S 24 + +/** DSI_HOST_VID_PKT_SIZE_REG register + * NA + */ +#define DSI_HOST_VID_PKT_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x3c) +/** DSI_HOST_VID_PKT_SIZE : R/W; bitpos: [13:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_PKT_SIZE 0x00003FFFU +#define DSI_HOST_VID_PKT_SIZE_M (DSI_HOST_VID_PKT_SIZE_V << DSI_HOST_VID_PKT_SIZE_S) +#define DSI_HOST_VID_PKT_SIZE_V 0x00003FFFU +#define DSI_HOST_VID_PKT_SIZE_S 0 + +/** DSI_HOST_VID_NUM_CHUNKS_REG register + * NA + */ +#define DSI_HOST_VID_NUM_CHUNKS_REG (DR_REG_DSI_HOST_BASE + 0x40) +/** DSI_HOST_VID_NUM_CHUNKS : R/W; bitpos: [12:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_NUM_CHUNKS 0x00001FFFU +#define DSI_HOST_VID_NUM_CHUNKS_M (DSI_HOST_VID_NUM_CHUNKS_V << DSI_HOST_VID_NUM_CHUNKS_S) +#define DSI_HOST_VID_NUM_CHUNKS_V 0x00001FFFU +#define DSI_HOST_VID_NUM_CHUNKS_S 0 + +/** DSI_HOST_VID_NULL_SIZE_REG register + * NA + */ +#define DSI_HOST_VID_NULL_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x44) +/** DSI_HOST_VID_NULL_SIZE : R/W; bitpos: [12:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_NULL_SIZE 0x00001FFFU +#define DSI_HOST_VID_NULL_SIZE_M (DSI_HOST_VID_NULL_SIZE_V << DSI_HOST_VID_NULL_SIZE_S) +#define DSI_HOST_VID_NULL_SIZE_V 0x00001FFFU +#define DSI_HOST_VID_NULL_SIZE_S 0 + +/** DSI_HOST_VID_HSA_TIME_REG register + * NA + */ +#define DSI_HOST_VID_HSA_TIME_REG (DR_REG_DSI_HOST_BASE + 0x48) +/** DSI_HOST_VID_HSA_TIME : R/W; bitpos: [11:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HSA_TIME 0x00000FFFU +#define DSI_HOST_VID_HSA_TIME_M (DSI_HOST_VID_HSA_TIME_V << DSI_HOST_VID_HSA_TIME_S) +#define DSI_HOST_VID_HSA_TIME_V 0x00000FFFU +#define DSI_HOST_VID_HSA_TIME_S 0 + +/** DSI_HOST_VID_HBP_TIME_REG register + * NA + */ +#define DSI_HOST_VID_HBP_TIME_REG (DR_REG_DSI_HOST_BASE + 0x4c) +/** DSI_HOST_VID_HBP_TIME : R/W; bitpos: [11:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HBP_TIME 0x00000FFFU +#define DSI_HOST_VID_HBP_TIME_M (DSI_HOST_VID_HBP_TIME_V << DSI_HOST_VID_HBP_TIME_S) +#define DSI_HOST_VID_HBP_TIME_V 0x00000FFFU +#define DSI_HOST_VID_HBP_TIME_S 0 + +/** DSI_HOST_VID_HLINE_TIME_REG register + * NA + */ +#define DSI_HOST_VID_HLINE_TIME_REG (DR_REG_DSI_HOST_BASE + 0x50) +/** DSI_HOST_VID_HLINE_TIME : R/W; bitpos: [14:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HLINE_TIME 0x00007FFFU +#define DSI_HOST_VID_HLINE_TIME_M (DSI_HOST_VID_HLINE_TIME_V << DSI_HOST_VID_HLINE_TIME_S) +#define DSI_HOST_VID_HLINE_TIME_V 0x00007FFFU +#define DSI_HOST_VID_HLINE_TIME_S 0 + +/** DSI_HOST_VID_VSA_LINES_REG register + * NA + */ +#define DSI_HOST_VID_VSA_LINES_REG (DR_REG_DSI_HOST_BASE + 0x54) +/** DSI_HOST_VSA_LINES : R/W; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VSA_LINES 0x000003FFU +#define DSI_HOST_VSA_LINES_M (DSI_HOST_VSA_LINES_V << DSI_HOST_VSA_LINES_S) +#define DSI_HOST_VSA_LINES_V 0x000003FFU +#define DSI_HOST_VSA_LINES_S 0 + +/** DSI_HOST_VID_VBP_LINES_REG register + * NA + */ +#define DSI_HOST_VID_VBP_LINES_REG (DR_REG_DSI_HOST_BASE + 0x58) +/** DSI_HOST_VBP_LINES : R/W; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VBP_LINES 0x000003FFU +#define DSI_HOST_VBP_LINES_M (DSI_HOST_VBP_LINES_V << DSI_HOST_VBP_LINES_S) +#define DSI_HOST_VBP_LINES_V 0x000003FFU +#define DSI_HOST_VBP_LINES_S 0 + +/** DSI_HOST_VID_VFP_LINES_REG register + * NA + */ +#define DSI_HOST_VID_VFP_LINES_REG (DR_REG_DSI_HOST_BASE + 0x5c) +/** DSI_HOST_VFP_LINES : R/W; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VFP_LINES 0x000003FFU +#define DSI_HOST_VFP_LINES_M (DSI_HOST_VFP_LINES_V << DSI_HOST_VFP_LINES_S) +#define DSI_HOST_VFP_LINES_V 0x000003FFU +#define DSI_HOST_VFP_LINES_S 0 + +/** DSI_HOST_VID_VACTIVE_LINES_REG register + * NA + */ +#define DSI_HOST_VID_VACTIVE_LINES_REG (DR_REG_DSI_HOST_BASE + 0x60) +/** DSI_HOST_V_ACTIVE_LINES : R/W; bitpos: [13:0]; default: 0; + * NA + */ +#define DSI_HOST_V_ACTIVE_LINES 0x00003FFFU +#define DSI_HOST_V_ACTIVE_LINES_M (DSI_HOST_V_ACTIVE_LINES_V << DSI_HOST_V_ACTIVE_LINES_S) +#define DSI_HOST_V_ACTIVE_LINES_V 0x00003FFFU +#define DSI_HOST_V_ACTIVE_LINES_S 0 + +/** DSI_HOST_EDPI_CMD_SIZE_REG register + * NA + */ +#define DSI_HOST_EDPI_CMD_SIZE_REG (DR_REG_DSI_HOST_BASE + 0x64) +/** DSI_HOST_EDPI_ALLOWED_CMD_SIZE : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE 0x0000FFFFU +#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_M (DSI_HOST_EDPI_ALLOWED_CMD_SIZE_V << DSI_HOST_EDPI_ALLOWED_CMD_SIZE_S) +#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_V 0x0000FFFFU +#define DSI_HOST_EDPI_ALLOWED_CMD_SIZE_S 0 + +/** DSI_HOST_CMD_MODE_CFG_REG register + * NA + */ +#define DSI_HOST_CMD_MODE_CFG_REG (DR_REG_DSI_HOST_BASE + 0x68) +/** DSI_HOST_TEAR_FX_EN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_TEAR_FX_EN (BIT(0)) +#define DSI_HOST_TEAR_FX_EN_M (DSI_HOST_TEAR_FX_EN_V << DSI_HOST_TEAR_FX_EN_S) +#define DSI_HOST_TEAR_FX_EN_V 0x00000001U +#define DSI_HOST_TEAR_FX_EN_S 0 +/** DSI_HOST_ACK_RQST_EN : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_ACK_RQST_EN (BIT(1)) +#define DSI_HOST_ACK_RQST_EN_M (DSI_HOST_ACK_RQST_EN_V << DSI_HOST_ACK_RQST_EN_S) +#define DSI_HOST_ACK_RQST_EN_V 0x00000001U +#define DSI_HOST_ACK_RQST_EN_S 1 +/** DSI_HOST_GEN_SW_0P_TX : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SW_0P_TX (BIT(8)) +#define DSI_HOST_GEN_SW_0P_TX_M (DSI_HOST_GEN_SW_0P_TX_V << DSI_HOST_GEN_SW_0P_TX_S) +#define DSI_HOST_GEN_SW_0P_TX_V 0x00000001U +#define DSI_HOST_GEN_SW_0P_TX_S 8 +/** DSI_HOST_GEN_SW_1P_TX : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SW_1P_TX (BIT(9)) +#define DSI_HOST_GEN_SW_1P_TX_M (DSI_HOST_GEN_SW_1P_TX_V << DSI_HOST_GEN_SW_1P_TX_S) +#define DSI_HOST_GEN_SW_1P_TX_V 0x00000001U +#define DSI_HOST_GEN_SW_1P_TX_S 9 +/** DSI_HOST_GEN_SW_2P_TX : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SW_2P_TX (BIT(10)) +#define DSI_HOST_GEN_SW_2P_TX_M (DSI_HOST_GEN_SW_2P_TX_V << DSI_HOST_GEN_SW_2P_TX_S) +#define DSI_HOST_GEN_SW_2P_TX_V 0x00000001U +#define DSI_HOST_GEN_SW_2P_TX_S 10 +/** DSI_HOST_GEN_SR_0P_TX : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SR_0P_TX (BIT(11)) +#define DSI_HOST_GEN_SR_0P_TX_M (DSI_HOST_GEN_SR_0P_TX_V << DSI_HOST_GEN_SR_0P_TX_S) +#define DSI_HOST_GEN_SR_0P_TX_V 0x00000001U +#define DSI_HOST_GEN_SR_0P_TX_S 11 +/** DSI_HOST_GEN_SR_1P_TX : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SR_1P_TX (BIT(12)) +#define DSI_HOST_GEN_SR_1P_TX_M (DSI_HOST_GEN_SR_1P_TX_V << DSI_HOST_GEN_SR_1P_TX_S) +#define DSI_HOST_GEN_SR_1P_TX_V 0x00000001U +#define DSI_HOST_GEN_SR_1P_TX_S 12 +/** DSI_HOST_GEN_SR_2P_TX : R/W; bitpos: [13]; default: 0; + * NA + */ +#define DSI_HOST_GEN_SR_2P_TX (BIT(13)) +#define DSI_HOST_GEN_SR_2P_TX_M (DSI_HOST_GEN_SR_2P_TX_V << DSI_HOST_GEN_SR_2P_TX_S) +#define DSI_HOST_GEN_SR_2P_TX_V 0x00000001U +#define DSI_HOST_GEN_SR_2P_TX_S 13 +/** DSI_HOST_GEN_LW_TX : R/W; bitpos: [14]; default: 0; + * NA + */ +#define DSI_HOST_GEN_LW_TX (BIT(14)) +#define DSI_HOST_GEN_LW_TX_M (DSI_HOST_GEN_LW_TX_V << DSI_HOST_GEN_LW_TX_S) +#define DSI_HOST_GEN_LW_TX_V 0x00000001U +#define DSI_HOST_GEN_LW_TX_S 14 +/** DSI_HOST_DCS_SW_0P_TX : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_DCS_SW_0P_TX (BIT(16)) +#define DSI_HOST_DCS_SW_0P_TX_M (DSI_HOST_DCS_SW_0P_TX_V << DSI_HOST_DCS_SW_0P_TX_S) +#define DSI_HOST_DCS_SW_0P_TX_V 0x00000001U +#define DSI_HOST_DCS_SW_0P_TX_S 16 +/** DSI_HOST_DCS_SW_1P_TX : R/W; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_DCS_SW_1P_TX (BIT(17)) +#define DSI_HOST_DCS_SW_1P_TX_M (DSI_HOST_DCS_SW_1P_TX_V << DSI_HOST_DCS_SW_1P_TX_S) +#define DSI_HOST_DCS_SW_1P_TX_V 0x00000001U +#define DSI_HOST_DCS_SW_1P_TX_S 17 +/** DSI_HOST_DCS_SR_0P_TX : R/W; bitpos: [18]; default: 0; + * NA + */ +#define DSI_HOST_DCS_SR_0P_TX (BIT(18)) +#define DSI_HOST_DCS_SR_0P_TX_M (DSI_HOST_DCS_SR_0P_TX_V << DSI_HOST_DCS_SR_0P_TX_S) +#define DSI_HOST_DCS_SR_0P_TX_V 0x00000001U +#define DSI_HOST_DCS_SR_0P_TX_S 18 +/** DSI_HOST_DCS_LW_TX : R/W; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_DCS_LW_TX (BIT(19)) +#define DSI_HOST_DCS_LW_TX_M (DSI_HOST_DCS_LW_TX_V << DSI_HOST_DCS_LW_TX_S) +#define DSI_HOST_DCS_LW_TX_V 0x00000001U +#define DSI_HOST_DCS_LW_TX_S 19 +/** DSI_HOST_MAX_RD_PKT_SIZE : R/W; bitpos: [24]; default: 0; + * NA + */ +#define DSI_HOST_MAX_RD_PKT_SIZE (BIT(24)) +#define DSI_HOST_MAX_RD_PKT_SIZE_M (DSI_HOST_MAX_RD_PKT_SIZE_V << DSI_HOST_MAX_RD_PKT_SIZE_S) +#define DSI_HOST_MAX_RD_PKT_SIZE_V 0x00000001U +#define DSI_HOST_MAX_RD_PKT_SIZE_S 24 + +/** DSI_HOST_GEN_HDR_REG register + * NA + */ +#define DSI_HOST_GEN_HDR_REG (DR_REG_DSI_HOST_BASE + 0x6c) +/** DSI_HOST_GEN_DT : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define DSI_HOST_GEN_DT 0x0000003FU +#define DSI_HOST_GEN_DT_M (DSI_HOST_GEN_DT_V << DSI_HOST_GEN_DT_S) +#define DSI_HOST_GEN_DT_V 0x0000003FU +#define DSI_HOST_GEN_DT_S 0 +/** DSI_HOST_GEN_VC : R/W; bitpos: [7:6]; default: 0; + * NA + */ +#define DSI_HOST_GEN_VC 0x00000003U +#define DSI_HOST_GEN_VC_M (DSI_HOST_GEN_VC_V << DSI_HOST_GEN_VC_S) +#define DSI_HOST_GEN_VC_V 0x00000003U +#define DSI_HOST_GEN_VC_S 6 +/** DSI_HOST_GEN_WC_LSBYTE : R/W; bitpos: [15:8]; default: 0; + * NA + */ +#define DSI_HOST_GEN_WC_LSBYTE 0x000000FFU +#define DSI_HOST_GEN_WC_LSBYTE_M (DSI_HOST_GEN_WC_LSBYTE_V << DSI_HOST_GEN_WC_LSBYTE_S) +#define DSI_HOST_GEN_WC_LSBYTE_V 0x000000FFU +#define DSI_HOST_GEN_WC_LSBYTE_S 8 +/** DSI_HOST_GEN_WC_MSBYTE : R/W; bitpos: [23:16]; default: 0; + * NA + */ +#define DSI_HOST_GEN_WC_MSBYTE 0x000000FFU +#define DSI_HOST_GEN_WC_MSBYTE_M (DSI_HOST_GEN_WC_MSBYTE_V << DSI_HOST_GEN_WC_MSBYTE_S) +#define DSI_HOST_GEN_WC_MSBYTE_V 0x000000FFU +#define DSI_HOST_GEN_WC_MSBYTE_S 16 + +/** DSI_HOST_GEN_PLD_DATA_REG register + * NA + */ +#define DSI_HOST_GEN_PLD_DATA_REG (DR_REG_DSI_HOST_BASE + 0x70) +/** DSI_HOST_GEN_PLD_B1 : R/W; bitpos: [7:0]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_B1 0x000000FFU +#define DSI_HOST_GEN_PLD_B1_M (DSI_HOST_GEN_PLD_B1_V << DSI_HOST_GEN_PLD_B1_S) +#define DSI_HOST_GEN_PLD_B1_V 0x000000FFU +#define DSI_HOST_GEN_PLD_B1_S 0 +/** DSI_HOST_GEN_PLD_B2 : R/W; bitpos: [15:8]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_B2 0x000000FFU +#define DSI_HOST_GEN_PLD_B2_M (DSI_HOST_GEN_PLD_B2_V << DSI_HOST_GEN_PLD_B2_S) +#define DSI_HOST_GEN_PLD_B2_V 0x000000FFU +#define DSI_HOST_GEN_PLD_B2_S 8 +/** DSI_HOST_GEN_PLD_B3 : R/W; bitpos: [23:16]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_B3 0x000000FFU +#define DSI_HOST_GEN_PLD_B3_M (DSI_HOST_GEN_PLD_B3_V << DSI_HOST_GEN_PLD_B3_S) +#define DSI_HOST_GEN_PLD_B3_V 0x000000FFU +#define DSI_HOST_GEN_PLD_B3_S 16 +/** DSI_HOST_GEN_PLD_B4 : R/W; bitpos: [31:24]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_B4 0x000000FFU +#define DSI_HOST_GEN_PLD_B4_M (DSI_HOST_GEN_PLD_B4_V << DSI_HOST_GEN_PLD_B4_S) +#define DSI_HOST_GEN_PLD_B4_V 0x000000FFU +#define DSI_HOST_GEN_PLD_B4_S 24 + +/** DSI_HOST_CMD_PKT_STATUS_REG register + * NA + */ +#define DSI_HOST_CMD_PKT_STATUS_REG (DR_REG_DSI_HOST_BASE + 0x74) +/** DSI_HOST_GEN_CMD_EMPTY : RO; bitpos: [0]; default: 1; + * NA + */ +#define DSI_HOST_GEN_CMD_EMPTY (BIT(0)) +#define DSI_HOST_GEN_CMD_EMPTY_M (DSI_HOST_GEN_CMD_EMPTY_V << DSI_HOST_GEN_CMD_EMPTY_S) +#define DSI_HOST_GEN_CMD_EMPTY_V 0x00000001U +#define DSI_HOST_GEN_CMD_EMPTY_S 0 +/** DSI_HOST_GEN_CMD_FULL : RO; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_GEN_CMD_FULL (BIT(1)) +#define DSI_HOST_GEN_CMD_FULL_M (DSI_HOST_GEN_CMD_FULL_V << DSI_HOST_GEN_CMD_FULL_S) +#define DSI_HOST_GEN_CMD_FULL_V 0x00000001U +#define DSI_HOST_GEN_CMD_FULL_S 1 +/** DSI_HOST_GEN_PLD_W_EMPTY : RO; bitpos: [2]; default: 1; + * NA + */ +#define DSI_HOST_GEN_PLD_W_EMPTY (BIT(2)) +#define DSI_HOST_GEN_PLD_W_EMPTY_M (DSI_HOST_GEN_PLD_W_EMPTY_V << DSI_HOST_GEN_PLD_W_EMPTY_S) +#define DSI_HOST_GEN_PLD_W_EMPTY_V 0x00000001U +#define DSI_HOST_GEN_PLD_W_EMPTY_S 2 +/** DSI_HOST_GEN_PLD_W_FULL : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_W_FULL (BIT(3)) +#define DSI_HOST_GEN_PLD_W_FULL_M (DSI_HOST_GEN_PLD_W_FULL_V << DSI_HOST_GEN_PLD_W_FULL_S) +#define DSI_HOST_GEN_PLD_W_FULL_V 0x00000001U +#define DSI_HOST_GEN_PLD_W_FULL_S 3 +/** DSI_HOST_GEN_PLD_R_EMPTY : RO; bitpos: [4]; default: 1; + * NA + */ +#define DSI_HOST_GEN_PLD_R_EMPTY (BIT(4)) +#define DSI_HOST_GEN_PLD_R_EMPTY_M (DSI_HOST_GEN_PLD_R_EMPTY_V << DSI_HOST_GEN_PLD_R_EMPTY_S) +#define DSI_HOST_GEN_PLD_R_EMPTY_V 0x00000001U +#define DSI_HOST_GEN_PLD_R_EMPTY_S 4 +/** DSI_HOST_GEN_PLD_R_FULL : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_R_FULL (BIT(5)) +#define DSI_HOST_GEN_PLD_R_FULL_M (DSI_HOST_GEN_PLD_R_FULL_V << DSI_HOST_GEN_PLD_R_FULL_S) +#define DSI_HOST_GEN_PLD_R_FULL_V 0x00000001U +#define DSI_HOST_GEN_PLD_R_FULL_S 5 +/** DSI_HOST_GEN_RD_CMD_BUSY : RO; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_GEN_RD_CMD_BUSY (BIT(6)) +#define DSI_HOST_GEN_RD_CMD_BUSY_M (DSI_HOST_GEN_RD_CMD_BUSY_V << DSI_HOST_GEN_RD_CMD_BUSY_S) +#define DSI_HOST_GEN_RD_CMD_BUSY_V 0x00000001U +#define DSI_HOST_GEN_RD_CMD_BUSY_S 6 +/** DSI_HOST_GEN_BUFF_CMD_EMPTY : RO; bitpos: [16]; default: 1; + * NA + */ +#define DSI_HOST_GEN_BUFF_CMD_EMPTY (BIT(16)) +#define DSI_HOST_GEN_BUFF_CMD_EMPTY_M (DSI_HOST_GEN_BUFF_CMD_EMPTY_V << DSI_HOST_GEN_BUFF_CMD_EMPTY_S) +#define DSI_HOST_GEN_BUFF_CMD_EMPTY_V 0x00000001U +#define DSI_HOST_GEN_BUFF_CMD_EMPTY_S 16 +/** DSI_HOST_GEN_BUFF_CMD_FULL : RO; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_GEN_BUFF_CMD_FULL (BIT(17)) +#define DSI_HOST_GEN_BUFF_CMD_FULL_M (DSI_HOST_GEN_BUFF_CMD_FULL_V << DSI_HOST_GEN_BUFF_CMD_FULL_S) +#define DSI_HOST_GEN_BUFF_CMD_FULL_V 0x00000001U +#define DSI_HOST_GEN_BUFF_CMD_FULL_S 17 +/** DSI_HOST_GEN_BUFF_PLD_EMPTY : RO; bitpos: [18]; default: 1; + * NA + */ +#define DSI_HOST_GEN_BUFF_PLD_EMPTY (BIT(18)) +#define DSI_HOST_GEN_BUFF_PLD_EMPTY_M (DSI_HOST_GEN_BUFF_PLD_EMPTY_V << DSI_HOST_GEN_BUFF_PLD_EMPTY_S) +#define DSI_HOST_GEN_BUFF_PLD_EMPTY_V 0x00000001U +#define DSI_HOST_GEN_BUFF_PLD_EMPTY_S 18 +/** DSI_HOST_GEN_BUFF_PLD_FULL : RO; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_GEN_BUFF_PLD_FULL (BIT(19)) +#define DSI_HOST_GEN_BUFF_PLD_FULL_M (DSI_HOST_GEN_BUFF_PLD_FULL_V << DSI_HOST_GEN_BUFF_PLD_FULL_S) +#define DSI_HOST_GEN_BUFF_PLD_FULL_V 0x00000001U +#define DSI_HOST_GEN_BUFF_PLD_FULL_S 19 + +/** DSI_HOST_TO_CNT_CFG_REG register + * NA + */ +#define DSI_HOST_TO_CNT_CFG_REG (DR_REG_DSI_HOST_BASE + 0x78) +/** DSI_HOST_LPRX_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_LPRX_TO_CNT 0x0000FFFFU +#define DSI_HOST_LPRX_TO_CNT_M (DSI_HOST_LPRX_TO_CNT_V << DSI_HOST_LPRX_TO_CNT_S) +#define DSI_HOST_LPRX_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_LPRX_TO_CNT_S 0 +/** DSI_HOST_HSTX_TO_CNT : R/W; bitpos: [31:16]; default: 0; + * NA + */ +#define DSI_HOST_HSTX_TO_CNT 0x0000FFFFU +#define DSI_HOST_HSTX_TO_CNT_M (DSI_HOST_HSTX_TO_CNT_V << DSI_HOST_HSTX_TO_CNT_S) +#define DSI_HOST_HSTX_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_HSTX_TO_CNT_S 16 + +/** DSI_HOST_HS_RD_TO_CNT_REG register + * NA + */ +#define DSI_HOST_HS_RD_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x7c) +/** DSI_HOST_HS_RD_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_HS_RD_TO_CNT 0x0000FFFFU +#define DSI_HOST_HS_RD_TO_CNT_M (DSI_HOST_HS_RD_TO_CNT_V << DSI_HOST_HS_RD_TO_CNT_S) +#define DSI_HOST_HS_RD_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_HS_RD_TO_CNT_S 0 + +/** DSI_HOST_LP_RD_TO_CNT_REG register + * NA + */ +#define DSI_HOST_LP_RD_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x80) +/** DSI_HOST_LP_RD_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_LP_RD_TO_CNT 0x0000FFFFU +#define DSI_HOST_LP_RD_TO_CNT_M (DSI_HOST_LP_RD_TO_CNT_V << DSI_HOST_LP_RD_TO_CNT_S) +#define DSI_HOST_LP_RD_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_LP_RD_TO_CNT_S 0 + +/** DSI_HOST_HS_WR_TO_CNT_REG register + * NA + */ +#define DSI_HOST_HS_WR_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x84) +/** DSI_HOST_HS_WR_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_HS_WR_TO_CNT 0x0000FFFFU +#define DSI_HOST_HS_WR_TO_CNT_M (DSI_HOST_HS_WR_TO_CNT_V << DSI_HOST_HS_WR_TO_CNT_S) +#define DSI_HOST_HS_WR_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_HS_WR_TO_CNT_S 0 + +/** DSI_HOST_LP_WR_TO_CNT_REG register + * NA + */ +#define DSI_HOST_LP_WR_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x88) +/** DSI_HOST_LP_WR_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_LP_WR_TO_CNT 0x0000FFFFU +#define DSI_HOST_LP_WR_TO_CNT_M (DSI_HOST_LP_WR_TO_CNT_V << DSI_HOST_LP_WR_TO_CNT_S) +#define DSI_HOST_LP_WR_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_LP_WR_TO_CNT_S 0 + +/** DSI_HOST_BTA_TO_CNT_REG register + * NA + */ +#define DSI_HOST_BTA_TO_CNT_REG (DR_REG_DSI_HOST_BASE + 0x8c) +/** DSI_HOST_BTA_TO_CNT : R/W; bitpos: [15:0]; default: 0; + * NA + */ +#define DSI_HOST_BTA_TO_CNT 0x0000FFFFU +#define DSI_HOST_BTA_TO_CNT_M (DSI_HOST_BTA_TO_CNT_V << DSI_HOST_BTA_TO_CNT_S) +#define DSI_HOST_BTA_TO_CNT_V 0x0000FFFFU +#define DSI_HOST_BTA_TO_CNT_S 0 + +/** DSI_HOST_SDF_3D_REG register + * NA + */ +#define DSI_HOST_SDF_3D_REG (DR_REG_DSI_HOST_BASE + 0x90) +/** DSI_HOST_MODE_3D : R/W; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_MODE_3D 0x00000003U +#define DSI_HOST_MODE_3D_M (DSI_HOST_MODE_3D_V << DSI_HOST_MODE_3D_S) +#define DSI_HOST_MODE_3D_V 0x00000003U +#define DSI_HOST_MODE_3D_S 0 +/** DSI_HOST_FORMAT_3D : R/W; bitpos: [3:2]; default: 0; + * NA + */ +#define DSI_HOST_FORMAT_3D 0x00000003U +#define DSI_HOST_FORMAT_3D_M (DSI_HOST_FORMAT_3D_V << DSI_HOST_FORMAT_3D_S) +#define DSI_HOST_FORMAT_3D_V 0x00000003U +#define DSI_HOST_FORMAT_3D_S 2 +/** DSI_HOST_SECOND_VSYNC : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_SECOND_VSYNC (BIT(4)) +#define DSI_HOST_SECOND_VSYNC_M (DSI_HOST_SECOND_VSYNC_V << DSI_HOST_SECOND_VSYNC_S) +#define DSI_HOST_SECOND_VSYNC_V 0x00000001U +#define DSI_HOST_SECOND_VSYNC_S 4 +/** DSI_HOST_RIGHT_FIRST : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_RIGHT_FIRST (BIT(5)) +#define DSI_HOST_RIGHT_FIRST_M (DSI_HOST_RIGHT_FIRST_V << DSI_HOST_RIGHT_FIRST_S) +#define DSI_HOST_RIGHT_FIRST_V 0x00000001U +#define DSI_HOST_RIGHT_FIRST_S 5 +/** DSI_HOST_SEND_3D_CFG : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_SEND_3D_CFG (BIT(16)) +#define DSI_HOST_SEND_3D_CFG_M (DSI_HOST_SEND_3D_CFG_V << DSI_HOST_SEND_3D_CFG_S) +#define DSI_HOST_SEND_3D_CFG_V 0x00000001U +#define DSI_HOST_SEND_3D_CFG_S 16 + +/** DSI_HOST_LPCLK_CTRL_REG register + * NA + */ +#define DSI_HOST_LPCLK_CTRL_REG (DR_REG_DSI_HOST_BASE + 0x94) +/** DSI_HOST_PHY_TXREQUESTCLKHS : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TXREQUESTCLKHS (BIT(0)) +#define DSI_HOST_PHY_TXREQUESTCLKHS_M (DSI_HOST_PHY_TXREQUESTCLKHS_V << DSI_HOST_PHY_TXREQUESTCLKHS_S) +#define DSI_HOST_PHY_TXREQUESTCLKHS_V 0x00000001U +#define DSI_HOST_PHY_TXREQUESTCLKHS_S 0 +/** DSI_HOST_AUTO_CLKLANE_CTRL : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_AUTO_CLKLANE_CTRL (BIT(1)) +#define DSI_HOST_AUTO_CLKLANE_CTRL_M (DSI_HOST_AUTO_CLKLANE_CTRL_V << DSI_HOST_AUTO_CLKLANE_CTRL_S) +#define DSI_HOST_AUTO_CLKLANE_CTRL_V 0x00000001U +#define DSI_HOST_AUTO_CLKLANE_CTRL_S 1 + +/** DSI_HOST_PHY_TMR_LPCLK_CFG_REG register + * NA + */ +#define DSI_HOST_PHY_TMR_LPCLK_CFG_REG (DR_REG_DSI_HOST_BASE + 0x98) +/** DSI_HOST_PHY_CLKLP2HS_TIME : R/W; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_CLKLP2HS_TIME 0x000003FFU +#define DSI_HOST_PHY_CLKLP2HS_TIME_M (DSI_HOST_PHY_CLKLP2HS_TIME_V << DSI_HOST_PHY_CLKLP2HS_TIME_S) +#define DSI_HOST_PHY_CLKLP2HS_TIME_V 0x000003FFU +#define DSI_HOST_PHY_CLKLP2HS_TIME_S 0 +/** DSI_HOST_PHY_CLKHS2LP_TIME : R/W; bitpos: [25:16]; default: 0; + * NA + */ +#define DSI_HOST_PHY_CLKHS2LP_TIME 0x000003FFU +#define DSI_HOST_PHY_CLKHS2LP_TIME_M (DSI_HOST_PHY_CLKHS2LP_TIME_V << DSI_HOST_PHY_CLKHS2LP_TIME_S) +#define DSI_HOST_PHY_CLKHS2LP_TIME_V 0x000003FFU +#define DSI_HOST_PHY_CLKHS2LP_TIME_S 16 + +/** DSI_HOST_PHY_TMR_CFG_REG register + * NA + */ +#define DSI_HOST_PHY_TMR_CFG_REG (DR_REG_DSI_HOST_BASE + 0x9c) +/** DSI_HOST_PHY_LP2HS_TIME : R/W; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_LP2HS_TIME 0x000003FFU +#define DSI_HOST_PHY_LP2HS_TIME_M (DSI_HOST_PHY_LP2HS_TIME_V << DSI_HOST_PHY_LP2HS_TIME_S) +#define DSI_HOST_PHY_LP2HS_TIME_V 0x000003FFU +#define DSI_HOST_PHY_LP2HS_TIME_S 0 +/** DSI_HOST_PHY_HS2LP_TIME : R/W; bitpos: [25:16]; default: 0; + * NA + */ +#define DSI_HOST_PHY_HS2LP_TIME 0x000003FFU +#define DSI_HOST_PHY_HS2LP_TIME_M (DSI_HOST_PHY_HS2LP_TIME_V << DSI_HOST_PHY_HS2LP_TIME_S) +#define DSI_HOST_PHY_HS2LP_TIME_V 0x000003FFU +#define DSI_HOST_PHY_HS2LP_TIME_S 16 + +/** DSI_HOST_PHY_RSTZ_REG register + * NA + */ +#define DSI_HOST_PHY_RSTZ_REG (DR_REG_DSI_HOST_BASE + 0xa0) +/** DSI_HOST_PHY_SHUTDOWNZ : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_SHUTDOWNZ (BIT(0)) +#define DSI_HOST_PHY_SHUTDOWNZ_M (DSI_HOST_PHY_SHUTDOWNZ_V << DSI_HOST_PHY_SHUTDOWNZ_S) +#define DSI_HOST_PHY_SHUTDOWNZ_V 0x00000001U +#define DSI_HOST_PHY_SHUTDOWNZ_S 0 +/** DSI_HOST_PHY_RSTZ : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_PHY_RSTZ (BIT(1)) +#define DSI_HOST_PHY_RSTZ_M (DSI_HOST_PHY_RSTZ_V << DSI_HOST_PHY_RSTZ_S) +#define DSI_HOST_PHY_RSTZ_V 0x00000001U +#define DSI_HOST_PHY_RSTZ_S 1 +/** DSI_HOST_PHY_ENABLECLK : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_PHY_ENABLECLK (BIT(2)) +#define DSI_HOST_PHY_ENABLECLK_M (DSI_HOST_PHY_ENABLECLK_V << DSI_HOST_PHY_ENABLECLK_S) +#define DSI_HOST_PHY_ENABLECLK_V 0x00000001U +#define DSI_HOST_PHY_ENABLECLK_S 2 +/** DSI_HOST_PHY_FORCEPLL : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_PHY_FORCEPLL (BIT(3)) +#define DSI_HOST_PHY_FORCEPLL_M (DSI_HOST_PHY_FORCEPLL_V << DSI_HOST_PHY_FORCEPLL_S) +#define DSI_HOST_PHY_FORCEPLL_V 0x00000001U +#define DSI_HOST_PHY_FORCEPLL_S 3 + +/** DSI_HOST_PHY_IF_CFG_REG register + * NA + */ +#define DSI_HOST_PHY_IF_CFG_REG (DR_REG_DSI_HOST_BASE + 0xa4) +/** DSI_HOST_N_LANES : R/W; bitpos: [1:0]; default: 1; + * NA + */ +#define DSI_HOST_N_LANES 0x00000003U +#define DSI_HOST_N_LANES_M (DSI_HOST_N_LANES_V << DSI_HOST_N_LANES_S) +#define DSI_HOST_N_LANES_V 0x00000003U +#define DSI_HOST_N_LANES_S 0 +/** DSI_HOST_PHY_STOP_WAIT_TIME : R/W; bitpos: [15:8]; default: 0; + * NA + */ +#define DSI_HOST_PHY_STOP_WAIT_TIME 0x000000FFU +#define DSI_HOST_PHY_STOP_WAIT_TIME_M (DSI_HOST_PHY_STOP_WAIT_TIME_V << DSI_HOST_PHY_STOP_WAIT_TIME_S) +#define DSI_HOST_PHY_STOP_WAIT_TIME_V 0x000000FFU +#define DSI_HOST_PHY_STOP_WAIT_TIME_S 8 + +/** DSI_HOST_PHY_ULPS_CTRL_REG register + * NA + */ +#define DSI_HOST_PHY_ULPS_CTRL_REG (DR_REG_DSI_HOST_BASE + 0xa8) +/** DSI_HOST_PHY_TXREQULPSCLK : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TXREQULPSCLK (BIT(0)) +#define DSI_HOST_PHY_TXREQULPSCLK_M (DSI_HOST_PHY_TXREQULPSCLK_V << DSI_HOST_PHY_TXREQULPSCLK_S) +#define DSI_HOST_PHY_TXREQULPSCLK_V 0x00000001U +#define DSI_HOST_PHY_TXREQULPSCLK_S 0 +/** DSI_HOST_PHY_TXEXITULPSCLK : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TXEXITULPSCLK (BIT(1)) +#define DSI_HOST_PHY_TXEXITULPSCLK_M (DSI_HOST_PHY_TXEXITULPSCLK_V << DSI_HOST_PHY_TXEXITULPSCLK_S) +#define DSI_HOST_PHY_TXEXITULPSCLK_V 0x00000001U +#define DSI_HOST_PHY_TXEXITULPSCLK_S 1 +/** DSI_HOST_PHY_TXREQULPSLAN : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TXREQULPSLAN (BIT(2)) +#define DSI_HOST_PHY_TXREQULPSLAN_M (DSI_HOST_PHY_TXREQULPSLAN_V << DSI_HOST_PHY_TXREQULPSLAN_S) +#define DSI_HOST_PHY_TXREQULPSLAN_V 0x00000001U +#define DSI_HOST_PHY_TXREQULPSLAN_S 2 +/** DSI_HOST_PHY_TXEXITULPSLAN : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TXEXITULPSLAN (BIT(3)) +#define DSI_HOST_PHY_TXEXITULPSLAN_M (DSI_HOST_PHY_TXEXITULPSLAN_V << DSI_HOST_PHY_TXEXITULPSLAN_S) +#define DSI_HOST_PHY_TXEXITULPSLAN_V 0x00000001U +#define DSI_HOST_PHY_TXEXITULPSLAN_S 3 + +/** DSI_HOST_PHY_TX_TRIGGERS_REG register + * NA + */ +#define DSI_HOST_PHY_TX_TRIGGERS_REG (DR_REG_DSI_HOST_BASE + 0xac) +/** DSI_HOST_PHY_TX_TRIGGERS : R/W; bitpos: [3:0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TX_TRIGGERS 0x0000000FU +#define DSI_HOST_PHY_TX_TRIGGERS_M (DSI_HOST_PHY_TX_TRIGGERS_V << DSI_HOST_PHY_TX_TRIGGERS_S) +#define DSI_HOST_PHY_TX_TRIGGERS_V 0x0000000FU +#define DSI_HOST_PHY_TX_TRIGGERS_S 0 + +/** DSI_HOST_PHY_STATUS_REG register + * NA + */ +#define DSI_HOST_PHY_STATUS_REG (DR_REG_DSI_HOST_BASE + 0xb0) +/** DSI_HOST_PHY_LOCK : RO; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_LOCK (BIT(0)) +#define DSI_HOST_PHY_LOCK_M (DSI_HOST_PHY_LOCK_V << DSI_HOST_PHY_LOCK_S) +#define DSI_HOST_PHY_LOCK_V 0x00000001U +#define DSI_HOST_PHY_LOCK_S 0 +/** DSI_HOST_PHY_DIRECTION : RO; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_PHY_DIRECTION (BIT(1)) +#define DSI_HOST_PHY_DIRECTION_M (DSI_HOST_PHY_DIRECTION_V << DSI_HOST_PHY_DIRECTION_S) +#define DSI_HOST_PHY_DIRECTION_V 0x00000001U +#define DSI_HOST_PHY_DIRECTION_S 1 +/** DSI_HOST_PHY_STOPSTATECLKLANE : RO; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_PHY_STOPSTATECLKLANE (BIT(2)) +#define DSI_HOST_PHY_STOPSTATECLKLANE_M (DSI_HOST_PHY_STOPSTATECLKLANE_V << DSI_HOST_PHY_STOPSTATECLKLANE_S) +#define DSI_HOST_PHY_STOPSTATECLKLANE_V 0x00000001U +#define DSI_HOST_PHY_STOPSTATECLKLANE_S 2 +/** DSI_HOST_PHY_ULPSACTIVENOTCLK : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_PHY_ULPSACTIVENOTCLK (BIT(3)) +#define DSI_HOST_PHY_ULPSACTIVENOTCLK_M (DSI_HOST_PHY_ULPSACTIVENOTCLK_V << DSI_HOST_PHY_ULPSACTIVENOTCLK_S) +#define DSI_HOST_PHY_ULPSACTIVENOTCLK_V 0x00000001U +#define DSI_HOST_PHY_ULPSACTIVENOTCLK_S 3 +/** DSI_HOST_PHY_STOPSTATE0LANE : RO; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_PHY_STOPSTATE0LANE (BIT(4)) +#define DSI_HOST_PHY_STOPSTATE0LANE_M (DSI_HOST_PHY_STOPSTATE0LANE_V << DSI_HOST_PHY_STOPSTATE0LANE_S) +#define DSI_HOST_PHY_STOPSTATE0LANE_V 0x00000001U +#define DSI_HOST_PHY_STOPSTATE0LANE_S 4 +/** DSI_HOST_PHY_ULPSACTIVENOT0LANE : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_PHY_ULPSACTIVENOT0LANE (BIT(5)) +#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_M (DSI_HOST_PHY_ULPSACTIVENOT0LANE_V << DSI_HOST_PHY_ULPSACTIVENOT0LANE_S) +#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_V 0x00000001U +#define DSI_HOST_PHY_ULPSACTIVENOT0LANE_S 5 +/** DSI_HOST_PHY_RXULPSESC0LANE : RO; bitpos: [6]; default: 1; + * NA + */ +#define DSI_HOST_PHY_RXULPSESC0LANE (BIT(6)) +#define DSI_HOST_PHY_RXULPSESC0LANE_M (DSI_HOST_PHY_RXULPSESC0LANE_V << DSI_HOST_PHY_RXULPSESC0LANE_S) +#define DSI_HOST_PHY_RXULPSESC0LANE_V 0x00000001U +#define DSI_HOST_PHY_RXULPSESC0LANE_S 6 +/** DSI_HOST_PHY_STOPSTATE1LANE : RO; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_PHY_STOPSTATE1LANE (BIT(7)) +#define DSI_HOST_PHY_STOPSTATE1LANE_M (DSI_HOST_PHY_STOPSTATE1LANE_V << DSI_HOST_PHY_STOPSTATE1LANE_S) +#define DSI_HOST_PHY_STOPSTATE1LANE_V 0x00000001U +#define DSI_HOST_PHY_STOPSTATE1LANE_S 7 +/** DSI_HOST_PHY_ULPSACTIVENOT1LANE : RO; bitpos: [8]; default: 1; + * NA + */ +#define DSI_HOST_PHY_ULPSACTIVENOT1LANE (BIT(8)) +#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_M (DSI_HOST_PHY_ULPSACTIVENOT1LANE_V << DSI_HOST_PHY_ULPSACTIVENOT1LANE_S) +#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_V 0x00000001U +#define DSI_HOST_PHY_ULPSACTIVENOT1LANE_S 8 + +/** DSI_HOST_PHY_TST_CTRL0_REG register + * NA + */ +#define DSI_HOST_PHY_TST_CTRL0_REG (DR_REG_DSI_HOST_BASE + 0xb4) +/** DSI_HOST_PHY_TESTCLR : R/W; bitpos: [0]; default: 1; + * NA + */ +#define DSI_HOST_PHY_TESTCLR (BIT(0)) +#define DSI_HOST_PHY_TESTCLR_M (DSI_HOST_PHY_TESTCLR_V << DSI_HOST_PHY_TESTCLR_S) +#define DSI_HOST_PHY_TESTCLR_V 0x00000001U +#define DSI_HOST_PHY_TESTCLR_S 0 +/** DSI_HOST_PHY_TESTCLK : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TESTCLK (BIT(1)) +#define DSI_HOST_PHY_TESTCLK_M (DSI_HOST_PHY_TESTCLK_V << DSI_HOST_PHY_TESTCLK_S) +#define DSI_HOST_PHY_TESTCLK_V 0x00000001U +#define DSI_HOST_PHY_TESTCLK_S 1 + +/** DSI_HOST_PHY_TST_CTRL1_REG register + * NA + */ +#define DSI_HOST_PHY_TST_CTRL1_REG (DR_REG_DSI_HOST_BASE + 0xb8) +/** DSI_HOST_PHY_TESTDIN : R/W; bitpos: [7:0]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TESTDIN 0x000000FFU +#define DSI_HOST_PHY_TESTDIN_M (DSI_HOST_PHY_TESTDIN_V << DSI_HOST_PHY_TESTDIN_S) +#define DSI_HOST_PHY_TESTDIN_V 0x000000FFU +#define DSI_HOST_PHY_TESTDIN_S 0 +/** DSI_HOST_PHT_TESTDOUT : RO; bitpos: [15:8]; default: 0; + * NA + */ +#define DSI_HOST_PHT_TESTDOUT 0x000000FFU +#define DSI_HOST_PHT_TESTDOUT_M (DSI_HOST_PHT_TESTDOUT_V << DSI_HOST_PHT_TESTDOUT_S) +#define DSI_HOST_PHT_TESTDOUT_V 0x000000FFU +#define DSI_HOST_PHT_TESTDOUT_S 8 +/** DSI_HOST_PHY_TESTEN : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_PHY_TESTEN (BIT(16)) +#define DSI_HOST_PHY_TESTEN_M (DSI_HOST_PHY_TESTEN_V << DSI_HOST_PHY_TESTEN_S) +#define DSI_HOST_PHY_TESTEN_V 0x00000001U +#define DSI_HOST_PHY_TESTEN_S 16 + +/** DSI_HOST_INT_ST0_REG register + * NA + */ +#define DSI_HOST_INT_ST0_REG (DR_REG_DSI_HOST_BASE + 0xbc) +/** DSI_HOST_ACK_WITH_ERR_0 : RO; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_0 (BIT(0)) +#define DSI_HOST_ACK_WITH_ERR_0_M (DSI_HOST_ACK_WITH_ERR_0_V << DSI_HOST_ACK_WITH_ERR_0_S) +#define DSI_HOST_ACK_WITH_ERR_0_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_0_S 0 +/** DSI_HOST_ACK_WITH_ERR_1 : RO; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_1 (BIT(1)) +#define DSI_HOST_ACK_WITH_ERR_1_M (DSI_HOST_ACK_WITH_ERR_1_V << DSI_HOST_ACK_WITH_ERR_1_S) +#define DSI_HOST_ACK_WITH_ERR_1_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_1_S 1 +/** DSI_HOST_ACK_WITH_ERR_2 : RO; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_2 (BIT(2)) +#define DSI_HOST_ACK_WITH_ERR_2_M (DSI_HOST_ACK_WITH_ERR_2_V << DSI_HOST_ACK_WITH_ERR_2_S) +#define DSI_HOST_ACK_WITH_ERR_2_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_2_S 2 +/** DSI_HOST_ACK_WITH_ERR_3 : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_3 (BIT(3)) +#define DSI_HOST_ACK_WITH_ERR_3_M (DSI_HOST_ACK_WITH_ERR_3_V << DSI_HOST_ACK_WITH_ERR_3_S) +#define DSI_HOST_ACK_WITH_ERR_3_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_3_S 3 +/** DSI_HOST_ACK_WITH_ERR_4 : RO; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_4 (BIT(4)) +#define DSI_HOST_ACK_WITH_ERR_4_M (DSI_HOST_ACK_WITH_ERR_4_V << DSI_HOST_ACK_WITH_ERR_4_S) +#define DSI_HOST_ACK_WITH_ERR_4_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_4_S 4 +/** DSI_HOST_ACK_WITH_ERR_5 : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_5 (BIT(5)) +#define DSI_HOST_ACK_WITH_ERR_5_M (DSI_HOST_ACK_WITH_ERR_5_V << DSI_HOST_ACK_WITH_ERR_5_S) +#define DSI_HOST_ACK_WITH_ERR_5_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_5_S 5 +/** DSI_HOST_ACK_WITH_ERR_6 : RO; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_6 (BIT(6)) +#define DSI_HOST_ACK_WITH_ERR_6_M (DSI_HOST_ACK_WITH_ERR_6_V << DSI_HOST_ACK_WITH_ERR_6_S) +#define DSI_HOST_ACK_WITH_ERR_6_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_6_S 6 +/** DSI_HOST_ACK_WITH_ERR_7 : RO; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_7 (BIT(7)) +#define DSI_HOST_ACK_WITH_ERR_7_M (DSI_HOST_ACK_WITH_ERR_7_V << DSI_HOST_ACK_WITH_ERR_7_S) +#define DSI_HOST_ACK_WITH_ERR_7_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_7_S 7 +/** DSI_HOST_ACK_WITH_ERR_8 : RO; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_8 (BIT(8)) +#define DSI_HOST_ACK_WITH_ERR_8_M (DSI_HOST_ACK_WITH_ERR_8_V << DSI_HOST_ACK_WITH_ERR_8_S) +#define DSI_HOST_ACK_WITH_ERR_8_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_8_S 8 +/** DSI_HOST_ACK_WITH_ERR_9 : RO; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_9 (BIT(9)) +#define DSI_HOST_ACK_WITH_ERR_9_M (DSI_HOST_ACK_WITH_ERR_9_V << DSI_HOST_ACK_WITH_ERR_9_S) +#define DSI_HOST_ACK_WITH_ERR_9_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_9_S 9 +/** DSI_HOST_ACK_WITH_ERR_10 : RO; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_10 (BIT(10)) +#define DSI_HOST_ACK_WITH_ERR_10_M (DSI_HOST_ACK_WITH_ERR_10_V << DSI_HOST_ACK_WITH_ERR_10_S) +#define DSI_HOST_ACK_WITH_ERR_10_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_10_S 10 +/** DSI_HOST_ACK_WITH_ERR_11 : RO; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_11 (BIT(11)) +#define DSI_HOST_ACK_WITH_ERR_11_M (DSI_HOST_ACK_WITH_ERR_11_V << DSI_HOST_ACK_WITH_ERR_11_S) +#define DSI_HOST_ACK_WITH_ERR_11_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_11_S 11 +/** DSI_HOST_ACK_WITH_ERR_12 : RO; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_12 (BIT(12)) +#define DSI_HOST_ACK_WITH_ERR_12_M (DSI_HOST_ACK_WITH_ERR_12_V << DSI_HOST_ACK_WITH_ERR_12_S) +#define DSI_HOST_ACK_WITH_ERR_12_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_12_S 12 +/** DSI_HOST_ACK_WITH_ERR_13 : RO; bitpos: [13]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_13 (BIT(13)) +#define DSI_HOST_ACK_WITH_ERR_13_M (DSI_HOST_ACK_WITH_ERR_13_V << DSI_HOST_ACK_WITH_ERR_13_S) +#define DSI_HOST_ACK_WITH_ERR_13_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_13_S 13 +/** DSI_HOST_ACK_WITH_ERR_14 : RO; bitpos: [14]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_14 (BIT(14)) +#define DSI_HOST_ACK_WITH_ERR_14_M (DSI_HOST_ACK_WITH_ERR_14_V << DSI_HOST_ACK_WITH_ERR_14_S) +#define DSI_HOST_ACK_WITH_ERR_14_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_14_S 14 +/** DSI_HOST_ACK_WITH_ERR_15 : RO; bitpos: [15]; default: 0; + * NA + */ +#define DSI_HOST_ACK_WITH_ERR_15 (BIT(15)) +#define DSI_HOST_ACK_WITH_ERR_15_M (DSI_HOST_ACK_WITH_ERR_15_V << DSI_HOST_ACK_WITH_ERR_15_S) +#define DSI_HOST_ACK_WITH_ERR_15_V 0x00000001U +#define DSI_HOST_ACK_WITH_ERR_15_S 15 +/** DSI_HOST_DPHY_ERRORS_0 : RO; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_DPHY_ERRORS_0 (BIT(16)) +#define DSI_HOST_DPHY_ERRORS_0_M (DSI_HOST_DPHY_ERRORS_0_V << DSI_HOST_DPHY_ERRORS_0_S) +#define DSI_HOST_DPHY_ERRORS_0_V 0x00000001U +#define DSI_HOST_DPHY_ERRORS_0_S 16 +/** DSI_HOST_DPHY_ERRORS_1 : RO; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_DPHY_ERRORS_1 (BIT(17)) +#define DSI_HOST_DPHY_ERRORS_1_M (DSI_HOST_DPHY_ERRORS_1_V << DSI_HOST_DPHY_ERRORS_1_S) +#define DSI_HOST_DPHY_ERRORS_1_V 0x00000001U +#define DSI_HOST_DPHY_ERRORS_1_S 17 +/** DSI_HOST_DPHY_ERRORS_2 : RO; bitpos: [18]; default: 0; + * NA + */ +#define DSI_HOST_DPHY_ERRORS_2 (BIT(18)) +#define DSI_HOST_DPHY_ERRORS_2_M (DSI_HOST_DPHY_ERRORS_2_V << DSI_HOST_DPHY_ERRORS_2_S) +#define DSI_HOST_DPHY_ERRORS_2_V 0x00000001U +#define DSI_HOST_DPHY_ERRORS_2_S 18 +/** DSI_HOST_DPHY_ERRORS_3 : RO; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_DPHY_ERRORS_3 (BIT(19)) +#define DSI_HOST_DPHY_ERRORS_3_M (DSI_HOST_DPHY_ERRORS_3_V << DSI_HOST_DPHY_ERRORS_3_S) +#define DSI_HOST_DPHY_ERRORS_3_V 0x00000001U +#define DSI_HOST_DPHY_ERRORS_3_S 19 +/** DSI_HOST_DPHY_ERRORS_4 : RO; bitpos: [20]; default: 0; + * NA + */ +#define DSI_HOST_DPHY_ERRORS_4 (BIT(20)) +#define DSI_HOST_DPHY_ERRORS_4_M (DSI_HOST_DPHY_ERRORS_4_V << DSI_HOST_DPHY_ERRORS_4_S) +#define DSI_HOST_DPHY_ERRORS_4_V 0x00000001U +#define DSI_HOST_DPHY_ERRORS_4_S 20 + +/** DSI_HOST_INT_ST1_REG register + * NA + */ +#define DSI_HOST_INT_ST1_REG (DR_REG_DSI_HOST_BASE + 0xc0) +/** DSI_HOST_TO_HS_TX : RO; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_TO_HS_TX (BIT(0)) +#define DSI_HOST_TO_HS_TX_M (DSI_HOST_TO_HS_TX_V << DSI_HOST_TO_HS_TX_S) +#define DSI_HOST_TO_HS_TX_V 0x00000001U +#define DSI_HOST_TO_HS_TX_S 0 +/** DSI_HOST_TO_LP_RX : RO; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_TO_LP_RX (BIT(1)) +#define DSI_HOST_TO_LP_RX_M (DSI_HOST_TO_LP_RX_V << DSI_HOST_TO_LP_RX_S) +#define DSI_HOST_TO_LP_RX_V 0x00000001U +#define DSI_HOST_TO_LP_RX_S 1 +/** DSI_HOST_ECC_SINGLE_ERR : RO; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_ECC_SINGLE_ERR (BIT(2)) +#define DSI_HOST_ECC_SINGLE_ERR_M (DSI_HOST_ECC_SINGLE_ERR_V << DSI_HOST_ECC_SINGLE_ERR_S) +#define DSI_HOST_ECC_SINGLE_ERR_V 0x00000001U +#define DSI_HOST_ECC_SINGLE_ERR_S 2 +/** DSI_HOST_ECC_MILTI_ERR : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_ECC_MILTI_ERR (BIT(3)) +#define DSI_HOST_ECC_MILTI_ERR_M (DSI_HOST_ECC_MILTI_ERR_V << DSI_HOST_ECC_MILTI_ERR_S) +#define DSI_HOST_ECC_MILTI_ERR_V 0x00000001U +#define DSI_HOST_ECC_MILTI_ERR_S 3 +/** DSI_HOST_CRC_ERR : RO; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_CRC_ERR (BIT(4)) +#define DSI_HOST_CRC_ERR_M (DSI_HOST_CRC_ERR_V << DSI_HOST_CRC_ERR_S) +#define DSI_HOST_CRC_ERR_V 0x00000001U +#define DSI_HOST_CRC_ERR_S 4 +/** DSI_HOST_PKT_SIZE_ERR : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_PKT_SIZE_ERR (BIT(5)) +#define DSI_HOST_PKT_SIZE_ERR_M (DSI_HOST_PKT_SIZE_ERR_V << DSI_HOST_PKT_SIZE_ERR_S) +#define DSI_HOST_PKT_SIZE_ERR_V 0x00000001U +#define DSI_HOST_PKT_SIZE_ERR_S 5 +/** DSI_HOST_EOPT_ERR : RO; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_EOPT_ERR (BIT(6)) +#define DSI_HOST_EOPT_ERR_M (DSI_HOST_EOPT_ERR_V << DSI_HOST_EOPT_ERR_S) +#define DSI_HOST_EOPT_ERR_V 0x00000001U +#define DSI_HOST_EOPT_ERR_S 6 +/** DSI_HOST_DPI_PLD_WR_ERR : RO; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_DPI_PLD_WR_ERR (BIT(7)) +#define DSI_HOST_DPI_PLD_WR_ERR_M (DSI_HOST_DPI_PLD_WR_ERR_V << DSI_HOST_DPI_PLD_WR_ERR_S) +#define DSI_HOST_DPI_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_DPI_PLD_WR_ERR_S 7 +/** DSI_HOST_GEN_CMD_WR_ERR : RO; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_GEN_CMD_WR_ERR (BIT(8)) +#define DSI_HOST_GEN_CMD_WR_ERR_M (DSI_HOST_GEN_CMD_WR_ERR_V << DSI_HOST_GEN_CMD_WR_ERR_S) +#define DSI_HOST_GEN_CMD_WR_ERR_V 0x00000001U +#define DSI_HOST_GEN_CMD_WR_ERR_S 8 +/** DSI_HOST_GEN_PLD_WR_ERR : RO; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_WR_ERR (BIT(9)) +#define DSI_HOST_GEN_PLD_WR_ERR_M (DSI_HOST_GEN_PLD_WR_ERR_V << DSI_HOST_GEN_PLD_WR_ERR_S) +#define DSI_HOST_GEN_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_GEN_PLD_WR_ERR_S 9 +/** DSI_HOST_GEN_PLD_SEND_ERR : RO; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_SEND_ERR (BIT(10)) +#define DSI_HOST_GEN_PLD_SEND_ERR_M (DSI_HOST_GEN_PLD_SEND_ERR_V << DSI_HOST_GEN_PLD_SEND_ERR_S) +#define DSI_HOST_GEN_PLD_SEND_ERR_V 0x00000001U +#define DSI_HOST_GEN_PLD_SEND_ERR_S 10 +/** DSI_HOST_GEN_PLD_RD_ERR : RO; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_RD_ERR (BIT(11)) +#define DSI_HOST_GEN_PLD_RD_ERR_M (DSI_HOST_GEN_PLD_RD_ERR_V << DSI_HOST_GEN_PLD_RD_ERR_S) +#define DSI_HOST_GEN_PLD_RD_ERR_V 0x00000001U +#define DSI_HOST_GEN_PLD_RD_ERR_S 11 +/** DSI_HOST_GEN_PLD_RECEV_ERR : RO; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_GEN_PLD_RECEV_ERR (BIT(12)) +#define DSI_HOST_GEN_PLD_RECEV_ERR_M (DSI_HOST_GEN_PLD_RECEV_ERR_V << DSI_HOST_GEN_PLD_RECEV_ERR_S) +#define DSI_HOST_GEN_PLD_RECEV_ERR_V 0x00000001U +#define DSI_HOST_GEN_PLD_RECEV_ERR_S 12 +/** DSI_HOST_DPI_BUFF_PLD_UNDER : RO; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_DPI_BUFF_PLD_UNDER (BIT(19)) +#define DSI_HOST_DPI_BUFF_PLD_UNDER_M (DSI_HOST_DPI_BUFF_PLD_UNDER_V << DSI_HOST_DPI_BUFF_PLD_UNDER_S) +#define DSI_HOST_DPI_BUFF_PLD_UNDER_V 0x00000001U +#define DSI_HOST_DPI_BUFF_PLD_UNDER_S 19 + +/** DSI_HOST_INT_MSK0_REG register + * NA + */ +#define DSI_HOST_INT_MSK0_REG (DR_REG_DSI_HOST_BASE + 0xc4) +/** DSI_HOST_MASK_ACK_WITH_ERR_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_0 (BIT(0)) +#define DSI_HOST_MASK_ACK_WITH_ERR_0_M (DSI_HOST_MASK_ACK_WITH_ERR_0_V << DSI_HOST_MASK_ACK_WITH_ERR_0_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_0_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_0_S 0 +/** DSI_HOST_MASK_ACK_WITH_ERR_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_1 (BIT(1)) +#define DSI_HOST_MASK_ACK_WITH_ERR_1_M (DSI_HOST_MASK_ACK_WITH_ERR_1_V << DSI_HOST_MASK_ACK_WITH_ERR_1_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_1_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_1_S 1 +/** DSI_HOST_MASK_ACK_WITH_ERR_2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_2 (BIT(2)) +#define DSI_HOST_MASK_ACK_WITH_ERR_2_M (DSI_HOST_MASK_ACK_WITH_ERR_2_V << DSI_HOST_MASK_ACK_WITH_ERR_2_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_2_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_2_S 2 +/** DSI_HOST_MASK_ACK_WITH_ERR_3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_3 (BIT(3)) +#define DSI_HOST_MASK_ACK_WITH_ERR_3_M (DSI_HOST_MASK_ACK_WITH_ERR_3_V << DSI_HOST_MASK_ACK_WITH_ERR_3_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_3_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_3_S 3 +/** DSI_HOST_MASK_ACK_WITH_ERR_4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_4 (BIT(4)) +#define DSI_HOST_MASK_ACK_WITH_ERR_4_M (DSI_HOST_MASK_ACK_WITH_ERR_4_V << DSI_HOST_MASK_ACK_WITH_ERR_4_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_4_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_4_S 4 +/** DSI_HOST_MASK_ACK_WITH_ERR_5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_5 (BIT(5)) +#define DSI_HOST_MASK_ACK_WITH_ERR_5_M (DSI_HOST_MASK_ACK_WITH_ERR_5_V << DSI_HOST_MASK_ACK_WITH_ERR_5_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_5_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_5_S 5 +/** DSI_HOST_MASK_ACK_WITH_ERR_6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_6 (BIT(6)) +#define DSI_HOST_MASK_ACK_WITH_ERR_6_M (DSI_HOST_MASK_ACK_WITH_ERR_6_V << DSI_HOST_MASK_ACK_WITH_ERR_6_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_6_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_6_S 6 +/** DSI_HOST_MASK_ACK_WITH_ERR_7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_7 (BIT(7)) +#define DSI_HOST_MASK_ACK_WITH_ERR_7_M (DSI_HOST_MASK_ACK_WITH_ERR_7_V << DSI_HOST_MASK_ACK_WITH_ERR_7_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_7_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_7_S 7 +/** DSI_HOST_MASK_ACK_WITH_ERR_8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_8 (BIT(8)) +#define DSI_HOST_MASK_ACK_WITH_ERR_8_M (DSI_HOST_MASK_ACK_WITH_ERR_8_V << DSI_HOST_MASK_ACK_WITH_ERR_8_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_8_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_8_S 8 +/** DSI_HOST_MASK_ACK_WITH_ERR_9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_9 (BIT(9)) +#define DSI_HOST_MASK_ACK_WITH_ERR_9_M (DSI_HOST_MASK_ACK_WITH_ERR_9_V << DSI_HOST_MASK_ACK_WITH_ERR_9_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_9_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_9_S 9 +/** DSI_HOST_MASK_ACK_WITH_ERR_10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_10 (BIT(10)) +#define DSI_HOST_MASK_ACK_WITH_ERR_10_M (DSI_HOST_MASK_ACK_WITH_ERR_10_V << DSI_HOST_MASK_ACK_WITH_ERR_10_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_10_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_10_S 10 +/** DSI_HOST_MASK_ACK_WITH_ERR_11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_11 (BIT(11)) +#define DSI_HOST_MASK_ACK_WITH_ERR_11_M (DSI_HOST_MASK_ACK_WITH_ERR_11_V << DSI_HOST_MASK_ACK_WITH_ERR_11_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_11_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_11_S 11 +/** DSI_HOST_MASK_ACK_WITH_ERR_12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_12 (BIT(12)) +#define DSI_HOST_MASK_ACK_WITH_ERR_12_M (DSI_HOST_MASK_ACK_WITH_ERR_12_V << DSI_HOST_MASK_ACK_WITH_ERR_12_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_12_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_12_S 12 +/** DSI_HOST_MASK_ACK_WITH_ERR_13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_13 (BIT(13)) +#define DSI_HOST_MASK_ACK_WITH_ERR_13_M (DSI_HOST_MASK_ACK_WITH_ERR_13_V << DSI_HOST_MASK_ACK_WITH_ERR_13_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_13_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_13_S 13 +/** DSI_HOST_MASK_ACK_WITH_ERR_14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_14 (BIT(14)) +#define DSI_HOST_MASK_ACK_WITH_ERR_14_M (DSI_HOST_MASK_ACK_WITH_ERR_14_V << DSI_HOST_MASK_ACK_WITH_ERR_14_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_14_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_14_S 14 +/** DSI_HOST_MASK_ACK_WITH_ERR_15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ACK_WITH_ERR_15 (BIT(15)) +#define DSI_HOST_MASK_ACK_WITH_ERR_15_M (DSI_HOST_MASK_ACK_WITH_ERR_15_V << DSI_HOST_MASK_ACK_WITH_ERR_15_S) +#define DSI_HOST_MASK_ACK_WITH_ERR_15_V 0x00000001U +#define DSI_HOST_MASK_ACK_WITH_ERR_15_S 15 +/** DSI_HOST_MASK_DPHY_ERRORS_0 : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPHY_ERRORS_0 (BIT(16)) +#define DSI_HOST_MASK_DPHY_ERRORS_0_M (DSI_HOST_MASK_DPHY_ERRORS_0_V << DSI_HOST_MASK_DPHY_ERRORS_0_S) +#define DSI_HOST_MASK_DPHY_ERRORS_0_V 0x00000001U +#define DSI_HOST_MASK_DPHY_ERRORS_0_S 16 +/** DSI_HOST_MASK_DPHY_ERRORS_1 : R/W; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPHY_ERRORS_1 (BIT(17)) +#define DSI_HOST_MASK_DPHY_ERRORS_1_M (DSI_HOST_MASK_DPHY_ERRORS_1_V << DSI_HOST_MASK_DPHY_ERRORS_1_S) +#define DSI_HOST_MASK_DPHY_ERRORS_1_V 0x00000001U +#define DSI_HOST_MASK_DPHY_ERRORS_1_S 17 +/** DSI_HOST_MASK_DPHY_ERRORS_2 : R/W; bitpos: [18]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPHY_ERRORS_2 (BIT(18)) +#define DSI_HOST_MASK_DPHY_ERRORS_2_M (DSI_HOST_MASK_DPHY_ERRORS_2_V << DSI_HOST_MASK_DPHY_ERRORS_2_S) +#define DSI_HOST_MASK_DPHY_ERRORS_2_V 0x00000001U +#define DSI_HOST_MASK_DPHY_ERRORS_2_S 18 +/** DSI_HOST_MASK_DPHY_ERRORS_3 : R/W; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPHY_ERRORS_3 (BIT(19)) +#define DSI_HOST_MASK_DPHY_ERRORS_3_M (DSI_HOST_MASK_DPHY_ERRORS_3_V << DSI_HOST_MASK_DPHY_ERRORS_3_S) +#define DSI_HOST_MASK_DPHY_ERRORS_3_V 0x00000001U +#define DSI_HOST_MASK_DPHY_ERRORS_3_S 19 +/** DSI_HOST_MASK_DPHY_ERRORS_4 : R/W; bitpos: [20]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPHY_ERRORS_4 (BIT(20)) +#define DSI_HOST_MASK_DPHY_ERRORS_4_M (DSI_HOST_MASK_DPHY_ERRORS_4_V << DSI_HOST_MASK_DPHY_ERRORS_4_S) +#define DSI_HOST_MASK_DPHY_ERRORS_4_V 0x00000001U +#define DSI_HOST_MASK_DPHY_ERRORS_4_S 20 + +/** DSI_HOST_INT_MSK1_REG register + * NA + */ +#define DSI_HOST_INT_MSK1_REG (DR_REG_DSI_HOST_BASE + 0xc8) +/** DSI_HOST_MASK_TO_HS_TX : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_MASK_TO_HS_TX (BIT(0)) +#define DSI_HOST_MASK_TO_HS_TX_M (DSI_HOST_MASK_TO_HS_TX_V << DSI_HOST_MASK_TO_HS_TX_S) +#define DSI_HOST_MASK_TO_HS_TX_V 0x00000001U +#define DSI_HOST_MASK_TO_HS_TX_S 0 +/** DSI_HOST_MASK_TO_LP_RX : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_MASK_TO_LP_RX (BIT(1)) +#define DSI_HOST_MASK_TO_LP_RX_M (DSI_HOST_MASK_TO_LP_RX_V << DSI_HOST_MASK_TO_LP_RX_S) +#define DSI_HOST_MASK_TO_LP_RX_V 0x00000001U +#define DSI_HOST_MASK_TO_LP_RX_S 1 +/** DSI_HOST_MASK_ECC_SINGLE_ERR : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ECC_SINGLE_ERR (BIT(2)) +#define DSI_HOST_MASK_ECC_SINGLE_ERR_M (DSI_HOST_MASK_ECC_SINGLE_ERR_V << DSI_HOST_MASK_ECC_SINGLE_ERR_S) +#define DSI_HOST_MASK_ECC_SINGLE_ERR_V 0x00000001U +#define DSI_HOST_MASK_ECC_SINGLE_ERR_S 2 +/** DSI_HOST_MASK_ECC_MILTI_ERR : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_MASK_ECC_MILTI_ERR (BIT(3)) +#define DSI_HOST_MASK_ECC_MILTI_ERR_M (DSI_HOST_MASK_ECC_MILTI_ERR_V << DSI_HOST_MASK_ECC_MILTI_ERR_S) +#define DSI_HOST_MASK_ECC_MILTI_ERR_V 0x00000001U +#define DSI_HOST_MASK_ECC_MILTI_ERR_S 3 +/** DSI_HOST_MASK_CRC_ERR : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_MASK_CRC_ERR (BIT(4)) +#define DSI_HOST_MASK_CRC_ERR_M (DSI_HOST_MASK_CRC_ERR_V << DSI_HOST_MASK_CRC_ERR_S) +#define DSI_HOST_MASK_CRC_ERR_V 0x00000001U +#define DSI_HOST_MASK_CRC_ERR_S 4 +/** DSI_HOST_MASK_PKT_SIZE_ERR : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_MASK_PKT_SIZE_ERR (BIT(5)) +#define DSI_HOST_MASK_PKT_SIZE_ERR_M (DSI_HOST_MASK_PKT_SIZE_ERR_V << DSI_HOST_MASK_PKT_SIZE_ERR_S) +#define DSI_HOST_MASK_PKT_SIZE_ERR_V 0x00000001U +#define DSI_HOST_MASK_PKT_SIZE_ERR_S 5 +/** DSI_HOST_MASK_EOPT_ERR : R/W; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_MASK_EOPT_ERR (BIT(6)) +#define DSI_HOST_MASK_EOPT_ERR_M (DSI_HOST_MASK_EOPT_ERR_V << DSI_HOST_MASK_EOPT_ERR_S) +#define DSI_HOST_MASK_EOPT_ERR_V 0x00000001U +#define DSI_HOST_MASK_EOPT_ERR_S 6 +/** DSI_HOST_MASK_DPI_PLD_WR_ERR : R/W; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPI_PLD_WR_ERR (BIT(7)) +#define DSI_HOST_MASK_DPI_PLD_WR_ERR_M (DSI_HOST_MASK_DPI_PLD_WR_ERR_V << DSI_HOST_MASK_DPI_PLD_WR_ERR_S) +#define DSI_HOST_MASK_DPI_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_MASK_DPI_PLD_WR_ERR_S 7 +/** DSI_HOST_MASK_GEN_CMD_WR_ERR : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_MASK_GEN_CMD_WR_ERR (BIT(8)) +#define DSI_HOST_MASK_GEN_CMD_WR_ERR_M (DSI_HOST_MASK_GEN_CMD_WR_ERR_V << DSI_HOST_MASK_GEN_CMD_WR_ERR_S) +#define DSI_HOST_MASK_GEN_CMD_WR_ERR_V 0x00000001U +#define DSI_HOST_MASK_GEN_CMD_WR_ERR_S 8 +/** DSI_HOST_MASK_GEN_PLD_WR_ERR : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_MASK_GEN_PLD_WR_ERR (BIT(9)) +#define DSI_HOST_MASK_GEN_PLD_WR_ERR_M (DSI_HOST_MASK_GEN_PLD_WR_ERR_V << DSI_HOST_MASK_GEN_PLD_WR_ERR_S) +#define DSI_HOST_MASK_GEN_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_MASK_GEN_PLD_WR_ERR_S 9 +/** DSI_HOST_MASK_GEN_PLD_SEND_ERR : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_MASK_GEN_PLD_SEND_ERR (BIT(10)) +#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_M (DSI_HOST_MASK_GEN_PLD_SEND_ERR_V << DSI_HOST_MASK_GEN_PLD_SEND_ERR_S) +#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_V 0x00000001U +#define DSI_HOST_MASK_GEN_PLD_SEND_ERR_S 10 +/** DSI_HOST_MASK_GEN_PLD_RD_ERR : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_MASK_GEN_PLD_RD_ERR (BIT(11)) +#define DSI_HOST_MASK_GEN_PLD_RD_ERR_M (DSI_HOST_MASK_GEN_PLD_RD_ERR_V << DSI_HOST_MASK_GEN_PLD_RD_ERR_S) +#define DSI_HOST_MASK_GEN_PLD_RD_ERR_V 0x00000001U +#define DSI_HOST_MASK_GEN_PLD_RD_ERR_S 11 +/** DSI_HOST_MASK_GEN_PLD_RECEV_ERR : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR (BIT(12)) +#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_M (DSI_HOST_MASK_GEN_PLD_RECEV_ERR_V << DSI_HOST_MASK_GEN_PLD_RECEV_ERR_S) +#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_V 0x00000001U +#define DSI_HOST_MASK_GEN_PLD_RECEV_ERR_S 12 +/** DSI_HOST_MASK_DPI_BUFF_PLD_UNDER : R/W; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER (BIT(19)) +#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_M (DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_V << DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_S) +#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_V 0x00000001U +#define DSI_HOST_MASK_DPI_BUFF_PLD_UNDER_S 19 + +/** DSI_HOST_PHY_CAL_REG register + * NA + */ +#define DSI_HOST_PHY_CAL_REG (DR_REG_DSI_HOST_BASE + 0xcc) +/** DSI_HOST_TXSKEWCALHS : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_TXSKEWCALHS (BIT(0)) +#define DSI_HOST_TXSKEWCALHS_M (DSI_HOST_TXSKEWCALHS_V << DSI_HOST_TXSKEWCALHS_S) +#define DSI_HOST_TXSKEWCALHS_V 0x00000001U +#define DSI_HOST_TXSKEWCALHS_S 0 + +/** DSI_HOST_INT_FORCE0_REG register + * NA + */ +#define DSI_HOST_INT_FORCE0_REG (DR_REG_DSI_HOST_BASE + 0xd8) +/** DSI_HOST_FORCE_ACK_WITH_ERR_0 : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_0 (BIT(0)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_0_M (DSI_HOST_FORCE_ACK_WITH_ERR_0_V << DSI_HOST_FORCE_ACK_WITH_ERR_0_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_0_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_0_S 0 +/** DSI_HOST_FORCE_ACK_WITH_ERR_1 : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_1 (BIT(1)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_1_M (DSI_HOST_FORCE_ACK_WITH_ERR_1_V << DSI_HOST_FORCE_ACK_WITH_ERR_1_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_1_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_1_S 1 +/** DSI_HOST_FORCE_ACK_WITH_ERR_2 : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_2 (BIT(2)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_2_M (DSI_HOST_FORCE_ACK_WITH_ERR_2_V << DSI_HOST_FORCE_ACK_WITH_ERR_2_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_2_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_2_S 2 +/** DSI_HOST_FORCE_ACK_WITH_ERR_3 : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_3 (BIT(3)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_3_M (DSI_HOST_FORCE_ACK_WITH_ERR_3_V << DSI_HOST_FORCE_ACK_WITH_ERR_3_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_3_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_3_S 3 +/** DSI_HOST_FORCE_ACK_WITH_ERR_4 : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_4 (BIT(4)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_4_M (DSI_HOST_FORCE_ACK_WITH_ERR_4_V << DSI_HOST_FORCE_ACK_WITH_ERR_4_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_4_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_4_S 4 +/** DSI_HOST_FORCE_ACK_WITH_ERR_5 : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_5 (BIT(5)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_5_M (DSI_HOST_FORCE_ACK_WITH_ERR_5_V << DSI_HOST_FORCE_ACK_WITH_ERR_5_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_5_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_5_S 5 +/** DSI_HOST_FORCE_ACK_WITH_ERR_6 : R/W; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_6 (BIT(6)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_6_M (DSI_HOST_FORCE_ACK_WITH_ERR_6_V << DSI_HOST_FORCE_ACK_WITH_ERR_6_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_6_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_6_S 6 +/** DSI_HOST_FORCE_ACK_WITH_ERR_7 : R/W; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_7 (BIT(7)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_7_M (DSI_HOST_FORCE_ACK_WITH_ERR_7_V << DSI_HOST_FORCE_ACK_WITH_ERR_7_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_7_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_7_S 7 +/** DSI_HOST_FORCE_ACK_WITH_ERR_8 : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_8 (BIT(8)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_8_M (DSI_HOST_FORCE_ACK_WITH_ERR_8_V << DSI_HOST_FORCE_ACK_WITH_ERR_8_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_8_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_8_S 8 +/** DSI_HOST_FORCE_ACK_WITH_ERR_9 : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_9 (BIT(9)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_9_M (DSI_HOST_FORCE_ACK_WITH_ERR_9_V << DSI_HOST_FORCE_ACK_WITH_ERR_9_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_9_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_9_S 9 +/** DSI_HOST_FORCE_ACK_WITH_ERR_10 : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_10 (BIT(10)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_10_M (DSI_HOST_FORCE_ACK_WITH_ERR_10_V << DSI_HOST_FORCE_ACK_WITH_ERR_10_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_10_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_10_S 10 +/** DSI_HOST_FORCE_ACK_WITH_ERR_11 : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_11 (BIT(11)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_11_M (DSI_HOST_FORCE_ACK_WITH_ERR_11_V << DSI_HOST_FORCE_ACK_WITH_ERR_11_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_11_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_11_S 11 +/** DSI_HOST_FORCE_ACK_WITH_ERR_12 : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_12 (BIT(12)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_12_M (DSI_HOST_FORCE_ACK_WITH_ERR_12_V << DSI_HOST_FORCE_ACK_WITH_ERR_12_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_12_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_12_S 12 +/** DSI_HOST_FORCE_ACK_WITH_ERR_13 : R/W; bitpos: [13]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_13 (BIT(13)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_13_M (DSI_HOST_FORCE_ACK_WITH_ERR_13_V << DSI_HOST_FORCE_ACK_WITH_ERR_13_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_13_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_13_S 13 +/** DSI_HOST_FORCE_ACK_WITH_ERR_14 : R/W; bitpos: [14]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_14 (BIT(14)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_14_M (DSI_HOST_FORCE_ACK_WITH_ERR_14_V << DSI_HOST_FORCE_ACK_WITH_ERR_14_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_14_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_14_S 14 +/** DSI_HOST_FORCE_ACK_WITH_ERR_15 : R/W; bitpos: [15]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ACK_WITH_ERR_15 (BIT(15)) +#define DSI_HOST_FORCE_ACK_WITH_ERR_15_M (DSI_HOST_FORCE_ACK_WITH_ERR_15_V << DSI_HOST_FORCE_ACK_WITH_ERR_15_S) +#define DSI_HOST_FORCE_ACK_WITH_ERR_15_V 0x00000001U +#define DSI_HOST_FORCE_ACK_WITH_ERR_15_S 15 +/** DSI_HOST_FORCE_DPHY_ERRORS_0 : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPHY_ERRORS_0 (BIT(16)) +#define DSI_HOST_FORCE_DPHY_ERRORS_0_M (DSI_HOST_FORCE_DPHY_ERRORS_0_V << DSI_HOST_FORCE_DPHY_ERRORS_0_S) +#define DSI_HOST_FORCE_DPHY_ERRORS_0_V 0x00000001U +#define DSI_HOST_FORCE_DPHY_ERRORS_0_S 16 +/** DSI_HOST_FORCE_DPHY_ERRORS_1 : R/W; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPHY_ERRORS_1 (BIT(17)) +#define DSI_HOST_FORCE_DPHY_ERRORS_1_M (DSI_HOST_FORCE_DPHY_ERRORS_1_V << DSI_HOST_FORCE_DPHY_ERRORS_1_S) +#define DSI_HOST_FORCE_DPHY_ERRORS_1_V 0x00000001U +#define DSI_HOST_FORCE_DPHY_ERRORS_1_S 17 +/** DSI_HOST_FORCE_DPHY_ERRORS_2 : R/W; bitpos: [18]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPHY_ERRORS_2 (BIT(18)) +#define DSI_HOST_FORCE_DPHY_ERRORS_2_M (DSI_HOST_FORCE_DPHY_ERRORS_2_V << DSI_HOST_FORCE_DPHY_ERRORS_2_S) +#define DSI_HOST_FORCE_DPHY_ERRORS_2_V 0x00000001U +#define DSI_HOST_FORCE_DPHY_ERRORS_2_S 18 +/** DSI_HOST_FORCE_DPHY_ERRORS_3 : R/W; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPHY_ERRORS_3 (BIT(19)) +#define DSI_HOST_FORCE_DPHY_ERRORS_3_M (DSI_HOST_FORCE_DPHY_ERRORS_3_V << DSI_HOST_FORCE_DPHY_ERRORS_3_S) +#define DSI_HOST_FORCE_DPHY_ERRORS_3_V 0x00000001U +#define DSI_HOST_FORCE_DPHY_ERRORS_3_S 19 +/** DSI_HOST_FORCE_DPHY_ERRORS_4 : R/W; bitpos: [20]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPHY_ERRORS_4 (BIT(20)) +#define DSI_HOST_FORCE_DPHY_ERRORS_4_M (DSI_HOST_FORCE_DPHY_ERRORS_4_V << DSI_HOST_FORCE_DPHY_ERRORS_4_S) +#define DSI_HOST_FORCE_DPHY_ERRORS_4_V 0x00000001U +#define DSI_HOST_FORCE_DPHY_ERRORS_4_S 20 + +/** DSI_HOST_INT_FORCE1_REG register + * NA + */ +#define DSI_HOST_INT_FORCE1_REG (DR_REG_DSI_HOST_BASE + 0xdc) +/** DSI_HOST_FORCE_TO_HS_TX : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_TO_HS_TX (BIT(0)) +#define DSI_HOST_FORCE_TO_HS_TX_M (DSI_HOST_FORCE_TO_HS_TX_V << DSI_HOST_FORCE_TO_HS_TX_S) +#define DSI_HOST_FORCE_TO_HS_TX_V 0x00000001U +#define DSI_HOST_FORCE_TO_HS_TX_S 0 +/** DSI_HOST_FORCE_TO_LP_RX : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_TO_LP_RX (BIT(1)) +#define DSI_HOST_FORCE_TO_LP_RX_M (DSI_HOST_FORCE_TO_LP_RX_V << DSI_HOST_FORCE_TO_LP_RX_S) +#define DSI_HOST_FORCE_TO_LP_RX_V 0x00000001U +#define DSI_HOST_FORCE_TO_LP_RX_S 1 +/** DSI_HOST_FORCE_ECC_SINGLE_ERR : R/W; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ECC_SINGLE_ERR (BIT(2)) +#define DSI_HOST_FORCE_ECC_SINGLE_ERR_M (DSI_HOST_FORCE_ECC_SINGLE_ERR_V << DSI_HOST_FORCE_ECC_SINGLE_ERR_S) +#define DSI_HOST_FORCE_ECC_SINGLE_ERR_V 0x00000001U +#define DSI_HOST_FORCE_ECC_SINGLE_ERR_S 2 +/** DSI_HOST_FORCE_ECC_MILTI_ERR : R/W; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_ECC_MILTI_ERR (BIT(3)) +#define DSI_HOST_FORCE_ECC_MILTI_ERR_M (DSI_HOST_FORCE_ECC_MILTI_ERR_V << DSI_HOST_FORCE_ECC_MILTI_ERR_S) +#define DSI_HOST_FORCE_ECC_MILTI_ERR_V 0x00000001U +#define DSI_HOST_FORCE_ECC_MILTI_ERR_S 3 +/** DSI_HOST_FORCE_CRC_ERR : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_CRC_ERR (BIT(4)) +#define DSI_HOST_FORCE_CRC_ERR_M (DSI_HOST_FORCE_CRC_ERR_V << DSI_HOST_FORCE_CRC_ERR_S) +#define DSI_HOST_FORCE_CRC_ERR_V 0x00000001U +#define DSI_HOST_FORCE_CRC_ERR_S 4 +/** DSI_HOST_FORCE_PKT_SIZE_ERR : R/W; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_PKT_SIZE_ERR (BIT(5)) +#define DSI_HOST_FORCE_PKT_SIZE_ERR_M (DSI_HOST_FORCE_PKT_SIZE_ERR_V << DSI_HOST_FORCE_PKT_SIZE_ERR_S) +#define DSI_HOST_FORCE_PKT_SIZE_ERR_V 0x00000001U +#define DSI_HOST_FORCE_PKT_SIZE_ERR_S 5 +/** DSI_HOST_FORCE_EOPT_ERR : R/W; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_EOPT_ERR (BIT(6)) +#define DSI_HOST_FORCE_EOPT_ERR_M (DSI_HOST_FORCE_EOPT_ERR_V << DSI_HOST_FORCE_EOPT_ERR_S) +#define DSI_HOST_FORCE_EOPT_ERR_V 0x00000001U +#define DSI_HOST_FORCE_EOPT_ERR_S 6 +/** DSI_HOST_FORCE_DPI_PLD_WR_ERR : R/W; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPI_PLD_WR_ERR (BIT(7)) +#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_M (DSI_HOST_FORCE_DPI_PLD_WR_ERR_V << DSI_HOST_FORCE_DPI_PLD_WR_ERR_S) +#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_FORCE_DPI_PLD_WR_ERR_S 7 +/** DSI_HOST_FORCE_GEN_CMD_WR_ERR : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_GEN_CMD_WR_ERR (BIT(8)) +#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_M (DSI_HOST_FORCE_GEN_CMD_WR_ERR_V << DSI_HOST_FORCE_GEN_CMD_WR_ERR_S) +#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_V 0x00000001U +#define DSI_HOST_FORCE_GEN_CMD_WR_ERR_S 8 +/** DSI_HOST_FORCE_GEN_PLD_WR_ERR : R/W; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_GEN_PLD_WR_ERR (BIT(9)) +#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_M (DSI_HOST_FORCE_GEN_PLD_WR_ERR_V << DSI_HOST_FORCE_GEN_PLD_WR_ERR_S) +#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_V 0x00000001U +#define DSI_HOST_FORCE_GEN_PLD_WR_ERR_S 9 +/** DSI_HOST_FORCE_GEN_PLD_SEND_ERR : R/W; bitpos: [10]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR (BIT(10)) +#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_M (DSI_HOST_FORCE_GEN_PLD_SEND_ERR_V << DSI_HOST_FORCE_GEN_PLD_SEND_ERR_S) +#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_V 0x00000001U +#define DSI_HOST_FORCE_GEN_PLD_SEND_ERR_S 10 +/** DSI_HOST_FORCE_GEN_PLD_RD_ERR : R/W; bitpos: [11]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_GEN_PLD_RD_ERR (BIT(11)) +#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_M (DSI_HOST_FORCE_GEN_PLD_RD_ERR_V << DSI_HOST_FORCE_GEN_PLD_RD_ERR_S) +#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_V 0x00000001U +#define DSI_HOST_FORCE_GEN_PLD_RD_ERR_S 11 +/** DSI_HOST_FORCE_GEN_PLD_RECEV_ERR : R/W; bitpos: [12]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR (BIT(12)) +#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_M (DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_V << DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_S) +#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_V 0x00000001U +#define DSI_HOST_FORCE_GEN_PLD_RECEV_ERR_S 12 +/** DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER : R/W; bitpos: [19]; default: 0; + * NA + */ +#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER (BIT(19)) +#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_M (DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_V << DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_S) +#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_V 0x00000001U +#define DSI_HOST_FORCE_DPI_BUFF_PLD_UNDER_S 19 + +/** DSI_HOST_DSC_PARAMETER_REG register + * NA + */ +#define DSI_HOST_DSC_PARAMETER_REG (DR_REG_DSI_HOST_BASE + 0xf0) +/** DSI_HOST_COMPRESSION_MODE : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_COMPRESSION_MODE (BIT(0)) +#define DSI_HOST_COMPRESSION_MODE_M (DSI_HOST_COMPRESSION_MODE_V << DSI_HOST_COMPRESSION_MODE_S) +#define DSI_HOST_COMPRESSION_MODE_V 0x00000001U +#define DSI_HOST_COMPRESSION_MODE_S 0 +/** DSI_HOST_COMPRESS_ALGO : R/W; bitpos: [9:8]; default: 0; + * NA + */ +#define DSI_HOST_COMPRESS_ALGO 0x00000003U +#define DSI_HOST_COMPRESS_ALGO_M (DSI_HOST_COMPRESS_ALGO_V << DSI_HOST_COMPRESS_ALGO_S) +#define DSI_HOST_COMPRESS_ALGO_V 0x00000003U +#define DSI_HOST_COMPRESS_ALGO_S 8 +/** DSI_HOST_PPS_SEL : R/W; bitpos: [17:16]; default: 0; + * NA + */ +#define DSI_HOST_PPS_SEL 0x00000003U +#define DSI_HOST_PPS_SEL_M (DSI_HOST_PPS_SEL_V << DSI_HOST_PPS_SEL_S) +#define DSI_HOST_PPS_SEL_V 0x00000003U +#define DSI_HOST_PPS_SEL_S 16 + +/** DSI_HOST_PHY_TMR_RD_CFG_REG register + * NA + */ +#define DSI_HOST_PHY_TMR_RD_CFG_REG (DR_REG_DSI_HOST_BASE + 0xf4) +/** DSI_HOST_MAX_RD_TIME : R/W; bitpos: [14:0]; default: 0; + * NA + */ +#define DSI_HOST_MAX_RD_TIME 0x00007FFFU +#define DSI_HOST_MAX_RD_TIME_M (DSI_HOST_MAX_RD_TIME_V << DSI_HOST_MAX_RD_TIME_S) +#define DSI_HOST_MAX_RD_TIME_V 0x00007FFFU +#define DSI_HOST_MAX_RD_TIME_S 0 + +/** DSI_HOST_VID_SHADOW_CTRL_REG register + * NA + */ +#define DSI_HOST_VID_SHADOW_CTRL_REG (DR_REG_DSI_HOST_BASE + 0x100) +/** DSI_HOST_VID_SHADOW_EN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_VID_SHADOW_EN (BIT(0)) +#define DSI_HOST_VID_SHADOW_EN_M (DSI_HOST_VID_SHADOW_EN_V << DSI_HOST_VID_SHADOW_EN_S) +#define DSI_HOST_VID_SHADOW_EN_V 0x00000001U +#define DSI_HOST_VID_SHADOW_EN_S 0 +/** DSI_HOST_VID_SHADOW_REQ : R/W; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_VID_SHADOW_REQ (BIT(8)) +#define DSI_HOST_VID_SHADOW_REQ_M (DSI_HOST_VID_SHADOW_REQ_V << DSI_HOST_VID_SHADOW_REQ_S) +#define DSI_HOST_VID_SHADOW_REQ_V 0x00000001U +#define DSI_HOST_VID_SHADOW_REQ_S 8 +/** DSI_HOST_VID_SHADOW_PIN_REQ : R/W; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_VID_SHADOW_PIN_REQ (BIT(16)) +#define DSI_HOST_VID_SHADOW_PIN_REQ_M (DSI_HOST_VID_SHADOW_PIN_REQ_V << DSI_HOST_VID_SHADOW_PIN_REQ_S) +#define DSI_HOST_VID_SHADOW_PIN_REQ_V 0x00000001U +#define DSI_HOST_VID_SHADOW_PIN_REQ_S 16 + +/** DSI_HOST_DPI_VCID_ACT_REG register + * NA + */ +#define DSI_HOST_DPI_VCID_ACT_REG (DR_REG_DSI_HOST_BASE + 0x10c) +/** DSI_HOST_DPI_VCID_ACT : RO; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_DPI_VCID_ACT 0x00000003U +#define DSI_HOST_DPI_VCID_ACT_M (DSI_HOST_DPI_VCID_ACT_V << DSI_HOST_DPI_VCID_ACT_S) +#define DSI_HOST_DPI_VCID_ACT_V 0x00000003U +#define DSI_HOST_DPI_VCID_ACT_S 0 + +/** DSI_HOST_DPI_COLOR_CODING_ACT_REG register + * NA + */ +#define DSI_HOST_DPI_COLOR_CODING_ACT_REG (DR_REG_DSI_HOST_BASE + 0x110) +/** DSI_HOST_DPI_COLOR_CODING_ACT : RO; bitpos: [3:0]; default: 0; + * NA + */ +#define DSI_HOST_DPI_COLOR_CODING_ACT 0x0000000FU +#define DSI_HOST_DPI_COLOR_CODING_ACT_M (DSI_HOST_DPI_COLOR_CODING_ACT_V << DSI_HOST_DPI_COLOR_CODING_ACT_S) +#define DSI_HOST_DPI_COLOR_CODING_ACT_V 0x0000000FU +#define DSI_HOST_DPI_COLOR_CODING_ACT_S 0 +/** DSI_HOST_LOOSELY18_EN_ACT : RO; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_LOOSELY18_EN_ACT (BIT(8)) +#define DSI_HOST_LOOSELY18_EN_ACT_M (DSI_HOST_LOOSELY18_EN_ACT_V << DSI_HOST_LOOSELY18_EN_ACT_S) +#define DSI_HOST_LOOSELY18_EN_ACT_V 0x00000001U +#define DSI_HOST_LOOSELY18_EN_ACT_S 8 + +/** DSI_HOST_DPI_LP_CMD_TIM_ACT_REG register + * NA + */ +#define DSI_HOST_DPI_LP_CMD_TIM_ACT_REG (DR_REG_DSI_HOST_BASE + 0x118) +/** DSI_HOST_INVACT_LPCMD_TIME_ACT : RO; bitpos: [7:0]; default: 0; + * NA + */ +#define DSI_HOST_INVACT_LPCMD_TIME_ACT 0x000000FFU +#define DSI_HOST_INVACT_LPCMD_TIME_ACT_M (DSI_HOST_INVACT_LPCMD_TIME_ACT_V << DSI_HOST_INVACT_LPCMD_TIME_ACT_S) +#define DSI_HOST_INVACT_LPCMD_TIME_ACT_V 0x000000FFU +#define DSI_HOST_INVACT_LPCMD_TIME_ACT_S 0 +/** DSI_HOST_OUTVACT_LPCMD_TIME_ACT : RO; bitpos: [23:16]; default: 0; + * NA + */ +#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT 0x000000FFU +#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_M (DSI_HOST_OUTVACT_LPCMD_TIME_ACT_V << DSI_HOST_OUTVACT_LPCMD_TIME_ACT_S) +#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_V 0x000000FFU +#define DSI_HOST_OUTVACT_LPCMD_TIME_ACT_S 16 + +/** DSI_HOST_EDPI_TE_HW_CFG_REG register + * NA + */ +#define DSI_HOST_EDPI_TE_HW_CFG_REG (DR_REG_DSI_HOST_BASE + 0x11c) +/** DSI_HOST_HW_TEAR_EFFECT_ON : R/W; bitpos: [0]; default: 0; + * NA + */ +#define DSI_HOST_HW_TEAR_EFFECT_ON (BIT(0)) +#define DSI_HOST_HW_TEAR_EFFECT_ON_M (DSI_HOST_HW_TEAR_EFFECT_ON_V << DSI_HOST_HW_TEAR_EFFECT_ON_S) +#define DSI_HOST_HW_TEAR_EFFECT_ON_V 0x00000001U +#define DSI_HOST_HW_TEAR_EFFECT_ON_S 0 +/** DSI_HOST_HW_TEAR_EFFECT_GEN : R/W; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_HW_TEAR_EFFECT_GEN (BIT(1)) +#define DSI_HOST_HW_TEAR_EFFECT_GEN_M (DSI_HOST_HW_TEAR_EFFECT_GEN_V << DSI_HOST_HW_TEAR_EFFECT_GEN_S) +#define DSI_HOST_HW_TEAR_EFFECT_GEN_V 0x00000001U +#define DSI_HOST_HW_TEAR_EFFECT_GEN_S 1 +/** DSI_HOST_HW_SET_SCAN_LINE : R/W; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_HW_SET_SCAN_LINE (BIT(4)) +#define DSI_HOST_HW_SET_SCAN_LINE_M (DSI_HOST_HW_SET_SCAN_LINE_V << DSI_HOST_HW_SET_SCAN_LINE_S) +#define DSI_HOST_HW_SET_SCAN_LINE_V 0x00000001U +#define DSI_HOST_HW_SET_SCAN_LINE_S 4 +/** DSI_HOST_SCAN_LINE_PARAMETER : R/W; bitpos: [31:16]; default: 0; + * NA + */ +#define DSI_HOST_SCAN_LINE_PARAMETER 0x0000FFFFU +#define DSI_HOST_SCAN_LINE_PARAMETER_M (DSI_HOST_SCAN_LINE_PARAMETER_V << DSI_HOST_SCAN_LINE_PARAMETER_S) +#define DSI_HOST_SCAN_LINE_PARAMETER_V 0x0000FFFFU +#define DSI_HOST_SCAN_LINE_PARAMETER_S 16 + +/** DSI_HOST_VID_MODE_CFG_ACT_REG register + * NA + */ +#define DSI_HOST_VID_MODE_CFG_ACT_REG (DR_REG_DSI_HOST_BASE + 0x138) +/** DSI_HOST_VID_MODE_TYPE_ACT : RO; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_MODE_TYPE_ACT 0x00000003U +#define DSI_HOST_VID_MODE_TYPE_ACT_M (DSI_HOST_VID_MODE_TYPE_ACT_V << DSI_HOST_VID_MODE_TYPE_ACT_S) +#define DSI_HOST_VID_MODE_TYPE_ACT_V 0x00000003U +#define DSI_HOST_VID_MODE_TYPE_ACT_S 0 +/** DSI_HOST_LP_VSA_EN_ACT : RO; bitpos: [2]; default: 0; + * NA + */ +#define DSI_HOST_LP_VSA_EN_ACT (BIT(2)) +#define DSI_HOST_LP_VSA_EN_ACT_M (DSI_HOST_LP_VSA_EN_ACT_V << DSI_HOST_LP_VSA_EN_ACT_S) +#define DSI_HOST_LP_VSA_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_VSA_EN_ACT_S 2 +/** DSI_HOST_LP_VBP_EN_ACT : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_LP_VBP_EN_ACT (BIT(3)) +#define DSI_HOST_LP_VBP_EN_ACT_M (DSI_HOST_LP_VBP_EN_ACT_V << DSI_HOST_LP_VBP_EN_ACT_S) +#define DSI_HOST_LP_VBP_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_VBP_EN_ACT_S 3 +/** DSI_HOST_LP_VFP_EN_ACT : RO; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_LP_VFP_EN_ACT (BIT(4)) +#define DSI_HOST_LP_VFP_EN_ACT_M (DSI_HOST_LP_VFP_EN_ACT_V << DSI_HOST_LP_VFP_EN_ACT_S) +#define DSI_HOST_LP_VFP_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_VFP_EN_ACT_S 4 +/** DSI_HOST_LP_VACT_EN_ACT : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_LP_VACT_EN_ACT (BIT(5)) +#define DSI_HOST_LP_VACT_EN_ACT_M (DSI_HOST_LP_VACT_EN_ACT_V << DSI_HOST_LP_VACT_EN_ACT_S) +#define DSI_HOST_LP_VACT_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_VACT_EN_ACT_S 5 +/** DSI_HOST_LP_HBP_EN_ACT : RO; bitpos: [6]; default: 0; + * NA + */ +#define DSI_HOST_LP_HBP_EN_ACT (BIT(6)) +#define DSI_HOST_LP_HBP_EN_ACT_M (DSI_HOST_LP_HBP_EN_ACT_V << DSI_HOST_LP_HBP_EN_ACT_S) +#define DSI_HOST_LP_HBP_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_HBP_EN_ACT_S 6 +/** DSI_HOST_LP_HFP_EN_ACT : RO; bitpos: [7]; default: 0; + * NA + */ +#define DSI_HOST_LP_HFP_EN_ACT (BIT(7)) +#define DSI_HOST_LP_HFP_EN_ACT_M (DSI_HOST_LP_HFP_EN_ACT_V << DSI_HOST_LP_HFP_EN_ACT_S) +#define DSI_HOST_LP_HFP_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_HFP_EN_ACT_S 7 +/** DSI_HOST_FRAME_BTA_ACK_EN_ACT : RO; bitpos: [8]; default: 0; + * NA + */ +#define DSI_HOST_FRAME_BTA_ACK_EN_ACT (BIT(8)) +#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_M (DSI_HOST_FRAME_BTA_ACK_EN_ACT_V << DSI_HOST_FRAME_BTA_ACK_EN_ACT_S) +#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_V 0x00000001U +#define DSI_HOST_FRAME_BTA_ACK_EN_ACT_S 8 +/** DSI_HOST_LP_CMD_EN_ACT : RO; bitpos: [9]; default: 0; + * NA + */ +#define DSI_HOST_LP_CMD_EN_ACT (BIT(9)) +#define DSI_HOST_LP_CMD_EN_ACT_M (DSI_HOST_LP_CMD_EN_ACT_V << DSI_HOST_LP_CMD_EN_ACT_S) +#define DSI_HOST_LP_CMD_EN_ACT_V 0x00000001U +#define DSI_HOST_LP_CMD_EN_ACT_S 9 + +/** DSI_HOST_VID_PKT_SIZE_ACT_REG register + * NA + */ +#define DSI_HOST_VID_PKT_SIZE_ACT_REG (DR_REG_DSI_HOST_BASE + 0x13c) +/** DSI_HOST_VID_PKT_SIZE_ACT : RO; bitpos: [13:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_PKT_SIZE_ACT 0x00003FFFU +#define DSI_HOST_VID_PKT_SIZE_ACT_M (DSI_HOST_VID_PKT_SIZE_ACT_V << DSI_HOST_VID_PKT_SIZE_ACT_S) +#define DSI_HOST_VID_PKT_SIZE_ACT_V 0x00003FFFU +#define DSI_HOST_VID_PKT_SIZE_ACT_S 0 + +/** DSI_HOST_VID_NUM_CHUNKS_ACT_REG register + * NA + */ +#define DSI_HOST_VID_NUM_CHUNKS_ACT_REG (DR_REG_DSI_HOST_BASE + 0x140) +/** DSI_HOST_VID_NUM_CHUNKS_ACT : RO; bitpos: [12:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_NUM_CHUNKS_ACT 0x00001FFFU +#define DSI_HOST_VID_NUM_CHUNKS_ACT_M (DSI_HOST_VID_NUM_CHUNKS_ACT_V << DSI_HOST_VID_NUM_CHUNKS_ACT_S) +#define DSI_HOST_VID_NUM_CHUNKS_ACT_V 0x00001FFFU +#define DSI_HOST_VID_NUM_CHUNKS_ACT_S 0 + +/** DSI_HOST_VID_NULL_SIZE_ACT_REG register + * NA + */ +#define DSI_HOST_VID_NULL_SIZE_ACT_REG (DR_REG_DSI_HOST_BASE + 0x144) +/** DSI_HOST_VID_NULL_SIZE_ACT : RO; bitpos: [12:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_NULL_SIZE_ACT 0x00001FFFU +#define DSI_HOST_VID_NULL_SIZE_ACT_M (DSI_HOST_VID_NULL_SIZE_ACT_V << DSI_HOST_VID_NULL_SIZE_ACT_S) +#define DSI_HOST_VID_NULL_SIZE_ACT_V 0x00001FFFU +#define DSI_HOST_VID_NULL_SIZE_ACT_S 0 + +/** DSI_HOST_VID_HSA_TIME_ACT_REG register + * NA + */ +#define DSI_HOST_VID_HSA_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x148) +/** DSI_HOST_VID_HSA_TIME_ACT : RO; bitpos: [11:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HSA_TIME_ACT 0x00000FFFU +#define DSI_HOST_VID_HSA_TIME_ACT_M (DSI_HOST_VID_HSA_TIME_ACT_V << DSI_HOST_VID_HSA_TIME_ACT_S) +#define DSI_HOST_VID_HSA_TIME_ACT_V 0x00000FFFU +#define DSI_HOST_VID_HSA_TIME_ACT_S 0 + +/** DSI_HOST_VID_HBP_TIME_ACT_REG register + * NA + */ +#define DSI_HOST_VID_HBP_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x14c) +/** DSI_HOST_VID_HBP_TIME_ACT : RO; bitpos: [11:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HBP_TIME_ACT 0x00000FFFU +#define DSI_HOST_VID_HBP_TIME_ACT_M (DSI_HOST_VID_HBP_TIME_ACT_V << DSI_HOST_VID_HBP_TIME_ACT_S) +#define DSI_HOST_VID_HBP_TIME_ACT_V 0x00000FFFU +#define DSI_HOST_VID_HBP_TIME_ACT_S 0 + +/** DSI_HOST_VID_HLINE_TIME_ACT_REG register + * NA + */ +#define DSI_HOST_VID_HLINE_TIME_ACT_REG (DR_REG_DSI_HOST_BASE + 0x150) +/** DSI_HOST_VID_HLINE_TIME_ACT : RO; bitpos: [14:0]; default: 0; + * NA + */ +#define DSI_HOST_VID_HLINE_TIME_ACT 0x00007FFFU +#define DSI_HOST_VID_HLINE_TIME_ACT_M (DSI_HOST_VID_HLINE_TIME_ACT_V << DSI_HOST_VID_HLINE_TIME_ACT_S) +#define DSI_HOST_VID_HLINE_TIME_ACT_V 0x00007FFFU +#define DSI_HOST_VID_HLINE_TIME_ACT_S 0 + +/** DSI_HOST_VID_VSA_LINES_ACT_REG register + * NA + */ +#define DSI_HOST_VID_VSA_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x154) +/** DSI_HOST_VSA_LINES_ACT : RO; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VSA_LINES_ACT 0x000003FFU +#define DSI_HOST_VSA_LINES_ACT_M (DSI_HOST_VSA_LINES_ACT_V << DSI_HOST_VSA_LINES_ACT_S) +#define DSI_HOST_VSA_LINES_ACT_V 0x000003FFU +#define DSI_HOST_VSA_LINES_ACT_S 0 + +/** DSI_HOST_VID_VBP_LINES_ACT_REG register + * NA + */ +#define DSI_HOST_VID_VBP_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x158) +/** DSI_HOST_VBP_LINES_ACT : RO; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VBP_LINES_ACT 0x000003FFU +#define DSI_HOST_VBP_LINES_ACT_M (DSI_HOST_VBP_LINES_ACT_V << DSI_HOST_VBP_LINES_ACT_S) +#define DSI_HOST_VBP_LINES_ACT_V 0x000003FFU +#define DSI_HOST_VBP_LINES_ACT_S 0 + +/** DSI_HOST_VID_VFP_LINES_ACT_REG register + * NA + */ +#define DSI_HOST_VID_VFP_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x15c) +/** DSI_HOST_VFP_LINES_ACT : RO; bitpos: [9:0]; default: 0; + * NA + */ +#define DSI_HOST_VFP_LINES_ACT 0x000003FFU +#define DSI_HOST_VFP_LINES_ACT_M (DSI_HOST_VFP_LINES_ACT_V << DSI_HOST_VFP_LINES_ACT_S) +#define DSI_HOST_VFP_LINES_ACT_V 0x000003FFU +#define DSI_HOST_VFP_LINES_ACT_S 0 + +/** DSI_HOST_VID_VACTIVE_LINES_ACT_REG register + * NA + */ +#define DSI_HOST_VID_VACTIVE_LINES_ACT_REG (DR_REG_DSI_HOST_BASE + 0x160) +/** DSI_HOST_V_ACTIVE_LINES_ACT : RO; bitpos: [13:0]; default: 0; + * NA + */ +#define DSI_HOST_V_ACTIVE_LINES_ACT 0x00003FFFU +#define DSI_HOST_V_ACTIVE_LINES_ACT_M (DSI_HOST_V_ACTIVE_LINES_ACT_V << DSI_HOST_V_ACTIVE_LINES_ACT_S) +#define DSI_HOST_V_ACTIVE_LINES_ACT_V 0x00003FFFU +#define DSI_HOST_V_ACTIVE_LINES_ACT_S 0 + +/** DSI_HOST_VID_PKT_STATUS_REG register + * NA + */ +#define DSI_HOST_VID_PKT_STATUS_REG (DR_REG_DSI_HOST_BASE + 0x168) +/** DSI_HOST_DPI_CMD_W_EMPTY : RO; bitpos: [0]; default: 1; + * NA + */ +#define DSI_HOST_DPI_CMD_W_EMPTY (BIT(0)) +#define DSI_HOST_DPI_CMD_W_EMPTY_M (DSI_HOST_DPI_CMD_W_EMPTY_V << DSI_HOST_DPI_CMD_W_EMPTY_S) +#define DSI_HOST_DPI_CMD_W_EMPTY_V 0x00000001U +#define DSI_HOST_DPI_CMD_W_EMPTY_S 0 +/** DSI_HOST_DPI_CMD_W_FULL : RO; bitpos: [1]; default: 0; + * NA + */ +#define DSI_HOST_DPI_CMD_W_FULL (BIT(1)) +#define DSI_HOST_DPI_CMD_W_FULL_M (DSI_HOST_DPI_CMD_W_FULL_V << DSI_HOST_DPI_CMD_W_FULL_S) +#define DSI_HOST_DPI_CMD_W_FULL_V 0x00000001U +#define DSI_HOST_DPI_CMD_W_FULL_S 1 +/** DSI_HOST_DPI_PLD_W_EMPTY : RO; bitpos: [2]; default: 1; + * NA + */ +#define DSI_HOST_DPI_PLD_W_EMPTY (BIT(2)) +#define DSI_HOST_DPI_PLD_W_EMPTY_M (DSI_HOST_DPI_PLD_W_EMPTY_V << DSI_HOST_DPI_PLD_W_EMPTY_S) +#define DSI_HOST_DPI_PLD_W_EMPTY_V 0x00000001U +#define DSI_HOST_DPI_PLD_W_EMPTY_S 2 +/** DSI_HOST_DPI_PLD_W_FULL : RO; bitpos: [3]; default: 0; + * NA + */ +#define DSI_HOST_DPI_PLD_W_FULL (BIT(3)) +#define DSI_HOST_DPI_PLD_W_FULL_M (DSI_HOST_DPI_PLD_W_FULL_V << DSI_HOST_DPI_PLD_W_FULL_S) +#define DSI_HOST_DPI_PLD_W_FULL_V 0x00000001U +#define DSI_HOST_DPI_PLD_W_FULL_S 3 +/** DSI_HOST_DPI_BUFF_PLD_EMPTY : RO; bitpos: [16]; default: 1; + * NA + */ +#define DSI_HOST_DPI_BUFF_PLD_EMPTY (BIT(16)) +#define DSI_HOST_DPI_BUFF_PLD_EMPTY_M (DSI_HOST_DPI_BUFF_PLD_EMPTY_V << DSI_HOST_DPI_BUFF_PLD_EMPTY_S) +#define DSI_HOST_DPI_BUFF_PLD_EMPTY_V 0x00000001U +#define DSI_HOST_DPI_BUFF_PLD_EMPTY_S 16 +/** DSI_HOST_DPI_BUFF_PLD_FULL : RO; bitpos: [17]; default: 0; + * NA + */ +#define DSI_HOST_DPI_BUFF_PLD_FULL (BIT(17)) +#define DSI_HOST_DPI_BUFF_PLD_FULL_M (DSI_HOST_DPI_BUFF_PLD_FULL_V << DSI_HOST_DPI_BUFF_PLD_FULL_S) +#define DSI_HOST_DPI_BUFF_PLD_FULL_V 0x00000001U +#define DSI_HOST_DPI_BUFF_PLD_FULL_S 17 + +/** DSI_HOST_SDF_3D_ACT_REG register + * NA + */ +#define DSI_HOST_SDF_3D_ACT_REG (DR_REG_DSI_HOST_BASE + 0x190) +/** DSI_HOST_MODE_3D_ACT : RO; bitpos: [1:0]; default: 0; + * NA + */ +#define DSI_HOST_MODE_3D_ACT 0x00000003U +#define DSI_HOST_MODE_3D_ACT_M (DSI_HOST_MODE_3D_ACT_V << DSI_HOST_MODE_3D_ACT_S) +#define DSI_HOST_MODE_3D_ACT_V 0x00000003U +#define DSI_HOST_MODE_3D_ACT_S 0 +/** DSI_HOST_FORMAT_3D_ACT : RO; bitpos: [3:2]; default: 0; + * NA + */ +#define DSI_HOST_FORMAT_3D_ACT 0x00000003U +#define DSI_HOST_FORMAT_3D_ACT_M (DSI_HOST_FORMAT_3D_ACT_V << DSI_HOST_FORMAT_3D_ACT_S) +#define DSI_HOST_FORMAT_3D_ACT_V 0x00000003U +#define DSI_HOST_FORMAT_3D_ACT_S 2 +/** DSI_HOST_SECOND_VSYNC_ACT : RO; bitpos: [4]; default: 0; + * NA + */ +#define DSI_HOST_SECOND_VSYNC_ACT (BIT(4)) +#define DSI_HOST_SECOND_VSYNC_ACT_M (DSI_HOST_SECOND_VSYNC_ACT_V << DSI_HOST_SECOND_VSYNC_ACT_S) +#define DSI_HOST_SECOND_VSYNC_ACT_V 0x00000001U +#define DSI_HOST_SECOND_VSYNC_ACT_S 4 +/** DSI_HOST_RIGHT_FIRST_ACT : RO; bitpos: [5]; default: 0; + * NA + */ +#define DSI_HOST_RIGHT_FIRST_ACT (BIT(5)) +#define DSI_HOST_RIGHT_FIRST_ACT_M (DSI_HOST_RIGHT_FIRST_ACT_V << DSI_HOST_RIGHT_FIRST_ACT_S) +#define DSI_HOST_RIGHT_FIRST_ACT_V 0x00000001U +#define DSI_HOST_RIGHT_FIRST_ACT_S 5 +/** DSI_HOST_SEND_3D_CFG_ACT : RO; bitpos: [16]; default: 0; + * NA + */ +#define DSI_HOST_SEND_3D_CFG_ACT (BIT(16)) +#define DSI_HOST_SEND_3D_CFG_ACT_M (DSI_HOST_SEND_3D_CFG_ACT_V << DSI_HOST_SEND_3D_CFG_ACT_S) +#define DSI_HOST_SEND_3D_CFG_ACT_V 0x00000001U +#define DSI_HOST_SEND_3D_CFG_ACT_S 16 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_struct.h new file mode 100644 index 0000000000..15e17eba71 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_struct.h @@ -0,0 +1,2008 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of version register + * NA + */ +typedef union { + struct { + /** version : RO; bitpos: [31:0]; default: 825504042; + * NA + */ + uint32_t version:32; + }; + uint32_t val; +} dsi_host_version_reg_t; + + +/** Group: Configuration Registers */ +/** Type of pwr_up register + * NA + */ +typedef union { + struct { + /** shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t shutdownz:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_pwr_up_reg_t; + +/** Type of clkmgr_cfg register + * NA + */ +typedef union { + struct { + /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t tx_esc_clk_division:8; + /** to_clk_division : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t to_clk_division:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_clkmgr_cfg_reg_t; + +/** Type of dpi_vcid register + * NA + */ +typedef union { + struct { + /** dpi_vcid : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dpi_vcid:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dpi_vcid_reg_t; + +/** Type of dpi_color_coding register + * NA + */ +typedef union { + struct { + /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t dpi_color_coding:4; + uint32_t reserved_4:4; + /** loosely18_en : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t loosely18_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_dpi_color_coding_reg_t; + +/** Type of dpi_cfg_pol register + * NA + */ +typedef union { + struct { + /** dataen_active_low : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t dataen_active_low:1; + /** vsync_active_low : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t vsync_active_low:1; + /** hsync_active_low : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t hsync_active_low:1; + /** shutd_active_low : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t shutd_active_low:1; + /** colorm_active_low : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t colorm_active_low:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} dsi_host_dpi_cfg_pol_reg_t; + +/** Type of dpi_lp_cmd_tim register + * NA + */ +typedef union { + struct { + /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t invact_lpcmd_time:8; + uint32_t reserved_8:8; + /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t outvact_lpcmd_time:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_dpi_lp_cmd_tim_reg_t; + +/** Type of dbi_vcid register + * NA + */ +typedef union { + struct { + /** dbi_vcid : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dbi_vcid:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dbi_vcid_reg_t; + +/** Type of dbi_cfg register + * NA + */ +typedef union { + struct { + /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t in_dbi_conf:4; + uint32_t reserved_4:4; + /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0; + * NA + */ + uint32_t out_dbi_conf:4; + uint32_t reserved_12:4; + /** lut_size_conf : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t lut_size_conf:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_dbi_cfg_reg_t; + +/** Type of dbi_partitioning_en register + * NA + */ +typedef union { + struct { + /** partitioning_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t partitioning_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_dbi_partitioning_en_reg_t; + +/** Type of dbi_cmdsize register + * NA + */ +typedef union { + struct { + /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t wr_cmd_size:16; + /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t allowed_cmd_size:16; + }; + uint32_t val; +} dsi_host_dbi_cmdsize_reg_t; + +/** Type of pckhdl_cfg register + * NA + */ +typedef union { + struct { + /** eotp_tx_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t eotp_tx_en:1; + /** eotp_rx_en : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t eotp_rx_en:1; + /** bta_en : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t bta_en:1; + /** ecc_rx_en : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t ecc_rx_en:1; + /** crc_rx_en : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t crc_rx_en:1; + /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t eotp_tx_lp_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} dsi_host_pckhdl_cfg_reg_t; + +/** Type of gen_vcid register + * NA + */ +typedef union { + struct { + /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t gen_vcid_rx:2; + uint32_t reserved_2:6; + /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0; + * NA + */ + uint32_t gen_vcid_tear_auto:2; + uint32_t reserved_10:6; + /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t gen_vcid_tx_auto:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_gen_vcid_reg_t; + +/** Type of mode_cfg register + * NA + */ +typedef union { + struct { + /** cmd_video_mode : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t cmd_video_mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_mode_cfg_reg_t; + +/** Type of vid_mode_cfg register + * NA + */ +typedef union { + struct { + /** vid_mode_type : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t vid_mode_type:2; + uint32_t reserved_2:6; + /** lp_vsa_en : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t lp_vsa_en:1; + /** lp_vbp_en : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t lp_vbp_en:1; + /** lp_vfp_en : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t lp_vfp_en:1; + /** lp_vact_en : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t lp_vact_en:1; + /** lp_hbp_en : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t lp_hbp_en:1; + /** lp_hfp_en : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t lp_hfp_en:1; + /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t frame_bta_ack_en:1; + /** lp_cmd_en : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t lp_cmd_en:1; + /** vpg_en : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t vpg_en:1; + uint32_t reserved_17:3; + /** vpg_mode : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t vpg_mode:1; + uint32_t reserved_21:3; + /** vpg_orientation : R/W; bitpos: [24]; default: 0; + * NA + */ + uint32_t vpg_orientation:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} dsi_host_vid_mode_cfg_reg_t; + +/** Type of vid_pkt_size register + * NA + */ +typedef union { + struct { + /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t vid_pkt_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_pkt_size_reg_t; + +/** Type of vid_num_chunks register + * NA + */ +typedef union { + struct { + /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_num_chunks:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_num_chunks_reg_t; + +/** Type of vid_null_size register + * NA + */ +typedef union { + struct { + /** vid_null_size : R/W; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_null_size:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_null_size_reg_t; + +/** Type of vid_hsa_time register + * NA + */ +typedef union { + struct { + /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hsa_time:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hsa_time_reg_t; + +/** Type of vid_hbp_time register + * NA + */ +typedef union { + struct { + /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hbp_time:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hbp_time_reg_t; + +/** Type of vid_hline_time register + * NA + */ +typedef union { + struct { + /** vid_hline_time : R/W; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t vid_hline_time:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_vid_hline_time_reg_t; + +/** Type of vid_vsa_lines register + * NA + */ +typedef union { + struct { + /** vsa_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vsa_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vsa_lines_reg_t; + +/** Type of vid_vbp_lines register + * NA + */ +typedef union { + struct { + /** vbp_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vbp_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vbp_lines_reg_t; + +/** Type of vid_vfp_lines register + * NA + */ +typedef union { + struct { + /** vfp_lines : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vfp_lines:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vfp_lines_reg_t; + +/** Type of vid_vactive_lines register + * NA + */ +typedef union { + struct { + /** v_active_lines : R/W; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t v_active_lines:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_vactive_lines_reg_t; + +/** Type of edpi_cmd_size register + * NA + */ +typedef union { + struct { + /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t edpi_allowed_cmd_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_edpi_cmd_size_reg_t; + +/** Type of cmd_mode_cfg register + * NA + */ +typedef union { + struct { + /** tear_fx_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t tear_fx_en:1; + /** ack_rqst_en : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t ack_rqst_en:1; + uint32_t reserved_2:6; + /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t gen_sw_0p_tx:1; + /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t gen_sw_1p_tx:1; + /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t gen_sw_2p_tx:1; + /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t gen_sr_0p_tx:1; + /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t gen_sr_1p_tx:1; + /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t gen_sr_2p_tx:1; + /** gen_lw_tx : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t gen_lw_tx:1; + uint32_t reserved_15:1; + /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t dcs_sw_0p_tx:1; + /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t dcs_sw_1p_tx:1; + /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t dcs_sr_0p_tx:1; + /** dcs_lw_tx : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t dcs_lw_tx:1; + uint32_t reserved_20:4; + /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0; + * NA + */ + uint32_t max_rd_pkt_size:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} dsi_host_cmd_mode_cfg_reg_t; + +/** Type of gen_hdr register + * NA + */ +typedef union { + struct { + /** gen_dt : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t gen_dt:6; + /** gen_vc : R/W; bitpos: [7:6]; default: 0; + * NA + */ + uint32_t gen_vc:2; + /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t gen_wc_lsbyte:8; + /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t gen_wc_msbyte:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_gen_hdr_reg_t; + +/** Type of gen_pld_data register + * NA + */ +typedef union { + struct { + /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t gen_pld_b1:8; + /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t gen_pld_b2:8; + /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t gen_pld_b3:8; + /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0; + * NA + */ + uint32_t gen_pld_b4:8; + }; + uint32_t val; +} dsi_host_gen_pld_data_reg_t; + +/** Type of to_cnt_cfg register + * NA + */ +typedef union { + struct { + /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lprx_to_cnt:16; + /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t hstx_to_cnt:16; + }; + uint32_t val; +} dsi_host_to_cnt_cfg_reg_t; + +/** Type of hs_rd_to_cnt register + * NA + */ +typedef union { + struct { + /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t hs_rd_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_hs_rd_to_cnt_reg_t; + +/** Type of lp_rd_to_cnt register + * NA + */ +typedef union { + struct { + /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lp_rd_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_lp_rd_to_cnt_reg_t; + +/** Type of hs_wr_to_cnt register + * NA + */ +typedef union { + struct { + /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t hs_wr_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_hs_wr_to_cnt_reg_t; + +/** Type of lp_wr_to_cnt register + * NA + */ +typedef union { + struct { + /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t lp_wr_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_lp_wr_to_cnt_reg_t; + +/** Type of bta_to_cnt register + * NA + */ +typedef union { + struct { + /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0; + * NA + */ + uint32_t bta_to_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_bta_to_cnt_reg_t; + +/** Type of sdf_3d register + * NA + */ +typedef union { + struct { + /** mode_3d : R/W; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t mode_3d:2; + /** format_3d : R/W; bitpos: [3:2]; default: 0; + * NA + */ + uint32_t format_3d:2; + /** second_vsync : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t second_vsync:1; + /** right_first : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t right_first:1; + uint32_t reserved_6:10; + /** send_3d_cfg : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t send_3d_cfg:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_sdf_3d_reg_t; + +/** Type of lpclk_ctrl register + * NA + */ +typedef union { + struct { + /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_txrequestclkhs:1; + /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t auto_clklane_ctrl:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_lpclk_ctrl_reg_t; + +/** Type of phy_tmr_lpclk_cfg register + * NA + */ +typedef union { + struct { + /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t phy_clklp2hs_time:10; + uint32_t reserved_10:6; + /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0; + * NA + */ + uint32_t phy_clkhs2lp_time:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} dsi_host_phy_tmr_lpclk_cfg_reg_t; + +/** Type of phy_tmr_cfg register + * NA + */ +typedef union { + struct { + /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t phy_lp2hs_time:10; + uint32_t reserved_10:6; + /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0; + * NA + */ + uint32_t phy_hs2lp_time:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} dsi_host_phy_tmr_cfg_reg_t; + +/** Type of phy_rstz register + * NA + */ +typedef union { + struct { + /** phy_shutdownz : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_shutdownz:1; + /** phy_rstz : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_rstz:1; + /** phy_enableclk : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_enableclk:1; + /** phy_forcepll : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_forcepll:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_rstz_reg_t; + +/** Type of phy_if_cfg register + * NA + */ +typedef union { + struct { + /** n_lanes : R/W; bitpos: [1:0]; default: 1; + * NA + */ + uint32_t n_lanes:2; + uint32_t reserved_2:6; + /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t phy_stop_wait_time:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} dsi_host_phy_if_cfg_reg_t; + +/** Type of phy_ulps_ctrl register + * NA + */ +typedef union { + struct { + /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_txrequlpsclk:1; + /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_txexitulpsclk:1; + /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_txrequlpslan:1; + /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_txexitulpslan:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_ulps_ctrl_reg_t; + +/** Type of phy_tx_triggers register + * NA + */ +typedef union { + struct { + /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t phy_tx_triggers:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} dsi_host_phy_tx_triggers_reg_t; + +/** Type of phy_tst_ctrl0 register + * NA + */ +typedef union { + struct { + /** phy_testclr : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t phy_testclr:1; + /** phy_testclk : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_testclk:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_phy_tst_ctrl0_reg_t; + +/** Type of phy_tst_ctrl1 register + * NA + */ +typedef union { + struct { + /** phy_testdin : R/W; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t phy_testdin:8; + /** pht_testdout : RO; bitpos: [15:8]; default: 0; + * NA + */ + uint32_t pht_testdout:8; + /** phy_testen : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t phy_testen:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_phy_tst_ctrl1_reg_t; + +/** Type of phy_cal register + * NA + */ +typedef union { + struct { + /** txskewcalhs : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t txskewcalhs:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} dsi_host_phy_cal_reg_t; + +/** Type of dsc_parameter register + * NA + */ +typedef union { + struct { + /** compression_mode : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t compression_mode:1; + uint32_t reserved_1:7; + /** compress_algo : R/W; bitpos: [9:8]; default: 0; + * NA + */ + uint32_t compress_algo:2; + uint32_t reserved_10:6; + /** pps_sel : R/W; bitpos: [17:16]; default: 0; + * NA + */ + uint32_t pps_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_dsc_parameter_reg_t; + +/** Type of phy_tmr_rd_cfg register + * NA + */ +typedef union { + struct { + /** max_rd_time : R/W; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t max_rd_time:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_phy_tmr_rd_cfg_reg_t; + +/** Type of vid_shadow_ctrl register + * NA + */ +typedef union { + struct { + /** vid_shadow_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t vid_shadow_en:1; + uint32_t reserved_1:7; + /** vid_shadow_req : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t vid_shadow_req:1; + uint32_t reserved_9:7; + /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t vid_shadow_pin_req:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_vid_shadow_ctrl_reg_t; + +/** Type of edpi_te_hw_cfg register + * NA + */ +typedef union { + struct { + /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t hw_tear_effect_on:1; + /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t hw_tear_effect_gen:1; + uint32_t reserved_2:2; + /** hw_set_scan_line : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t hw_set_scan_line:1; + uint32_t reserved_5:11; + /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0; + * NA + */ + uint32_t scan_line_parameter:16; + }; + uint32_t val; +} dsi_host_edpi_te_hw_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of cmd_pkt_status register + * NA + */ +typedef union { + struct { + /** gen_cmd_empty : RO; bitpos: [0]; default: 1; + * NA + */ + uint32_t gen_cmd_empty:1; + /** gen_cmd_full : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t gen_cmd_full:1; + /** gen_pld_w_empty : RO; bitpos: [2]; default: 1; + * NA + */ + uint32_t gen_pld_w_empty:1; + /** gen_pld_w_full : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t gen_pld_w_full:1; + /** gen_pld_r_empty : RO; bitpos: [4]; default: 1; + * NA + */ + uint32_t gen_pld_r_empty:1; + /** gen_pld_r_full : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t gen_pld_r_full:1; + /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t gen_rd_cmd_busy:1; + uint32_t reserved_7:9; + /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t gen_buff_cmd_empty:1; + /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t gen_buff_cmd_full:1; + /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1; + * NA + */ + uint32_t gen_buff_pld_empty:1; + /** gen_buff_pld_full : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t gen_buff_pld_full:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_cmd_pkt_status_reg_t; + +/** Type of phy_status register + * NA + */ +typedef union { + struct { + /** phy_lock : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t phy_lock:1; + /** phy_direction : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t phy_direction:1; + /** phy_stopstateclklane : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t phy_stopstateclklane:1; + /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t phy_ulpsactivenotclk:1; + /** phy_stopstate0lane : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t phy_stopstate0lane:1; + /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t phy_ulpsactivenot0lane:1; + /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1; + * NA + */ + uint32_t phy_rxulpsesc0lane:1; + /** phy_stopstate1lane : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t phy_stopstate1lane:1; + /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1; + * NA + */ + uint32_t phy_ulpsactivenot1lane:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_phy_status_reg_t; + +/** Type of dpi_vcid_act register + * NA + */ +typedef union { + struct { + /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t dpi_vcid_act:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} dsi_host_dpi_vcid_act_reg_t; + +/** Type of dpi_color_coding_act register + * NA + */ +typedef union { + struct { + /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0; + * NA + */ + uint32_t dpi_color_coding_act:4; + uint32_t reserved_4:4; + /** loosely18_en_act : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t loosely18_en_act:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} dsi_host_dpi_color_coding_act_reg_t; + +/** Type of dpi_lp_cmd_tim_act register + * NA + */ +typedef union { + struct { + /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0; + * NA + */ + uint32_t invact_lpcmd_time_act:8; + uint32_t reserved_8:8; + /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0; + * NA + */ + uint32_t outvact_lpcmd_time_act:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} dsi_host_dpi_lp_cmd_tim_act_reg_t; + +/** Type of vid_mode_cfg_act register + * NA + */ +typedef union { + struct { + /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t vid_mode_type_act:2; + /** lp_vsa_en_act : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t lp_vsa_en_act:1; + /** lp_vbp_en_act : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t lp_vbp_en_act:1; + /** lp_vfp_en_act : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t lp_vfp_en_act:1; + /** lp_vact_en_act : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t lp_vact_en_act:1; + /** lp_hbp_en_act : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t lp_hbp_en_act:1; + /** lp_hfp_en_act : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t lp_hfp_en_act:1; + /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t frame_bta_ack_en_act:1; + /** lp_cmd_en_act : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t lp_cmd_en_act:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_mode_cfg_act_reg_t; + +/** Type of vid_pkt_size_act register + * NA + */ +typedef union { + struct { + /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t vid_pkt_size_act:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_pkt_size_act_reg_t; + +/** Type of vid_num_chunks_act register + * NA + */ +typedef union { + struct { + /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_num_chunks_act:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_num_chunks_act_reg_t; + +/** Type of vid_null_size_act register + * NA + */ +typedef union { + struct { + /** vid_null_size_act : RO; bitpos: [12:0]; default: 0; + * NA + */ + uint32_t vid_null_size_act:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} dsi_host_vid_null_size_act_reg_t; + +/** Type of vid_hsa_time_act register + * NA + */ +typedef union { + struct { + /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hsa_time_act:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hsa_time_act_reg_t; + +/** Type of vid_hbp_time_act register + * NA + */ +typedef union { + struct { + /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0; + * NA + */ + uint32_t vid_hbp_time_act:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} dsi_host_vid_hbp_time_act_reg_t; + +/** Type of vid_hline_time_act register + * NA + */ +typedef union { + struct { + /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0; + * NA + */ + uint32_t vid_hline_time_act:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} dsi_host_vid_hline_time_act_reg_t; + +/** Type of vid_vsa_lines_act register + * NA + */ +typedef union { + struct { + /** vsa_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vsa_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vsa_lines_act_reg_t; + +/** Type of vid_vbp_lines_act register + * NA + */ +typedef union { + struct { + /** vbp_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vbp_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vbp_lines_act_reg_t; + +/** Type of vid_vfp_lines_act register + * NA + */ +typedef union { + struct { + /** vfp_lines_act : RO; bitpos: [9:0]; default: 0; + * NA + */ + uint32_t vfp_lines_act:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} dsi_host_vid_vfp_lines_act_reg_t; + +/** Type of vid_vactive_lines_act register + * NA + */ +typedef union { + struct { + /** v_active_lines_act : RO; bitpos: [13:0]; default: 0; + * NA + */ + uint32_t v_active_lines_act:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} dsi_host_vid_vactive_lines_act_reg_t; + +/** Type of vid_pkt_status register + * NA + */ +typedef union { + struct { + /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1; + * NA + */ + uint32_t dpi_cmd_w_empty:1; + /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t dpi_cmd_w_full:1; + /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1; + * NA + */ + uint32_t dpi_pld_w_empty:1; + /** dpi_pld_w_full : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t dpi_pld_w_full:1; + uint32_t reserved_4:12; + /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1; + * NA + */ + uint32_t dpi_buff_pld_empty:1; + /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t dpi_buff_pld_full:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} dsi_host_vid_pkt_status_reg_t; + +/** Type of sdf_3d_act register + * NA + */ +typedef union { + struct { + /** mode_3d_act : RO; bitpos: [1:0]; default: 0; + * NA + */ + uint32_t mode_3d_act:2; + /** format_3d_act : RO; bitpos: [3:2]; default: 0; + * NA + */ + uint32_t format_3d_act:2; + /** second_vsync_act : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t second_vsync_act:1; + /** right_first_act : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t right_first_act:1; + uint32_t reserved_6:10; + /** send_3d_cfg_act : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t send_3d_cfg_act:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} dsi_host_sdf_3d_act_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_st0 register + * NA + */ +typedef union { + struct { + /** ack_with_err_0 : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t ack_with_err_0:1; + /** ack_with_err_1 : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t ack_with_err_1:1; + /** ack_with_err_2 : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t ack_with_err_2:1; + /** ack_with_err_3 : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t ack_with_err_3:1; + /** ack_with_err_4 : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t ack_with_err_4:1; + /** ack_with_err_5 : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t ack_with_err_5:1; + /** ack_with_err_6 : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t ack_with_err_6:1; + /** ack_with_err_7 : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t ack_with_err_7:1; + /** ack_with_err_8 : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t ack_with_err_8:1; + /** ack_with_err_9 : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t ack_with_err_9:1; + /** ack_with_err_10 : RO; bitpos: [10]; default: 0; + * NA + */ + uint32_t ack_with_err_10:1; + /** ack_with_err_11 : RO; bitpos: [11]; default: 0; + * NA + */ + uint32_t ack_with_err_11:1; + /** ack_with_err_12 : RO; bitpos: [12]; default: 0; + * NA + */ + uint32_t ack_with_err_12:1; + /** ack_with_err_13 : RO; bitpos: [13]; default: 0; + * NA + */ + uint32_t ack_with_err_13:1; + /** ack_with_err_14 : RO; bitpos: [14]; default: 0; + * NA + */ + uint32_t ack_with_err_14:1; + /** ack_with_err_15 : RO; bitpos: [15]; default: 0; + * NA + */ + uint32_t ack_with_err_15:1; + /** dphy_errors_0 : RO; bitpos: [16]; default: 0; + * NA + */ + uint32_t dphy_errors_0:1; + /** dphy_errors_1 : RO; bitpos: [17]; default: 0; + * NA + */ + uint32_t dphy_errors_1:1; + /** dphy_errors_2 : RO; bitpos: [18]; default: 0; + * NA + */ + uint32_t dphy_errors_2:1; + /** dphy_errors_3 : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t dphy_errors_3:1; + /** dphy_errors_4 : RO; bitpos: [20]; default: 0; + * NA + */ + uint32_t dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_st0_reg_t; + +/** Type of int_st1 register + * NA + */ +typedef union { + struct { + /** to_hs_tx : RO; bitpos: [0]; default: 0; + * NA + */ + uint32_t to_hs_tx:1; + /** to_lp_rx : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t to_lp_rx:1; + /** ecc_single_err : RO; bitpos: [2]; default: 0; + * NA + */ + uint32_t ecc_single_err:1; + /** ecc_milti_err : RO; bitpos: [3]; default: 0; + * NA + */ + uint32_t ecc_milti_err:1; + /** crc_err : RO; bitpos: [4]; default: 0; + * NA + */ + uint32_t crc_err:1; + /** pkt_size_err : RO; bitpos: [5]; default: 0; + * NA + */ + uint32_t pkt_size_err:1; + /** eopt_err : RO; bitpos: [6]; default: 0; + * NA + */ + uint32_t eopt_err:1; + /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0; + * NA + */ + uint32_t dpi_pld_wr_err:1; + /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0; + * NA + */ + uint32_t gen_cmd_wr_err:1; + /** gen_pld_wr_err : RO; bitpos: [9]; default: 0; + * NA + */ + uint32_t gen_pld_wr_err:1; + /** gen_pld_send_err : RO; bitpos: [10]; default: 0; + * NA + */ + uint32_t gen_pld_send_err:1; + /** gen_pld_rd_err : RO; bitpos: [11]; default: 0; + * NA + */ + uint32_t gen_pld_rd_err:1; + /** gen_pld_recev_err : RO; bitpos: [12]; default: 0; + * NA + */ + uint32_t gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0; + * NA + */ + uint32_t dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_st1_reg_t; + +/** Type of int_msk0 register + * NA + */ +typedef union { + struct { + /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_0:1; + /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_1:1; + /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_2:1; + /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_3:1; + /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_4:1; + /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_5:1; + /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_6:1; + /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_7:1; + /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_8:1; + /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_9:1; + /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_10:1; + /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_11:1; + /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_12:1; + /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_13:1; + /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_14:1; + /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t mask_ack_with_err_15:1; + /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_0:1; + /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_1:1; + /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_2:1; + /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_3:1; + /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t mask_dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_msk0_reg_t; + +/** Type of int_msk1 register + * NA + */ +typedef union { + struct { + /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t mask_to_hs_tx:1; + /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t mask_to_lp_rx:1; + /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t mask_ecc_single_err:1; + /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t mask_ecc_milti_err:1; + /** mask_crc_err : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t mask_crc_err:1; + /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t mask_pkt_size_err:1; + /** mask_eopt_err : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t mask_eopt_err:1; + /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t mask_dpi_pld_wr_err:1; + /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t mask_gen_cmd_wr_err:1; + /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t mask_gen_pld_wr_err:1; + /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t mask_gen_pld_send_err:1; + /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t mask_gen_pld_rd_err:1; + /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t mask_gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t mask_dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_msk1_reg_t; + +/** Type of int_force0 register + * NA + */ +typedef union { + struct { + /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_ack_with_err_0:1; + /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_ack_with_err_1:1; + /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_ack_with_err_2:1; + /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_ack_with_err_3:1; + /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_ack_with_err_4:1; + /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_ack_with_err_5:1; + /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_ack_with_err_6:1; + /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_ack_with_err_7:1; + /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_ack_with_err_8:1; + /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_ack_with_err_9:1; + /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_ack_with_err_10:1; + /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_ack_with_err_11:1; + /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_ack_with_err_12:1; + /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0; + * NA + */ + uint32_t force_ack_with_err_13:1; + /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0; + * NA + */ + uint32_t force_ack_with_err_14:1; + /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0; + * NA + */ + uint32_t force_ack_with_err_15:1; + /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t force_dphy_errors_0:1; + /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t force_dphy_errors_1:1; + /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t force_dphy_errors_2:1; + /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t force_dphy_errors_3:1; + /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0; + * NA + */ + uint32_t force_dphy_errors_4:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} dsi_host_int_force0_reg_t; + +/** Type of int_force1 register + * NA + */ +typedef union { + struct { + /** force_to_hs_tx : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t force_to_hs_tx:1; + /** force_to_lp_rx : R/W; bitpos: [1]; default: 0; + * NA + */ + uint32_t force_to_lp_rx:1; + /** force_ecc_single_err : R/W; bitpos: [2]; default: 0; + * NA + */ + uint32_t force_ecc_single_err:1; + /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0; + * NA + */ + uint32_t force_ecc_milti_err:1; + /** force_crc_err : R/W; bitpos: [4]; default: 0; + * NA + */ + uint32_t force_crc_err:1; + /** force_pkt_size_err : R/W; bitpos: [5]; default: 0; + * NA + */ + uint32_t force_pkt_size_err:1; + /** force_eopt_err : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t force_eopt_err:1; + /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t force_dpi_pld_wr_err:1; + /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; + * NA + */ + uint32_t force_gen_cmd_wr_err:1; + /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; + * NA + */ + uint32_t force_gen_pld_wr_err:1; + /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0; + * NA + */ + uint32_t force_gen_pld_send_err:1; + /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; + * NA + */ + uint32_t force_gen_pld_rd_err:1; + /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; + * NA + */ + uint32_t force_gen_pld_recev_err:1; + uint32_t reserved_13:6; + /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t force_dpi_buff_pld_under:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} dsi_host_int_force1_reg_t; + + +typedef struct dsi_host_dev_t { + volatile dsi_host_version_reg_t version; + volatile dsi_host_pwr_up_reg_t pwr_up; + volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg; + volatile dsi_host_dpi_vcid_reg_t dpi_vcid; + volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding; + volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol; + volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim; + volatile dsi_host_dbi_vcid_reg_t dbi_vcid; + volatile dsi_host_dbi_cfg_reg_t dbi_cfg; + volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en; + volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize; + volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg; + volatile dsi_host_gen_vcid_reg_t gen_vcid; + volatile dsi_host_mode_cfg_reg_t mode_cfg; + volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg; + volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size; + volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks; + volatile dsi_host_vid_null_size_reg_t vid_null_size; + volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time; + volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time; + volatile dsi_host_vid_hline_time_reg_t vid_hline_time; + volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines; + volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines; + volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines; + volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines; + volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size; + volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg; + volatile dsi_host_gen_hdr_reg_t gen_hdr; + volatile dsi_host_gen_pld_data_reg_t gen_pld_data; + volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status; + volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg; + volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_timeout_cnt; + volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_timeout_cnt; + volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_timeout_cnt; + volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_timeout_cnt; + volatile dsi_host_bta_to_cnt_reg_t bta_timeout_cnt; + volatile dsi_host_sdf_3d_reg_t sdf_3d; + volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl; + volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg; + volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg; + volatile dsi_host_phy_rstz_reg_t phy_rstz; + volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg; + volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl; + volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers; + volatile dsi_host_phy_status_reg_t phy_status; + volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0; + volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1; + volatile dsi_host_int_st0_reg_t int_st0; + volatile dsi_host_int_st1_reg_t int_st1; + volatile dsi_host_int_msk0_reg_t int_msk0; + volatile dsi_host_int_msk1_reg_t int_msk1; + volatile dsi_host_phy_cal_reg_t phy_cal; + uint32_t reserved_0d0[2]; + volatile dsi_host_int_force0_reg_t int_force0; + volatile dsi_host_int_force1_reg_t int_force1; + uint32_t reserved_0e0[4]; + volatile dsi_host_dsc_parameter_reg_t dsc_parameter; + volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg; + uint32_t reserved_0f8[2]; + volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl; + uint32_t reserved_104[2]; + volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act; + volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act; + uint32_t reserved_114; + volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act; + volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg; + uint32_t reserved_120[6]; + volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act; + volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act; + volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act; + volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act; + volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act; + volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act; + volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act; + volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act; + volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act; + volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act; + volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act; + uint32_t reserved_164; + volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status; + uint32_t reserved_16c[9]; + volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act; +} dsi_host_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure"); +#endif + +extern dsi_host_dev_t MIPI_DSI_HOST; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/parl_io_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/parl_io_reg.h new file mode 100644 index 0000000000..eafecf99ee --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/parl_io_reg.h @@ -0,0 +1,495 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PARL_IO_RX_MODE_CFG_REG register + * Parallel RX Sampling mode configuration register. + */ +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) +/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ +#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S) +#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_S 21 +/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0; + * Write 1 to enable data sampling by software. + */ +#define PARL_IO_RX_SW_EN (BIT(25)) +#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S) +#define PARL_IO_RX_SW_EN_V 0x00000001U +#define PARL_IO_RX_SW_EN_S 25 +/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0; + * Write 1 to invert the external enable signal. + */ +#define PARL_IO_RX_EXT_EN_INV (BIT(26)) +#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S) +#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U +#define PARL_IO_RX_EXT_EN_INV_S 26 +/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 0: positive pulse start(data bit included) && positive pulse end(data bit included) + * 1: positive pulse start(data bit included) && positive pulse end (data bit excluded) + * 2: positive pulse start(data bit excluded) && positive pulse end (data bit included) + * 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) + * 4: positive pulse start(data bit included) && length end + * 5: positive pulse start(data bit excluded) && length end + */ +#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S) +#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27 +/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 0: external level enable mode + * 1: external pulse enable mode + * 2: internal software enable mode + */ +#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S) +#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_S 30 + +/** PARL_IO_RX_DATA_CFG_REG register + * Parallel RX data configuration register. + */ +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) +/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ +#define PARL_IO_RX_BITLEN 0x0007FFFFU +#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S) +#define PARL_IO_RX_BITLEN_V 0x0007FFFFU +#define PARL_IO_RX_BITLEN_S 9 +/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Write 1 to invert bit order of one byte sent from RX_FIFO to DMA. + */ +#define PARL_IO_RX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S) +#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_RX_DATA_ORDER_INV_S 28 +/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 0: bus width is 1. + * 1: bus width is 2. + * 2: bus width is 4. + * 3: bus width is 8. + */ +#define PARL_IO_RX_BUS_WID_SEL 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S) +#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_S 29 + +/** PARL_IO_RX_GENRL_CFG_REG register + * Parallel RX general configuration register. + */ +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) +/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; + * Write 1 to enable the clock gating of output rx clock. + */ +#define PARL_IO_RX_GATING_EN (BIT(12)) +#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S) +#define PARL_IO_RX_GATING_EN_V 0x00000001U +#define PARL_IO_RX_GATING_EN_S 12 +/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ +#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S) +#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_S 13 +/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1; + * Write 1 to enable timeout function to generate error eof. + */ +#define PARL_IO_RX_TIMEOUT_EN (BIT(29)) +#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S) +#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U +#define PARL_IO_RX_TIMEOUT_EN_S 29 +/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ +#define PARL_IO_RX_EOF_GEN_SEL (BIT(30)) +#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S) +#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_RX_EOF_GEN_SEL_S 30 + +/** PARL_IO_RX_START_CFG_REG register + * Parallel RX Start configuration register. + */ +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) +/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; + * Write 1 to start rx data sampling. + */ +#define PARL_IO_RX_START (BIT(31)) +#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S) +#define PARL_IO_RX_START_V 0x00000001U +#define PARL_IO_RX_START_S 31 + +/** PARL_IO_TX_DATA_CFG_REG register + * Parallel TX data configuration register. + */ +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) +/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ +#define PARL_IO_TX_BITLEN 0x0007FFFFU +#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S) +#define PARL_IO_TX_BITLEN_V 0x0007FFFFU +#define PARL_IO_TX_BITLEN_S 9 +/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Write 1 to invert bit order of one byte sent from TX_FIFO to IO data. + */ +#define PARL_IO_TX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S) +#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_TX_DATA_ORDER_INV_S 28 +/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 0: bus width is 1. + * 1: bus width is 2. + * 2: bus width is 4. + * 3: bus width is 8. + */ +#define PARL_IO_TX_BUS_WID_SEL 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S) +#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_S 29 + +/** PARL_IO_TX_START_CFG_REG register + * Parallel TX Start configuration register. + */ +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) +/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; + * Write 1 to start tx data transmit. + */ +#define PARL_IO_TX_START (BIT(31)) +#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S) +#define PARL_IO_TX_START_V 0x00000001U +#define PARL_IO_TX_START_S 31 + +/** PARL_IO_TX_GENRL_CFG_REG register + * Parallel TX general configuration register. + */ +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) +/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ +#define PARL_IO_TX_EOF_GEN_SEL (BIT(13)) +#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S) +#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_TX_EOF_GEN_SEL_S 13 +/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ +#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S) +#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_S 14 +/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0; + * Write 1 to enable the clock gating of output tx clock. + */ +#define PARL_IO_TX_GATING_EN (BIT(30)) +#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S) +#define PARL_IO_TX_GATING_EN_V 0x00000001U +#define PARL_IO_TX_GATING_EN_S 30 +/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0; + * Write 1 to enable the output of tx data valid signal. + */ +#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31)) +#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S) +#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U +#define PARL_IO_TX_VALID_OUTPUT_EN_S 31 + +/** PARL_IO_FIFO_CFG_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) +/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; + * Write 1 to reset async fifo in tx module. + */ +#define PARL_IO_TX_FIFO_SRST (BIT(30)) +#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S) +#define PARL_IO_TX_FIFO_SRST_V 0x00000001U +#define PARL_IO_TX_FIFO_SRST_S 30 +/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0; + * Write 1 to reset async fifo in rx module. + */ +#define PARL_IO_RX_FIFO_SRST (BIT(31)) +#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S) +#define PARL_IO_RX_FIFO_SRST_V 0x00000001U +#define PARL_IO_RX_FIFO_SRST_S 31 + +/** PARL_IO_REG_UPDATE_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) +/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; + * Write 1 to update rx register configuration. + */ +#define PARL_IO_RX_REG_UPDATE (BIT(31)) +#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S) +#define PARL_IO_RX_REG_UPDATE_V 0x00000001U +#define PARL_IO_RX_REG_UPDATE_S 31 + +/** PARL_IO_ST_REG register + * Parallel IO module status register0. + */ +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) +/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ +#define PARL_IO_TX_READY (BIT(31)) +#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S) +#define PARL_IO_TX_READY_V 0x00000001U +#define PARL_IO_TX_READY_S 31 + +/** PARL_IO_INT_ENA_REG register + * Parallel IO interrupt enable signal configuration register. + */ +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) +/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1 +/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ENA (BIT(2)) +#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S) +#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ENA_S 2 + +/** PARL_IO_INT_RAW_REG register + * Parallel IO interrupt raw signal status register. + */ +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) +/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1 +/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_RAW (BIT(2)) +#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S) +#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U +#define PARL_IO_TX_EOF_INT_RAW_S 2 + +/** PARL_IO_INT_ST_REG register + * Parallel IO interrupt signal status register. + */ +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) +/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1 +/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ST (BIT(2)) +#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S) +#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ST_S 2 + +/** PARL_IO_INT_CLR_REG register + * Parallel IO interrupt clear signal configuration register. + */ +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) +/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1 +/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_CLR (BIT(2)) +#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S) +#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U +#define PARL_IO_TX_EOF_INT_CLR_S 2 + +/** PARL_IO_RX_ST0_REG register + * Parallel IO RX status register0 + */ +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) +/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ +#define PARL_IO_RX_CNT 0x0000001FU +#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S) +#define PARL_IO_RX_CNT_V 0x0000001FU +#define PARL_IO_RX_CNT_S 8 +/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ +#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S) +#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13 + +/** PARL_IO_RX_ST1_REG register + * Parallel IO RX status register1 + */ +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) +/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ +#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_TX_ST0_REG register + * Parallel IO TX status register0 + */ +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) +/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ +#define PARL_IO_TX_CNT 0x0000007FU +#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S) +#define PARL_IO_TX_CNT_V 0x0000007FU +#define PARL_IO_TX_CNT_S 6 +/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ +#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_RX_CLK_CFG_REG register + * Parallel IO RX clk configuration register + */ +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) +/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Write 1 to invert the input Rx core clock. + */ +#define PARL_IO_RX_CLK_I_INV (BIT(30)) +#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S) +#define PARL_IO_RX_CLK_I_INV_V 0x00000001U +#define PARL_IO_RX_CLK_I_INV_S 30 +/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Write 1 to invert the output Rx core clock. + */ +#define PARL_IO_RX_CLK_O_INV (BIT(31)) +#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S) +#define PARL_IO_RX_CLK_O_INV_V 0x00000001U +#define PARL_IO_RX_CLK_O_INV_S 31 + +/** PARL_IO_TX_CLK_CFG_REG register + * Parallel IO TX clk configuration register + */ +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) +/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Write 1 to invert the input Tx core clock. + */ +#define PARL_IO_TX_CLK_I_INV (BIT(30)) +#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S) +#define PARL_IO_TX_CLK_I_INV_V 0x00000001U +#define PARL_IO_TX_CLK_I_INV_S 30 +/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Write 1 to invert the output Tx core clock. + */ +#define PARL_IO_TX_CLK_O_INV (BIT(31)) +#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S) +#define PARL_IO_TX_CLK_O_INV_V 0x00000001U +#define PARL_IO_TX_CLK_O_INV_S 31 + +/** PARL_IO_TX_CS_CFG_REG register + * Parallel IO tx_cs_o generate configuration + */ +#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c) +/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0; + * configure the delay between data tx end and tx_cs_o posedge + */ +#define PARL_IO_TX_CS_STOP_DELAY 0x0000FFFFU +#define PARL_IO_TX_CS_STOP_DELAY_M (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S) +#define PARL_IO_TX_CS_STOP_DELAY_V 0x0000FFFFU +#define PARL_IO_TX_CS_STOP_DELAY_S 0 +/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0; + * configure the delay between tx_cs_o negedge and data tx start + */ +#define PARL_IO_TX_CS_START_DELAY 0x0000FFFFU +#define PARL_IO_TX_CS_START_DELAY_M (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S) +#define PARL_IO_TX_CS_START_DELAY_V 0x0000FFFFU +#define PARL_IO_TX_CS_START_DELAY_S 16 + +/** PARL_IO_CLK_REG register + * Parallel IO clk configuration register + */ +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) +/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ +#define PARL_IO_CLK_EN (BIT(31)) +#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S) +#define PARL_IO_CLK_EN_V 0x00000001U +#define PARL_IO_CLK_EN_S 31 + +/** PARL_IO_VERSION_REG register + * Version register. + */ +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160; + * Version of this register file + */ +#define PARL_IO_DATE 0x0FFFFFFFU +#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S) +#define PARL_IO_DATE_V 0x0FFFFFFFU +#define PARL_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/parl_io_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/parl_io_struct.h new file mode 100644 index 0000000000..e58956022c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/parl_io_struct.h @@ -0,0 +1,525 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PARL_IO RX Mode Configuration */ +/** Type of rx_mode_cfg register + * Parallel RX Sampling mode configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ + uint32_t rx_ext_en_sel:4; + /** rx_sw_en : R/W; bitpos: [25]; default: 0; + * Write 1 to enable data sampling by software. + */ + uint32_t rx_sw_en:1; + /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0; + * Write 1 to invert the external enable signal. + */ + uint32_t rx_ext_en_inv:1; + /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 0: positive pulse start(data bit included) && positive pulse end(data bit included) + * 1: positive pulse start(data bit included) && positive pulse end (data bit excluded) + * 2: positive pulse start(data bit excluded) && positive pulse end (data bit included) + * 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) + * 4: positive pulse start(data bit included) && length end + * 5: positive pulse start(data bit excluded) && length end + */ + uint32_t rx_pulse_submode_sel:3; + /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 0: external level enable mode + * 1: external pulse enable mode + * 2: internal software enable mode + */ + uint32_t rx_smp_mode_sel:2; + }; + uint32_t val; +} parl_io_rx_mode_cfg_reg_t; + + +/** Group: PARL_IO RX Data Configuration */ +/** Type of rx_data_cfg register + * Parallel RX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** rx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ + uint32_t rx_bitlen:19; + /** rx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Write 1 to invert bit order of one byte sent from RX_FIFO to DMA. + */ + uint32_t rx_data_order_inv:1; + /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 0: bus width is 1. + * 1: bus width is 2. + * 2: bus width is 4. + * 3: bus width is 8. + */ + uint32_t rx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_rx_data_cfg_reg_t; + + +/** Group: PARL_IO RX General Configuration */ +/** Type of rx_genrl_cfg register + * Parallel RX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rx_gating_en : R/W; bitpos: [12]; default: 0; + * Write 1 to enable the clock gating of output rx clock. + */ + uint32_t rx_gating_en:1; + /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ + uint32_t rx_timeout_thres:16; + /** rx_timeout_en : R/W; bitpos: [29]; default: 1; + * Write 1 to enable timeout function to generate error eof. + */ + uint32_t rx_timeout_en:1; + /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ + uint32_t rx_eof_gen_sel:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} parl_io_rx_genrl_cfg_reg_t; + + +/** Group: PARL_IO RX Start Configuration */ +/** Type of rx_start_cfg register + * Parallel RX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_start : R/W; bitpos: [31]; default: 0; + * Write 1 to start rx data sampling. + */ + uint32_t rx_start:1; + }; + uint32_t val; +} parl_io_rx_start_cfg_reg_t; + + +/** Group: PARL_IO TX Data Configuration */ +/** Type of tx_data_cfg register + * Parallel TX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ + uint32_t tx_bitlen:19; + /** tx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Write 1 to invert bit order of one byte sent from TX_FIFO to IO data. + */ + uint32_t tx_data_order_inv:1; + /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 0: bus width is 1. + * 1: bus width is 2. + * 2: bus width is 4. + * 3: bus width is 8. + */ + uint32_t tx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_tx_data_cfg_reg_t; + + +/** Group: PARL_IO TX Start Configuration */ +/** Type of tx_start_cfg register + * Parallel TX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_start : R/W; bitpos: [31]; default: 0; + * Write 1 to start tx data transmit. + */ + uint32_t tx_start:1; + }; + uint32_t val; +} parl_io_tx_start_cfg_reg_t; + + +/** Group: PARL_IO TX General Configuration */ +/** Type of tx_genrl_cfg register + * Parallel TX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ + uint32_t tx_eof_gen_sel:1; + /** tx_idle_value : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ + uint32_t tx_idle_value:16; + /** tx_gating_en : R/W; bitpos: [30]; default: 0; + * Write 1 to enable the clock gating of output tx clock. + */ + uint32_t tx_gating_en:1; + /** tx_valid_output_en : R/W; bitpos: [31]; default: 0; + * Write 1 to enable the output of tx data valid signal. + */ + uint32_t tx_valid_output_en:1; + }; + uint32_t val; +} parl_io_tx_genrl_cfg_reg_t; + + +/** Group: PARL_IO FIFO Configuration */ +/** Type of fifo_cfg register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_fifo_srst : R/W; bitpos: [30]; default: 0; + * Write 1 to reset async fifo in tx module. + */ + uint32_t tx_fifo_srst:1; + /** rx_fifo_srst : R/W; bitpos: [31]; default: 0; + * Write 1 to reset async fifo in rx module. + */ + uint32_t rx_fifo_srst:1; + }; + uint32_t val; +} parl_io_fifo_cfg_reg_t; + + +/** Group: PARL_IO Register Update Configuration */ +/** Type of reg_update register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_reg_update : WT; bitpos: [31]; default: 0; + * Write 1 to update rx register configuration. + */ + uint32_t rx_reg_update:1; + }; + uint32_t val; +} parl_io_reg_update_reg_t; + + +/** Group: PARL_IO Status */ +/** Type of st register + * Parallel IO module status register0. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_ready : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ + uint32_t tx_ready:1; + }; + uint32_t val; +} parl_io_st_reg_t; + + +/** Group: PARL_IO Interrupt Configuration and Status */ +/** Type of int_ena register + * Parallel IO interrupt enable signal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_ena:1; + /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_ena:1; + /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable TX_EOF_INT. + */ + uint32_t tx_eof_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_ena_reg_t; + +/** Type of int_raw register + * Parallel IO interrupt raw signal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_raw:1; + /** rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_raw:1; + /** tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_raw_reg_t; + +/** Type of int_st register + * Parallel IO interrupt signal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_st:1; + /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_st:1; + /** tx_eof_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_st_reg_t; + +/** Type of int_clr register + * Parallel IO interrupt clear signal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_clr:1; + /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_clr:1; + /** tx_eof_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear TX_EOF_INT. + */ + uint32_t tx_eof_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_clr_reg_t; + + +/** Group: PARL_IO Rx Status0 */ +/** Type of rx_st0 register + * Parallel IO RX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** rx_cnt : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ + uint32_t rx_cnt:5; + /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ + uint32_t rx_fifo_wr_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st0_reg_t; + + +/** Group: PARL_IO Rx Status1 */ +/** Type of rx_st1 register + * Parallel IO RX status register1 + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ + uint32_t rx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st1_reg_t; + + +/** Group: PARL_IO Tx Status0 */ +/** Type of tx_st0 register + * Parallel IO TX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** tx_cnt : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ + uint32_t tx_cnt:7; + /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ + uint32_t tx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_tx_st0_reg_t; + + +/** Group: PARL_IO Rx Clock Configuration */ +/** Type of rx_clk_cfg register + * Parallel IO RX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Write 1 to invert the input Rx core clock. + */ + uint32_t rx_clk_i_inv:1; + /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Write 1 to invert the output Rx core clock. + */ + uint32_t rx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_rx_clk_cfg_reg_t; + + +/** Group: PARL_IO Tx Clock Configuration */ +/** Type of tx_clk_cfg register + * Parallel IO TX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Write 1 to invert the input Tx core clock. + */ + uint32_t tx_clk_i_inv:1; + /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Write 1 to invert the output Tx core clock. + */ + uint32_t tx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_tx_clk_cfg_reg_t; + + +/** Group: PARL_TX_CS Configuration */ +/** Type of tx_cs_cfg register + * Parallel IO tx_cs_o generate configuration + */ +typedef union { + struct { + /** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0; + * configure the delay between data tx end and tx_cs_o posedge + */ + uint32_t tx_cs_stop_delay:16; + /** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0; + * configure the delay between tx_cs_o negedge and data tx start + */ + uint32_t tx_cs_start_delay:16; + }; + uint32_t val; +} parl_io_tx_cs_cfg_reg_t; + + +/** Group: PARL_IO Clock Configuration */ +/** Type of clk register + * Parallel IO clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + }; + uint32_t val; +} parl_io_clk_reg_t; + + +/** Group: PARL_IO Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37786160; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} parl_io_version_reg_t; + + +typedef struct parl_io_dev_t { + volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; + volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; + volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; + volatile parl_io_rx_start_cfg_reg_t rx_start_cfg; + volatile parl_io_tx_data_cfg_reg_t tx_data_cfg; + volatile parl_io_tx_start_cfg_reg_t tx_start_cfg; + volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg; + volatile parl_io_fifo_cfg_reg_t fifo_cfg; + volatile parl_io_reg_update_reg_t reg_update; + volatile parl_io_st_reg_t st; + volatile parl_io_int_ena_reg_t int_ena; + volatile parl_io_int_raw_reg_t int_raw; + volatile parl_io_int_st_reg_t int_st; + volatile parl_io_int_clr_reg_t int_clr; + volatile parl_io_rx_st0_reg_t rx_st0; + volatile parl_io_rx_st1_reg_t rx_st1; + volatile parl_io_tx_st0_reg_t tx_st0; + volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg; + volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg; + volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg; + uint32_t reserved_050[52]; + volatile parl_io_clk_reg_t clk; + uint32_t reserved_124[182]; + volatile parl_io_version_reg_t version; +} parl_io_dev_t; + +extern parl_io_dev_t PARL_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pau_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/pau_reg.h new file mode 100644 index 0000000000..16ec86ea23 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pau_reg.h @@ -0,0 +1,332 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 36705040; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pau_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pau_struct.h new file mode 100644 index 0000000000..13b5c39a32 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pau_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36705040; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_040[239]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pcnt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_eco5_struct.h new file mode 100644 index 0000000000..ada36b8ff1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_eco5_struct.h @@ -0,0 +1,504 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres_un : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres_un:10; + /** filter_en_un : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en_un:1; + /** thr_zero_en_un : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en_un:1; + /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ + uint32_t thr_h_lim_en_un:1; + /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ + uint32_t thr_l_lim_en_un:1; + /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en_un:1; + /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en_un:1; + /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode_un:2; + /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode_un:2; + /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode_un:2; + /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode_un:2; + /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode_un:2; + /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode_un:2; + /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode_un:2; + /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode_un:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0_un:16; + /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1_un:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_h_lim_un:16; + /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_l_lim_un:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t dalta_change_en_u0:1; + /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t dalta_change_en_u1:1; + /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t dalta_change_en_u2:1; + /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t dalta_change_en_u3:1; + uint32_t reserved_12:4; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + +/** Type of u3_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ + uint32_t cnt_step_u3:16; + /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ + uint32_t cnt_step_lim_u3:16; + }; + uint32_t val; +} pcnt_u3_change_conf_reg_t; + +/** Type of u2_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 2. + */ + uint32_t cnt_step_u2:16; + /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 2. + */ + uint32_t cnt_step_lim_u2:16; + }; + uint32_t val; +} pcnt_u2_change_conf_reg_t; + +/** Type of u1_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 1. + */ + uint32_t cnt_step_u1:16; + /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 1. + */ + uint32_t cnt_step_lim_u1:16; + }; + uint32_t val; +} pcnt_u1_change_conf_reg_t; + +/** Type of u0_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 0. + */ + uint32_t cnt_step_u0:16; + /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 0. + */ + uint32_t cnt_step_lim_u0:16; + }; + uint32_t val; +} pcnt_u0_change_conf_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt_un:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode_un:2; + /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat_un:1; + /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat_un:1; + /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat_un:1; + /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat_un:1; + /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_Un when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat_un:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35721985; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + + +typedef struct { + volatile pcnt_un_conf0_reg_t u0_conf0; + volatile pcnt_un_conf1_reg_t u0_conf1; + volatile pcnt_un_conf2_reg_t u0_conf2; + volatile pcnt_un_conf0_reg_t u1_conf0; + volatile pcnt_un_conf1_reg_t u1_conf1; + volatile pcnt_un_conf2_reg_t u1_conf2; + volatile pcnt_un_conf0_reg_t u2_conf0; + volatile pcnt_un_conf1_reg_t u2_conf1; + volatile pcnt_un_conf2_reg_t u2_conf2; + volatile pcnt_un_conf0_reg_t u3_conf0; + volatile pcnt_un_conf1_reg_t u3_conf1; + volatile pcnt_un_conf2_reg_t u3_conf2; + volatile pcnt_un_cnt_reg_t un_cnt[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t un_status[4]; + volatile pcnt_ctrl_reg_t ctrl; + volatile pcnt_u3_change_conf_reg_t u3_change_conf; + volatile pcnt_u2_change_conf_reg_t u2_change_conf; + volatile pcnt_u1_change_conf_reg_t u1_change_conf; + volatile pcnt_u0_change_conf_reg_t u0_change_conf; + uint32_t reserved_074[34]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pcnt_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_reg.h new file mode 100644 index 0000000000..a15eac4f18 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_reg.h @@ -0,0 +1,1346 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U0 (BIT(8)) +#define PCNT_DALTA_CHANGE_EN_U0_M (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S) +#define PCNT_DALTA_CHANGE_EN_U0_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U0_S 8 +/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U1 (BIT(9)) +#define PCNT_DALTA_CHANGE_EN_U1_M (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S) +#define PCNT_DALTA_CHANGE_EN_U1_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U1_S 9 +/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U2 (BIT(10)) +#define PCNT_DALTA_CHANGE_EN_U2_M (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S) +#define PCNT_DALTA_CHANGE_EN_U2_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U2_S 10 +/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U3 (BIT(11)) +#define PCNT_DALTA_CHANGE_EN_U3_M (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S) +#define PCNT_DALTA_CHANGE_EN_U3_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U3_S 11 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_U3_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U3_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x64) +/** PCNT_CNT_STEP_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ +#define PCNT_CNT_STEP_U3 0x0000FFFFU +#define PCNT_CNT_STEP_U3_M (PCNT_CNT_STEP_U3_V << PCNT_CNT_STEP_U3_S) +#define PCNT_CNT_STEP_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_U3_S 0 +/** PCNT_CNT_STEP_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ +#define PCNT_CNT_STEP_LIM_U3 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_M (PCNT_CNT_STEP_LIM_U3_V << PCNT_CNT_STEP_LIM_U3_S) +#define PCNT_CNT_STEP_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_S 16 + +/** PCNT_U2_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U2_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x68) +/** PCNT_CNT_STEP_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 2. + */ +#define PCNT_CNT_STEP_U2 0x0000FFFFU +#define PCNT_CNT_STEP_U2_M (PCNT_CNT_STEP_U2_V << PCNT_CNT_STEP_U2_S) +#define PCNT_CNT_STEP_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_U2_S 0 +/** PCNT_CNT_STEP_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 2. + */ +#define PCNT_CNT_STEP_LIM_U2 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_M (PCNT_CNT_STEP_LIM_U2_V << PCNT_CNT_STEP_LIM_U2_S) +#define PCNT_CNT_STEP_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_S 16 + +/** PCNT_U1_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U1_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x6c) +/** PCNT_CNT_STEP_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 1. + */ +#define PCNT_CNT_STEP_U1 0x0000FFFFU +#define PCNT_CNT_STEP_U1_M (PCNT_CNT_STEP_U1_V << PCNT_CNT_STEP_U1_S) +#define PCNT_CNT_STEP_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_U1_S 0 +/** PCNT_CNT_STEP_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 1. + */ +#define PCNT_CNT_STEP_LIM_U1 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_M (PCNT_CNT_STEP_LIM_U1_V << PCNT_CNT_STEP_LIM_U1_S) +#define PCNT_CNT_STEP_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_S 16 + +/** PCNT_U0_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U0_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x70) +/** PCNT_CNT_STEP_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 0. + */ +#define PCNT_CNT_STEP_U0 0x0000FFFFU +#define PCNT_CNT_STEP_U0_M (PCNT_CNT_STEP_U0_V << PCNT_CNT_STEP_U0_S) +#define PCNT_CNT_STEP_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_U0_S 0 +/** PCNT_CNT_STEP_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 0. + */ +#define PCNT_CNT_STEP_LIM_U0 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_M (PCNT_CNT_STEP_LIM_U0_V << PCNT_CNT_STEP_LIM_U0_S) +#define PCNT_CNT_STEP_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 35721985; + * This is the PCNT version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pcnt_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_struct.h new file mode 100644 index 0000000000..03b63407cf --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pcnt_struct.h @@ -0,0 +1,442 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres:10; + /** filter_en : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en:1; + /** thr_zero_en : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en:1; + /** thr_h_lim_en : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ + uint32_t thr_h_lim_en:1; + /** thr_l_lim_en : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ + uint32_t thr_l_lim_en:1; + /** thr_thres0_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en:1; + /** thr_thres1_en : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en:1; + /** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode:2; + /** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode:2; + /** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode:2; + /** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode:2; + /** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode:2; + /** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode:2; + /** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode:2; + /** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0:16; + /** cnt_thres1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_h_lim:16; + /** cnt_l_lim : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_l_lim:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + /** delta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t delta_change_en_u0:1; + /** delta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t delta_change_en_u1:1; + /** delta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t delta_change_en_u2:1; + /** delta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t delta_change_en_u3:1; + uint32_t reserved_12:4; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + +/** Type of change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit n. + */ + uint32_t cnt_step:16; + /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit n. + */ + uint32_t cnt_step_lim:16; + }; + uint32_t val; +} pcnt_un_change_conf_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode:2; + /** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat:1; + /** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat:1; + /** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat:1; + /** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat:1; + /** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 571021568; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + +typedef struct pcnt_dev_t { + volatile struct { + pcnt_un_conf0_reg_t conf0; + pcnt_un_conf1_reg_t conf1; + pcnt_un_conf2_reg_t conf2; + } conf_unit[4]; + volatile pcnt_un_cnt_reg_t cnt_unit[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t status_unit[4]; + volatile pcnt_ctrl_reg_t ctrl; + volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210 + uint32_t reserved_074[34]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_reg.h new file mode 100644 index 0000000000..3d574d64cf --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_reg.h @@ -0,0 +1,4968 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_M (PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V << PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN (BIT(23)) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_M (PMU_HP_ACTIVE_PD_CNNT_PD_EN_V << PMU_HP_ACTIVE_PD_CNNT_PD_EN_S) +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(21)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 21 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(22)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 22 +/** PMU_HP_ACTIVE_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_I2C_M (PMU_HP_ACTIVE_XPD_PLL_I2C_V << PMU_HP_ACTIVE_XPD_PLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_I2C_S 23 +/** PMU_HP_ACTIVE_XPD_PLL : R/W; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_PLL 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_M (PMU_HP_ACTIVE_XPD_PLL_V << PMU_HP_ACTIVE_XPD_PLL_S) +#define PMU_HP_ACTIVE_XPD_PLL_V 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_S 27 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [22:18]; default: 20; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) +#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_S 18 +/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) +#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_S 23 +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_M (PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V << PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_CNNT_PD_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_CNNT_PD_EN_M (PMU_HP_MODEM_PD_CNNT_PD_EN_V << PMU_HP_MODEM_PD_CNNT_PD_EN_S) +#define PMU_HP_MODEM_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_CNNT_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : WT; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_MODEM_UART_WAKEUP_EN : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(21)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 21 +/** PMU_HP_MODEM_I2C_RETENTION : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(22)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 22 +/** PMU_HP_MODEM_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_I2C_M (PMU_HP_MODEM_XPD_PLL_I2C_V << PMU_HP_MODEM_XPD_PLL_I2C_S) +#define PMU_HP_MODEM_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_I2C_S 23 +/** PMU_HP_MODEM_XPD_PLL : WT; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_PLL 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_M (PMU_HP_MODEM_XPD_PLL_V << PMU_HP_MODEM_XPD_PLL_S) +#define PMU_HP_MODEM_XPD_PLL_V 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_S 27 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_VSET 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) +#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_S 18 +/** PMU_HP_MODEM_DCM_MODE : WT; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_MODE 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) +#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_S 23 +/** PMU_HP_MODEM_XPD_BIAS : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : WT; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : WT; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : WT; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : WT; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : WT; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : WT; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : WT; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : WT; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_M (PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V << PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN (BIT(23)) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_M (PMU_HP_SLEEP_PD_CNNT_PD_EN_V << PMU_HP_SLEEP_PD_CNNT_PD_EN_S) +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(21)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 21 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(22)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 22 +/** PMU_HP_SLEEP_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_I2C_M (PMU_HP_SLEEP_XPD_PLL_I2C_V << PMU_HP_SLEEP_XPD_PLL_I2C_S) +#define PMU_HP_SLEEP_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_I2C_S 23 +/** PMU_HP_SLEEP_XPD_PLL : R/W; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_PLL 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_M (PMU_HP_SLEEP_XPD_PLL_V << PMU_HP_SLEEP_XPD_PLL_S) +#define PMU_HP_SLEEP_XPD_PLL_V 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_S 27 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [22:18]; default: 20; + * need_des + */ +#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) +#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_S 18 +/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCM_MODE 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) +#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_S 23 +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL (BIT(26)) +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_M (PMU_HP_SLEEP_LP_PAD_SLP_SEL_V << PMU_HP_SLEEP_LP_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_S 26 +/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_M (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S) +#define PMU_HP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_HP_SLEEP_XPD_LPPLL_M (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S) +#define PMU_HP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_LPPLL_S 27 +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000003FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 26 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL (BIT(26)) +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_M (PMU_LP_SLEEP_LP_PAD_SLP_SEL_V << PMU_LP_SLEEP_LP_PAD_SLP_SEL_S) +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_V 0x00000001U +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_S 26 +/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_M (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S) +#define PMU_LP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_LP_SLEEP_XPD_LPPLL_M (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S) +#define PMU_LP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_LPPLL_S 27 +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_CALI_XTAL_ICG : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_CALI_XTAL_ICG (BIT(0)) +#define PMU_TIE_LOW_CALI_XTAL_ICG_M (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S) +#define PMU_TIE_LOW_CALI_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_CALI_XTAL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_PLL_ICG : WT; bitpos: [4:1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_PLL_ICG 0x0000000FU +#define PMU_TIE_LOW_GLOBAL_PLL_ICG_M (PMU_TIE_LOW_GLOBAL_PLL_ICG_V << PMU_TIE_LOW_GLOBAL_PLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_PLL_ICG_V 0x0000000FU +#define PMU_TIE_LOW_GLOBAL_PLL_ICG_S 1 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(5)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 5 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(6)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 6 +/** PMU_TIE_LOW_XPD_PLL_I2C : WT; bitpos: [10:7]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_PLL_I2C 0x0000000FU +#define PMU_TIE_LOW_XPD_PLL_I2C_M (PMU_TIE_LOW_XPD_PLL_I2C_V << PMU_TIE_LOW_XPD_PLL_I2C_S) +#define PMU_TIE_LOW_XPD_PLL_I2C_V 0x0000000FU +#define PMU_TIE_LOW_XPD_PLL_I2C_S 7 +/** PMU_TIE_LOW_XPD_PLL : WT; bitpos: [14:11]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_PLL 0x0000000FU +#define PMU_TIE_LOW_XPD_PLL_M (PMU_TIE_LOW_XPD_PLL_V << PMU_TIE_LOW_XPD_PLL_S) +#define PMU_TIE_LOW_XPD_PLL_V 0x0000000FU +#define PMU_TIE_LOW_XPD_PLL_S 11 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(15)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 15 +/** PMU_TIE_HIGH_CALI_XTAL_ICG : R/W; bitpos: [16]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_CALI_XTAL_ICG (BIT(16)) +#define PMU_TIE_HIGH_CALI_XTAL_ICG_M (PMU_TIE_HIGH_CALI_XTAL_ICG_V << PMU_TIE_HIGH_CALI_XTAL_ICG_S) +#define PMU_TIE_HIGH_CALI_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_CALI_XTAL_ICG_S 16 +/** PMU_TIE_HIGH_GLOBAL_PLL_ICG : WT; bitpos: [20:17]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_PLL_ICG 0x0000000FU +#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_M (PMU_TIE_HIGH_GLOBAL_PLL_ICG_V << PMU_TIE_HIGH_GLOBAL_PLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_V 0x0000000FU +#define PMU_TIE_HIGH_GLOBAL_PLL_ICG_S 17 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(21)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 21 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(22)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 22 +/** PMU_TIE_HIGH_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_PLL_I2C 0x0000000FU +#define PMU_TIE_HIGH_XPD_PLL_I2C_M (PMU_TIE_HIGH_XPD_PLL_I2C_V << PMU_TIE_HIGH_XPD_PLL_I2C_S) +#define PMU_TIE_HIGH_XPD_PLL_I2C_V 0x0000000FU +#define PMU_TIE_HIGH_XPD_PLL_I2C_S 23 +/** PMU_TIE_HIGH_XPD_PLL : WT; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_PLL 0x0000000FU +#define PMU_TIE_HIGH_XPD_PLL_M (PMU_TIE_HIGH_XPD_PLL_V << PMU_TIE_HIGH_XPD_PLL_S) +#define PMU_TIE_HIGH_XPD_PLL_V 0x0000000FU +#define PMU_TIE_HIGH_XPD_PLL_S 27 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_PAD_SLP_SEL : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_PAD_SLP_SEL (BIT(0)) +#define PMU_PAD_SLP_SEL_M (PMU_PAD_SLP_SEL_V << PMU_PAD_SLP_SEL_S) +#define PMU_PAD_SLP_SEL_V 0x00000001U +#define PMU_PAD_SLP_SEL_S 0 +/** PMU_LP_PAD_HOLD_ALL : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_PAD_HOLD_ALL (BIT(1)) +#define PMU_LP_PAD_HOLD_ALL_M (PMU_LP_PAD_HOLD_ALL_V << PMU_LP_PAD_HOLD_ALL_S) +#define PMU_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_LP_PAD_HOLD_ALL_S 1 +/** PMU_HP_PAD_HOLD_ALL : RO; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_HP_PAD_HOLD_ALL (BIT(2)) +#define PMU_HP_PAD_HOLD_ALL_M (PMU_HP_PAD_HOLD_ALL_V << PMU_HP_PAD_HOLD_ALL_S) +#define PMU_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_PAD_HOLD_ALL_S 2 +/** PMU_TIE_HIGH_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_PAD_SLP_SEL (BIT(26)) +#define PMU_TIE_HIGH_PAD_SLP_SEL_M (PMU_TIE_HIGH_PAD_SLP_SEL_V << PMU_TIE_HIGH_PAD_SLP_SEL_S) +#define PMU_TIE_HIGH_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_PAD_SLP_SEL_S 26 +/** PMU_TIE_LOW_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_PAD_SLP_SEL (BIT(27)) +#define PMU_TIE_LOW_PAD_SLP_SEL_M (PMU_TIE_LOW_PAD_SLP_SEL_V << PMU_TIE_LOW_PAD_SLP_SEL_S) +#define PMU_TIE_LOW_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_PAD_SLP_SEL_S 27 +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_LP_POWERDOWN_TIMER_S 5 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_LP_POWERUP_TIMER_S 14 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 + +/** PMU_POWER_PD_CNNT_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_CNNT_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_CNNT_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_RESET (BIT(0)) +#define PMU_FORCE_CNNT_RESET_M (PMU_FORCE_CNNT_RESET_V << PMU_FORCE_CNNT_RESET_S) +#define PMU_FORCE_CNNT_RESET_V 0x00000001U +#define PMU_FORCE_CNNT_RESET_S 0 +/** PMU_FORCE_CNNT_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_ISO (BIT(1)) +#define PMU_FORCE_CNNT_ISO_M (PMU_FORCE_CNNT_ISO_V << PMU_FORCE_CNNT_ISO_S) +#define PMU_FORCE_CNNT_ISO_V 0x00000001U +#define PMU_FORCE_CNNT_ISO_S 1 +/** PMU_FORCE_CNNT_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_PU (BIT(2)) +#define PMU_FORCE_CNNT_PU_M (PMU_FORCE_CNNT_PU_V << PMU_FORCE_CNNT_PU_S) +#define PMU_FORCE_CNNT_PU_V 0x00000001U +#define PMU_FORCE_CNNT_PU_S 2 +/** PMU_FORCE_CNNT_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_NO_RESET (BIT(3)) +#define PMU_FORCE_CNNT_NO_RESET_M (PMU_FORCE_CNNT_NO_RESET_V << PMU_FORCE_CNNT_NO_RESET_S) +#define PMU_FORCE_CNNT_NO_RESET_V 0x00000001U +#define PMU_FORCE_CNNT_NO_RESET_S 3 +/** PMU_FORCE_CNNT_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_NO_ISO (BIT(4)) +#define PMU_FORCE_CNNT_NO_ISO_M (PMU_FORCE_CNNT_NO_ISO_V << PMU_FORCE_CNNT_NO_ISO_S) +#define PMU_FORCE_CNNT_NO_ISO_V 0x00000001U +#define PMU_FORCE_CNNT_NO_ISO_S 4 +/** PMU_FORCE_CNNT_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_PD (BIT(5)) +#define PMU_FORCE_CNNT_PD_M (PMU_FORCE_CNNT_PD_V << PMU_FORCE_CNNT_PD_S) +#define PMU_FORCE_CNNT_PD_V 0x00000001U +#define PMU_FORCE_CNNT_PD_S 5 + +/** PMU_POWER_PD_HPMEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPMEM_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_MEM_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_RESET (BIT(0)) +#define PMU_FORCE_HP_MEM_RESET_M (PMU_FORCE_HP_MEM_RESET_V << PMU_FORCE_HP_MEM_RESET_S) +#define PMU_FORCE_HP_MEM_RESET_V 0x00000001U +#define PMU_FORCE_HP_MEM_RESET_S 0 +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO (BIT(1)) +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x00000001U +#define PMU_FORCE_HP_MEM_ISO_S 1 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU (BIT(2)) +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x00000001U +#define PMU_FORCE_HP_MEM_PU_S 2 +/** PMU_FORCE_HP_MEM_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_MEM_NO_RESET_M (PMU_FORCE_HP_MEM_NO_RESET_V << PMU_FORCE_HP_MEM_NO_RESET_S) +#define PMU_FORCE_HP_MEM_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_MEM_NO_RESET_S 3 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_MEM_NO_ISO_S 4 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD (BIT(5)) +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x00000001U +#define PMU_FORCE_HP_MEM_PD_S 5 + +/** PMU_POWER_PD_TOP_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_MASK_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_XPD_TOP_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_TOP_MASK 0x0000001FU +#define PMU_XPD_TOP_MASK_M (PMU_XPD_TOP_MASK_V << PMU_XPD_TOP_MASK_S) +#define PMU_XPD_TOP_MASK_V 0x0000001FU +#define PMU_XPD_TOP_MASK_S 0 +/** PMU_PD_TOP_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 27 + +/** PMU_POWER_PD_CNNT_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_CNNT_MASK_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_XPD_CNNT_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_CNNT_MASK 0x0000001FU +#define PMU_XPD_CNNT_MASK_M (PMU_XPD_CNNT_MASK_V << PMU_XPD_CNNT_MASK_S) +#define PMU_XPD_CNNT_MASK_V 0x0000001FU +#define PMU_XPD_CNNT_MASK_S 0 +/** PMU_PD_CNNT_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_CNNT_MASK 0x0000001FU +#define PMU_PD_CNNT_MASK_M (PMU_PD_CNNT_MASK_V << PMU_PD_CNNT_MASK_S) +#define PMU_PD_CNNT_MASK_V 0x0000001FU +#define PMU_PD_CNNT_MASK_S 27 + +/** PMU_POWER_PD_HPMEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_HPMEM_MASK_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_XPD_HP_MEM_MASK : R/W; bitpos: [5:0]; default: 0; + * need_des + */ +#define PMU_XPD_HP_MEM_MASK 0x0000003FU +#define PMU_XPD_HP_MEM_MASK_M (PMU_XPD_HP_MEM_MASK_V << PMU_XPD_HP_MEM_MASK_S) +#define PMU_XPD_HP_MEM_MASK_V 0x0000003FU +#define PMU_XPD_HP_MEM_MASK_S 0 +/** PMU_PD_HP_MEM_MASK : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM_MASK 0x0000003FU +#define PMU_PD_HP_MEM_MASK_M (PMU_PD_HP_MEM_MASK_V << PMU_PD_HP_MEM_MASK_S) +#define PMU_PD_HP_MEM_MASK_V 0x0000003FU +#define PMU_PD_HP_MEM_MASK_S 26 + +/** PMU_POWER_DCDC_SWITCH_REG register + * need_des + */ +#define PMU_POWER_DCDC_SWITCH_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_DCDC_SWITCH_PU : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FORCE_DCDC_SWITCH_PU (BIT(0)) +#define PMU_FORCE_DCDC_SWITCH_PU_M (PMU_FORCE_DCDC_SWITCH_PU_V << PMU_FORCE_DCDC_SWITCH_PU_S) +#define PMU_FORCE_DCDC_SWITCH_PU_V 0x00000001U +#define PMU_FORCE_DCDC_SWITCH_PU_S 0 +/** PMU_FORCE_DCDC_SWITCH_PD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_DCDC_SWITCH_PD (BIT(1)) +#define PMU_FORCE_DCDC_SWITCH_PD_M (PMU_FORCE_DCDC_SWITCH_PD_V << PMU_FORCE_DCDC_SWITCH_PD_S) +#define PMU_FORCE_DCDC_SWITCH_PD_V 0x00000001U +#define PMU_FORCE_DCDC_SWITCH_PD_S 1 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_LPPERI_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_MASK_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_XPD_LP_PERI_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_LP_PERI_MASK 0x0000001FU +#define PMU_XPD_LP_PERI_MASK_M (PMU_XPD_LP_PERI_MASK_V << PMU_XPD_LP_PERI_MASK_S) +#define PMU_XPD_LP_PERI_MASK_V 0x0000001FU +#define PMU_XPD_LP_PERI_MASK_S 0 +/** PMU_PD_LP_PERI_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_LP_PERI_MASK 0x0000001FU +#define PMU_PD_LP_PERI_MASK_M (PMU_PD_LP_PERI_MASK_V << PMU_PD_LP_PERI_MASK_S) +#define PMU_PD_LP_PERI_MASK_V 0x0000001FU +#define PMU_PD_LP_PERI_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_PMU_WAIT_XTL_STABLE_M (PMU_PMU_WAIT_XTL_STABLE_V << PMU_PMU_WAIT_XTL_STABLE_S) +#define PMU_PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_PMU_WAIT_XTL_STABLE_S 0 +/** PMU_PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_PMU_WAIT_PLL_STABLE_M (PMU_PMU_WAIT_PLL_STABLE_V << PMU_PMU_WAIT_PLL_STABLE_S) +#define PMU_PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0x7FFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0x7FFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET_EXPAND : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET_EXPAND 0x00000003U +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_M (PMU_LP_ANA_WAIT_TARGET_EXPAND_V << PMU_LP_ANA_WAIT_TARGET_EXPAND_S) +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_V 0x00000003U +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_S 22 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_CNTL8_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL8_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_LP_LITE_WAKEUP_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_LITE_WAKEUP_ENA (BIT(31)) +#define PMU_LP_LITE_WAKEUP_ENA_M (PMU_LP_LITE_WAKEUP_ENA_V << PMU_LP_LITE_WAKEUP_ENA_S) +#define PMU_LP_LITE_WAKEUP_ENA_V 0x00000001U +#define PMU_LP_LITE_WAKEUP_ENA_S 31 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0x7FFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0x7FFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0x7FFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0x7FFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS2_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_LP_LITE_WAKEUP_CAUSE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_LITE_WAKEUP_CAUSE (BIT(31)) +#define PMU_LP_LITE_WAKEUP_CAUSE_M (PMU_LP_LITE_WAKEUP_CAUSE_V << PMU_LP_LITE_WAKEUP_CAUSE_S) +#define PMU_LP_LITE_WAKEUP_CAUSE_V 0x00000001U +#define PMU_LP_LITE_WAKEUP_CAUSE_S 31 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_MSPI_PHY_XPD : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MSPI_PHY_XPD (BIT(24)) +#define PMU_MSPI_PHY_XPD_M (PMU_MSPI_PHY_XPD_V << PMU_MSPI_PHY_XPD_S) +#define PMU_MSPI_PHY_XPD_V 0x00000001U +#define PMU_MSPI_PHY_XPD_S 24 +/** PMU_SDIO_PLL_XPD : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_SDIO_PLL_XPD (BIT(25)) +#define PMU_SDIO_PLL_XPD_M (PMU_SDIO_PLL_XPD_V << PMU_SDIO_PLL_XPD_S) +#define PMU_SDIO_PLL_XPD_V 0x00000001U +#define PMU_SDIO_PLL_XPD_S 25 +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 25 +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S 25 +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 25 +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 25 +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_M (PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V << PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 25 +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_SLEEP_REJECT_INT_ST : RO; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_M (PMU_LP_CPU_SLEEP_REJECT_INT_ST_V << PMU_LP_CPU_SLEEP_REJECT_INT_ST_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S 25 +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_SLEEP_REJECT_INT_ENA : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_M (PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V << PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 25 +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR : WT; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_M (PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V << PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S) +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 25 +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_LP_CPU_PWR2_REG register + * need_des + */ +#define PMU_LP_CPU_PWR2_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 + +/** PMU_LP_CPU_PWR3_REG register + * need_des + */ +#define PMU_LP_CPU_PWR3_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_LP_CPU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_CAUSE 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_CAUSE_M (PMU_LP_CPU_WAKEUP_CAUSE_V << PMU_LP_CPU_WAKEUP_CAUSE_S) +#define PMU_LP_CPU_WAKEUP_CAUSE_V 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_CAUSE_S 0 + +/** PMU_LP_CPU_PWR4_REG register + * need_des + */ +#define PMU_LP_CPU_PWR4_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_LP_CPU_REJECT_EN : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_REJECT_EN 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_EN_M (PMU_LP_CPU_REJECT_EN_V << PMU_LP_CPU_REJECT_EN_S) +#define PMU_LP_CPU_REJECT_EN_V 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_EN_S 0 + +/** PMU_LP_CPU_PWR5_REG register + * need_des + */ +#define PMU_LP_CPU_PWR5_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_LP_CPU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_REJECT_CAUSE 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_CAUSE_M (PMU_LP_CPU_REJECT_CAUSE_V << PMU_LP_CPU_REJECT_CAUSE_S) +#define PMU_LP_CPU_REJECT_CAUSE_V 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_CAUSE_S 0 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_ENABLE_CALI_PMU_CNTL : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_ENABLE_CALI_PMU_CNTL (BIT(0)) +#define PMU_ENABLE_CALI_PMU_CNTL_M (PMU_ENABLE_CALI_PMU_CNTL_V << PMU_ENABLE_CALI_PMU_CNTL_S) +#define PMU_ENABLE_CALI_PMU_CNTL_V 0x00000001U +#define PMU_ENABLE_CALI_PMU_CNTL_S 0 +/** PMU_PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_LAST_ST_STATE_M (PMU_PMU_MAIN_LAST_ST_STATE_V << PMU_PMU_MAIN_LAST_ST_STATE_S) +#define PMU_PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_TAR_ST_STATE_M (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S) +#define PMU_PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; + * need_des + */ +#define PMU_PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_CUR_ST_STATE_M (PMU_PMU_MAIN_CUR_ST_STATE_V << PMU_PMU_MAIN_CUR_ST_STATE_S) +#define PMU_PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) +/** PMU_PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_PMU_BACKUP_ST_STATE_M (PMU_PMU_BACKUP_ST_STATE_V << PMU_PMU_BACKUP_ST_STATE_S) +#define PMU_PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_PMU_BACKUP_ST_STATE_S 13 +/** PMU_PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_PMU_LP_PWR_ST_STATE_M (PMU_PMU_LP_PWR_ST_STATE_V << PMU_PMU_LP_PWR_ST_STATE_S) +#define PMU_PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_PMU_LP_PWR_ST_STATE_S 18 +/** PMU_PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_PMU_HP_PWR_ST_STATE_M (PMU_PMU_HP_PWR_ST_STATE_V << PMU_PMU_HP_PWR_ST_STATE_S) +#define PMU_PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) +/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 0; + * need_des + */ +#define PMU_STABLE_XPD_PLL_STATE 0x00000007U +#define PMU_STABLE_XPD_PLL_STATE_M (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S) +#define PMU_STABLE_XPD_PLL_STATE_V 0x00000007U +#define PMU_STABLE_XPD_PLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(3)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 3 +/** PMU_PMU_ANA_XPD_PLL_I2C_STATE : RO; bitpos: [6:4]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE 0x00000007U +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_M (PMU_PMU_ANA_XPD_PLL_I2C_STATE_V << PMU_PMU_ANA_XPD_PLL_I2C_STATE_S) +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_V 0x00000007U +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_S 4 +/** PMU_PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE (BIT(10)) +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_S 10 +/** PMU_PMU_SYS_CLK_SEL_STATE : RO; bitpos: [12:11]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_PMU_SYS_CLK_SEL_STATE_M (PMU_PMU_SYS_CLK_SEL_STATE_V << PMU_PMU_SYS_CLK_SEL_STATE_S) +#define PMU_PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_PMU_SYS_CLK_SEL_STATE_S 11 +/** PMU_PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_NO_DIV_STATE (BIT(13)) +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_M (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_S 13 +/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_PMU_ICG_SYS_CLK_EN_STATE (BIT(14)) +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_M (PMU_PMU_ICG_SYS_CLK_EN_STATE_V << PMU_PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_S 14 +/** PMU_PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_MODEM_SWITCH_STATE (BIT(15)) +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_M (PMU_PMU_ICG_MODEM_SWITCH_STATE_V << PMU_PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_S 15 +/** PMU_PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_PMU_ICG_MODEM_CODE_STATE_M (PMU_PMU_ICG_MODEM_CODE_STATE_V << PMU_PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_PMU_ICG_MODEM_CODE_STATE_S 16 +/** PMU_PMU_ICG_SLP_SEL_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_SLP_SEL_STATE (BIT(18)) +#define PMU_PMU_ICG_SLP_SEL_STATE_M (PMU_PMU_ICG_SLP_SEL_STATE_V << PMU_PMU_ICG_SLP_SEL_STATE_S) +#define PMU_PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_PMU_ICG_SLP_SEL_STATE_S 18 +/** PMU_PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE (BIT(19)) +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_S 19 +/** PMU_PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [23:20]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_GLOBAL_PLL_STATE 0x0000000FU +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_M (PMU_PMU_ICG_GLOBAL_PLL_STATE_V << PMU_PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_V 0x0000000FU +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_S 20 +/** PMU_PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_I2C_ISO_EN_STATE (BIT(24)) +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_M (PMU_PMU_ANA_I2C_ISO_EN_STATE_V << PMU_PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_S 24 +/** PMU_PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_I2C_RETENTION_STATE (BIT(25)) +#define PMU_PMU_ANA_I2C_RETENTION_STATE_M (PMU_PMU_ANA_I2C_RETENTION_STATE_V << PMU_PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_PMU_ANA_I2C_RETENTION_STATE_S 25 +/** PMU_PMU_ANA_XPD_PLL_STATE : RO; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_XPD_PLL_STATE 0x0000000FU +#define PMU_PMU_ANA_XPD_PLL_STATE_M (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S) +#define PMU_PMU_ANA_XPD_PLL_STATE_V 0x0000000FU +#define PMU_PMU_ANA_XPD_PLL_STATE_S 27 +/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_PMU_ANA_XPD_XTAL_STATE_M (PMU_PMU_ANA_XPD_XTAL_STATE_V << PMU_PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) +/** PMU_PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_PMU_ICG_FUNC_EN_STATE_M (PMU_PMU_ICG_FUNC_EN_STATE_V << PMU_PMU_ICG_FUNC_EN_STATE_S) +#define PMU_PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) +/** PMU_PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_PMU_ICG_APB_EN_STATE_M (PMU_PMU_ICG_APB_EN_STATE_V << PMU_PMU_ICG_APB_EN_STATE_S) +#define PMU_PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_EXT_LDO_P0_0P1A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_0P1A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P1A_CNT_CLR_0 (BIT(6)) +#define PMU_0P1A_CNT_CLR_0_M (PMU_0P1A_CNT_CLR_0_V << PMU_0P1A_CNT_CLR_0_S) +#define PMU_0P1A_CNT_CLR_0_V 0x00000001U +#define PMU_0P1A_CNT_CLR_0_S 6 +/** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P1A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P1A_FORCE_TIEH_SEL_0_M (PMU_0P1A_FORCE_TIEH_SEL_0_V << PMU_0P1A_FORCE_TIEH_SEL_0_S) +#define PMU_0P1A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P1A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P1A_XPD_0 : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define PMU_0P1A_XPD_0 (BIT(8)) +#define PMU_0P1A_XPD_0_M (PMU_0P1A_XPD_0_V << PMU_0P1A_XPD_0_S) +#define PMU_0P1A_XPD_0_V 0x00000001U +#define PMU_0P1A_XPD_0_S 8 +/** PMU_0P1A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_SEL_0 0x00000007U +#define PMU_0P1A_TIEH_SEL_0_M (PMU_0P1A_TIEH_SEL_0_V << PMU_0P1A_TIEH_SEL_0_S) +#define PMU_0P1A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P1A_TIEH_SEL_0_S 9 +/** PMU_0P1A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P1A_TIEH_POS_EN_0_M (PMU_0P1A_TIEH_POS_EN_0_V << PMU_0P1A_TIEH_POS_EN_0_S) +#define PMU_0P1A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P1A_TIEH_POS_EN_0_S 12 +/** PMU_0P1A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P1A_TIEH_NEG_EN_0_M (PMU_0P1A_TIEH_NEG_EN_0_V << PMU_0P1A_TIEH_NEG_EN_0_S) +#define PMU_0P1A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P1A_TIEH_NEG_EN_0_S 13 +/** PMU_0P1A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_0 (BIT(14)) +#define PMU_0P1A_TIEH_0_M (PMU_0P1A_TIEH_0_V << PMU_0P1A_TIEH_0_S) +#define PMU_0P1A_TIEH_0_V 0x00000001U +#define PMU_0P1A_TIEH_0_S 14 +/** PMU_0P1A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P1A_TARGET1_0 0x000000FFU +#define PMU_0P1A_TARGET1_0_M (PMU_0P1A_TARGET1_0_V << PMU_0P1A_TARGET1_0_S) +#define PMU_0P1A_TARGET1_0_V 0x000000FFU +#define PMU_0P1A_TARGET1_0_S 15 +/** PMU_0P1A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P1A_TARGET0_0 0x000000FFU +#define PMU_0P1A_TARGET0_0_M (PMU_0P1A_TARGET0_0_V << PMU_0P1A_TARGET0_0_S) +#define PMU_0P1A_TARGET0_0_V 0x000000FFU +#define PMU_0P1A_TARGET0_0_S 23 +/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P1A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_ANA_0P1A_MUL_0 : R/W; bitpos: [25:23]; default: 2; + * need_des + */ +#define PMU_ANA_0P1A_MUL_0 0x00000007U +#define PMU_ANA_0P1A_MUL_0_M (PMU_ANA_0P1A_MUL_0_V << PMU_ANA_0P1A_MUL_0_S) +#define PMU_ANA_0P1A_MUL_0_V 0x00000007U +#define PMU_ANA_0P1A_MUL_0_S 23 +/** PMU_ANA_0P1A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P1A_EN_VDET_0_M (PMU_ANA_0P1A_EN_VDET_0_V << PMU_ANA_0P1A_EN_VDET_0_S) +#define PMU_ANA_0P1A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P1A_EN_VDET_0_S 26 +/** PMU_ANA_0P1A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P1A_EN_CUR_LIM_0_M (PMU_ANA_0P1A_EN_CUR_LIM_0_V << PMU_ANA_0P1A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P1A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P1A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P1A_DREF_0 : R/W; bitpos: [31:28]; default: 11; + * need_des + */ +#define PMU_ANA_0P1A_DREF_0 0x0000000FU +#define PMU_ANA_0P1A_DREF_0_M (PMU_ANA_0P1A_DREF_0_V << PMU_ANA_0P1A_DREF_0_S) +#define PMU_ANA_0P1A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P1A_DREF_0_S 28 + +/** PMU_EXT_LDO_P0_0P2A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0) +/** PMU_0P2A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P2A_CNT_CLR_0 (BIT(6)) +#define PMU_0P2A_CNT_CLR_0_M (PMU_0P2A_CNT_CLR_0_V << PMU_0P2A_CNT_CLR_0_S) +#define PMU_0P2A_CNT_CLR_0_V 0x00000001U +#define PMU_0P2A_CNT_CLR_0_S 6 +/** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P2A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P2A_FORCE_TIEH_SEL_0_M (PMU_0P2A_FORCE_TIEH_SEL_0_V << PMU_0P2A_FORCE_TIEH_SEL_0_S) +#define PMU_0P2A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P2A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P2A_XPD_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P2A_XPD_0 (BIT(8)) +#define PMU_0P2A_XPD_0_M (PMU_0P2A_XPD_0_V << PMU_0P2A_XPD_0_S) +#define PMU_0P2A_XPD_0_V 0x00000001U +#define PMU_0P2A_XPD_0_S 8 +/** PMU_0P2A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_SEL_0 0x00000007U +#define PMU_0P2A_TIEH_SEL_0_M (PMU_0P2A_TIEH_SEL_0_V << PMU_0P2A_TIEH_SEL_0_S) +#define PMU_0P2A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P2A_TIEH_SEL_0_S 9 +/** PMU_0P2A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P2A_TIEH_POS_EN_0_M (PMU_0P2A_TIEH_POS_EN_0_V << PMU_0P2A_TIEH_POS_EN_0_S) +#define PMU_0P2A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P2A_TIEH_POS_EN_0_S 12 +/** PMU_0P2A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P2A_TIEH_NEG_EN_0_M (PMU_0P2A_TIEH_NEG_EN_0_V << PMU_0P2A_TIEH_NEG_EN_0_S) +#define PMU_0P2A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P2A_TIEH_NEG_EN_0_S 13 +/** PMU_0P2A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_0 (BIT(14)) +#define PMU_0P2A_TIEH_0_M (PMU_0P2A_TIEH_0_V << PMU_0P2A_TIEH_0_S) +#define PMU_0P2A_TIEH_0_V 0x00000001U +#define PMU_0P2A_TIEH_0_S 14 +/** PMU_0P2A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P2A_TARGET1_0 0x000000FFU +#define PMU_0P2A_TARGET1_0_M (PMU_0P2A_TARGET1_0_V << PMU_0P2A_TARGET1_0_S) +#define PMU_0P2A_TARGET1_0_V 0x000000FFU +#define PMU_0P2A_TARGET1_0_S 15 +/** PMU_0P2A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P2A_TARGET0_0 0x000000FFU +#define PMU_0P2A_TARGET0_0_M (PMU_0P2A_TARGET0_0_V << PMU_0P2A_TARGET0_0_S) +#define PMU_0P2A_TARGET0_0_V 0x000000FFU +#define PMU_0P2A_TARGET0_0_S 23 +/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P2A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1c4) +/** PMU_ANA_0P2A_MUL_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_MUL_0 0x00000007U +#define PMU_ANA_0P2A_MUL_0_M (PMU_ANA_0P2A_MUL_0_V << PMU_ANA_0P2A_MUL_0_S) +#define PMU_ANA_0P2A_MUL_0_V 0x00000007U +#define PMU_ANA_0P2A_MUL_0_S 23 +/** PMU_ANA_0P2A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P2A_EN_VDET_0_M (PMU_ANA_0P2A_EN_VDET_0_V << PMU_ANA_0P2A_EN_VDET_0_S) +#define PMU_ANA_0P2A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P2A_EN_VDET_0_S 26 +/** PMU_ANA_0P2A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P2A_EN_CUR_LIM_0_M (PMU_ANA_0P2A_EN_CUR_LIM_0_V << PMU_ANA_0P2A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P2A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P2A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P2A_DREF_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P2A_DREF_0 0x0000000FU +#define PMU_ANA_0P2A_DREF_0_M (PMU_ANA_0P2A_DREF_0_V << PMU_ANA_0P2A_DREF_0_S) +#define PMU_ANA_0P2A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P2A_DREF_0_S 28 + +/** PMU_EXT_LDO_P0_0P3A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8) +/** PMU_0P3A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P3A_CNT_CLR_0 (BIT(6)) +#define PMU_0P3A_CNT_CLR_0_M (PMU_0P3A_CNT_CLR_0_V << PMU_0P3A_CNT_CLR_0_S) +#define PMU_0P3A_CNT_CLR_0_V 0x00000001U +#define PMU_0P3A_CNT_CLR_0_S 6 +/** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P3A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P3A_FORCE_TIEH_SEL_0_M (PMU_0P3A_FORCE_TIEH_SEL_0_V << PMU_0P3A_FORCE_TIEH_SEL_0_S) +#define PMU_0P3A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P3A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P3A_XPD_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P3A_XPD_0 (BIT(8)) +#define PMU_0P3A_XPD_0_M (PMU_0P3A_XPD_0_V << PMU_0P3A_XPD_0_S) +#define PMU_0P3A_XPD_0_V 0x00000001U +#define PMU_0P3A_XPD_0_S 8 +/** PMU_0P3A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_SEL_0 0x00000007U +#define PMU_0P3A_TIEH_SEL_0_M (PMU_0P3A_TIEH_SEL_0_V << PMU_0P3A_TIEH_SEL_0_S) +#define PMU_0P3A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P3A_TIEH_SEL_0_S 9 +/** PMU_0P3A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P3A_TIEH_POS_EN_0_M (PMU_0P3A_TIEH_POS_EN_0_V << PMU_0P3A_TIEH_POS_EN_0_S) +#define PMU_0P3A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P3A_TIEH_POS_EN_0_S 12 +/** PMU_0P3A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P3A_TIEH_NEG_EN_0_M (PMU_0P3A_TIEH_NEG_EN_0_V << PMU_0P3A_TIEH_NEG_EN_0_S) +#define PMU_0P3A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P3A_TIEH_NEG_EN_0_S 13 +/** PMU_0P3A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_0 (BIT(14)) +#define PMU_0P3A_TIEH_0_M (PMU_0P3A_TIEH_0_V << PMU_0P3A_TIEH_0_S) +#define PMU_0P3A_TIEH_0_V 0x00000001U +#define PMU_0P3A_TIEH_0_S 14 +/** PMU_0P3A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P3A_TARGET1_0 0x000000FFU +#define PMU_0P3A_TARGET1_0_M (PMU_0P3A_TARGET1_0_V << PMU_0P3A_TARGET1_0_S) +#define PMU_0P3A_TARGET1_0_V 0x000000FFU +#define PMU_0P3A_TARGET1_0_S 15 +/** PMU_0P3A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P3A_TARGET0_0 0x000000FFU +#define PMU_0P3A_TARGET0_0_M (PMU_0P3A_TARGET0_0_V << PMU_0P3A_TARGET0_0_S) +#define PMU_0P3A_TARGET0_0_V 0x000000FFU +#define PMU_0P3A_TARGET0_0_S 23 +/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P3A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1cc) +/** PMU_ANA_0P3A_MUL_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_MUL_0 0x00000007U +#define PMU_ANA_0P3A_MUL_0_M (PMU_ANA_0P3A_MUL_0_V << PMU_ANA_0P3A_MUL_0_S) +#define PMU_ANA_0P3A_MUL_0_V 0x00000007U +#define PMU_ANA_0P3A_MUL_0_S 23 +/** PMU_ANA_0P3A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P3A_EN_VDET_0_M (PMU_ANA_0P3A_EN_VDET_0_V << PMU_ANA_0P3A_EN_VDET_0_S) +#define PMU_ANA_0P3A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P3A_EN_VDET_0_S 26 +/** PMU_ANA_0P3A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P3A_EN_CUR_LIM_0_M (PMU_ANA_0P3A_EN_CUR_LIM_0_V << PMU_ANA_0P3A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P3A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P3A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P3A_DREF_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P3A_DREF_0 0x0000000FU +#define PMU_ANA_0P3A_DREF_0_M (PMU_ANA_0P3A_DREF_0_V << PMU_ANA_0P3A_DREF_0_S) +#define PMU_ANA_0P3A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P3A_DREF_0_S 28 + +/** PMU_EXT_LDO_P1_0P1A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0) +/** PMU_0P1A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P1A_CNT_CLR_1 (BIT(6)) +#define PMU_0P1A_CNT_CLR_1_M (PMU_0P1A_CNT_CLR_1_V << PMU_0P1A_CNT_CLR_1_S) +#define PMU_0P1A_CNT_CLR_1_V 0x00000001U +#define PMU_0P1A_CNT_CLR_1_S 6 +/** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P1A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P1A_FORCE_TIEH_SEL_1_M (PMU_0P1A_FORCE_TIEH_SEL_1_V << PMU_0P1A_FORCE_TIEH_SEL_1_S) +#define PMU_0P1A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P1A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P1A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P1A_XPD_1 (BIT(8)) +#define PMU_0P1A_XPD_1_M (PMU_0P1A_XPD_1_V << PMU_0P1A_XPD_1_S) +#define PMU_0P1A_XPD_1_V 0x00000001U +#define PMU_0P1A_XPD_1_S 8 +/** PMU_0P1A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_SEL_1 0x00000007U +#define PMU_0P1A_TIEH_SEL_1_M (PMU_0P1A_TIEH_SEL_1_V << PMU_0P1A_TIEH_SEL_1_S) +#define PMU_0P1A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P1A_TIEH_SEL_1_S 9 +/** PMU_0P1A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P1A_TIEH_POS_EN_1_M (PMU_0P1A_TIEH_POS_EN_1_V << PMU_0P1A_TIEH_POS_EN_1_S) +#define PMU_0P1A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P1A_TIEH_POS_EN_1_S 12 +/** PMU_0P1A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P1A_TIEH_NEG_EN_1_M (PMU_0P1A_TIEH_NEG_EN_1_V << PMU_0P1A_TIEH_NEG_EN_1_S) +#define PMU_0P1A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P1A_TIEH_NEG_EN_1_S 13 +/** PMU_0P1A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_1 (BIT(14)) +#define PMU_0P1A_TIEH_1_M (PMU_0P1A_TIEH_1_V << PMU_0P1A_TIEH_1_S) +#define PMU_0P1A_TIEH_1_V 0x00000001U +#define PMU_0P1A_TIEH_1_S 14 +/** PMU_0P1A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P1A_TARGET1_1 0x000000FFU +#define PMU_0P1A_TARGET1_1_M (PMU_0P1A_TARGET1_1_V << PMU_0P1A_TARGET1_1_S) +#define PMU_0P1A_TARGET1_1_V 0x000000FFU +#define PMU_0P1A_TARGET1_1_S 15 +/** PMU_0P1A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P1A_TARGET0_1 0x000000FFU +#define PMU_0P1A_TARGET0_1_M (PMU_0P1A_TARGET0_1_V << PMU_0P1A_TARGET0_1_S) +#define PMU_0P1A_TARGET0_1_V 0x000000FFU +#define PMU_0P1A_TARGET0_1_S 23 +/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P1A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1d4) +/** PMU_ANA_0P1A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_MUL_1 0x00000007U +#define PMU_ANA_0P1A_MUL_1_M (PMU_ANA_0P1A_MUL_1_V << PMU_ANA_0P1A_MUL_1_S) +#define PMU_ANA_0P1A_MUL_1_V 0x00000007U +#define PMU_ANA_0P1A_MUL_1_S 23 +/** PMU_ANA_0P1A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P1A_EN_VDET_1_M (PMU_ANA_0P1A_EN_VDET_1_V << PMU_ANA_0P1A_EN_VDET_1_S) +#define PMU_ANA_0P1A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P1A_EN_VDET_1_S 26 +/** PMU_ANA_0P1A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P1A_EN_CUR_LIM_1_M (PMU_ANA_0P1A_EN_CUR_LIM_1_V << PMU_ANA_0P1A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P1A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P1A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P1A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P1A_DREF_1 0x0000000FU +#define PMU_ANA_0P1A_DREF_1_M (PMU_ANA_0P1A_DREF_1_V << PMU_ANA_0P1A_DREF_1_S) +#define PMU_ANA_0P1A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P1A_DREF_1_S 28 + +/** PMU_EXT_LDO_P1_0P2A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8) +/** PMU_0P2A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P2A_CNT_CLR_1 (BIT(6)) +#define PMU_0P2A_CNT_CLR_1_M (PMU_0P2A_CNT_CLR_1_V << PMU_0P2A_CNT_CLR_1_S) +#define PMU_0P2A_CNT_CLR_1_V 0x00000001U +#define PMU_0P2A_CNT_CLR_1_S 6 +/** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P2A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P2A_FORCE_TIEH_SEL_1_M (PMU_0P2A_FORCE_TIEH_SEL_1_V << PMU_0P2A_FORCE_TIEH_SEL_1_S) +#define PMU_0P2A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P2A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P2A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P2A_XPD_1 (BIT(8)) +#define PMU_0P2A_XPD_1_M (PMU_0P2A_XPD_1_V << PMU_0P2A_XPD_1_S) +#define PMU_0P2A_XPD_1_V 0x00000001U +#define PMU_0P2A_XPD_1_S 8 +/** PMU_0P2A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_SEL_1 0x00000007U +#define PMU_0P2A_TIEH_SEL_1_M (PMU_0P2A_TIEH_SEL_1_V << PMU_0P2A_TIEH_SEL_1_S) +#define PMU_0P2A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P2A_TIEH_SEL_1_S 9 +/** PMU_0P2A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P2A_TIEH_POS_EN_1_M (PMU_0P2A_TIEH_POS_EN_1_V << PMU_0P2A_TIEH_POS_EN_1_S) +#define PMU_0P2A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P2A_TIEH_POS_EN_1_S 12 +/** PMU_0P2A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P2A_TIEH_NEG_EN_1_M (PMU_0P2A_TIEH_NEG_EN_1_V << PMU_0P2A_TIEH_NEG_EN_1_S) +#define PMU_0P2A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P2A_TIEH_NEG_EN_1_S 13 +/** PMU_0P2A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_1 (BIT(14)) +#define PMU_0P2A_TIEH_1_M (PMU_0P2A_TIEH_1_V << PMU_0P2A_TIEH_1_S) +#define PMU_0P2A_TIEH_1_V 0x00000001U +#define PMU_0P2A_TIEH_1_S 14 +/** PMU_0P2A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P2A_TARGET1_1 0x000000FFU +#define PMU_0P2A_TARGET1_1_M (PMU_0P2A_TARGET1_1_V << PMU_0P2A_TARGET1_1_S) +#define PMU_0P2A_TARGET1_1_V 0x000000FFU +#define PMU_0P2A_TARGET1_1_S 15 +/** PMU_0P2A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P2A_TARGET0_1 0x000000FFU +#define PMU_0P2A_TARGET0_1_M (PMU_0P2A_TARGET0_1_V << PMU_0P2A_TARGET0_1_S) +#define PMU_0P2A_TARGET0_1_V 0x000000FFU +#define PMU_0P2A_TARGET0_1_S 23 +/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P2A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1dc) +/** PMU_ANA_0P2A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_MUL_1 0x00000007U +#define PMU_ANA_0P2A_MUL_1_M (PMU_ANA_0P2A_MUL_1_V << PMU_ANA_0P2A_MUL_1_S) +#define PMU_ANA_0P2A_MUL_1_V 0x00000007U +#define PMU_ANA_0P2A_MUL_1_S 23 +/** PMU_ANA_0P2A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P2A_EN_VDET_1_M (PMU_ANA_0P2A_EN_VDET_1_V << PMU_ANA_0P2A_EN_VDET_1_S) +#define PMU_ANA_0P2A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P2A_EN_VDET_1_S 26 +/** PMU_ANA_0P2A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P2A_EN_CUR_LIM_1_M (PMU_ANA_0P2A_EN_CUR_LIM_1_V << PMU_ANA_0P2A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P2A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P2A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P2A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P2A_DREF_1 0x0000000FU +#define PMU_ANA_0P2A_DREF_1_M (PMU_ANA_0P2A_DREF_1_V << PMU_ANA_0P2A_DREF_1_S) +#define PMU_ANA_0P2A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P2A_DREF_1_S 28 + +/** PMU_EXT_LDO_P1_0P3A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0) +/** PMU_0P3A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P3A_CNT_CLR_1 (BIT(6)) +#define PMU_0P3A_CNT_CLR_1_M (PMU_0P3A_CNT_CLR_1_V << PMU_0P3A_CNT_CLR_1_S) +#define PMU_0P3A_CNT_CLR_1_V 0x00000001U +#define PMU_0P3A_CNT_CLR_1_S 6 +/** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P3A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P3A_FORCE_TIEH_SEL_1_M (PMU_0P3A_FORCE_TIEH_SEL_1_V << PMU_0P3A_FORCE_TIEH_SEL_1_S) +#define PMU_0P3A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P3A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P3A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P3A_XPD_1 (BIT(8)) +#define PMU_0P3A_XPD_1_M (PMU_0P3A_XPD_1_V << PMU_0P3A_XPD_1_S) +#define PMU_0P3A_XPD_1_V 0x00000001U +#define PMU_0P3A_XPD_1_S 8 +/** PMU_0P3A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_SEL_1 0x00000007U +#define PMU_0P3A_TIEH_SEL_1_M (PMU_0P3A_TIEH_SEL_1_V << PMU_0P3A_TIEH_SEL_1_S) +#define PMU_0P3A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P3A_TIEH_SEL_1_S 9 +/** PMU_0P3A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P3A_TIEH_POS_EN_1_M (PMU_0P3A_TIEH_POS_EN_1_V << PMU_0P3A_TIEH_POS_EN_1_S) +#define PMU_0P3A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P3A_TIEH_POS_EN_1_S 12 +/** PMU_0P3A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P3A_TIEH_NEG_EN_1_M (PMU_0P3A_TIEH_NEG_EN_1_V << PMU_0P3A_TIEH_NEG_EN_1_S) +#define PMU_0P3A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P3A_TIEH_NEG_EN_1_S 13 +/** PMU_0P3A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_1 (BIT(14)) +#define PMU_0P3A_TIEH_1_M (PMU_0P3A_TIEH_1_V << PMU_0P3A_TIEH_1_S) +#define PMU_0P3A_TIEH_1_V 0x00000001U +#define PMU_0P3A_TIEH_1_S 14 +/** PMU_0P3A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P3A_TARGET1_1 0x000000FFU +#define PMU_0P3A_TARGET1_1_M (PMU_0P3A_TARGET1_1_V << PMU_0P3A_TARGET1_1_S) +#define PMU_0P3A_TARGET1_1_V 0x000000FFU +#define PMU_0P3A_TARGET1_1_S 15 +/** PMU_0P3A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P3A_TARGET0_1 0x000000FFU +#define PMU_0P3A_TARGET0_1_M (PMU_0P3A_TARGET0_1_V << PMU_0P3A_TARGET0_1_S) +#define PMU_0P3A_TARGET0_1_V 0x000000FFU +#define PMU_0P3A_TARGET0_1_S 23 +/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P3A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1e4) +/** PMU_ANA_0P3A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_MUL_1 0x00000007U +#define PMU_ANA_0P3A_MUL_1_M (PMU_ANA_0P3A_MUL_1_V << PMU_ANA_0P3A_MUL_1_S) +#define PMU_ANA_0P3A_MUL_1_V 0x00000007U +#define PMU_ANA_0P3A_MUL_1_S 23 +/** PMU_ANA_0P3A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P3A_EN_VDET_1_M (PMU_ANA_0P3A_EN_VDET_1_V << PMU_ANA_0P3A_EN_VDET_1_S) +#define PMU_ANA_0P3A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P3A_EN_VDET_1_S 26 +/** PMU_ANA_0P3A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P3A_EN_CUR_LIM_1_M (PMU_ANA_0P3A_EN_CUR_LIM_1_V << PMU_ANA_0P3A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P3A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P3A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P3A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P3A_DREF_1 0x0000000FU +#define PMU_ANA_0P3A_DREF_1_M (PMU_ANA_0P3A_DREF_1_V << PMU_ANA_0P3A_DREF_1_S) +#define PMU_ANA_0P3A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P3A_DREF_1_S 28 + +/** PMU_EXT_WAKEUP_LV_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_LV_REG (DR_REG_PMU_BASE + 0x1e8) +/** PMU_EXT_WAKEUP_LV : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_LV 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_LV_M (PMU_EXT_WAKEUP_LV_V << PMU_EXT_WAKEUP_LV_S) +#define PMU_EXT_WAKEUP_LV_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_LV_S 0 + +/** PMU_EXT_WAKEUP_SEL_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_SEL_REG (DR_REG_PMU_BASE + 0x1ec) +/** PMU_EXT_WAKEUP_SEL : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_SEL 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_SEL_M (PMU_EXT_WAKEUP_SEL_V << PMU_EXT_WAKEUP_SEL_S) +#define PMU_EXT_WAKEUP_SEL_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_SEL_S 0 + +/** PMU_EXT_WAKEUP_ST_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_ST_REG (DR_REG_PMU_BASE + 0x1f0) +/** PMU_EXT_WAKEUP_STATUS : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_STATUS 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_STATUS_M (PMU_EXT_WAKEUP_STATUS_V << PMU_EXT_WAKEUP_STATUS_S) +#define PMU_EXT_WAKEUP_STATUS_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_STATUS_S 0 + +/** PMU_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f4) +/** PMU_EXT_WAKEUP_STATUS_CLR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_STATUS_CLR (BIT(30)) +#define PMU_EXT_WAKEUP_STATUS_CLR_M (PMU_EXT_WAKEUP_STATUS_CLR_V << PMU_EXT_WAKEUP_STATUS_CLR_S) +#define PMU_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define PMU_EXT_WAKEUP_STATUS_CLR_S 30 +/** PMU_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_FILTER (BIT(31)) +#define PMU_EXT_WAKEUP_FILTER_M (PMU_EXT_WAKEUP_FILTER_V << PMU_EXT_WAKEUP_FILTER_S) +#define PMU_EXT_WAKEUP_FILTER_V 0x00000001U +#define PMU_EXT_WAKEUP_FILTER_S 31 + +/** PMU_SDIO_WAKEUP_CNTL_REG register + * need_des + */ +#define PMU_SDIO_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f8) +/** PMU_SDIO_ACT_DNUM : R/W; bitpos: [9:0]; default: 1023; + * need_des + */ +#define PMU_SDIO_ACT_DNUM 0x000003FFU +#define PMU_SDIO_ACT_DNUM_M (PMU_SDIO_ACT_DNUM_V << PMU_SDIO_ACT_DNUM_S) +#define PMU_SDIO_ACT_DNUM_V 0x000003FFU +#define PMU_SDIO_ACT_DNUM_S 0 + +/** PMU_XTAL_SLP_REG register + * need_des + */ +#define PMU_XTAL_SLP_REG (DR_REG_PMU_BASE + 0x1fc) +/** PMU_XTAL_SLP_CNT_TARGET : R/W; bitpos: [31:16]; default: 15; + * need_des + */ +#define PMU_XTAL_SLP_CNT_TARGET 0x0000FFFFU +#define PMU_XTAL_SLP_CNT_TARGET_M (PMU_XTAL_SLP_CNT_TARGET_V << PMU_XTAL_SLP_CNT_TARGET_S) +#define PMU_XTAL_SLP_CNT_TARGET_V 0x0000FFFFU +#define PMU_XTAL_SLP_CNT_TARGET_S 16 + +/** PMU_CPU_SW_STALL_REG register + * need_des + */ +#define PMU_CPU_SW_STALL_REG (DR_REG_PMU_BASE + 0x200) +/** PMU_HPCORE1_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * need_des + */ +#define PMU_HPCORE1_SW_STALL_CODE 0x000000FFU +#define PMU_HPCORE1_SW_STALL_CODE_M (PMU_HPCORE1_SW_STALL_CODE_V << PMU_HPCORE1_SW_STALL_CODE_S) +#define PMU_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define PMU_HPCORE1_SW_STALL_CODE_S 16 +/** PMU_HPCORE0_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * need_des + */ +#define PMU_HPCORE0_SW_STALL_CODE 0x000000FFU +#define PMU_HPCORE0_SW_STALL_CODE_M (PMU_HPCORE0_SW_STALL_CODE_V << PMU_HPCORE0_SW_STALL_CODE_S) +#define PMU_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define PMU_HPCORE0_SW_STALL_CODE_S 24 + +/** PMU_DCM_CTRL_REG register + * need_des + */ +#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x204) +/** PMU_DCDC_ON_REQ : WT; bitpos: [0]; default: 0; + * SW trigger dcdc on + */ +#define PMU_DCDC_ON_REQ (BIT(0)) +#define PMU_DCDC_ON_REQ_M (PMU_DCDC_ON_REQ_V << PMU_DCDC_ON_REQ_S) +#define PMU_DCDC_ON_REQ_V 0x00000001U +#define PMU_DCDC_ON_REQ_S 0 +/** PMU_DCDC_OFF_REQ : WT; bitpos: [1]; default: 0; + * SW trigger dcdc off + */ +#define PMU_DCDC_OFF_REQ (BIT(1)) +#define PMU_DCDC_OFF_REQ_M (PMU_DCDC_OFF_REQ_V << PMU_DCDC_OFF_REQ_S) +#define PMU_DCDC_OFF_REQ_V 0x00000001U +#define PMU_DCDC_OFF_REQ_S 1 +/** PMU_DCDC_LIGHTSLP_REQ : WT; bitpos: [2]; default: 0; + * SW trigger dcdc enter lightsleep + */ +#define PMU_DCDC_LIGHTSLP_REQ (BIT(2)) +#define PMU_DCDC_LIGHTSLP_REQ_M (PMU_DCDC_LIGHTSLP_REQ_V << PMU_DCDC_LIGHTSLP_REQ_S) +#define PMU_DCDC_LIGHTSLP_REQ_V 0x00000001U +#define PMU_DCDC_LIGHTSLP_REQ_S 2 +/** PMU_DCDC_DEEPSLP_REQ : WT; bitpos: [3]; default: 0; + * SW trigger dcdc enter deepsleep + */ +#define PMU_DCDC_DEEPSLP_REQ (BIT(3)) +#define PMU_DCDC_DEEPSLP_REQ_M (PMU_DCDC_DEEPSLP_REQ_V << PMU_DCDC_DEEPSLP_REQ_S) +#define PMU_DCDC_DEEPSLP_REQ_V 0x00000001U +#define PMU_DCDC_DEEPSLP_REQ_S 3 +/** PMU_DCDC_DONE_FORCE : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_DCDC_DONE_FORCE (BIT(7)) +#define PMU_DCDC_DONE_FORCE_M (PMU_DCDC_DONE_FORCE_V << PMU_DCDC_DONE_FORCE_S) +#define PMU_DCDC_DONE_FORCE_V 0x00000001U +#define PMU_DCDC_DONE_FORCE_S 7 +/** PMU_DCDC_ON_FORCE_PU : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_DCDC_ON_FORCE_PU (BIT(8)) +#define PMU_DCDC_ON_FORCE_PU_M (PMU_DCDC_ON_FORCE_PU_V << PMU_DCDC_ON_FORCE_PU_S) +#define PMU_DCDC_ON_FORCE_PU_V 0x00000001U +#define PMU_DCDC_ON_FORCE_PU_S 8 +/** PMU_DCDC_ON_FORCE_PD : R/W; bitpos: [9]; default: 0; + * need_des + */ +#define PMU_DCDC_ON_FORCE_PD (BIT(9)) +#define PMU_DCDC_ON_FORCE_PD_M (PMU_DCDC_ON_FORCE_PD_V << PMU_DCDC_ON_FORCE_PD_S) +#define PMU_DCDC_ON_FORCE_PD_V 0x00000001U +#define PMU_DCDC_ON_FORCE_PD_S 9 +/** PMU_DCDC_FB_RES_FORCE_PU : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_DCDC_FB_RES_FORCE_PU (BIT(10)) +#define PMU_DCDC_FB_RES_FORCE_PU_M (PMU_DCDC_FB_RES_FORCE_PU_V << PMU_DCDC_FB_RES_FORCE_PU_S) +#define PMU_DCDC_FB_RES_FORCE_PU_V 0x00000001U +#define PMU_DCDC_FB_RES_FORCE_PU_S 10 +/** PMU_DCDC_FB_RES_FORCE_PD : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_DCDC_FB_RES_FORCE_PD (BIT(11)) +#define PMU_DCDC_FB_RES_FORCE_PD_M (PMU_DCDC_FB_RES_FORCE_PD_V << PMU_DCDC_FB_RES_FORCE_PD_S) +#define PMU_DCDC_FB_RES_FORCE_PD_V 0x00000001U +#define PMU_DCDC_FB_RES_FORCE_PD_S 11 +/** PMU_DCDC_LS_FORCE_PU : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_DCDC_LS_FORCE_PU (BIT(12)) +#define PMU_DCDC_LS_FORCE_PU_M (PMU_DCDC_LS_FORCE_PU_V << PMU_DCDC_LS_FORCE_PU_S) +#define PMU_DCDC_LS_FORCE_PU_V 0x00000001U +#define PMU_DCDC_LS_FORCE_PU_S 12 +/** PMU_DCDC_LS_FORCE_PD : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_DCDC_LS_FORCE_PD (BIT(13)) +#define PMU_DCDC_LS_FORCE_PD_M (PMU_DCDC_LS_FORCE_PD_V << PMU_DCDC_LS_FORCE_PD_S) +#define PMU_DCDC_LS_FORCE_PD_V 0x00000001U +#define PMU_DCDC_LS_FORCE_PD_S 13 +/** PMU_DCDC_DS_FORCE_PU : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_DCDC_DS_FORCE_PU (BIT(14)) +#define PMU_DCDC_DS_FORCE_PU_M (PMU_DCDC_DS_FORCE_PU_V << PMU_DCDC_DS_FORCE_PU_S) +#define PMU_DCDC_DS_FORCE_PU_V 0x00000001U +#define PMU_DCDC_DS_FORCE_PU_S 14 +/** PMU_DCDC_DS_FORCE_PD : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DCDC_DS_FORCE_PD (BIT(15)) +#define PMU_DCDC_DS_FORCE_PD_M (PMU_DCDC_DS_FORCE_PD_V << PMU_DCDC_DS_FORCE_PD_S) +#define PMU_DCDC_DS_FORCE_PD_V 0x00000001U +#define PMU_DCDC_DS_FORCE_PD_S 15 +/** PMU_DCM_CUR_ST : RO; bitpos: [23:16]; default: 1; + * need_des + */ +#define PMU_DCM_CUR_ST 0x000000FFU +#define PMU_DCM_CUR_ST_M (PMU_DCM_CUR_ST_V << PMU_DCM_CUR_ST_S) +#define PMU_DCM_CUR_ST_V 0x000000FFU +#define PMU_DCM_CUR_ST_S 16 +/** PMU_DCDC_EN_AMUX_TEST : R/W; bitpos: [29]; default: 0; + * Enable analog mux to pull PAD TEST_DCDC voltage signal + */ +#define PMU_DCDC_EN_AMUX_TEST (BIT(29)) +#define PMU_DCDC_EN_AMUX_TEST_M (PMU_DCDC_EN_AMUX_TEST_V << PMU_DCDC_EN_AMUX_TEST_S) +#define PMU_DCDC_EN_AMUX_TEST_V 0x00000001U +#define PMU_DCDC_EN_AMUX_TEST_S 29 + +/** PMU_DCM_WAIT_DELAY_REG register + * need_des + */ +#define PMU_DCM_WAIT_DELAY_REG (DR_REG_PMU_BASE + 0x208) +/** PMU_DCDC_PRE_DELAY : R/W; bitpos: [7:0]; default: 5; + * DCDC pre-on/post off delay + */ +#define PMU_DCDC_PRE_DELAY 0x000000FFU +#define PMU_DCDC_PRE_DELAY_M (PMU_DCDC_PRE_DELAY_V << PMU_DCDC_PRE_DELAY_S) +#define PMU_DCDC_PRE_DELAY_V 0x000000FFU +#define PMU_DCDC_PRE_DELAY_S 0 +/** PMU_DCDC_RES_OFF_DELAY : R/W; bitpos: [15:8]; default: 2; + * DCDC fb res off delay + */ +#define PMU_DCDC_RES_OFF_DELAY 0x000000FFU +#define PMU_DCDC_RES_OFF_DELAY_M (PMU_DCDC_RES_OFF_DELAY_V << PMU_DCDC_RES_OFF_DELAY_S) +#define PMU_DCDC_RES_OFF_DELAY_V 0x000000FFU +#define PMU_DCDC_RES_OFF_DELAY_S 8 +/** PMU_DCDC_STABLE_DELAY : R/W; bitpos: [25:16]; default: 75; + * DCDC stable delay + */ +#define PMU_DCDC_STABLE_DELAY 0x000003FFU +#define PMU_DCDC_STABLE_DELAY_M (PMU_DCDC_STABLE_DELAY_V << PMU_DCDC_STABLE_DELAY_S) +#define PMU_DCDC_STABLE_DELAY_V 0x000003FFU +#define PMU_DCDC_STABLE_DELAY_S 16 + +/** PMU_VDDBAT_CFG_REG register + * need_des + */ +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x20c) +/** PMU_ANA_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; + * need_des + */ +#define PMU_ANA_VDDBAT_MODE 0x00000003U +#define PMU_ANA_VDDBAT_MODE_M (PMU_ANA_VDDBAT_MODE_V << PMU_ANA_VDDBAT_MODE_S) +#define PMU_ANA_VDDBAT_MODE_V 0x00000003U +#define PMU_ANA_VDDBAT_MODE_S 0 +/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDDBAT_SW_UPDATE (BIT(31)) +#define PMU_VDDBAT_SW_UPDATE_M (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S) +#define PMU_VDDBAT_SW_UPDATE_V 0x00000001U +#define PMU_VDDBAT_SW_UPDATE_S 31 + +/** PMU_TOUCH_PWR_CNTL_REG register + * need_des + */ +#define PMU_TOUCH_PWR_CNTL_REG (DR_REG_PMU_BASE + 0x210) +/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [13:5]; default: 10; + * need_des + */ +#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) +#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_S 5 +/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 100; + * need_des + */ +#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) +#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_S 14 +/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TOUCH_FORCE_DONE (BIT(30)) +#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) +#define PMU_TOUCH_FORCE_DONE_V 0x00000001U +#define PMU_TOUCH_FORCE_DONE_S 30 +/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(31)) +#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) +#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U +#define PMU_TOUCH_SLEEP_TIMER_EN_S 31 + +/** PMU_RDN_ECO_REG register + * need_des + */ +#define PMU_RDN_ECO_REG (DR_REG_PMU_BASE + 0x214) +/** PMU_PMU_RDN_ECO_RESULT : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_PMU_RDN_ECO_RESULT (BIT(0)) +#define PMU_PMU_RDN_ECO_RESULT_M (PMU_PMU_RDN_ECO_RESULT_V << PMU_PMU_RDN_ECO_RESULT_S) +#define PMU_PMU_RDN_ECO_RESULT_V 0x00000001U +#define PMU_PMU_RDN_ECO_RESULT_S 0 +/** PMU_PMU_RDN_ECO_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_PMU_RDN_ECO_EN (BIT(31)) +#define PMU_PMU_RDN_ECO_EN_M (PMU_PMU_RDN_ECO_EN_V << PMU_PMU_RDN_ECO_EN_S) +#define PMU_PMU_RDN_ECO_EN_V 0x00000001U +#define PMU_PMU_RDN_ECO_EN_S 31 + +/** PMU_POWER_PD_HP_CPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HP_CPU_CNTL_REG (DR_REG_PMU_BASE + 0x218) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 + +/** PMU_POWER_PD_HP_CPU_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_HP_CPU_MASK_REG (DR_REG_PMU_BASE + 0x21c) +/** PMU_XPD_HP_CPU_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_HP_CPU_MASK 0x0000001FU +#define PMU_XPD_HP_CPU_MASK_M (PMU_XPD_HP_CPU_MASK_V << PMU_XPD_HP_CPU_MASK_S) +#define PMU_XPD_HP_CPU_MASK_V 0x0000001FU +#define PMU_XPD_HP_CPU_MASK_S 0 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 27 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38801456; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_struct.h new file mode 100644 index 0000000000..b800521b0d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pmu_eco5_struct.h @@ -0,0 +1,3973 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_dcdc_switch_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:1; + uint32_t reserved_24:5; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cnnt_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** hp_active_hp_power_det_bypass : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t hp_active_hp_power_det_bypass:1; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_i2c_iso_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_pll_i2c:4; + /** hp_active_xpd_pll : R/W; bitpos: [30:27]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_pll:4; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_active_dcm_vset : R/W; bitpos: [22:18]; default: 20; + * need_des + */ + uint32_t hp_active_dcm_vset:5; + /** hp_active_dcm_mode : R/W; bitpos: [24:23]; default: 0; + * need_des + */ + uint32_t hp_active_dcm_mode:2; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_active_dbg_atten:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:6; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_dcdc_switch_pd_en:1; + /** hp_modem_hp_mem_dslp : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : WT; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_modem_pd_hp_cpu_pd_en : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_cnnt_pd_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cnnt_pd_en:1; + /** hp_modem_pd_top_pd_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : WT; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** hp_modem_hp_power_det_bypass : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_power_det_bypass:1; + /** hp_modem_uart_wakeup_en : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_i2c_iso_en : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_pll_i2c:4; + /** hp_modem_xpd_pll : WT; bitpos: [30:27]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_pll:4; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_modem_dcm_vset : WT; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t hp_modem_dcm_vset:5; + /** hp_modem_dcm_mode : WT; bitpos: [24:23]; default: 0; + * need_des + */ + uint32_t hp_modem_dcm_mode:2; + /** hp_modem_xpd_bias : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + /** hp_modem_dbg_atten : WT; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_modem_dbg_atten:4; + /** hp_modem_pd_cur : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : WT; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : WT; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : WT; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : WT; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : WT; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : WT; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_modem_hp_regulator_slp_mem_xpd : WT; bitpos: [16]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : WT; bitpos: [17]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : WT; bitpos: [18]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : WT; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : WT; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : WT; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : WT; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcdc_switch_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:1; + uint32_t reserved_24:5; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cnnt_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_power_det_bypass:1; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_pll_i2c:4; + /** hp_sleep_xpd_pll : R/W; bitpos: [30:27]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_pll:4; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_sleep_dcm_vset : R/W; bitpos: [22:18]; default: 20; + * need_des + */ + uint32_t hp_sleep_dcm_vset:5; + /** hp_sleep_dcm_mode : R/W; bitpos: [24:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcm_mode:2; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dbg_atten:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:6; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:6; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_slp_sel:1; + /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_bod_source_sel:1; + /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_vddbat_mode:2; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_lppll:1; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:6; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** lp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_pad_slp_sel:1; + /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_bod_source_sel:1; + /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_vddbat_mode:2; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_lppll:1; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_dbg_atten:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_cali_xtal_icg : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_cali_xtal_icg:1; + /** tie_low_global_pll_icg : WT; bitpos: [4:1]; default: 0; + * need_des + */ + uint32_t tie_low_global_pll_icg:4; + /** tie_low_global_xtal_icg : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_pll_i2c : WT; bitpos: [10:7]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_pll_i2c:4; + /** tie_low_xpd_pll : WT; bitpos: [14:11]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_pll:4; + /** tie_low_xpd_xtal : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + /** tie_high_cali_xtal_icg : R/W; bitpos: [16]; default: 0; + * need_des + */ + uint32_t tie_high_cali_xtal_icg:1; + /** tie_high_global_pll_icg : WT; bitpos: [20:17]; default: 0; + * need_des + */ + uint32_t tie_high_global_pll_icg:4; + /** tie_high_global_xtal_icg : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_pll_i2c:4; + /** tie_high_xpd_pll : WT; bitpos: [30:27]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_pll:4; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + /** pad_slp_sel : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t pad_slp_sel:1; + /** lp_pad_hold_all : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_pad_hold_all:1; + /** hp_pad_hold_all : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t hp_pad_hold_all:1; + uint32_t reserved_3:23; + /** tie_high_pad_slp_sel : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_pad_slp_sel:1; + /** tie_low_pad_slp_sel : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_low_pad_slp_sel:1; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_lp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_lp_powerdown_timer:9; + /** dg_lp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_lp_powerup_timer:9; + /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_cnnt_cntl register + * need_des + */ +typedef union { + struct { + /** force_cnnt_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_cnnt_reset:1; + /** force_cnnt_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_cnnt_iso:1; + /** force_cnnt_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_cnnt_pu:1; + /** force_cnnt_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_cnnt_no_reset:1; + /** force_cnnt_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_cnnt_no_iso:1; + /** force_cnnt_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_cnnt_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_cnnt_cntl_reg_t; + +/** Type of power_pd_hpmem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_reset:1; + /** force_hp_mem_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:1; + /** force_hp_mem_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_mem_pu:1; + /** force_hp_mem_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_mem_no_reset:1; + /** force_hp_mem_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_mem_no_iso:1; + /** force_hp_mem_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_hpmem_cntl_reg_t; + +/** Type of power_pd_top_mask register + * need_des + */ +typedef union { + struct { + /** xpd_top_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t xpd_top_mask:5; + uint32_t reserved_5:22; + /** pd_top_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_mask_reg_t; + +/** Type of power_pd_cnnt_mask register + * need_des + */ +typedef union { + struct { + /** xpd_cnnt_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t xpd_cnnt_mask:5; + uint32_t reserved_5:22; + /** pd_cnnt_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_cnnt_mask:5; + }; + uint32_t val; +} pmu_power_pd_cnnt_mask_reg_t; + +/** Type of power_pd_hpmem_mask register + * need_des + */ +typedef union { + struct { + /** xpd_hp_mem_mask : R/W; bitpos: [5:0]; default: 0; + * need_des + */ + uint32_t xpd_hp_mem_mask:6; + uint32_t reserved_6:20; + /** pd_hp_mem_mask : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t pd_hp_mem_mask:6; + }; + uint32_t val; +} pmu_power_pd_hpmem_mask_reg_t; + +/** Type of power_dcdc_switch register + * need_des + */ +typedef union { + struct { + /** force_dcdc_switch_pu : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t force_dcdc_switch_pu:1; + /** force_dcdc_switch_pd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_dcdc_switch_pd:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_dcdc_switch_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_lpperi_mask register + * need_des + */ +typedef union { + struct { + /** xpd_lp_peri_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t xpd_lp_peri_mask:5; + uint32_t reserved_5:22; + /** pd_lp_peri_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_lp_peri_mask:5; + }; + uint32_t val; +} pmu_power_pd_lpperi_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** pmu_wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t pmu_wait_xtl_stable:16; + /** pmu_wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t pmu_wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:2; + /** lp_ana_wait_target_expand : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t lp_ana_wait_target_expand:2; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_cntl8 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_lite_wakeup_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_lite_wakeup_ena:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl8_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t reject_cause:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of slp_wakeup_status2 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_lite_wakeup_cause : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_lite_wakeup_cause:1; + }; + uint32_t val; +} pmu_slp_wakeup_status2_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** mspi_phy_xpd : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t mspi_phy_xpd:1; + /** sdio_pll_xpd : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t sdio_pll_xpd:1; + /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t perif_i2c_rstb:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_txrf_i2c:1; + /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_pbus:1; + /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_ckgen_i2c:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** pmu_0p1a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_raw:1; + /** pmu_0p1a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_raw:1; + /** pmu_0p1a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_raw:1; + /** pmu_0p1a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_raw:1; + /** pmu_0p2a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_raw:1; + /** pmu_0p2a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_raw:1; + /** pmu_0p2a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_raw:1; + /** pmu_0p2a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_raw:1; + /** pmu_0p3a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_raw:1; + /** pmu_0p3a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_raw:1; + /** pmu_0p3a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_raw:1; + /** pmu_0p3a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_raw:1; + uint32_t reserved_26:1; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** pmu_0p1a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_st:1; + /** pmu_0p1a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_st:1; + /** pmu_0p1a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_st:1; + /** pmu_0p1a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_st:1; + /** pmu_0p2a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_st:1; + /** pmu_0p2a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_st:1; + /** pmu_0p2a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_st:1; + /** pmu_0p2a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_st:1; + /** pmu_0p3a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_st:1; + /** pmu_0p3a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_st:1; + /** pmu_0p3a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_st:1; + /** pmu_0p3a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_st:1; + uint32_t reserved_26:1; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** pmu_0p1a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_ena:1; + /** pmu_0p1a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_ena:1; + /** pmu_0p1a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_ena:1; + /** pmu_0p1a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_ena:1; + /** pmu_0p2a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_ena:1; + /** pmu_0p2a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_ena:1; + /** pmu_0p2a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_ena:1; + /** pmu_0p2a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_ena:1; + /** pmu_0p3a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_ena:1; + /** pmu_0p3a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_ena:1; + /** pmu_0p3a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_ena:1; + /** pmu_0p3a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_ena:1; + uint32_t reserved_26:1; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** pmu_0p1a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_clr:1; + /** pmu_0p1a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_clr:1; + /** pmu_0p1a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_clr:1; + /** pmu_0p1a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_clr:1; + /** pmu_0p2a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_clr:1; + /** pmu_0p2a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_clr:1; + /** pmu_0p2a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_clr:1; + /** pmu_0p2a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_clr:1; + /** pmu_0p3a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_clr:1; + /** pmu_0p3a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_clr:1; + /** pmu_0p3a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_clr:1; + /** pmu_0p3a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_clr:1; + uint32_t reserved_26:1; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** lp_cpu_sleep_reject_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_reject_int_raw:1; + /** pmu_0p1a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_raw:1; + /** pmu_0p1a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_raw:1; + /** pmu_0p1a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_raw:1; + /** pmu_0p1a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_raw:1; + /** pmu_0p2a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_raw:1; + /** pmu_0p2a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_raw:1; + /** pmu_0p2a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_raw:1; + /** pmu_0p2a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_raw:1; + /** pmu_0p3a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_raw:1; + /** pmu_0p3a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_raw:1; + /** pmu_0p3a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_raw:1; + /** pmu_0p3a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_raw:1; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** lp_cpu_sleep_reject_int_st : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_reject_int_st:1; + /** pmu_0p1a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_st:1; + /** pmu_0p1a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_st:1; + /** pmu_0p1a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_st:1; + /** pmu_0p1a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_st:1; + /** pmu_0p2a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_st:1; + /** pmu_0p2a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_st:1; + /** pmu_0p2a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_st:1; + /** pmu_0p2a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_st:1; + /** pmu_0p3a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_st:1; + /** pmu_0p3a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_st:1; + /** pmu_0p3a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_st:1; + /** pmu_0p3a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_st:1; + /** lp_cpu_wakeup_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** lp_cpu_sleep_reject_int_ena : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_reject_int_ena:1; + /** pmu_0p1a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_ena:1; + /** pmu_0p1a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_ena:1; + /** pmu_0p1a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_ena:1; + /** pmu_0p1a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_ena:1; + /** pmu_0p2a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_ena:1; + /** pmu_0p2a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_ena:1; + /** pmu_0p2a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_ena:1; + /** pmu_0p2a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_ena:1; + /** pmu_0p3a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_ena:1; + /** pmu_0p3a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_ena:1; + /** pmu_0p3a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_ena:1; + /** pmu_0p3a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_ena:1; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** lp_cpu_sleep_reject_lp_int_clr : WT; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_reject_lp_int_clr:1; + /** pmu_0p1a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_clr:1; + /** pmu_0p1a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_clr:1; + /** pmu_0p1a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_clr:1; + /** pmu_0p1a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_clr:1; + /** pmu_0p2a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_clr:1; + /** pmu_0p2a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_clr:1; + /** pmu_0p2a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_clr:1; + /** pmu_0p2a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_clr:1; + /** pmu_0p3a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_clr:1; + /** pmu_0p3a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_clr:1; + /** pmu_0p3a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ + uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_clr:1; + /** pmu_0p3a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ + uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_clr:1; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of lp_cpu_pwr2 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr2_reg_t; + +/** Type of lp_cpu_pwr3 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_cause : RO; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_cause:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr3_reg_t; + +/** Type of lp_cpu_pwr4 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_reject_en : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_reject_en:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr4_reg_t; + +/** Type of lp_cpu_pwr5 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_reject_cause : RO; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_reject_cause:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr5_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + /** enable_cali_pmu_cntl : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t enable_cali_pmu_cntl:1; + uint32_t reserved_1:10; + /** pmu_main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t pmu_main_last_st_state:7; + /** pmu_main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t pmu_main_tar_st_state:7; + /** pmu_main_cur_st_state : RO; bitpos: [31:25]; default: 1; + * need_des + */ + uint32_t pmu_main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** pmu_backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t pmu_backup_st_state:5; + /** pmu_lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t pmu_lp_pwr_st_state:5; + /** pmu_hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t pmu_hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of ext_ldo_p0_0p1a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p1a_cnt_clr_0 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_cnt_clr_0:1; + /** pmu_0p1a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_force_tieh_sel_0:1; + /** pmu_0p1a_xpd_0 : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t pmu_0p1a_xpd_0:1; + /** pmu_0p1a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_sel_0:3; + /** pmu_0p1a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_pos_en_0:1; + /** pmu_0p1a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_neg_en_0:1; + /** pmu_0p1a_tieh_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_0:1; + /** pmu_0p1a_target1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p1a_target1_0:8; + /** pmu_0p1a_target0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p1a_target0_0:8; + /** pmu_0p1a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_0:1; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p1a_reg_t; + +/** Type of ext_ldo_p0_0p1a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p1a_mul_0 : R/W; bitpos: [25:23]; default: 2; + * need_des + */ + uint32_t ana_0p1a_mul_0:3; + /** ana_0p1a_en_vdet_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p1a_en_vdet_0:1; + /** ana_0p1a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p1a_en_cur_lim_0:1; + /** ana_0p1a_dref_0 : R/W; bitpos: [31:28]; default: 11; + * need_des + */ + uint32_t ana_0p1a_dref_0:4; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p1a_ana_reg_t; + +/** Type of ext_ldo_p0_0p2a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p2a_cnt_clr_0 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_cnt_clr_0:1; + /** 0p2a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_force_tieh_sel_0:1; + /** pmu_0p2a_xpd_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_xpd_0:1; + /** pmu_0p2a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_sel_0:3; + /** pmu_0p2a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_pos_en_0:1; + /** pmu_0p2a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_neg_en_0:1; + /** pmu_0p2a_tieh_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_0:1; + /** pmu_0p2a_target1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p2a_target1_0:8; + /** pmu_0p2a_target0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p2a_target0_0:8; + /** pmu_0p2a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_0:1; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p2a_reg_t; + +/** Type of ext_ldo_p0_0p2a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p2a_mul_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t ana_0p2a_mul_0:3; + /** ana_0p2a_en_vdet_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p2a_en_vdet_0:1; + /** ana_0p2a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p2a_en_cur_lim_0:1; + /** ana_0p2a_dref_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ + uint32_t ana_0p2a_dref_0:4; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p2a_ana_reg_t; + +/** Type of ext_ldo_p0_0p3a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p3a_cnt_clr_0 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_cnt_clr_0:1; + /** pmu_0p3a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_force_tieh_sel_0:1; + /** pmu_0p3a_xpd_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_xpd_0:1; + /** pmu_0p3a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_sel_0:3; + /** pmu_0p3a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_pos_en_0:1; + /** pmu_0p3a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_neg_en_0:1; + /** pmu_0p3a_tieh_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_0:1; + /** pmu_0p3a_target1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p3a_target1_0:8; + /** pmu_0p3a_target0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p3a_target0_0:8; + /** pmu_0p3a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_0:1; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p3a_reg_t; + +/** Type of ext_ldo_p0_0p3a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p3a_mul_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t ana_0p3a_mul_0:3; + /** ana_0p3a_en_vdet_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p3a_en_vdet_0:1; + /** ana_0p3a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p3a_en_cur_lim_0:1; + /** ana_0p3a_dref_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ + uint32_t ana_0p3a_dref_0:4; + }; + uint32_t val; +} pmu_ext_ldo_p0_0p3a_ana_reg_t; + +/** Type of ext_ldo_p1_0p1a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p1a_cnt_clr_1 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_cnt_clr_1:1; + /** pmu_0p1a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_force_tieh_sel_1:1; + /** pmu_0p1a_xpd_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_xpd_1:1; + /** pmu_0p1a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_sel_1:3; + /** pmu_0p1a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_pos_en_1:1; + /** pmu_0p1a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_neg_en_1:1; + /** pmu_0p1a_tieh_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_tieh_1:1; + /** pmu_0p1a_target1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p1a_target1_1:8; + /** pmu_0p1a_target0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p1a_target0_1:8; + /** pmu_0p1a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_1:1; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p1a_reg_t; + +/** Type of ext_ldo_p1_0p1a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p1a_mul_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t ana_0p1a_mul_1:3; + /** ana_0p1a_en_vdet_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p1a_en_vdet_1:1; + /** ana_0p1a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p1a_en_cur_lim_1:1; + /** ana_0p1a_dref_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ + uint32_t ana_0p1a_dref_1:4; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p1a_ana_reg_t; + +/** Type of ext_ldo_p1_0p2a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p2a_cnt_clr_1 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_cnt_clr_1:1; + /** pmu_0p2a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_force_tieh_sel_1:1; + /** pmu_0p2a_xpd_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_xpd_1:1; + /** pmu_0p2a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_sel_1:3; + /** pmu_0p2a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_pos_en_1:1; + /** pmu_0p2a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_neg_en_1:1; + /** pmu_0p2a_tieh_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_tieh_1:1; + /** pmu_0p2a_target1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p2a_target1_1:8; + /** pmu_0p2a_target0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p2a_target0_1:8; + /** pmu_0p2a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_1:1; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p2a_reg_t; + +/** Type of ext_ldo_p1_0p2a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p2a_mul_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t ana_0p2a_mul_1:3; + /** ana_0p2a_en_vdet_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p2a_en_vdet_1:1; + /** ana_0p2a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p2a_en_cur_lim_1:1; + /** ana_0p2a_dref_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ + uint32_t ana_0p2a_dref_1:4; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p2a_ana_reg_t; + +/** Type of ext_ldo_p1_0p3a register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** pmu_0p3a_cnt_clr_1 : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_cnt_clr_1:1; + /** pmu_0p3a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_force_tieh_sel_1:1; + /** pmu_0p3a_xpd_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_xpd_1:1; + /** pmu_0p3a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_sel_1:3; + /** pmu_0p3a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_pos_en_1:1; + /** pmu_0p3a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_neg_en_1:1; + /** pmu_0p3a_tieh_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_tieh_1:1; + /** pmu_0p3a_target1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ + uint32_t pmu_0p3a_target1_1:8; + /** pmu_0p3a_target0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ + uint32_t pmu_0p3a_target0_1:8; + /** pmu_0p3a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_1:1; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p3a_reg_t; + +/** Type of ext_ldo_p1_0p3a_ana register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ana_0p3a_mul_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t ana_0p3a_mul_1:3; + /** ana_0p3a_en_vdet_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_0p3a_en_vdet_1:1; + /** ana_0p3a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_0p3a_en_cur_lim_1:1; + /** ana_0p3a_dref_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ + uint32_t ana_0p3a_dref_1:4; + }; + uint32_t val; +} pmu_ext_ldo_p1_0p3a_ana_reg_t; + +/** Type of ext_wakeup_lv register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_lv : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:32; + }; + uint32_t val; +} pmu_ext_wakeup_lv_reg_t; + +/** Type of ext_wakeup_sel register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_sel : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:32; + }; + uint32_t val; +} pmu_ext_wakeup_sel_reg_t; + +/** Type of ext_wakeup_st register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:32; + }; + uint32_t val; +} pmu_ext_wakeup_st_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** ext_wakeup_status_clr : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} pmu_ext_wakeup_cntl_reg_t; + +/** Type of sdio_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** sdio_act_dnum : R/W; bitpos: [9:0]; default: 1023; + * need_des + */ + uint32_t sdio_act_dnum:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} pmu_sdio_wakeup_cntl_reg_t; + +/** Type of cpu_sw_stall register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hpcore1_sw_stall_code : R/W; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t hpcore1_sw_stall_code:8; + /** hpcore0_sw_stall_code : R/W; bitpos: [31:24]; default: 0; + * need_des + */ + uint32_t hpcore0_sw_stall_code:8; + }; + uint32_t val; +} pmu_cpu_sw_stall_reg_t; + +/** Type of dcm_ctrl register + * need_des + */ +typedef union { + struct { + /** dcdc_on_req : WT; bitpos: [0]; default: 0; + * SW trigger dcdc on + */ + uint32_t dcdc_on_req:1; + /** dcdc_off_req : WT; bitpos: [1]; default: 0; + * SW trigger dcdc off + */ + uint32_t dcdc_off_req:1; + /** dcdc_lightslp_req : WT; bitpos: [2]; default: 0; + * SW trigger dcdc enter lightsleep + */ + uint32_t dcdc_lightslp_req:1; + /** dcdc_deepslp_req : WT; bitpos: [3]; default: 0; + * SW trigger dcdc enter deepsleep + */ + uint32_t dcdc_deepslp_req:1; + uint32_t reserved_4:3; + /** dcdc_done_force : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t dcdc_done_force:1; + /** dcdc_on_force_pu : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t dcdc_on_force_pu:1; + /** dcdc_on_force_pd : R/W; bitpos: [9]; default: 0; + * need_des + */ + uint32_t dcdc_on_force_pd:1; + /** dcdc_fb_res_force_pu : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t dcdc_fb_res_force_pu:1; + /** dcdc_fb_res_force_pd : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t dcdc_fb_res_force_pd:1; + /** dcdc_ls_force_pu : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t dcdc_ls_force_pu:1; + /** dcdc_ls_force_pd : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t dcdc_ls_force_pd:1; + /** dcdc_ds_force_pu : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t dcdc_ds_force_pu:1; + /** dcdc_ds_force_pd : R/W; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dcdc_ds_force_pd:1; + /** dcm_cur_st : RO; bitpos: [23:16]; default: 1; + * need_des + */ + uint32_t dcm_cur_st:8; + uint32_t reserved_24:5; + /** dcdc_en_amux_test : R/W; bitpos: [29]; default: 0; + * Enable analog mux to pull PAD TEST_DCDC voltage signal + */ + uint32_t dcdc_en_amux_test:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +/** Type of dcm_wait_delay register + * need_des + */ +typedef union { + struct { + /** dcdc_pre_delay : R/W; bitpos: [7:0]; default: 5; + * DCDC pre-on/post off delay + */ + uint32_t dcdc_pre_delay:8; + /** dcdc_res_off_delay : R/W; bitpos: [15:8]; default: 2; + * DCDC fb res off delay + */ + uint32_t dcdc_res_off_delay:8; + /** dcdc_stable_delay : R/W; bitpos: [25:16]; default: 75; + * DCDC stable delay + */ + uint32_t dcdc_stable_delay:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} pmu_dcm_wait_delay_reg_t; + +/** Type of vddbat_cfg register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_mode : RO; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_mode:2; + uint32_t reserved_2:29; + /** vddbat_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vddbat_sw_update:1; + }; + uint32_t val; +} pmu_vddbat_cfg_reg_t; + +/** Type of touch_pwr_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** touch_wait_cycles : R/W; bitpos: [13:5]; default: 10; + * need_des + */ + uint32_t touch_wait_cycles:9; + /** touch_sleep_cycles : R/W; bitpos: [29:14]; default: 100; + * need_des + */ + uint32_t touch_sleep_cycles:16; + /** touch_force_done : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t touch_force_done:1; + /** touch_sleep_timer_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t touch_sleep_timer_en:1; + }; + uint32_t val; +} pmu_touch_pwr_cntl_reg_t; + +/** Type of rdn_eco register + * need_des + */ +typedef union { + struct { + /** pmu_rdn_eco_result : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t pmu_rdn_eco_result:1; + uint32_t reserved_1:30; + /** pmu_rdn_eco_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t pmu_rdn_eco_en:1; + }; + uint32_t val; +} pmu_rdn_eco_reg_t; + +/** Type of power_pd_hp_cpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_hp_cpu_cntl_reg_t; + +/** Type of power_pd_hp_cpu_mask register + * need_des + */ +typedef union { + struct { + /** xpd_hp_cpu_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t xpd_hp_cpu_mask:5; + uint32_t reserved_5:22; + /** pd_hp_cpu_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + }; + uint32_t val; +} pmu_power_pd_hp_cpu_mask_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 38801456; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_pll_state : RO; bitpos: [2:0]; default: 0; + * need_des + */ + uint32_t stable_xpd_pll_state:3; + /** stable_xpd_xtal_state : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + /** pmu_ana_xpd_pll_i2c_state : RO; bitpos: [6:4]; default: 0; + * need_des + */ + uint32_t pmu_ana_xpd_pll_i2c_state:3; + uint32_t reserved_7:3; + /** pmu_sys_clk_slp_sel_state : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t pmu_sys_clk_slp_sel_state:1; + /** pmu_sys_clk_sel_state : RO; bitpos: [12:11]; default: 0; + * need_des + */ + uint32_t pmu_sys_clk_sel_state:2; + /** pmu_sys_clk_no_div_state : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t pmu_sys_clk_no_div_state:1; + /** pmu_icg_sys_clk_en_state : RO; bitpos: [14]; default: 1; + * need_des + */ + uint32_t pmu_icg_sys_clk_en_state:1; + /** pmu_icg_modem_switch_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t pmu_icg_modem_switch_state:1; + /** pmu_icg_modem_code_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t pmu_icg_modem_code_state:2; + /** pmu_icg_slp_sel_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t pmu_icg_slp_sel_state:1; + /** pmu_icg_global_xtal_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t pmu_icg_global_xtal_state:1; + /** pmu_icg_global_pll_state : RO; bitpos: [23:20]; default: 0; + * need_des + */ + uint32_t pmu_icg_global_pll_state:4; + /** pmu_ana_i2c_iso_en_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t pmu_ana_i2c_iso_en_state:1; + /** pmu_ana_i2c_retention_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t pmu_ana_i2c_retention_state:1; + uint32_t reserved_26:1; + /** pmu_ana_xpd_pll_state : RO; bitpos: [30:27]; default: 0; + * need_des + */ + uint32_t pmu_ana_xpd_pll_state:4; + /** pmu_ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t pmu_ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** pmu_icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t pmu_icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** pmu_icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t pmu_icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of xtal_slp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** xtal_slp_cnt_target : R/W; bitpos: [31:16]; default: 15; + * need_des + */ + uint32_t xtal_slp_cnt_target:16; + }; + uint32_t val; +} pmu_xtal_slp_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + uint32_t reserved_0a4; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + uint32_t reserved_0b0; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_cnnt_cntl_reg_t power_pd_cnnt_cntl; + volatile pmu_power_pd_hpmem_cntl_reg_t power_pd_hpmem_cntl; + volatile pmu_power_pd_top_mask_reg_t power_pd_top_mask; + volatile pmu_power_pd_cnnt_mask_reg_t power_pd_cnnt_mask; + volatile pmu_power_pd_hpmem_mask_reg_t power_pd_hpmem_mask; + volatile pmu_power_dcdc_switch_reg_t power_dcdc_switch; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_lpperi_mask_reg_t power_pd_lpperi_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_cntl8_reg_t slp_wakeup_cntl8; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_slp_wakeup_status2_reg_t slp_wakeup_status2; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_lp_cpu_pwr2_reg_t lp_cpu_pwr2; + volatile pmu_lp_cpu_pwr3_reg_t lp_cpu_pwr3; + volatile pmu_lp_cpu_pwr4_reg_t lp_cpu_pwr4; + volatile pmu_lp_cpu_pwr5_reg_t lp_cpu_pwr5; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_ext_ldo_p0_0p1a_reg_t ext_ldo_p0_0p1a; + volatile pmu_ext_ldo_p0_0p1a_ana_reg_t ext_ldo_p0_0p1a_ana; + volatile pmu_ext_ldo_p0_0p2a_reg_t ext_ldo_p0_0p2a; + volatile pmu_ext_ldo_p0_0p2a_ana_reg_t ext_ldo_p0_0p2a_ana; + volatile pmu_ext_ldo_p0_0p3a_reg_t ext_ldo_p0_0p3a; + volatile pmu_ext_ldo_p0_0p3a_ana_reg_t ext_ldo_p0_0p3a_ana; + volatile pmu_ext_ldo_p1_0p1a_reg_t ext_ldo_p1_0p1a; + volatile pmu_ext_ldo_p1_0p1a_ana_reg_t ext_ldo_p1_0p1a_ana; + volatile pmu_ext_ldo_p1_0p2a_reg_t ext_ldo_p1_0p2a; + volatile pmu_ext_ldo_p1_0p2a_ana_reg_t ext_ldo_p1_0p2a_ana; + volatile pmu_ext_ldo_p1_0p3a_reg_t ext_ldo_p1_0p3a; + volatile pmu_ext_ldo_p1_0p3a_ana_reg_t ext_ldo_p1_0p3a_ana; + volatile pmu_ext_wakeup_lv_reg_t ext_wakeup_lv; + volatile pmu_ext_wakeup_sel_reg_t ext_wakeup_sel; + volatile pmu_ext_wakeup_st_reg_t ext_wakeup_st; + volatile pmu_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile pmu_sdio_wakeup_cntl_reg_t sdio_wakeup_cntl; + volatile pmu_xtal_slp_reg_t xtal_slp; + volatile pmu_cpu_sw_stall_reg_t cpu_sw_stall; + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_wait_delay_reg_t dcm_wait_delay; + volatile pmu_vddbat_cfg_reg_t vddbat_cfg; + volatile pmu_touch_pwr_cntl_reg_t touch_pwr_cntl; + volatile pmu_rdn_eco_reg_t rdn_eco; + volatile pmu_power_pd_hp_cpu_cntl_reg_t power_pd_hp_cpu_cntl; + volatile pmu_power_pd_hp_cpu_mask_reg_t power_pd_hp_cpu_mask; + uint32_t reserved_220[119]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pmu_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/pmu_reg.h new file mode 100644 index 0000000000..bb17970949 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pmu_reg.h @@ -0,0 +1,4967 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: IDF-13420 + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_M (PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V << PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN (BIT(23)) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_M (PMU_HP_ACTIVE_PD_CNNT_PD_EN_V << PMU_HP_ACTIVE_PD_CNNT_PD_EN_S) +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CNNT_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(21)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 21 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(22)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 22 +/** PMU_HP_ACTIVE_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_I2C_M (PMU_HP_ACTIVE_XPD_PLL_I2C_V << PMU_HP_ACTIVE_XPD_PLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_I2C_S 23 +/** PMU_HP_ACTIVE_XPD_PLL : R/W; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_PLL 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_M (PMU_HP_ACTIVE_XPD_PLL_V << PMU_HP_ACTIVE_XPD_PLL_S) +#define PMU_HP_ACTIVE_XPD_PLL_V 0x0000000FU +#define PMU_HP_ACTIVE_XPD_PLL_S 27 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [22:18]; default: 20; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) +#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_S 18 +/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) +#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_S 23 +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_M (PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V << PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_CNNT_PD_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_CNNT_PD_EN_M (PMU_HP_MODEM_PD_CNNT_PD_EN_V << PMU_HP_MODEM_PD_CNNT_PD_EN_S) +#define PMU_HP_MODEM_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_CNNT_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : WT; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_MODEM_UART_WAKEUP_EN : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(21)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 21 +/** PMU_HP_MODEM_I2C_RETENTION : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(22)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 22 +/** PMU_HP_MODEM_XPD_PLL_I2C : WT; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_I2C_M (PMU_HP_MODEM_XPD_PLL_I2C_V << PMU_HP_MODEM_XPD_PLL_I2C_S) +#define PMU_HP_MODEM_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_I2C_S 23 +/** PMU_HP_MODEM_XPD_PLL : WT; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_PLL 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_M (PMU_HP_MODEM_XPD_PLL_V << PMU_HP_MODEM_XPD_PLL_S) +#define PMU_HP_MODEM_XPD_PLL_V 0x0000000FU +#define PMU_HP_MODEM_XPD_PLL_S 27 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 20; + * need_des + */ +#define PMU_HP_MODEM_DCM_VSET 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) +#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_S 18 +/** PMU_HP_MODEM_DCM_MODE : WT; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_MODE 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) +#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_S 23 +/** PMU_HP_MODEM_XPD_BIAS : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : WT; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : WT; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : WT; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : WT; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : WT; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : WT; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : WT; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : WT; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_DCDC_SWITCH_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_M (PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V << PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S) +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_SWITCH_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN (BIT(23)) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CNNT_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_M (PMU_HP_SLEEP_PD_CNNT_PD_EN_V << PMU_HP_SLEEP_PD_CNNT_PD_EN_S) +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_CNNT_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_HP_POWER_DET_BYPASS : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS (BIT(23)) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_M (PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V << PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S) +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_SLEEP_HP_POWER_DET_BYPASS_S 23 +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(21)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 21 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(22)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 22 +/** PMU_HP_SLEEP_XPD_PLL_I2C : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_PLL_I2C 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_I2C_M (PMU_HP_SLEEP_XPD_PLL_I2C_V << PMU_HP_SLEEP_XPD_PLL_I2C_S) +#define PMU_HP_SLEEP_XPD_PLL_I2C_V 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_I2C_S 23 +/** PMU_HP_SLEEP_XPD_PLL : R/W; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_PLL 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_M (PMU_HP_SLEEP_XPD_PLL_V << PMU_HP_SLEEP_XPD_PLL_S) +#define PMU_HP_SLEEP_XPD_PLL_V 0x0000000FU +#define PMU_HP_SLEEP_XPD_PLL_S 27 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [22:18]; default: 20; + * need_des + */ +#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) +#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_S 18 +/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [24:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCM_MODE 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) +#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_S 23 +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000003FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 26 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL (BIT(26)) +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_M (PMU_HP_SLEEP_LP_PAD_SLP_SEL_V << PMU_HP_SLEEP_LP_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_SLP_SEL_S 26 +/** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_M (PMU_HP_SLEEP_BOD_SOURCE_SEL_V << PMU_HP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_HP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_HP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_M (PMU_HP_SLEEP_VDDBAT_MODE_V << PMU_HP_SLEEP_VDDBAT_MODE_S) +#define PMU_HP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_HP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_HP_SLEEP_XPD_LPPLL_M (PMU_HP_SLEEP_XPD_LPPLL_V << PMU_HP_SLEEP_XPD_LPPLL_S) +#define PMU_HP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_LPPLL_S 27 +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000003FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 26 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_PAD_SLP_SEL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL (BIT(26)) +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_M (PMU_LP_SLEEP_LP_PAD_SLP_SEL_V << PMU_LP_SLEEP_LP_PAD_SLP_SEL_S) +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_V 0x00000001U +#define PMU_LP_SLEEP_LP_PAD_SLP_SEL_S 26 +/** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BOD_SOURCE_SEL (BIT(27)) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_M (PMU_LP_SLEEP_BOD_SOURCE_SEL_V << PMU_LP_SLEEP_BOD_SOURCE_SEL_S) +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_V 0x00000001U +#define PMU_LP_SLEEP_BOD_SOURCE_SEL_S 27 +/** PMU_LP_SLEEP_VDDBAT_MODE : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDDBAT_MODE 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_M (PMU_LP_SLEEP_VDDBAT_MODE_V << PMU_LP_SLEEP_VDDBAT_MODE_S) +#define PMU_LP_SLEEP_VDDBAT_MODE_V 0x00000003U +#define PMU_LP_SLEEP_VDDBAT_MODE_S 28 +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_LPPLL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_LPPLL (BIT(27)) +#define PMU_LP_SLEEP_XPD_LPPLL_M (PMU_LP_SLEEP_XPD_LPPLL_V << PMU_LP_SLEEP_XPD_LPPLL_S) +#define PMU_LP_SLEEP_XPD_LPPLL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_LPPLL_S 27 +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_CALI_XTAL_ICG : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_CALI_XTAL_ICG (BIT(0)) +#define PMU_TIE_LOW_CALI_XTAL_ICG_M (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S) +#define PMU_TIE_LOW_CALI_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_CALI_XTAL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_CPLL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_M (PMU_TIE_LOW_GLOBAL_CPLL_ICG_V << PMU_TIE_LOW_GLOBAL_CPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_CPLL_ICG_S 1 +/** PMU_TIE_LOW_GLOBAL_SPLL_ICG : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_SPLL_ICG (BIT(2)) +#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_M (PMU_TIE_LOW_GLOBAL_SPLL_ICG_V << PMU_TIE_LOW_GLOBAL_SPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_SPLL_ICG_S 2 +/** PMU_TIE_LOW_GLOBAL_APLL_ICG : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_APLL_ICG (BIT(3)) +#define PMU_TIE_LOW_GLOBAL_APLL_ICG_M (PMU_TIE_LOW_GLOBAL_APLL_ICG_V << PMU_TIE_LOW_GLOBAL_APLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_APLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_APLL_ICG_S 3 +/** PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG (BIT(4)) +#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_M (PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_V << PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_SDIOPLL_ICG_S 4 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(5)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 5 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(6)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 6 +/** PMU_TIE_LOW_XPD_CPLL_I2C : WT; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_CPLL_I2C (BIT(7)) +#define PMU_TIE_LOW_XPD_CPLL_I2C_M (PMU_TIE_LOW_XPD_CPLL_I2C_V << PMU_TIE_LOW_XPD_CPLL_I2C_S) +#define PMU_TIE_LOW_XPD_CPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_CPLL_I2C_S 7 +/** PMU_TIE_LOW_XPD_SPLL_I2C : WT; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_SPLL_I2C (BIT(8)) +#define PMU_TIE_LOW_XPD_SPLL_I2C_M (PMU_TIE_LOW_XPD_SPLL_I2C_V << PMU_TIE_LOW_XPD_SPLL_I2C_S) +#define PMU_TIE_LOW_XPD_SPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_SPLL_I2C_S 8 +/** PMU_TIE_LOW_XPD_APLL_I2C : WT; bitpos: [9]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_APLL_I2C (BIT(9)) +#define PMU_TIE_LOW_XPD_APLL_I2C_M (PMU_TIE_LOW_XPD_APLL_I2C_V << PMU_TIE_LOW_XPD_APLL_I2C_S) +#define PMU_TIE_LOW_XPD_APLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_APLL_I2C_S 9 +/** PMU_TIE_LOW_XPD_SDIOPLL_I2C : WT; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_SDIOPLL_I2C (BIT(10)) +#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_M (PMU_TIE_LOW_XPD_SDIOPLL_I2C_V << PMU_TIE_LOW_XPD_SDIOPLL_I2C_S) +#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_SDIOPLL_I2C_S 10 +/** PMU_TIE_LOW_XPD_CPLL : WT; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_CPLL (BIT(11)) +#define PMU_TIE_LOW_XPD_CPLL_M (PMU_TIE_LOW_XPD_CPLL_V << PMU_TIE_LOW_XPD_CPLL_S) +#define PMU_TIE_LOW_XPD_CPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_CPLL_S 11 +/** PMU_TIE_LOW_XPD_SPLL : WT; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_SPLL (BIT(12)) +#define PMU_TIE_LOW_XPD_SPLL_M (PMU_TIE_LOW_XPD_SPLL_V << PMU_TIE_LOW_XPD_SPLL_S) +#define PMU_TIE_LOW_XPD_SPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_SPLL_S 12 +/** PMU_TIE_LOW_XPD_APLL : WT; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_APLL (BIT(13)) +#define PMU_TIE_LOW_XPD_APLL_M (PMU_TIE_LOW_XPD_APLL_V << PMU_TIE_LOW_XPD_APLL_S) +#define PMU_TIE_LOW_XPD_APLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_APLL_S 13 +/** PMU_TIE_LOW_XPD_SDIOPLL : WT; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_SDIOPLL (BIT(14)) +#define PMU_TIE_LOW_XPD_SDIOPLL_M (PMU_TIE_LOW_XPD_SDIOPLL_V << PMU_TIE_LOW_XPD_SDIOPLL_S) +#define PMU_TIE_LOW_XPD_SDIOPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_SDIOPLL_S 14 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(15)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 15 +/** PMU_TIE_HIGH_CALI_XTAL_ICG : R/W; bitpos: [16]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_CALI_XTAL_ICG (BIT(16)) +#define PMU_TIE_HIGH_CALI_XTAL_ICG_M (PMU_TIE_HIGH_CALI_XTAL_ICG_V << PMU_TIE_HIGH_CALI_XTAL_ICG_S) +#define PMU_TIE_HIGH_CALI_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_CALI_XTAL_ICG_S 16 +/** PMU_TIE_HIGH_GLOBAL_CPLL_ICG : WT; bitpos: [17]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG (BIT(17)) +#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_CPLL_ICG_S 17 +/** PMU_TIE_HIGH_GLOBAL_SPLL_ICG : WT; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG (BIT(18)) +#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_SPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_SPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_SPLL_ICG_S 18 +/** PMU_TIE_HIGH_GLOBAL_APLL_ICG : WT; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_APLL_ICG (BIT(19)) +#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_M (PMU_TIE_HIGH_GLOBAL_APLL_ICG_V << PMU_TIE_HIGH_GLOBAL_APLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_APLL_ICG_S 19 +/** PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG (BIT(20)) +#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG_S 20 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(21)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 21 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(22)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 22 +/** PMU_TIE_HIGH_XPD_CPLL_I2C : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_CPLL_I2C (BIT(23)) +#define PMU_TIE_HIGH_XPD_CPLL_I2C_M (PMU_TIE_HIGH_XPD_CPLL_I2C_V << PMU_TIE_HIGH_XPD_CPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_CPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_CPLL_I2C_S 23 +/** PMU_TIE_HIGH_XPD_SPLL_I2C : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_SPLL_I2C (BIT(24)) +#define PMU_TIE_HIGH_XPD_SPLL_I2C_M (PMU_TIE_HIGH_XPD_SPLL_I2C_V << PMU_TIE_HIGH_XPD_SPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_SPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_SPLL_I2C_S 24 +/** PMU_TIE_HIGH_XPD_APLL_I2C : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_APLL_I2C (BIT(25)) +#define PMU_TIE_HIGH_XPD_APLL_I2C_M (PMU_TIE_HIGH_XPD_APLL_I2C_V << PMU_TIE_HIGH_XPD_APLL_I2C_S) +#define PMU_TIE_HIGH_XPD_APLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_APLL_I2C_S 25 +/** PMU_TIE_HIGH_XPD_SDIOPLL_I2C : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C (BIT(26)) +#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_M (PMU_TIE_HIGH_XPD_SDIOPLL_I2C_V << PMU_TIE_HIGH_XPD_SDIOPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_SDIOPLL_I2C_S 26 +/** PMU_TIE_HIGH_XPD_CPLL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_CPLL (BIT(27)) +#define PMU_TIE_HIGH_XPD_CPLL_M (PMU_TIE_HIGH_XPD_CPLL_V << PMU_TIE_HIGH_XPD_CPLL_S) +#define PMU_TIE_HIGH_XPD_CPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_CPLL_S 27 +/** PMU_TIE_HIGH_XPD_SPLL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_SPLL (BIT(28)) +#define PMU_TIE_HIGH_XPD_SPLL_M (PMU_TIE_HIGH_XPD_SPLL_V << PMU_TIE_HIGH_XPD_SPLL_S) +#define PMU_TIE_HIGH_XPD_SPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_SPLL_S 28 +/** PMU_TIE_HIGH_XPD_APLL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_APLL (BIT(29)) +#define PMU_TIE_HIGH_XPD_APLL_M (PMU_TIE_HIGH_XPD_APLL_V << PMU_TIE_HIGH_XPD_APLL_S) +#define PMU_TIE_HIGH_XPD_APLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_APLL_S 29 +/** PMU_TIE_HIGH_XPD_SDIOPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_SDIOPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_SDIOPLL_M (PMU_TIE_HIGH_XPD_SDIOPLL_V << PMU_TIE_HIGH_XPD_SDIOPLL_S) +#define PMU_TIE_HIGH_XPD_SDIOPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_SDIOPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_PAD_SLP_SEL : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_PAD_SLP_SEL (BIT(0)) +#define PMU_PAD_SLP_SEL_M (PMU_PAD_SLP_SEL_V << PMU_PAD_SLP_SEL_S) +#define PMU_PAD_SLP_SEL_V 0x00000001U +#define PMU_PAD_SLP_SEL_S 0 +/** PMU_LP_PAD_HOLD_ALL : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_PAD_HOLD_ALL (BIT(1)) +#define PMU_LP_PAD_HOLD_ALL_M (PMU_LP_PAD_HOLD_ALL_V << PMU_LP_PAD_HOLD_ALL_S) +#define PMU_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_LP_PAD_HOLD_ALL_S 1 +/** PMU_HP_PAD_HOLD_ALL : RO; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_HP_PAD_HOLD_ALL (BIT(2)) +#define PMU_HP_PAD_HOLD_ALL_M (PMU_HP_PAD_HOLD_ALL_V << PMU_HP_PAD_HOLD_ALL_S) +#define PMU_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_PAD_HOLD_ALL_S 2 +/** PMU_TIE_HIGH_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_PAD_SLP_SEL (BIT(26)) +#define PMU_TIE_HIGH_PAD_SLP_SEL_M (PMU_TIE_HIGH_PAD_SLP_SEL_V << PMU_TIE_HIGH_PAD_SLP_SEL_S) +#define PMU_TIE_HIGH_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_PAD_SLP_SEL_S 26 +/** PMU_TIE_LOW_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_PAD_SLP_SEL (BIT(27)) +#define PMU_TIE_LOW_PAD_SLP_SEL_M (PMU_TIE_LOW_PAD_SLP_SEL_V << PMU_TIE_LOW_PAD_SLP_SEL_S) +#define PMU_TIE_LOW_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_PAD_SLP_SEL_S 27 +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_LP_POWERDOWN_TIMER_S 5 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_LP_POWERUP_TIMER_S 14 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 + +/** PMU_POWER_PD_CNNT_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_CNNT_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_CNNT_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_RESET (BIT(0)) +#define PMU_FORCE_CNNT_RESET_M (PMU_FORCE_CNNT_RESET_V << PMU_FORCE_CNNT_RESET_S) +#define PMU_FORCE_CNNT_RESET_V 0x00000001U +#define PMU_FORCE_CNNT_RESET_S 0 +/** PMU_FORCE_CNNT_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_ISO (BIT(1)) +#define PMU_FORCE_CNNT_ISO_M (PMU_FORCE_CNNT_ISO_V << PMU_FORCE_CNNT_ISO_S) +#define PMU_FORCE_CNNT_ISO_V 0x00000001U +#define PMU_FORCE_CNNT_ISO_S 1 +/** PMU_FORCE_CNNT_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_PU (BIT(2)) +#define PMU_FORCE_CNNT_PU_M (PMU_FORCE_CNNT_PU_V << PMU_FORCE_CNNT_PU_S) +#define PMU_FORCE_CNNT_PU_V 0x00000001U +#define PMU_FORCE_CNNT_PU_S 2 +/** PMU_FORCE_CNNT_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_NO_RESET (BIT(3)) +#define PMU_FORCE_CNNT_NO_RESET_M (PMU_FORCE_CNNT_NO_RESET_V << PMU_FORCE_CNNT_NO_RESET_S) +#define PMU_FORCE_CNNT_NO_RESET_V 0x00000001U +#define PMU_FORCE_CNNT_NO_RESET_S 3 +/** PMU_FORCE_CNNT_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_CNNT_NO_ISO (BIT(4)) +#define PMU_FORCE_CNNT_NO_ISO_M (PMU_FORCE_CNNT_NO_ISO_V << PMU_FORCE_CNNT_NO_ISO_S) +#define PMU_FORCE_CNNT_NO_ISO_V 0x00000001U +#define PMU_FORCE_CNNT_NO_ISO_S 4 +/** PMU_FORCE_CNNT_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_CNNT_PD (BIT(5)) +#define PMU_FORCE_CNNT_PD_M (PMU_FORCE_CNNT_PD_V << PMU_FORCE_CNNT_PD_S) +#define PMU_FORCE_CNNT_PD_V 0x00000001U +#define PMU_FORCE_CNNT_PD_S 5 + +/** PMU_POWER_PD_HPMEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPMEM_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_MEM_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_RESET (BIT(0)) +#define PMU_FORCE_HP_MEM_RESET_M (PMU_FORCE_HP_MEM_RESET_V << PMU_FORCE_HP_MEM_RESET_S) +#define PMU_FORCE_HP_MEM_RESET_V 0x00000001U +#define PMU_FORCE_HP_MEM_RESET_S 0 +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO (BIT(1)) +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x00000001U +#define PMU_FORCE_HP_MEM_ISO_S 1 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU (BIT(2)) +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x00000001U +#define PMU_FORCE_HP_MEM_PU_S 2 +/** PMU_FORCE_HP_MEM_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_MEM_NO_RESET_M (PMU_FORCE_HP_MEM_NO_RESET_V << PMU_FORCE_HP_MEM_NO_RESET_S) +#define PMU_FORCE_HP_MEM_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_MEM_NO_RESET_S 3 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_MEM_NO_ISO_S 4 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD (BIT(5)) +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x00000001U +#define PMU_FORCE_HP_MEM_PD_S 5 + +/** PMU_POWER_PD_TOP_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_MASK_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_XPD_TOP_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_TOP_MASK 0x0000001FU +#define PMU_XPD_TOP_MASK_M (PMU_XPD_TOP_MASK_V << PMU_XPD_TOP_MASK_S) +#define PMU_XPD_TOP_MASK_V 0x0000001FU +#define PMU_XPD_TOP_MASK_S 0 +/** PMU_PD_TOP_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 27 + +/** PMU_POWER_PD_CNNT_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_CNNT_MASK_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_XPD_CNNT_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_CNNT_MASK 0x0000001FU +#define PMU_XPD_CNNT_MASK_M (PMU_XPD_CNNT_MASK_V << PMU_XPD_CNNT_MASK_S) +#define PMU_XPD_CNNT_MASK_V 0x0000001FU +#define PMU_XPD_CNNT_MASK_S 0 +/** PMU_PD_CNNT_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_CNNT_MASK 0x0000001FU +#define PMU_PD_CNNT_MASK_M (PMU_PD_CNNT_MASK_V << PMU_PD_CNNT_MASK_S) +#define PMU_PD_CNNT_MASK_V 0x0000001FU +#define PMU_PD_CNNT_MASK_S 27 + +/** PMU_POWER_PD_HPMEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_HPMEM_MASK_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_XPD_HP_MEM_MASK : R/W; bitpos: [5:0]; default: 0; + * need_des + */ +#define PMU_XPD_HP_MEM_MASK 0x0000003FU +#define PMU_XPD_HP_MEM_MASK_M (PMU_XPD_HP_MEM_MASK_V << PMU_XPD_HP_MEM_MASK_S) +#define PMU_XPD_HP_MEM_MASK_V 0x0000003FU +#define PMU_XPD_HP_MEM_MASK_S 0 +/** PMU_PD_HP_MEM_MASK : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM_MASK 0x0000003FU +#define PMU_PD_HP_MEM_MASK_M (PMU_PD_HP_MEM_MASK_V << PMU_PD_HP_MEM_MASK_S) +#define PMU_PD_HP_MEM_MASK_V 0x0000003FU +#define PMU_PD_HP_MEM_MASK_S 26 + +/** PMU_POWER_DCDC_SWITCH_REG register + * need_des + */ +#define PMU_POWER_DCDC_SWITCH_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_DCDC_SWITCH_PU : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FORCE_DCDC_SWITCH_PU (BIT(0)) +#define PMU_FORCE_DCDC_SWITCH_PU_M (PMU_FORCE_DCDC_SWITCH_PU_V << PMU_FORCE_DCDC_SWITCH_PU_S) +#define PMU_FORCE_DCDC_SWITCH_PU_V 0x00000001U +#define PMU_FORCE_DCDC_SWITCH_PU_S 0 +/** PMU_FORCE_DCDC_SWITCH_PD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_DCDC_SWITCH_PD (BIT(1)) +#define PMU_FORCE_DCDC_SWITCH_PD_M (PMU_FORCE_DCDC_SWITCH_PD_V << PMU_FORCE_DCDC_SWITCH_PD_S) +#define PMU_FORCE_DCDC_SWITCH_PD_V 0x00000001U +#define PMU_FORCE_DCDC_SWITCH_PD_S 1 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_LPPERI_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_MASK_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_XPD_LP_PERI_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_LP_PERI_MASK 0x0000001FU +#define PMU_XPD_LP_PERI_MASK_M (PMU_XPD_LP_PERI_MASK_V << PMU_XPD_LP_PERI_MASK_S) +#define PMU_XPD_LP_PERI_MASK_V 0x0000001FU +#define PMU_XPD_LP_PERI_MASK_S 0 +/** PMU_PD_LP_PERI_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_LP_PERI_MASK 0x0000001FU +#define PMU_PD_LP_PERI_MASK_M (PMU_PD_LP_PERI_MASK_V << PMU_PD_LP_PERI_MASK_S) +#define PMU_PD_LP_PERI_MASK_V 0x0000001FU +#define PMU_PD_LP_PERI_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_PMU_WAIT_XTL_STABLE_M (PMU_PMU_WAIT_XTL_STABLE_V << PMU_PMU_WAIT_XTL_STABLE_S) +#define PMU_PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_PMU_WAIT_XTL_STABLE_S 0 +/** PMU_PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_PMU_WAIT_PLL_STABLE_M (PMU_PMU_WAIT_PLL_STABLE_V << PMU_PMU_WAIT_PLL_STABLE_S) +#define PMU_PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0x7FFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0x7FFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_CNTL8_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL8_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_LP_LITE_WAKEUP_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_LITE_WAKEUP_ENA (BIT(31)) +#define PMU_LP_LITE_WAKEUP_ENA_M (PMU_LP_LITE_WAKEUP_ENA_V << PMU_LP_LITE_WAKEUP_ENA_S) +#define PMU_LP_LITE_WAKEUP_ENA_V 0x00000001U +#define PMU_LP_LITE_WAKEUP_ENA_S 31 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0x7FFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0x7FFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0x7FFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0x7FFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS2_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_LP_LITE_WAKEUP_CAUSE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_LITE_WAKEUP_CAUSE (BIT(31)) +#define PMU_LP_LITE_WAKEUP_CAUSE_M (PMU_LP_LITE_WAKEUP_CAUSE_V << PMU_LP_LITE_WAKEUP_CAUSE_S) +#define PMU_LP_LITE_WAKEUP_CAUSE_V 0x00000001U +#define PMU_LP_LITE_WAKEUP_CAUSE_S 31 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_MSPI_PHY_XPD : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MSPI_PHY_XPD (BIT(24)) +#define PMU_MSPI_PHY_XPD_M (PMU_MSPI_PHY_XPD_V << PMU_MSPI_PHY_XPD_S) +#define PMU_MSPI_PHY_XPD_V 0x00000001U +#define PMU_MSPI_PHY_XPD_S 24 +/** PMU_SDIO_PLL_XPD : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_SDIO_PLL_XPD (BIT(25)) +#define PMU_SDIO_PLL_XPD_M (PMU_SDIO_PLL_XPD_V << PMU_SDIO_PLL_XPD_S) +#define PMU_SDIO_PLL_XPD_V 0x00000001U +#define PMU_SDIO_PLL_XPD_S 25 +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_S 25 +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_S 25 +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_S 25 +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_S 25 +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_M (PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V << PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_RAW_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_S 25 +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_SLEEP_REJECT_INT_ST : RO; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_M (PMU_LP_CPU_SLEEP_REJECT_INT_ST_V << PMU_LP_CPU_SLEEP_REJECT_INT_ST_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_ST_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : RO; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : RO; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : RO; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : RO; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_S 25 +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_SLEEP_REJECT_INT_ENA : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_M (PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V << PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S) +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_INT_ENA_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : R/W; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : R/W; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : R/W; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : R/W; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_S 25 +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR : WT; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR (BIT(13)) +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_M (PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V << PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S) +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REJECT_LP_INT_CLR_S 13 +/** PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [14]; default: 0; + * reg_0p1a_0_counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(14)) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 14 +/** PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [15]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(15)) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 15 +/** PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [16]; default: 0; + * reg_0p1a_0 counter after xpd reach target0 + */ +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(16)) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 16 +/** PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [17]; default: 0; + * reg_0p1a_1_counter after xpd reach target1 + */ +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(17)) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 17 +/** PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [18]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(18)) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 18 +/** PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [19]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(19)) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 19 +/** PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [20]; default: 0; + * reg_0p2a_0 counter after xpd reach target0 + */ +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(20)) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 20 +/** PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [21]; default: 0; + * reg_0p2a_1_counter after xpd reach target1 + */ +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(21)) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 21 +/** PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : WT; bitpos: [22]; default: 0; + * reg_0p3a_0 counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR (BIT(22)) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_S 22 +/** PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : WT; bitpos: [23]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR (BIT(23)) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_S 23 +/** PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : WT; bitpos: [24]; default: 0; + * reg_0p3a_0_counter after xpd reach target0 + */ +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR (BIT(24)) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_S 24 +/** PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : WT; bitpos: [25]; default: 0; + * reg_0p3a_1_counter after xpd reach target1 + */ +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR (BIT(25)) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_M (PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V << PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S) +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_V 0x00000001U +#define PMU_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_S 25 +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(26)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 27 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(28)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 28 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(29)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_LP_CPU_PWR2_REG register + * need_des + */ +#define PMU_LP_CPU_PWR2_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 + +/** PMU_LP_CPU_PWR3_REG register + * need_des + */ +#define PMU_LP_CPU_PWR3_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_LP_CPU_WAKEUP_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_CAUSE 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_CAUSE_M (PMU_LP_CPU_WAKEUP_CAUSE_V << PMU_LP_CPU_WAKEUP_CAUSE_S) +#define PMU_LP_CPU_WAKEUP_CAUSE_V 0x7FFFFFFFU +#define PMU_LP_CPU_WAKEUP_CAUSE_S 0 + +/** PMU_LP_CPU_PWR4_REG register + * need_des + */ +#define PMU_LP_CPU_PWR4_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_LP_CPU_REJECT_EN : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_REJECT_EN 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_EN_M (PMU_LP_CPU_REJECT_EN_V << PMU_LP_CPU_REJECT_EN_S) +#define PMU_LP_CPU_REJECT_EN_V 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_EN_S 0 + +/** PMU_LP_CPU_PWR5_REG register + * need_des + */ +#define PMU_LP_CPU_PWR5_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_LP_CPU_REJECT_CAUSE : RO; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_REJECT_CAUSE 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_CAUSE_M (PMU_LP_CPU_REJECT_CAUSE_V << PMU_LP_CPU_REJECT_CAUSE_S) +#define PMU_LP_CPU_REJECT_CAUSE_V 0x7FFFFFFFU +#define PMU_LP_CPU_REJECT_CAUSE_S 0 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_ENABLE_CALI_PMU_CNTL : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_ENABLE_CALI_PMU_CNTL (BIT(0)) +#define PMU_ENABLE_CALI_PMU_CNTL_M (PMU_ENABLE_CALI_PMU_CNTL_V << PMU_ENABLE_CALI_PMU_CNTL_S) +#define PMU_ENABLE_CALI_PMU_CNTL_V 0x00000001U +#define PMU_ENABLE_CALI_PMU_CNTL_S 0 +/** PMU_PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_LAST_ST_STATE_M (PMU_PMU_MAIN_LAST_ST_STATE_V << PMU_PMU_MAIN_LAST_ST_STATE_S) +#define PMU_PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_TAR_ST_STATE_M (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S) +#define PMU_PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_PMU_MAIN_CUR_ST_STATE_M (PMU_PMU_MAIN_CUR_ST_STATE_V << PMU_PMU_MAIN_CUR_ST_STATE_S) +#define PMU_PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) +/** PMU_PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_PMU_BACKUP_ST_STATE_M (PMU_PMU_BACKUP_ST_STATE_V << PMU_PMU_BACKUP_ST_STATE_S) +#define PMU_PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_PMU_BACKUP_ST_STATE_S 13 +/** PMU_PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_PMU_LP_PWR_ST_STATE_M (PMU_PMU_LP_PWR_ST_STATE_V << PMU_PMU_LP_PWR_ST_STATE_S) +#define PMU_PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_PMU_LP_PWR_ST_STATE_S 18 +/** PMU_PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_PMU_HP_PWR_ST_STATE_M (PMU_PMU_HP_PWR_ST_STATE_V << PMU_PMU_HP_PWR_ST_STATE_S) +#define PMU_PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) +/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 7; + * need_des + */ +#define PMU_STABLE_XPD_PLL_STATE 0x00000007U +#define PMU_STABLE_XPD_PLL_STATE_M (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S) +#define PMU_STABLE_XPD_PLL_STATE_V 0x00000007U +#define PMU_STABLE_XPD_PLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(3)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 3 +/** PMU_PMU_ANA_XPD_PLL_I2C_STATE : RO; bitpos: [6:4]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE 0x00000007U +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_M (PMU_PMU_ANA_XPD_PLL_I2C_STATE_V << PMU_PMU_ANA_XPD_PLL_I2C_STATE_S) +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_V 0x00000007U +#define PMU_PMU_ANA_XPD_PLL_I2C_STATE_S 4 +/** PMU_PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE (BIT(10)) +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_PMU_SYS_CLK_SLP_SEL_STATE_S 10 +/** PMU_PMU_SYS_CLK_SEL_STATE : RO; bitpos: [12:11]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_PMU_SYS_CLK_SEL_STATE_M (PMU_PMU_SYS_CLK_SEL_STATE_V << PMU_PMU_SYS_CLK_SEL_STATE_S) +#define PMU_PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_PMU_SYS_CLK_SEL_STATE_S 11 +/** PMU_PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_PMU_SYS_CLK_NO_DIV_STATE (BIT(13)) +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_M (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_PMU_SYS_CLK_NO_DIV_STATE_S 13 +/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_SYS_CLK_EN_STATE (BIT(14)) +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_M (PMU_PMU_ICG_SYS_CLK_EN_STATE_V << PMU_PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_PMU_ICG_SYS_CLK_EN_STATE_S 14 +/** PMU_PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_MODEM_SWITCH_STATE (BIT(15)) +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_M (PMU_PMU_ICG_MODEM_SWITCH_STATE_V << PMU_PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_PMU_ICG_MODEM_SWITCH_STATE_S 15 +/** PMU_PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_PMU_ICG_MODEM_CODE_STATE_M (PMU_PMU_ICG_MODEM_CODE_STATE_V << PMU_PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_PMU_ICG_MODEM_CODE_STATE_S 16 +/** PMU_PMU_ICG_SLP_SEL_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_SLP_SEL_STATE (BIT(18)) +#define PMU_PMU_ICG_SLP_SEL_STATE_M (PMU_PMU_ICG_SLP_SEL_STATE_V << PMU_PMU_ICG_SLP_SEL_STATE_S) +#define PMU_PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_PMU_ICG_SLP_SEL_STATE_S 18 +/** PMU_PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE (BIT(19)) +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_PMU_ICG_GLOBAL_XTAL_STATE_S 19 +/** PMU_PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [23:20]; default: 0; + * need_des + */ +#define PMU_PMU_ICG_GLOBAL_PLL_STATE 0x0000000FU +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_M (PMU_PMU_ICG_GLOBAL_PLL_STATE_V << PMU_PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_V 0x0000000FU +#define PMU_PMU_ICG_GLOBAL_PLL_STATE_S 20 +/** PMU_PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_I2C_ISO_EN_STATE (BIT(24)) +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_M (PMU_PMU_ANA_I2C_ISO_EN_STATE_V << PMU_PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_PMU_ANA_I2C_ISO_EN_STATE_S 24 +/** PMU_PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_I2C_RETENTION_STATE (BIT(25)) +#define PMU_PMU_ANA_I2C_RETENTION_STATE_M (PMU_PMU_ANA_I2C_RETENTION_STATE_V << PMU_PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_PMU_ANA_I2C_RETENTION_STATE_S 25 +/** PMU_PMU_ANA_XPD_PLL_STATE : RO; bitpos: [30:27]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_XPD_PLL_STATE 0x0000000FU +#define PMU_PMU_ANA_XPD_PLL_STATE_M (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S) +#define PMU_PMU_ANA_XPD_PLL_STATE_V 0x0000000FU +#define PMU_PMU_ANA_XPD_PLL_STATE_S 27 +/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_PMU_ANA_XPD_XTAL_STATE_M (PMU_PMU_ANA_XPD_XTAL_STATE_V << PMU_PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) +/** PMU_PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_PMU_ICG_FUNC_EN_STATE_M (PMU_PMU_ICG_FUNC_EN_STATE_V << PMU_PMU_ICG_FUNC_EN_STATE_S) +#define PMU_PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) +/** PMU_PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_PMU_ICG_APB_EN_STATE_M (PMU_PMU_ICG_APB_EN_STATE_V << PMU_PMU_ICG_APB_EN_STATE_S) +#define PMU_PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_EXT_LDO_P0_0P1A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P1A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P1A_FORCE_TIEH_SEL_0_M (PMU_0P1A_FORCE_TIEH_SEL_0_V << PMU_0P1A_FORCE_TIEH_SEL_0_S) +#define PMU_0P1A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P1A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P1A_XPD_0 : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define PMU_0P1A_XPD_0 (BIT(8)) +#define PMU_0P1A_XPD_0_M (PMU_0P1A_XPD_0_V << PMU_0P1A_XPD_0_S) +#define PMU_0P1A_XPD_0_V 0x00000001U +#define PMU_0P1A_XPD_0_S 8 +/** PMU_0P1A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_SEL_0 0x00000007U +#define PMU_0P1A_TIEH_SEL_0_M (PMU_0P1A_TIEH_SEL_0_V << PMU_0P1A_TIEH_SEL_0_S) +#define PMU_0P1A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P1A_TIEH_SEL_0_S 9 +/** PMU_0P1A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P1A_TIEH_POS_EN_0_M (PMU_0P1A_TIEH_POS_EN_0_V << PMU_0P1A_TIEH_POS_EN_0_S) +#define PMU_0P1A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P1A_TIEH_POS_EN_0_S 12 +/** PMU_0P1A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P1A_TIEH_NEG_EN_0_M (PMU_0P1A_TIEH_NEG_EN_0_V << PMU_0P1A_TIEH_NEG_EN_0_S) +#define PMU_0P1A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P1A_TIEH_NEG_EN_0_S 13 +/** PMU_0P1A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_0 (BIT(14)) +#define PMU_0P1A_TIEH_0_M (PMU_0P1A_TIEH_0_V << PMU_0P1A_TIEH_0_S) +#define PMU_0P1A_TIEH_0_V 0x00000001U +#define PMU_0P1A_TIEH_0_S 14 +/** PMU_0P1A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P1A_TARGET1_0 0x000000FFU +#define PMU_0P1A_TARGET1_0_M (PMU_0P1A_TARGET1_0_V << PMU_0P1A_TARGET1_0_S) +#define PMU_0P1A_TARGET1_0_V 0x000000FFU +#define PMU_0P1A_TARGET1_0_S 15 +/** PMU_0P1A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P1A_TARGET0_0 0x000000FFU +#define PMU_0P1A_TARGET0_0_M (PMU_0P1A_TARGET0_0_V << PMU_0P1A_TARGET0_0_S) +#define PMU_0P1A_TARGET0_0_V 0x000000FFU +#define PMU_0P1A_TARGET0_0_S 23 +/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P1A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_ANA_0P1A_MUL_0 : R/W; bitpos: [25:23]; default: 2; + * need_des + */ +#define PMU_ANA_0P1A_MUL_0 0x00000007U +#define PMU_ANA_0P1A_MUL_0_M (PMU_ANA_0P1A_MUL_0_V << PMU_ANA_0P1A_MUL_0_S) +#define PMU_ANA_0P1A_MUL_0_V 0x00000007U +#define PMU_ANA_0P1A_MUL_0_S 23 +/** PMU_ANA_0P1A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P1A_EN_VDET_0_M (PMU_ANA_0P1A_EN_VDET_0_V << PMU_ANA_0P1A_EN_VDET_0_S) +#define PMU_ANA_0P1A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P1A_EN_VDET_0_S 26 +/** PMU_ANA_0P1A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P1A_EN_CUR_LIM_0_M (PMU_ANA_0P1A_EN_CUR_LIM_0_V << PMU_ANA_0P1A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P1A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P1A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P1A_DREF_0 : R/W; bitpos: [31:28]; default: 11; + * need_des + */ +#define PMU_ANA_0P1A_DREF_0 0x0000000FU +#define PMU_ANA_0P1A_DREF_0_M (PMU_ANA_0P1A_DREF_0_V << PMU_ANA_0P1A_DREF_0_S) +#define PMU_ANA_0P1A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P1A_DREF_0_S 28 + +/** PMU_EXT_LDO_P0_0P2A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0) +/** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P2A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P2A_FORCE_TIEH_SEL_0_M (PMU_0P2A_FORCE_TIEH_SEL_0_V << PMU_0P2A_FORCE_TIEH_SEL_0_S) +#define PMU_0P2A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P2A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P2A_XPD_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P2A_XPD_0 (BIT(8)) +#define PMU_0P2A_XPD_0_M (PMU_0P2A_XPD_0_V << PMU_0P2A_XPD_0_S) +#define PMU_0P2A_XPD_0_V 0x00000001U +#define PMU_0P2A_XPD_0_S 8 +/** PMU_0P2A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_SEL_0 0x00000007U +#define PMU_0P2A_TIEH_SEL_0_M (PMU_0P2A_TIEH_SEL_0_V << PMU_0P2A_TIEH_SEL_0_S) +#define PMU_0P2A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P2A_TIEH_SEL_0_S 9 +/** PMU_0P2A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P2A_TIEH_POS_EN_0_M (PMU_0P2A_TIEH_POS_EN_0_V << PMU_0P2A_TIEH_POS_EN_0_S) +#define PMU_0P2A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P2A_TIEH_POS_EN_0_S 12 +/** PMU_0P2A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P2A_TIEH_NEG_EN_0_M (PMU_0P2A_TIEH_NEG_EN_0_V << PMU_0P2A_TIEH_NEG_EN_0_S) +#define PMU_0P2A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P2A_TIEH_NEG_EN_0_S 13 +/** PMU_0P2A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_0 (BIT(14)) +#define PMU_0P2A_TIEH_0_M (PMU_0P2A_TIEH_0_V << PMU_0P2A_TIEH_0_S) +#define PMU_0P2A_TIEH_0_V 0x00000001U +#define PMU_0P2A_TIEH_0_S 14 +/** PMU_0P2A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P2A_TARGET1_0 0x000000FFU +#define PMU_0P2A_TARGET1_0_M (PMU_0P2A_TARGET1_0_V << PMU_0P2A_TARGET1_0_S) +#define PMU_0P2A_TARGET1_0_V 0x000000FFU +#define PMU_0P2A_TARGET1_0_S 15 +/** PMU_0P2A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P2A_TARGET0_0 0x000000FFU +#define PMU_0P2A_TARGET0_0_M (PMU_0P2A_TARGET0_0_V << PMU_0P2A_TARGET0_0_S) +#define PMU_0P2A_TARGET0_0_V 0x000000FFU +#define PMU_0P2A_TARGET0_0_S 23 +/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P2A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1c4) +/** PMU_ANA_0P2A_MUL_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_MUL_0 0x00000007U +#define PMU_ANA_0P2A_MUL_0_M (PMU_ANA_0P2A_MUL_0_V << PMU_ANA_0P2A_MUL_0_S) +#define PMU_ANA_0P2A_MUL_0_V 0x00000007U +#define PMU_ANA_0P2A_MUL_0_S 23 +/** PMU_ANA_0P2A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P2A_EN_VDET_0_M (PMU_ANA_0P2A_EN_VDET_0_V << PMU_ANA_0P2A_EN_VDET_0_S) +#define PMU_ANA_0P2A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P2A_EN_VDET_0_S 26 +/** PMU_ANA_0P2A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P2A_EN_CUR_LIM_0_M (PMU_ANA_0P2A_EN_CUR_LIM_0_V << PMU_ANA_0P2A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P2A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P2A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P2A_DREF_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P2A_DREF_0 0x0000000FU +#define PMU_ANA_0P2A_DREF_0_M (PMU_ANA_0P2A_DREF_0_V << PMU_ANA_0P2A_DREF_0_S) +#define PMU_ANA_0P2A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P2A_DREF_0_S 28 + +/** PMU_EXT_LDO_P0_0P3A_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8) +/** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P3A_FORCE_TIEH_SEL_0 (BIT(7)) +#define PMU_0P3A_FORCE_TIEH_SEL_0_M (PMU_0P3A_FORCE_TIEH_SEL_0_V << PMU_0P3A_FORCE_TIEH_SEL_0_S) +#define PMU_0P3A_FORCE_TIEH_SEL_0_V 0x00000001U +#define PMU_0P3A_FORCE_TIEH_SEL_0_S 7 +/** PMU_0P3A_XPD_0 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P3A_XPD_0 (BIT(8)) +#define PMU_0P3A_XPD_0_M (PMU_0P3A_XPD_0_V << PMU_0P3A_XPD_0_S) +#define PMU_0P3A_XPD_0_V 0x00000001U +#define PMU_0P3A_XPD_0_S 8 +/** PMU_0P3A_TIEH_SEL_0 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_SEL_0 0x00000007U +#define PMU_0P3A_TIEH_SEL_0_M (PMU_0P3A_TIEH_SEL_0_V << PMU_0P3A_TIEH_SEL_0_S) +#define PMU_0P3A_TIEH_SEL_0_V 0x00000007U +#define PMU_0P3A_TIEH_SEL_0_S 9 +/** PMU_0P3A_TIEH_POS_EN_0 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_POS_EN_0 (BIT(12)) +#define PMU_0P3A_TIEH_POS_EN_0_M (PMU_0P3A_TIEH_POS_EN_0_V << PMU_0P3A_TIEH_POS_EN_0_S) +#define PMU_0P3A_TIEH_POS_EN_0_V 0x00000001U +#define PMU_0P3A_TIEH_POS_EN_0_S 12 +/** PMU_0P3A_TIEH_NEG_EN_0 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_NEG_EN_0 (BIT(13)) +#define PMU_0P3A_TIEH_NEG_EN_0_M (PMU_0P3A_TIEH_NEG_EN_0_V << PMU_0P3A_TIEH_NEG_EN_0_S) +#define PMU_0P3A_TIEH_NEG_EN_0_V 0x00000001U +#define PMU_0P3A_TIEH_NEG_EN_0_S 13 +/** PMU_0P3A_TIEH_0 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_0 (BIT(14)) +#define PMU_0P3A_TIEH_0_M (PMU_0P3A_TIEH_0_V << PMU_0P3A_TIEH_0_S) +#define PMU_0P3A_TIEH_0_V 0x00000001U +#define PMU_0P3A_TIEH_0_S 14 +/** PMU_0P3A_TARGET1_0 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P3A_TARGET1_0 0x000000FFU +#define PMU_0P3A_TARGET1_0_M (PMU_0P3A_TARGET1_0_V << PMU_0P3A_TARGET1_0_S) +#define PMU_0P3A_TARGET1_0_V 0x000000FFU +#define PMU_0P3A_TARGET1_0_S 15 +/** PMU_0P3A_TARGET0_0 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P3A_TARGET0_0 0x000000FFU +#define PMU_0P3A_TARGET0_0_M (PMU_0P3A_TARGET0_0_V << PMU_0P3A_TARGET0_0_S) +#define PMU_0P3A_TARGET0_0_V 0x000000FFU +#define PMU_0P3A_TARGET0_0_S 23 +/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0 (BIT(31)) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_M (PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_V 0x00000001U +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_0_S 31 + +/** PMU_EXT_LDO_P0_0P3A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P0_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1cc) +/** PMU_ANA_0P3A_MUL_0 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_MUL_0 0x00000007U +#define PMU_ANA_0P3A_MUL_0_M (PMU_ANA_0P3A_MUL_0_V << PMU_ANA_0P3A_MUL_0_S) +#define PMU_ANA_0P3A_MUL_0_V 0x00000007U +#define PMU_ANA_0P3A_MUL_0_S 23 +/** PMU_ANA_0P3A_EN_VDET_0 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_VDET_0 (BIT(26)) +#define PMU_ANA_0P3A_EN_VDET_0_M (PMU_ANA_0P3A_EN_VDET_0_V << PMU_ANA_0P3A_EN_VDET_0_S) +#define PMU_ANA_0P3A_EN_VDET_0_V 0x00000001U +#define PMU_ANA_0P3A_EN_VDET_0_S 26 +/** PMU_ANA_0P3A_EN_CUR_LIM_0 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_CUR_LIM_0 (BIT(27)) +#define PMU_ANA_0P3A_EN_CUR_LIM_0_M (PMU_ANA_0P3A_EN_CUR_LIM_0_V << PMU_ANA_0P3A_EN_CUR_LIM_0_S) +#define PMU_ANA_0P3A_EN_CUR_LIM_0_V 0x00000001U +#define PMU_ANA_0P3A_EN_CUR_LIM_0_S 27 +/** PMU_ANA_0P3A_DREF_0 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P3A_DREF_0 0x0000000FU +#define PMU_ANA_0P3A_DREF_0_M (PMU_ANA_0P3A_DREF_0_V << PMU_ANA_0P3A_DREF_0_S) +#define PMU_ANA_0P3A_DREF_0_V 0x0000000FU +#define PMU_ANA_0P3A_DREF_0_S 28 + +/** PMU_EXT_LDO_P1_0P1A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0) +/** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P1A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P1A_FORCE_TIEH_SEL_1_M (PMU_0P1A_FORCE_TIEH_SEL_1_V << PMU_0P1A_FORCE_TIEH_SEL_1_S) +#define PMU_0P1A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P1A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P1A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P1A_XPD_1 (BIT(8)) +#define PMU_0P1A_XPD_1_M (PMU_0P1A_XPD_1_V << PMU_0P1A_XPD_1_S) +#define PMU_0P1A_XPD_1_V 0x00000001U +#define PMU_0P1A_XPD_1_S 8 +/** PMU_0P1A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_SEL_1 0x00000007U +#define PMU_0P1A_TIEH_SEL_1_M (PMU_0P1A_TIEH_SEL_1_V << PMU_0P1A_TIEH_SEL_1_S) +#define PMU_0P1A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P1A_TIEH_SEL_1_S 9 +/** PMU_0P1A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P1A_TIEH_POS_EN_1_M (PMU_0P1A_TIEH_POS_EN_1_V << PMU_0P1A_TIEH_POS_EN_1_S) +#define PMU_0P1A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P1A_TIEH_POS_EN_1_S 12 +/** PMU_0P1A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P1A_TIEH_NEG_EN_1_M (PMU_0P1A_TIEH_NEG_EN_1_V << PMU_0P1A_TIEH_NEG_EN_1_S) +#define PMU_0P1A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P1A_TIEH_NEG_EN_1_S 13 +/** PMU_0P1A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P1A_TIEH_1 (BIT(14)) +#define PMU_0P1A_TIEH_1_M (PMU_0P1A_TIEH_1_V << PMU_0P1A_TIEH_1_S) +#define PMU_0P1A_TIEH_1_V 0x00000001U +#define PMU_0P1A_TIEH_1_S 14 +/** PMU_0P1A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P1A_TARGET1_1 0x000000FFU +#define PMU_0P1A_TARGET1_1_M (PMU_0P1A_TARGET1_1_V << PMU_0P1A_TARGET1_1_S) +#define PMU_0P1A_TARGET1_1_V 0x000000FFU +#define PMU_0P1A_TARGET1_1_S 15 +/** PMU_0P1A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P1A_TARGET0_1 0x000000FFU +#define PMU_0P1A_TARGET0_1_M (PMU_0P1A_TARGET0_1_V << PMU_0P1A_TARGET0_1_S) +#define PMU_0P1A_TARGET0_1_V 0x000000FFU +#define PMU_0P1A_TARGET0_1_S 23 +/** PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P1A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P1A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P1A_ANA_REG (DR_REG_PMU_BASE + 0x1d4) +/** PMU_ANA_0P1A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_MUL_1 0x00000007U +#define PMU_ANA_0P1A_MUL_1_M (PMU_ANA_0P1A_MUL_1_V << PMU_ANA_0P1A_MUL_1_S) +#define PMU_ANA_0P1A_MUL_1_V 0x00000007U +#define PMU_ANA_0P1A_MUL_1_S 23 +/** PMU_ANA_0P1A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P1A_EN_VDET_1_M (PMU_ANA_0P1A_EN_VDET_1_V << PMU_ANA_0P1A_EN_VDET_1_S) +#define PMU_ANA_0P1A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P1A_EN_VDET_1_S 26 +/** PMU_ANA_0P1A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P1A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P1A_EN_CUR_LIM_1_M (PMU_ANA_0P1A_EN_CUR_LIM_1_V << PMU_ANA_0P1A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P1A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P1A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P1A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P1A_DREF_1 0x0000000FU +#define PMU_ANA_0P1A_DREF_1_M (PMU_ANA_0P1A_DREF_1_V << PMU_ANA_0P1A_DREF_1_S) +#define PMU_ANA_0P1A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P1A_DREF_1_S 28 + +/** PMU_EXT_LDO_P1_0P2A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8) +/** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P2A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P2A_FORCE_TIEH_SEL_1_M (PMU_0P2A_FORCE_TIEH_SEL_1_V << PMU_0P2A_FORCE_TIEH_SEL_1_S) +#define PMU_0P2A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P2A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P2A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P2A_XPD_1 (BIT(8)) +#define PMU_0P2A_XPD_1_M (PMU_0P2A_XPD_1_V << PMU_0P2A_XPD_1_S) +#define PMU_0P2A_XPD_1_V 0x00000001U +#define PMU_0P2A_XPD_1_S 8 +/** PMU_0P2A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_SEL_1 0x00000007U +#define PMU_0P2A_TIEH_SEL_1_M (PMU_0P2A_TIEH_SEL_1_V << PMU_0P2A_TIEH_SEL_1_S) +#define PMU_0P2A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P2A_TIEH_SEL_1_S 9 +/** PMU_0P2A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P2A_TIEH_POS_EN_1_M (PMU_0P2A_TIEH_POS_EN_1_V << PMU_0P2A_TIEH_POS_EN_1_S) +#define PMU_0P2A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P2A_TIEH_POS_EN_1_S 12 +/** PMU_0P2A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P2A_TIEH_NEG_EN_1_M (PMU_0P2A_TIEH_NEG_EN_1_V << PMU_0P2A_TIEH_NEG_EN_1_S) +#define PMU_0P2A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P2A_TIEH_NEG_EN_1_S 13 +/** PMU_0P2A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P2A_TIEH_1 (BIT(14)) +#define PMU_0P2A_TIEH_1_M (PMU_0P2A_TIEH_1_V << PMU_0P2A_TIEH_1_S) +#define PMU_0P2A_TIEH_1_V 0x00000001U +#define PMU_0P2A_TIEH_1_S 14 +/** PMU_0P2A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P2A_TARGET1_1 0x000000FFU +#define PMU_0P2A_TARGET1_1_M (PMU_0P2A_TARGET1_1_V << PMU_0P2A_TARGET1_1_S) +#define PMU_0P2A_TARGET1_1_V 0x000000FFU +#define PMU_0P2A_TARGET1_1_S 15 +/** PMU_0P2A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P2A_TARGET0_1 0x000000FFU +#define PMU_0P2A_TARGET0_1_M (PMU_0P2A_TARGET0_1_V << PMU_0P2A_TARGET0_1_S) +#define PMU_0P2A_TARGET0_1_V 0x000000FFU +#define PMU_0P2A_TARGET0_1_S 23 +/** PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P2A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P2A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P2A_ANA_REG (DR_REG_PMU_BASE + 0x1dc) +/** PMU_ANA_0P2A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_MUL_1 0x00000007U +#define PMU_ANA_0P2A_MUL_1_M (PMU_ANA_0P2A_MUL_1_V << PMU_ANA_0P2A_MUL_1_S) +#define PMU_ANA_0P2A_MUL_1_V 0x00000007U +#define PMU_ANA_0P2A_MUL_1_S 23 +/** PMU_ANA_0P2A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P2A_EN_VDET_1_M (PMU_ANA_0P2A_EN_VDET_1_V << PMU_ANA_0P2A_EN_VDET_1_S) +#define PMU_ANA_0P2A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P2A_EN_VDET_1_S 26 +/** PMU_ANA_0P2A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P2A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P2A_EN_CUR_LIM_1_M (PMU_ANA_0P2A_EN_CUR_LIM_1_V << PMU_ANA_0P2A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P2A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P2A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P2A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P2A_DREF_1 0x0000000FU +#define PMU_ANA_0P2A_DREF_1_M (PMU_ANA_0P2A_DREF_1_V << PMU_ANA_0P2A_DREF_1_S) +#define PMU_ANA_0P2A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P2A_DREF_1_S 28 + +/** PMU_EXT_LDO_P1_0P3A_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0) +/** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_0P3A_FORCE_TIEH_SEL_1 (BIT(7)) +#define PMU_0P3A_FORCE_TIEH_SEL_1_M (PMU_0P3A_FORCE_TIEH_SEL_1_V << PMU_0P3A_FORCE_TIEH_SEL_1_S) +#define PMU_0P3A_FORCE_TIEH_SEL_1_V 0x00000001U +#define PMU_0P3A_FORCE_TIEH_SEL_1_S 7 +/** PMU_0P3A_XPD_1 : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_0P3A_XPD_1 (BIT(8)) +#define PMU_0P3A_XPD_1_M (PMU_0P3A_XPD_1_V << PMU_0P3A_XPD_1_S) +#define PMU_0P3A_XPD_1_V 0x00000001U +#define PMU_0P3A_XPD_1_S 8 +/** PMU_0P3A_TIEH_SEL_1 : R/W; bitpos: [11:9]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_SEL_1 0x00000007U +#define PMU_0P3A_TIEH_SEL_1_M (PMU_0P3A_TIEH_SEL_1_V << PMU_0P3A_TIEH_SEL_1_S) +#define PMU_0P3A_TIEH_SEL_1_V 0x00000007U +#define PMU_0P3A_TIEH_SEL_1_S 9 +/** PMU_0P3A_TIEH_POS_EN_1 : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_POS_EN_1 (BIT(12)) +#define PMU_0P3A_TIEH_POS_EN_1_M (PMU_0P3A_TIEH_POS_EN_1_V << PMU_0P3A_TIEH_POS_EN_1_S) +#define PMU_0P3A_TIEH_POS_EN_1_V 0x00000001U +#define PMU_0P3A_TIEH_POS_EN_1_S 12 +/** PMU_0P3A_TIEH_NEG_EN_1 : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_NEG_EN_1 (BIT(13)) +#define PMU_0P3A_TIEH_NEG_EN_1_M (PMU_0P3A_TIEH_NEG_EN_1_V << PMU_0P3A_TIEH_NEG_EN_1_S) +#define PMU_0P3A_TIEH_NEG_EN_1_V 0x00000001U +#define PMU_0P3A_TIEH_NEG_EN_1_S 13 +/** PMU_0P3A_TIEH_1 : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_0P3A_TIEH_1 (BIT(14)) +#define PMU_0P3A_TIEH_1_M (PMU_0P3A_TIEH_1_V << PMU_0P3A_TIEH_1_S) +#define PMU_0P3A_TIEH_1_V 0x00000001U +#define PMU_0P3A_TIEH_1_S 14 +/** PMU_0P3A_TARGET1_1 : R/W; bitpos: [22:15]; default: 64; + * need_des + */ +#define PMU_0P3A_TARGET1_1 0x000000FFU +#define PMU_0P3A_TARGET1_1_M (PMU_0P3A_TARGET1_1_V << PMU_0P3A_TARGET1_1_S) +#define PMU_0P3A_TARGET1_1_V 0x000000FFU +#define PMU_0P3A_TARGET1_1_S 15 +/** PMU_0P3A_TARGET0_1 : R/W; bitpos: [30:23]; default: 128; + * need_des + */ +#define PMU_0P3A_TARGET0_1 0x000000FFU +#define PMU_0P3A_TARGET0_1_M (PMU_0P3A_TARGET0_1_V << PMU_0P3A_TARGET0_1_S) +#define PMU_0P3A_TARGET0_1_V 0x000000FFU +#define PMU_0P3A_TARGET0_1_S 23 +/** PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1 (BIT(31)) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_M (PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V << PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S) +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_V 0x00000001U +#define PMU_0P3A_LDO_CNT_PRESCALER_SEL_1_S 31 + +/** PMU_EXT_LDO_P1_0P3A_ANA_REG register + * need_des + */ +#define PMU_EXT_LDO_P1_0P3A_ANA_REG (DR_REG_PMU_BASE + 0x1e4) +/** PMU_ANA_0P3A_MUL_1 : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_MUL_1 0x00000007U +#define PMU_ANA_0P3A_MUL_1_M (PMU_ANA_0P3A_MUL_1_V << PMU_ANA_0P3A_MUL_1_S) +#define PMU_ANA_0P3A_MUL_1_V 0x00000007U +#define PMU_ANA_0P3A_MUL_1_S 23 +/** PMU_ANA_0P3A_EN_VDET_1 : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_VDET_1 (BIT(26)) +#define PMU_ANA_0P3A_EN_VDET_1_M (PMU_ANA_0P3A_EN_VDET_1_V << PMU_ANA_0P3A_EN_VDET_1_S) +#define PMU_ANA_0P3A_EN_VDET_1_V 0x00000001U +#define PMU_ANA_0P3A_EN_VDET_1_S 26 +/** PMU_ANA_0P3A_EN_CUR_LIM_1 : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_0P3A_EN_CUR_LIM_1 (BIT(27)) +#define PMU_ANA_0P3A_EN_CUR_LIM_1_M (PMU_ANA_0P3A_EN_CUR_LIM_1_V << PMU_ANA_0P3A_EN_CUR_LIM_1_S) +#define PMU_ANA_0P3A_EN_CUR_LIM_1_V 0x00000001U +#define PMU_ANA_0P3A_EN_CUR_LIM_1_S 27 +/** PMU_ANA_0P3A_DREF_1 : R/W; bitpos: [31:28]; default: 10; + * need_des + */ +#define PMU_ANA_0P3A_DREF_1 0x0000000FU +#define PMU_ANA_0P3A_DREF_1_M (PMU_ANA_0P3A_DREF_1_V << PMU_ANA_0P3A_DREF_1_S) +#define PMU_ANA_0P3A_DREF_1_V 0x0000000FU +#define PMU_ANA_0P3A_DREF_1_S 28 + +/** PMU_EXT_WAKEUP_LV_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_LV_REG (DR_REG_PMU_BASE + 0x1e8) +/** PMU_EXT_WAKEUP_LV : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_LV 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_LV_M (PMU_EXT_WAKEUP_LV_V << PMU_EXT_WAKEUP_LV_S) +#define PMU_EXT_WAKEUP_LV_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_LV_S 0 + +/** PMU_EXT_WAKEUP_SEL_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_SEL_REG (DR_REG_PMU_BASE + 0x1ec) +/** PMU_EXT_WAKEUP_SEL : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_SEL 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_SEL_M (PMU_EXT_WAKEUP_SEL_V << PMU_EXT_WAKEUP_SEL_S) +#define PMU_EXT_WAKEUP_SEL_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_SEL_S 0 + +/** PMU_EXT_WAKEUP_ST_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_ST_REG (DR_REG_PMU_BASE + 0x1f0) +/** PMU_EXT_WAKEUP_STATUS : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_STATUS 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_STATUS_M (PMU_EXT_WAKEUP_STATUS_V << PMU_EXT_WAKEUP_STATUS_S) +#define PMU_EXT_WAKEUP_STATUS_V 0xFFFFFFFFU +#define PMU_EXT_WAKEUP_STATUS_S 0 + +/** PMU_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define PMU_EXT_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f4) +/** PMU_EXT_WAKEUP_STATUS_CLR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_STATUS_CLR (BIT(30)) +#define PMU_EXT_WAKEUP_STATUS_CLR_M (PMU_EXT_WAKEUP_STATUS_CLR_V << PMU_EXT_WAKEUP_STATUS_CLR_S) +#define PMU_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define PMU_EXT_WAKEUP_STATUS_CLR_S 30 +/** PMU_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_EXT_WAKEUP_FILTER (BIT(31)) +#define PMU_EXT_WAKEUP_FILTER_M (PMU_EXT_WAKEUP_FILTER_V << PMU_EXT_WAKEUP_FILTER_S) +#define PMU_EXT_WAKEUP_FILTER_V 0x00000001U +#define PMU_EXT_WAKEUP_FILTER_S 31 + +/** PMU_SDIO_WAKEUP_CNTL_REG register + * need_des + */ +#define PMU_SDIO_WAKEUP_CNTL_REG (DR_REG_PMU_BASE + 0x1f8) +/** PMU_SDIO_ACT_DNUM : R/W; bitpos: [9:0]; default: 1023; + * need_des + */ +#define PMU_SDIO_ACT_DNUM 0x000003FFU +#define PMU_SDIO_ACT_DNUM_M (PMU_SDIO_ACT_DNUM_V << PMU_SDIO_ACT_DNUM_S) +#define PMU_SDIO_ACT_DNUM_V 0x000003FFU +#define PMU_SDIO_ACT_DNUM_S 0 + +/** PMU_XTAL_SLP_REG register + * need_des + */ +#define PMU_XTAL_SLP_REG (DR_REG_PMU_BASE + 0x1fc) +/** PMU_XTAL_SLP_CNT_TARGET : R/W; bitpos: [31:16]; default: 15; + * need_des + */ +#define PMU_XTAL_SLP_CNT_TARGET 0x0000FFFFU +#define PMU_XTAL_SLP_CNT_TARGET_M (PMU_XTAL_SLP_CNT_TARGET_V << PMU_XTAL_SLP_CNT_TARGET_S) +#define PMU_XTAL_SLP_CNT_TARGET_V 0x0000FFFFU +#define PMU_XTAL_SLP_CNT_TARGET_S 16 + +/** PMU_CPU_SW_STALL_REG register + * need_des + */ +#define PMU_CPU_SW_STALL_REG (DR_REG_PMU_BASE + 0x200) +/** PMU_HPCORE1_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * need_des + */ +#define PMU_HPCORE1_SW_STALL_CODE 0x000000FFU +#define PMU_HPCORE1_SW_STALL_CODE_M (PMU_HPCORE1_SW_STALL_CODE_V << PMU_HPCORE1_SW_STALL_CODE_S) +#define PMU_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define PMU_HPCORE1_SW_STALL_CODE_S 16 +/** PMU_HPCORE0_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * need_des + */ +#define PMU_HPCORE0_SW_STALL_CODE 0x000000FFU +#define PMU_HPCORE0_SW_STALL_CODE_M (PMU_HPCORE0_SW_STALL_CODE_V << PMU_HPCORE0_SW_STALL_CODE_S) +#define PMU_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define PMU_HPCORE0_SW_STALL_CODE_S 24 + +/** PMU_DCM_CTRL_REG register + * need_des + */ +#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x204) +/** PMU_DCDC_ON_REQ : WT; bitpos: [0]; default: 0; + * SW trigger dcdc on + */ +#define PMU_DCDC_ON_REQ (BIT(0)) +#define PMU_DCDC_ON_REQ_M (PMU_DCDC_ON_REQ_V << PMU_DCDC_ON_REQ_S) +#define PMU_DCDC_ON_REQ_V 0x00000001U +#define PMU_DCDC_ON_REQ_S 0 +/** PMU_DCDC_OFF_REQ : WT; bitpos: [1]; default: 0; + * SW trigger dcdc off + */ +#define PMU_DCDC_OFF_REQ (BIT(1)) +#define PMU_DCDC_OFF_REQ_M (PMU_DCDC_OFF_REQ_V << PMU_DCDC_OFF_REQ_S) +#define PMU_DCDC_OFF_REQ_V 0x00000001U +#define PMU_DCDC_OFF_REQ_S 1 +/** PMU_DCDC_LIGHTSLP_REQ : WT; bitpos: [2]; default: 0; + * SW trigger dcdc enter lightsleep + */ +#define PMU_DCDC_LIGHTSLP_REQ (BIT(2)) +#define PMU_DCDC_LIGHTSLP_REQ_M (PMU_DCDC_LIGHTSLP_REQ_V << PMU_DCDC_LIGHTSLP_REQ_S) +#define PMU_DCDC_LIGHTSLP_REQ_V 0x00000001U +#define PMU_DCDC_LIGHTSLP_REQ_S 2 +/** PMU_DCDC_DEEPSLP_REQ : WT; bitpos: [3]; default: 0; + * SW trigger dcdc enter deepsleep + */ +#define PMU_DCDC_DEEPSLP_REQ (BIT(3)) +#define PMU_DCDC_DEEPSLP_REQ_M (PMU_DCDC_DEEPSLP_REQ_V << PMU_DCDC_DEEPSLP_REQ_S) +#define PMU_DCDC_DEEPSLP_REQ_V 0x00000001U +#define PMU_DCDC_DEEPSLP_REQ_S 3 +/** PMU_DCDC_DONE_FORCE : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_DCDC_DONE_FORCE (BIT(7)) +#define PMU_DCDC_DONE_FORCE_M (PMU_DCDC_DONE_FORCE_V << PMU_DCDC_DONE_FORCE_S) +#define PMU_DCDC_DONE_FORCE_V 0x00000001U +#define PMU_DCDC_DONE_FORCE_S 7 +/** PMU_DCDC_ON_FORCE_PU : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_DCDC_ON_FORCE_PU (BIT(8)) +#define PMU_DCDC_ON_FORCE_PU_M (PMU_DCDC_ON_FORCE_PU_V << PMU_DCDC_ON_FORCE_PU_S) +#define PMU_DCDC_ON_FORCE_PU_V 0x00000001U +#define PMU_DCDC_ON_FORCE_PU_S 8 +/** PMU_DCDC_ON_FORCE_PD : R/W; bitpos: [9]; default: 0; + * need_des + */ +#define PMU_DCDC_ON_FORCE_PD (BIT(9)) +#define PMU_DCDC_ON_FORCE_PD_M (PMU_DCDC_ON_FORCE_PD_V << PMU_DCDC_ON_FORCE_PD_S) +#define PMU_DCDC_ON_FORCE_PD_V 0x00000001U +#define PMU_DCDC_ON_FORCE_PD_S 9 +/** PMU_DCDC_FB_RES_FORCE_PU : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_DCDC_FB_RES_FORCE_PU (BIT(10)) +#define PMU_DCDC_FB_RES_FORCE_PU_M (PMU_DCDC_FB_RES_FORCE_PU_V << PMU_DCDC_FB_RES_FORCE_PU_S) +#define PMU_DCDC_FB_RES_FORCE_PU_V 0x00000001U +#define PMU_DCDC_FB_RES_FORCE_PU_S 10 +/** PMU_DCDC_FB_RES_FORCE_PD : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_DCDC_FB_RES_FORCE_PD (BIT(11)) +#define PMU_DCDC_FB_RES_FORCE_PD_M (PMU_DCDC_FB_RES_FORCE_PD_V << PMU_DCDC_FB_RES_FORCE_PD_S) +#define PMU_DCDC_FB_RES_FORCE_PD_V 0x00000001U +#define PMU_DCDC_FB_RES_FORCE_PD_S 11 +/** PMU_DCDC_LS_FORCE_PU : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_DCDC_LS_FORCE_PU (BIT(12)) +#define PMU_DCDC_LS_FORCE_PU_M (PMU_DCDC_LS_FORCE_PU_V << PMU_DCDC_LS_FORCE_PU_S) +#define PMU_DCDC_LS_FORCE_PU_V 0x00000001U +#define PMU_DCDC_LS_FORCE_PU_S 12 +/** PMU_DCDC_LS_FORCE_PD : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_DCDC_LS_FORCE_PD (BIT(13)) +#define PMU_DCDC_LS_FORCE_PD_M (PMU_DCDC_LS_FORCE_PD_V << PMU_DCDC_LS_FORCE_PD_S) +#define PMU_DCDC_LS_FORCE_PD_V 0x00000001U +#define PMU_DCDC_LS_FORCE_PD_S 13 +/** PMU_DCDC_DS_FORCE_PU : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define PMU_DCDC_DS_FORCE_PU (BIT(14)) +#define PMU_DCDC_DS_FORCE_PU_M (PMU_DCDC_DS_FORCE_PU_V << PMU_DCDC_DS_FORCE_PU_S) +#define PMU_DCDC_DS_FORCE_PU_V 0x00000001U +#define PMU_DCDC_DS_FORCE_PU_S 14 +/** PMU_DCDC_DS_FORCE_PD : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DCDC_DS_FORCE_PD (BIT(15)) +#define PMU_DCDC_DS_FORCE_PD_M (PMU_DCDC_DS_FORCE_PD_V << PMU_DCDC_DS_FORCE_PD_S) +#define PMU_DCDC_DS_FORCE_PD_V 0x00000001U +#define PMU_DCDC_DS_FORCE_PD_S 15 +/** PMU_DCM_CUR_ST : RO; bitpos: [23:16]; default: 1; + * need_des + */ +#define PMU_DCM_CUR_ST 0x000000FFU +#define PMU_DCM_CUR_ST_M (PMU_DCM_CUR_ST_V << PMU_DCM_CUR_ST_S) +#define PMU_DCM_CUR_ST_V 0x000000FFU +#define PMU_DCM_CUR_ST_S 16 +/** PMU_DCDC_EN_AMUX_TEST : R/W; bitpos: [29]; default: 0; + * Enable analog mux to pull PAD TEST_DCDC voltage signal + */ +#define PMU_DCDC_EN_AMUX_TEST (BIT(29)) +#define PMU_DCDC_EN_AMUX_TEST_M (PMU_DCDC_EN_AMUX_TEST_V << PMU_DCDC_EN_AMUX_TEST_S) +#define PMU_DCDC_EN_AMUX_TEST_V 0x00000001U +#define PMU_DCDC_EN_AMUX_TEST_S 29 + +/** PMU_DCM_WAIT_DELAY_REG register + * need_des + */ +#define PMU_DCM_WAIT_DELAY_REG (DR_REG_PMU_BASE + 0x208) +/** PMU_DCDC_PRE_DELAY : R/W; bitpos: [7:0]; default: 5; + * DCDC pre-on/post off delay + */ +#define PMU_DCDC_PRE_DELAY 0x000000FFU +#define PMU_DCDC_PRE_DELAY_M (PMU_DCDC_PRE_DELAY_V << PMU_DCDC_PRE_DELAY_S) +#define PMU_DCDC_PRE_DELAY_V 0x000000FFU +#define PMU_DCDC_PRE_DELAY_S 0 +/** PMU_DCDC_RES_OFF_DELAY : R/W; bitpos: [15:8]; default: 2; + * DCDC fb res off delay + */ +#define PMU_DCDC_RES_OFF_DELAY 0x000000FFU +#define PMU_DCDC_RES_OFF_DELAY_M (PMU_DCDC_RES_OFF_DELAY_V << PMU_DCDC_RES_OFF_DELAY_S) +#define PMU_DCDC_RES_OFF_DELAY_V 0x000000FFU +#define PMU_DCDC_RES_OFF_DELAY_S 8 +/** PMU_DCDC_STABLE_DELAY : R/W; bitpos: [25:16]; default: 75; + * DCDC stable delay + */ +#define PMU_DCDC_STABLE_DELAY 0x000003FFU +#define PMU_DCDC_STABLE_DELAY_M (PMU_DCDC_STABLE_DELAY_V << PMU_DCDC_STABLE_DELAY_S) +#define PMU_DCDC_STABLE_DELAY_V 0x000003FFU +#define PMU_DCDC_STABLE_DELAY_S 16 + +/** PMU_VDDBAT_CFG_REG register + * need_des + */ +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x20c) +/** PMU_ANA_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; + * need_des + */ +#define PMU_ANA_VDDBAT_MODE 0x00000003U +#define PMU_ANA_VDDBAT_MODE_M (PMU_ANA_VDDBAT_MODE_V << PMU_ANA_VDDBAT_MODE_S) +#define PMU_ANA_VDDBAT_MODE_V 0x00000003U +#define PMU_ANA_VDDBAT_MODE_S 0 +/** PMU_VDDBAT_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDDBAT_SW_UPDATE (BIT(31)) +#define PMU_VDDBAT_SW_UPDATE_M (PMU_VDDBAT_SW_UPDATE_V << PMU_VDDBAT_SW_UPDATE_S) +#define PMU_VDDBAT_SW_UPDATE_V 0x00000001U +#define PMU_VDDBAT_SW_UPDATE_S 31 + +/** PMU_TOUCH_PWR_CNTL_REG register + * need_des + */ +#define PMU_TOUCH_PWR_CNTL_REG (DR_REG_PMU_BASE + 0x210) +/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [13:5]; default: 10; + * need_des + */ +#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) +#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_S 5 +/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 100; + * need_des + */ +#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) +#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_S 14 +/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TOUCH_FORCE_DONE (BIT(30)) +#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) +#define PMU_TOUCH_FORCE_DONE_V 0x00000001U +#define PMU_TOUCH_FORCE_DONE_S 30 +/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(31)) +#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) +#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U +#define PMU_TOUCH_SLEEP_TIMER_EN_S 31 + +/** PMU_RDN_ECO_REG register + * need_des + */ +#define PMU_RDN_ECO_REG (DR_REG_PMU_BASE + 0x214) +/** PMU_PMU_RDN_ECO_RESULT : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_PMU_RDN_ECO_RESULT (BIT(0)) +#define PMU_PMU_RDN_ECO_RESULT_M (PMU_PMU_RDN_ECO_RESULT_V << PMU_PMU_RDN_ECO_RESULT_S) +#define PMU_PMU_RDN_ECO_RESULT_V 0x00000001U +#define PMU_PMU_RDN_ECO_RESULT_S 0 +/** PMU_PMU_RDN_ECO_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_PMU_RDN_ECO_EN (BIT(31)) +#define PMU_PMU_RDN_ECO_EN_M (PMU_PMU_RDN_ECO_EN_V << PMU_PMU_RDN_ECO_EN_S) +#define PMU_PMU_RDN_ECO_EN_V 0x00000001U +#define PMU_PMU_RDN_ECO_EN_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36712768; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pmu_struct.h new file mode 100644 index 0000000000..8d9e91538a --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pmu_struct.h @@ -0,0 +1,942 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/pmu_reg.h" +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: IDF-13420 + +typedef union { + struct { + uint32_t reserved0 : 21; + uint32_t dcdc_switch_pd_en :1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 1; + uint32_t reserved1 : 6; + uint32_t cnnt_pd_en : 1; + uint32_t top_pd_en : 1; + }; + uint32_t val; +} pmu_hp_dig_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 23; + uint32_t power_det_bypass : 1; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; + }; + uint32_t val; +} pmu_hp_sys_cntl_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 21; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_pll_i2c : 4; + uint32_t xpd_pll : 4; + uint32_t reserved1 : 1; + }; + uint32_t val; +} pmu_hp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 18; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + uint32_t val; +} pmu_hp_bias_reg_t; + +typedef union { + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 2; + uint32_t hp_active_retention_mode : 1; + uint32_t hp_sleep2active_retention_en : 1; + uint32_t hp_modem2active_retention_en : 1; + uint32_t reserved2 : 1; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t reserved3 : 2; + uint32_t hp_sleep2active_backup_mode : 3; + uint32_t hp_modem2active_backup_mode : 3; + uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved5 : 1; + }; + struct { /* HP: Modem State */ + uint32_t reserved6 : 32; + }; + struct { /* HP: Sleep State */ + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t hp_sleep_retention_mode : 1; + uint32_t reserved13 : 1; + uint32_t hp_modem2sleep_retention_en : 1; + uint32_t hp_active2sleep_retention_en : 1; + uint32_t reserved14 : 2; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t reserved15 : 3; + uint32_t hp_modem2sleep_backup_mode : 3; + uint32_t hp_active2sleep_backup_mode : 3; + uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; + }; + uint32_t val; +} pmu_hp_backup_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; + }; + uint32_t val; +} pmu_hp_sysclk_reg_t; + +typedef union { + // For chip_revsion < 1.0 + struct { + uint32_t reserved0 : 4; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; /* slp_mem_dbias is not used on chip_revision < 100 */ + uint32_t slp_logic_dbias: 4; + uint32_t dbias : 5; + }; + // For chip revision >= 100 + struct { + uint32_t reserved1 : 19; + uint32_t xpd_0p1a : 4; /* slp_mem_dbias[3] is used to control the volt output of VO1 on chip_revision >= 1.0 */ + uint32_t reserved2 : 9; + }; + uint32_t val; +} pmu_hp_regulator0_reg_t; + +typedef union { + struct { + uint32_t reserved0: 26; + uint32_t drv_b : 6; + }; + uint32_t val; +} pmu_hp_regulator1_reg_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_hp_xtal_reg_t; + +typedef struct pmu_hp_hw_regmap_t { + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + uint32_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; + }; + uint32_t val; +} pmu_lp_regulator0_reg_t; + +typedef union { + struct { + uint32_t reserved0: 26; + uint32_t drv_b : 6; + }; + uint32_t val; +} pmu_lp_regulator1_reg_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; + }; + uint32_t val; +} pmu_lp_xtal_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 26; + uint32_t lp_pad_slp_sel : 1; + uint32_t bod_source_sel : 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en: 1; + }; + uint32_t val; +} pmu_lp_dig_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 27; + uint32_t xpd_lppll : 1; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; + }; + uint32_t val; +} pmu_lp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; + }; + uint32_t val; +} pmu_lp_bias_reg_t; + +typedef struct pmu_lp_hw_regmap_t { + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +} pmu_lp_hw_regmap_t; + + +typedef union { + struct { + uint32_t tie_low_cali_xtal_icg : 1; + uint32_t tie_low_global_pll_icg : 4; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_pll_i2c : 4; + uint32_t tie_low_xpd_pll : 4; + uint32_t tie_low_xpd_xtal : 1; + uint32_t tie_high_cali_xtal_icg : 1; + uint32_t tie_high_global_pll_icg : 4; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_pll_i2c : 4; + uint32_t tie_high_xpd_pll : 4; + uint32_t tie_high_xpd_xtal : 1; + }; + uint32_t val; +} pmu_imm_hp_clk_power_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +typedef union { + struct { + uint32_t pad_slp_sel : 1; + uint32_t lp_pad_hold_all : 1; + uint32_t hp_pad_hold_all : 1; + uint32_t reserved0 : 23; + uint32_t tie_high_pad_slp_sel : 1; + uint32_t tie_low_pad_slp_sel : 1; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; + }; + uint32_t val; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap_t { + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +typedef union { + struct { + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t reserved0 : 26; /* Invalid of lp peripherals */ + }; + uint32_t val; +} pmu_power_domain_cntl_reg_t; + +typedef union { + struct { + uint32_t pd_top_mask : 5; + uint32_t reserved0 : 22; /* Invalid of lp peripherals */ + uint32_t top_pd_mask : 5; + }; + uint32_t val; +} pmu_power_domain_mask_reg_t; + +typedef union { + struct { + uint32_t force_pu : 1; + uint32_t force_pd : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; +} pmu_power_dcdc_switch_reg_t; + +typedef union { + struct { + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +typedef union { + struct { + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; + }; + uint32_t val; +} pmu_power_clk_wait_cntl_reg_t; + +typedef struct pmu_power_hw_regmap_t { + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_domain_cntl_reg_t hp_pd[3]; + pmu_power_domain_mask_reg_t hp_pd_mask[3]; + pmu_power_dcdc_switch_reg_t dcdc_switch; + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_domain_mask_reg_t lp_peri_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t sleep_req: 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +typedef union { + struct { + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +typedef union { + struct { + uint32_t wakeup_ena: 31; + uint32_t reserved0 : 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +typedef union { + struct { + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +typedef union { + struct { + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +typedef union { + struct { + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 16; + uint32_t ana_wait_target: 16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t lp_lite_wakeup_ena : 1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl8_reg_t; + +typedef struct pmu_wakeup_hw_regmap_t { + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + pmu_slp_wakeup_cntl2_reg_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + pmu_slp_wakeup_cntl8_reg_t cntl8; + uint32_t status0; + uint32_t status1; + uint32_t status2; +} pmu_wakeup_hw_regmap_t; + +typedef union { + struct { + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; + }; + uint32_t val; +} pmu_hp_clk_poweron_reg_t; + +typedef union { + struct { + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; + }; + uint32_t val; +} pmu_hp_clk_cntl_reg_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t por_done : 1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 24; + uint32_t mspi_phy_xpd : 1; + uint32_t sdio_pll_xpd : 1; + uint32_t perif_i2c_rstb: 1; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_txrf_i2c : 1; + uint32_t xpd_rfrx_pbus : 1; + uint32_t xpd_ckgen_i2c : 1; + uint32_t reserved1 : 1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +typedef union { + struct { + uint32_t reserved0 : 14; + uint32_t pmu_0p1a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p1a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p1a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p1a_cnt_target1_reach_1 : 1; + uint32_t pmu_0p2a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p2a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p2a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p2a_cnt_target1_reach_1 : 1; + uint32_t pmu_0p3a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p3a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p3a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p3a_cnt_target1_reach_1 : 1; + uint32_t reserved1 : 1; + uint32_t lp_exception: 1; + uint32_t sdio_idle: 1; + uint32_t sw : 1; + uint32_t reject : 1; + uint32_t wakeup : 1; + }; + uint32_t val; +} pmu_hp_intr_reg_t; + +typedef struct pmu_hp_ext_hw_regmap_t { + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved0 : 13; + uint32_t sleep_reject : 1; + uint32_t pmu_0p1a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p1a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p1a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p1a_cnt_target1_reach_1 : 1; + uint32_t pmu_0p2a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p2a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p2a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p2a_cnt_target1_reach_1 : 1; + uint32_t pmu_0p3a_cnt_target0_reach_0 : 1; + uint32_t pmu_0p3a_cnt_target1_reach_0 : 1; + uint32_t pmu_0p3a_cnt_target0_reach_1 : 1; + uint32_t pmu_0p3a_cnt_target1_reach_1 : 1; + uint32_t lp_wakeup : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t active_switch_sleep_end : 1; + uint32_t sleep_switch_active_start : 1; + uint32_t active_switch_sleep_start : 1; + uint32_t hp_sw_trigger : 1; + }; + uint32_t val; +} pmu_lp_intr_reg_t; + +typedef union { + struct { + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +typedef union { + struct { + uint32_t reserved0: 31; + uint32_t sleep_req: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +typedef union { + struct { + uint32_t wakeup_en: 31; + uint32_t reserved0: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr2_reg_t; + +typedef union { + struct { + uint32_t wakeup_cause: 31; + uint32_t reserved0: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr3_reg_t; + +typedef union { + struct { + uint32_t sleep_reject: 31; + uint32_t reserved0: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr4_reg_t; + +typedef union { + struct { + uint32_t sleep_reject_cause: 31; + uint32_t reserved0: 1; + }; + uint32_t val; +} pmu_lp_cpu_pwr5_reg_t; + +typedef struct pmu_lp_ext_hw_regmap_t { + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; + pmu_lp_cpu_pwr2_reg_t pwr2; + pmu_lp_cpu_pwr3_reg_t pwr3; + pmu_lp_cpu_pwr4_reg_t pwr4; + pmu_lp_cpu_pwr5_reg_t pwr5; +} pmu_lp_ext_hw_regmap_t; + +typedef union { + struct { + uint32_t reserved_0:7; + uint32_t force_tieh_sel:1; + uint32_t xpd:1; + uint32_t tieh_sel:3; + uint32_t tieh_pos_en:1; + uint32_t tieh_neg_en:1; + uint32_t tieh:1; + uint32_t target1:8; + uint32_t target0:8; + uint32_t ldo_cnt_prescaler_sel:1; + }; + uint32_t val; +} pmu_ext_ldo_reg_t; + +typedef union { + struct { + uint32_t reserved_0:23; + uint32_t mul:3; + uint32_t en_vdet:1; + uint32_t en_cur_lim:1; + uint32_t dref:4; + }; + uint32_t val; +} pmu_ext_ldo_ana_reg_t; + + +typedef struct pmu_ext_ldo_info_t { + pmu_ext_ldo_reg_t pmu_ext_ldo; + pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana; +} pmu_ext_ldo_info_t; + + +typedef union { + struct { + uint32_t on_req : 1; + uint32_t off_req : 1; + uint32_t lightslp_req : 1; + uint32_t deepslp_req : 1; + uint32_t reserved0 : 3; + uint32_t done_force : 1; + uint32_t on_force_pu : 1; + uint32_t on_force_pd : 1; + uint32_t fb_res_force_pu : 1; + uint32_t fb_res_force_pd : 1; + uint32_t ls_force_pu : 1; + uint32_t ls_force_pd : 1; + uint32_t ds_force_pu : 1; + uint32_t ds_force_pd : 1; + uint32_t dcm_cur_st : 8; + uint32_t reserved1 : 5; + uint32_t en_amux_test : 1; + uint32_t reserved2 : 2; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +typedef union { + struct { + uint32_t pre_delay : 8; + uint32_t res_off_delay : 8; + uint32_t stable_delay : 10; + uint32_t reserved0 : 6; + }; + uint32_t val; +} pmu_dcm_wait_delay_t; + +typedef union { + struct { + uint32_t ana_vddbat_mode : 2; + uint32_t reserved1 : 29; + uint32_t sw_update : 1; + }; + uint32_t val; +} pmu_vddbat_cfg_t; + +typedef union { + struct { + uint32_t reserved0 : 5; + uint32_t wait_cycles : 9; + uint32_t sleep_cycles : 16; + uint32_t force_done : 1; + uint32_t sleep_timer_en : 1; + }; + uint32_t val; +} pmu_touch_sensor_pwr_cntl_t; + +typedef struct pmu_dev_t { + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; + + union { + struct { + volatile uint32_t reserved0 : 30; + volatile uint32_t lp_trigger_hp: 1; + volatile uint32_t hp_trigger_lp: 1; + }; + volatile uint32_t val; + } hp_lp_cpu_comm; + + union { + struct { + volatile uint32_t reserved0 : 31; + volatile uint32_t dig_regulator_en_cal: 1; + }; + volatile uint32_t val; + } hp_regulator_cfg; + + union { + struct { + volatile uint32_t en_cali_pmu_cntl : 1; + volatile uint32_t reserved0 : 10; + volatile uint32_t last_st : 7; + volatile uint32_t target_st : 7; + volatile uint32_t current_st: 7; + }; + volatile uint32_t val; + } main_state; + + union { + struct { + volatile uint32_t reserved0: 13; + volatile uint32_t backup_st: 5; + volatile uint32_t lp_pwr_st: 5; + volatile uint32_t hp_pwr_st: 9; + }; + volatile int32_t val; + } pwr_state; + + union { + struct { + volatile uint32_t stable_xpd_bbpll : 3; + volatile uint32_t stable_xpd_xtal : 1; + volatile uint32_t ana_xpd_pll_i2c : 3; + volatile uint32_t reserved0 : 3; + volatile uint32_t sysclk_slp_sel : 1; + volatile uint32_t sysclk_sel : 2; + volatile uint32_t sysclk_nodiv : 1; + volatile uint32_t icg_sysclk_en : 1; + volatile uint32_t icg_modem_switch : 1; + volatile uint32_t icg_modem_code : 2; + volatile uint32_t icg_slp_sel : 1; + volatile uint32_t icg_global_xtal : 1; + volatile uint32_t icg_global_pll : 4; + volatile uint32_t ana_i2c_iso_en : 1; + volatile uint32_t ana_i2c_retention: 1; + volatile uint32_t reserved1 : 1; + volatile uint32_t ana_xpd_pll : 4; + volatile uint32_t ana_xpd_xtal : 1; + }; + volatile uint32_t val; + } clk_state0; + + volatile uint32_t clk_state1; + volatile uint32_t clk_state2; + + volatile pmu_ext_ldo_info_t ext_ldo[6]; + + volatile uint32_t ext_wakeup_lv; + volatile uint32_t ext_wakeup_sel; + volatile uint32_t ext_wakeup_st; + union { + struct { + volatile uint32_t reserved0 : 30; + volatile uint32_t status_clr : 1; + volatile uint32_t filter : 1; + }; + volatile uint32_t val; + } ext_wakeup_cntl; + + union { + struct { + volatile uint32_t act_dnum : 10; + volatile uint32_t reserved0 : 22; + }; + volatile uint32_t val; + } sdio_wakeup_cntl; + + union { + struct { + volatile uint32_t reserved0 : 16; + volatile uint32_t cnt_target : 16; + }; + volatile uint32_t val; + } xtal_slp; + + union { + struct { + volatile uint32_t reserved0 : 16; + volatile uint32_t hpcore1_stall_code : 8; + volatile uint32_t hpcore0_stall_code : 8; + }; + volatile uint32_t val; + } cpu_sw_stall; + + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_wait_delay_t dcm_delay; + volatile pmu_vddbat_cfg_t vbat_cfg; + volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl; + + union { + struct { + volatile uint32_t eco_result:1; + volatile uint32_t reserved0 : 30; + volatile uint32_t eco_en: 1; + + }; + volatile uint32_t val; + } pmu_rdn_eco; + + + uint32_t reserved[121]; + + union { + struct { + volatile uint32_t pmu_date: 31; + volatile uint32_t clk_en : 1; + }; + volatile uint32_t val; + } date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); + +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ppa_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ppa_eco5_struct.h new file mode 100644 index 0000000000..4d0f664733 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ppa_eco5_struct.h @@ -0,0 +1,1025 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of blend0_clut_data register + * CLUT sram data read/write register in background plane of blender + */ +typedef union { + struct { + /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in background plane of blender engine through + * this field in fifo mode. + */ + uint32_t rdwr_word_blend0_clut:32; + }; + uint32_t val; +} ppa_blend0_clut_data_reg_t; + +/** Type of blend1_clut_data register + * CLUT sram data read/write register in foreground plane of blender + */ +typedef union { + struct { + /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in foreground plane of blender engine through + * this field in fifo mode. + */ + uint32_t rdwr_word_blend1_clut:32; + }; + uint32_t val; +} ppa_blend1_clut_data_reg_t; + +/** Type of clut_conf register + * CLUT configure register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register + * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access sr clut and should be 10 to access blend0 clut and should be + * 11 to access blend 1 clut in memory mode. + */ + uint32_t apb_fifo_mask:1; + /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND0 CLUT. + */ + uint32_t blend0_clut_mem_rst:1; + /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND1 CLUT. + */ + uint32_t blend1_clut_mem_rst:1; + /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + */ + uint32_t blend0_clut_mem_rdaddr_rst:1; + /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + */ + uint32_t blend1_clut_mem_rdaddr_rst:1; + /** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0; + * 1: force power down BLEND CLUT memory. + */ + uint32_t blend0_clut_mem_force_pd:1; + /** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0; + * 1: force power up BLEND CLUT memory. + */ + uint32_t blend0_clut_mem_force_pu:1; + /** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0; + * 1: Force clock on for BLEND CLUT memory. + */ + uint32_t blend0_clut_mem_clk_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ppa_clut_conf_reg_t; + +/** Type of sr_color_mode register + * Scaling and rotating engine color mode register + */ +typedef union { + struct { + /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: + * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. + */ + uint32_t sr_rx_cm:4; + /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; + * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. + * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. + */ + uint32_t sr_tx_cm:4; + /** yuv_rx_range : R/W; bitpos: [8]; default: 0; + * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + */ + uint32_t yuv_rx_range:1; + /** yuv_tx_range : R/W; bitpos: [9]; default: 0; + * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + */ + uint32_t yuv_tx_range:1; + /** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0; + * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + */ + uint32_t yuv2rgb_protocal:1; + /** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0; + * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + */ + uint32_t rgb2yuv_protocal:1; + /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t yuv422_rx_byte_order:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} ppa_sr_color_mode_reg_t; + +/** Type of blend_color_mode register + * blending engine color mode register + */ +typedef union { + struct { + /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY + */ + uint32_t blend0_rx_cm:4; + /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; + * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + */ + uint32_t blend1_rx_cm:4; + /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; + * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY + */ + uint32_t blend_tx_cm:4; + /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; + * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend0_rx_yuv_range:1; + /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; + * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend_tx_yuv_range:1; + /** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0; + * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend0_rx_yuv2rgb_protocal:1; + /** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0; + * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend_tx_rgb2yuv_protocal:1; + /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t blend0_rx_yuv422_byte_order:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} ppa_blend_color_mode_reg_t; + +/** Type of sr_byte_order register + * Scaling and rotating engine byte order register + */ +typedef union { + struct { + /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t sr_rx_byte_swap_en:1; + /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t sr_rx_rgb_swap_en:1; + /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to bypass the macro block order function. This function is used + * to improve efficient accessing external memory. + */ + uint32_t sr_macro_bk_ro_bypass:1; + /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; + * sel srm pix_blk size, 0:32x32, 1:16x16 + */ + uint32_t sr_bk_size_sel:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_sr_byte_order_reg_t; + +/** Type of blend_byte_order register + * Blending engine byte order register + */ +typedef union { + struct { + /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t blend0_rx_byte_swap_en:1; + /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t blend1_rx_byte_swap_en:1; + /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t blend0_rx_rgb_swap_en:1; + /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t blend1_rx_rgb_swap_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_blend_byte_order_reg_t; + +/** Type of blend_trans_mode register + * Blending engine mode configure register + */ +typedef union { + struct { + /** blend_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable alpha blending. + */ + uint32_t blend_en:1; + /** blend_bypass : R/W; bitpos: [1]; default: 0; + * Set this bit to bypass blender. Then background date would be output. + */ + uint32_t blend_bypass:1; + /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0; + * This bit is used to enable fix pixel filling. When this mode is enable only Tx + * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + */ + uint32_t blend_fix_pixel_fill_en:1; + /** blend_trans_mode_update : WT; bitpos: [3]; default: 0; + * Set this bit to update the transfer mode. Only the bit is set the transfer mode is + * valid. + */ + uint32_t blend_trans_mode_update:1; + /** blend_rst : R/W; bitpos: [4]; default: 0; + * write 1 then write 0 to reset blending engine. + */ + uint32_t blend_rst:1; + /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; + * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and + * ls_enc + */ + uint32_t blend_tx_inf_sel:2; + uint32_t reserved_7:25; + }; + uint32_t val; +} ppa_blend_trans_mode_reg_t; + +/** Type of sr_fix_alpha register + * Scaling and rotating engine alpha override register + */ +typedef union { + struct { + /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for Scaling and Rotating + * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t sr_rx_fix_alpha:8; + /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t sr_rx_alpha_mod:2; + /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t sr_rx_alpha_inv:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} ppa_sr_fix_alpha_reg_t; + +/** Type of blend_tx_size register + * Fix pixel filling mode image size register + */ +typedef union { + struct { + /** blend_hb : R/W; bitpos: [13:0]; default: 0; + * The horizontal width of image block that would be filled in fix pixel filling mode + * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 + */ + uint32_t blend_hb:14; + /** blend_vb : R/W; bitpos: [27:14]; default: 0; + * The vertical width of image block that would be filled in fix pixel filling mode or + * blend mode. The unit is pixel. Must be even num when YUV420 + */ + uint32_t blend_vb:14; + uint32_t reserved_28:4; + }; + uint32_t val; +} ppa_blend_tx_size_reg_t; + +/** Type of blend_fix_alpha register + * Blending engine alpha override register + */ +typedef union { + struct { + /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for background plane of + * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t blend0_rx_fix_alpha:8; + /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128; + * The value would replace the alpha value in received pixel for foreground plane of + * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t blend1_rx_fix_alpha:8; + /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t blend0_rx_alpha_mod:2; + /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t blend1_rx_alpha_mod:2; + /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t blend0_rx_alpha_inv:1; + /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t blend1_rx_alpha_inv:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ppa_blend_fix_alpha_reg_t; + +/** Type of blend_rgb register + * RGB color register + */ +typedef union { + struct { + /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128; + * blue color for A4/A8 mode. + */ + uint32_t blend1_rx_b:8; + /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128; + * green color for A4/A8 mode. + */ + uint32_t blend1_rx_g:8; + /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128; + * red color for A4/A8 mode. + */ + uint32_t blend1_rx_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_blend_rgb_reg_t; + +/** Type of blend_fix_pixel register + * Blending engine fix pixel register + */ +typedef union { + struct { + /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0; + * The configure fix pixel in fix pixel filling mode for blender engine. + */ + uint32_t blend_tx_fix_pixel:32; + }; + uint32_t val; +} ppa_blend_fix_pixel_reg_t; + +/** Type of ck_fg_low register + * foreground color key lower threshold + */ +typedef union { + struct { + /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of foreground b channel + */ + uint32_t colorkey_fg_b_low:8; + /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of foreground g channel + */ + uint32_t colorkey_fg_g_low:8; + /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of foreground r channel + */ + uint32_t colorkey_fg_r_low:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_fg_low_reg_t; + +/** Type of ck_fg_high register + * foreground color key higher threshold + */ +typedef union { + struct { + /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of foreground b channel + */ + uint32_t colorkey_fg_b_high:8; + /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of foreground g channel + */ + uint32_t colorkey_fg_g_high:8; + /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of foreground r channel + */ + uint32_t colorkey_fg_r_high:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_fg_high_reg_t; + +/** Type of ck_bg_low register + * background color key lower threshold + */ +typedef union { + struct { + /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of background b channel + */ + uint32_t colorkey_bg_b_low:8; + /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of background g channel + */ + uint32_t colorkey_bg_g_low:8; + /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of background r channel + */ + uint32_t colorkey_bg_r_low:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_bg_low_reg_t; + +/** Type of ck_bg_high register + * background color key higher threshold + */ +typedef union { + struct { + /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of background b channel + */ + uint32_t colorkey_bg_b_high:8; + /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of background g channel + */ + uint32_t colorkey_bg_g_high:8; + /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of background r channel + */ + uint32_t colorkey_bg_r_high:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_bg_high_reg_t; + +/** Type of ck_default register + * default value when foreground and background both in color key range + */ +typedef union { + struct { + /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; + * default B channel value of color key + */ + uint32_t colorkey_default_b:8; + /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; + * default G channel value of color key + */ + uint32_t colorkey_default_g:8; + /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; + * default R channel value of color key + */ + uint32_t colorkey_default_r:8; + /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; + * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the + * result is fg + */ + uint32_t colorkey_fg_bg_reverse:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} ppa_ck_default_reg_t; + +/** Type of sr_scal_rotate register + * Scaling and rotating coefficient register + */ +typedef union { + struct { + /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1; + * The integrated part of scaling coefficient in X direction. + */ + uint32_t sr_scal_x_int:8; + /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0; + * The fragment part of scaling coefficient in X direction. + */ + uint32_t sr_scal_x_frag:4; + /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1; + * The integrated part of scaling coefficient in Y direction. + */ + uint32_t sr_scal_y_int:8; + /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0; + * The fragment part of scaling coefficient in Y direction. + */ + uint32_t sr_scal_y_frag:4; + /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0; + * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + */ + uint32_t sr_rotate_angle:2; + /** scal_rotate_rst : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset scaling and rotating engine. + */ + uint32_t scal_rotate_rst:1; + /** scal_rotate_start : WT; bitpos: [27]; default: 0; + * Write 1 to enable scaling and rotating engine after parameter is configured. + */ + uint32_t scal_rotate_start:1; + /** sr_mirror_x : R/W; bitpos: [28]; default: 0; + * Image mirror in X direction. 0: disable, 1: enable + */ + uint32_t sr_mirror_x:1; + /** sr_mirror_y : R/W; bitpos: [29]; default: 0; + * Image mirror in Y direction. 0: disable, 1: enable + */ + uint32_t sr_mirror_y:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ppa_sr_scal_rotate_reg_t; + +/** Type of sr_mem_pd register + * SR memory power done register + */ +typedef union { + struct { + /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to force clock enable of scaling and rotating engine's data memory. + */ + uint32_t sr_mem_clk_ena:1; + /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force power down scaling and rotating engine's data memory. + */ + uint32_t sr_mem_force_pd:1; + /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up scaling and rotating engine's data memory. + */ + uint32_t sr_mem_force_pu:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_sr_mem_pd_reg_t; + +/** Type of reg_conf register + * Register clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * PPA register clock gate enable signal. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ppa_reg_conf_reg_t; + +/** Type of eco_low register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rnd_eco_low:32; + }; + uint32_t val; +} ppa_eco_low_reg_t; + +/** Type of eco_high register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t rnd_eco_high:32; + }; + uint32_t val; +} ppa_eco_high_reg_t; + +/** Type of sram_ctrl register + * PPA SRAM Control Register + */ +typedef union { + struct { + /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ + uint32_t mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} ppa_sram_ctrl_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Raw status interrupt + */ +typedef union { + struct { + /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when scaling and rotating engine + * calculate one frame image. + */ + uint32_t sr_eof_int_raw:1; + /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when blending engine calculate one frame + * image. + */ + uint32_t blend_eof_int_raw:1; + /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the configured scaling and rotating + * coefficient is wrong. User can check the reasons through register + * PPA_SR_PARAM_ERR_ST_REG. + */ + uint32_t sr_param_cfg_err_int_raw:1; + /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the configured blending coefficient + * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. + */ + uint32_t blend_param_cfg_err_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt + */ +typedef union { + struct { + /** sr_eof_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_st:1; + /** blend_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_st:1; + /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_st:1; + /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_ena:1; + /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_ena:1; + /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_ena:1; + /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** sr_eof_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_clr:1; + /** blend_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_clr:1; + /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_clr:1; + /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of clut_cnt register + * BLEND CLUT write counter register + */ +typedef union { + struct { + /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0; + * The write data counter of BLEND0 CLUT in fifo mode. + */ + uint32_t blend0_clut_cnt:9; + /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0; + * The write data counter of BLEND1 CLUT in fifo mode. + */ + uint32_t blend1_clut_cnt:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} ppa_clut_cnt_reg_t; + +/** Type of blend_st register + * Blending engine status register + */ +typedef union { + struct { + /** blend_size_diff_st : RO; bitpos: [0]; default: 0; + * 1: indicate the size of two image is different. + */ + uint32_t blend_size_diff_st:1; + /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; + * Represents that x param is an odd num when enable yuv422 or yuv420 + */ + uint32_t blend_yuv_x_scale_err_st:1; + /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; + * Represents that y param is an odd num when enable yuv420 + */ + uint32_t blend_yuv_y_scale_err_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_blend_st_reg_t; + +/** Type of sr_param_err_st register + * Scaling and rotating coefficient error register + */ +typedef union { + struct { + /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0; + * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive + * descriptor is larger than VA in 2DDMA receive descriptor. + */ + uint32_t tx_dscr_vb_err_st:1; + /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0; + * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive + * descriptor is larger than HA in 2DDMA receive descriptor. + */ + uint32_t tx_dscr_hb_err_st:1; + /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0; + * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + */ + uint32_t y_rx_scal_equal_0_err_st:1; + /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0; + * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in + * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + */ + uint32_t rx_dscr_vb_err_st:1; + /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0; + * The error is that the scaled image width is 0. For example. when source width is + * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as + * the result would be floored. + */ + uint32_t ydst_len_too_samll_err_st:1; + /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0; + * The error is that the scaled width is larger than (2^13 - 1). + */ + uint32_t ydst_len_too_large_err_st:1; + /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0; + * The error is that the scaled image height is 0. + */ + uint32_t x_rx_scal_equal_0_err_st:1; + /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0; + * The error is that the HB in 2DDMA transmit descriptor plus the offset of X + * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit + * descriptor. + */ + uint32_t rx_dscr_hb_err_st:1; + /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0; + * The error is that the scaled image height is 0. For example. when source height is + * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as + * the result would be floored. + */ + uint32_t xdst_len_too_samll_err_st:1; + /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0; + * The error is that the scaled image height is larger than (2^13 - 1). + */ + uint32_t xdst_len_too_large_err_st:1; + /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv422 or yuv420 rx + */ + uint32_t x_yuv420_rx_scale_err_st:1; + /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 rx + */ + uint32_t y_yuv420_rx_scale_err_st:1; + /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv422 or yuv420 tx + */ + uint32_t x_yuv420_tx_scale_err_st:1; + /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 tx + */ + uint32_t y_yuv420_tx_scale_err_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} ppa_sr_param_err_st_reg_t; + +/** Type of sr_status register + * SR FSM register + */ +typedef union { + struct { + /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0; + * Reserved. + */ + uint32_t sr_rx_dscr_sample_state:2; + /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0; + * Reserved. + */ + uint32_t sr_rx_scan_state:2; + /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0; + * Reserved. + */ + uint32_t sr_tx_dscr_sample_state:2; + /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0; + * Reserved. + */ + uint32_t sr_tx_scan_state:3; + uint32_t reserved_9:23; + }; + uint32_t val; +} ppa_sr_status_reg_t; + +/** Type of eco_cell_ctrl register + * Reserved. + */ +typedef union { + struct { + /** rdn_result : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t rdn_result:1; + /** rdn_ena : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t rdn_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ppa_eco_cell_ctrl_reg_t; + + +/** Group: Debug Register */ +/** Type of debug_ctrl0 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx + * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: + * blend output + */ + uint32_t dbg_replace_sel:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_debug_ctrl0_reg_t; + +/** Type of debug_ctrl1 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; + * Configures the replace data + */ + uint32_t dbg_replace_data:32; + }; + uint32_t val; +} ppa_debug_ctrl1_reg_t; + + +/** Group: Configuration Register */ +/** Type of rgb2gray register + * rgb2gray register + */ +typedef union { + struct { + /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; + * Configures the b parameter for rgb2gray + */ + uint32_t rgb2gray_b:8; + /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; + * Configures the g parameter for rgb2gray + */ + uint32_t rgb2gray_g:8; + /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; + * Configures the r parameter for rgb2gray + */ + uint32_t rgb2gray_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_rgb2gray_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PPA Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 539234848; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} ppa_date_reg_t; + + +typedef struct ppa_dev_t { + volatile ppa_blend0_clut_data_reg_t blend0_clut_data; + volatile ppa_blend1_clut_data_reg_t blend1_clut_data; + uint32_t reserved_008; + volatile ppa_clut_conf_reg_t clut_conf; + volatile ppa_int_raw_reg_t int_raw; + volatile ppa_int_st_reg_t int_st; + volatile ppa_int_ena_reg_t int_ena; + volatile ppa_int_clr_reg_t int_clr; + volatile ppa_sr_color_mode_reg_t sr_color_mode; + volatile ppa_blend_color_mode_reg_t blend_color_mode; + volatile ppa_sr_byte_order_reg_t sr_byte_order; + volatile ppa_blend_byte_order_reg_t blend_byte_order; + uint32_t reserved_030; + volatile ppa_blend_trans_mode_reg_t blend_trans_mode; + volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha; + volatile ppa_blend_tx_size_reg_t blend_tx_size; + volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha; + uint32_t reserved_044; + volatile ppa_blend_rgb_reg_t blend_rgb; + volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel; + volatile ppa_ck_fg_low_reg_t ck_fg_low; + volatile ppa_ck_fg_high_reg_t ck_fg_high; + volatile ppa_ck_bg_low_reg_t ck_bg_low; + volatile ppa_ck_bg_high_reg_t ck_bg_high; + volatile ppa_ck_default_reg_t ck_default; + volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate; + volatile ppa_sr_mem_pd_reg_t sr_mem_pd; + volatile ppa_reg_conf_reg_t reg_conf; + volatile ppa_clut_cnt_reg_t clut_cnt; + volatile ppa_blend_st_reg_t blend_st; + volatile ppa_sr_param_err_st_reg_t sr_param_err_st; + volatile ppa_sr_status_reg_t sr_status; + volatile ppa_eco_low_reg_t eco_low; + volatile ppa_eco_high_reg_t eco_high; + volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; + volatile ppa_sram_ctrl_reg_t sram_ctrl; + volatile ppa_debug_ctrl0_reg_t debug_ctrl0; + volatile ppa_debug_ctrl1_reg_t debug_ctrl1; + volatile ppa_rgb2gray_reg_t rgb2gray; + uint32_t reserved_09c[25]; + volatile ppa_date_reg_t date; +} ppa_dev_t; + +extern ppa_dev_t PPA; + +#ifndef __cplusplus +_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ppa_reg.h new file mode 100644 index 0000000000..f843b5b49d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ppa_reg.h @@ -0,0 +1,1185 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PPA_BLEND0_CLUT_DATA_REG register + * CLUT sram data read/write register in background plane of blender + */ +#define PPA_BLEND0_CLUT_DATA_REG (DR_REG_PPA_BASE + 0x0) +/** PPA_RDWR_WORD_BLEND0_CLUT : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in background plane of blender engine through + * this field in fifo mode. + */ +#define PPA_RDWR_WORD_BLEND0_CLUT 0xFFFFFFFFU +#define PPA_RDWR_WORD_BLEND0_CLUT_M (PPA_RDWR_WORD_BLEND0_CLUT_V << PPA_RDWR_WORD_BLEND0_CLUT_S) +#define PPA_RDWR_WORD_BLEND0_CLUT_V 0xFFFFFFFFU +#define PPA_RDWR_WORD_BLEND0_CLUT_S 0 + +/** PPA_BLEND1_CLUT_DATA_REG register + * CLUT sram data read/write register in foreground plane of blender + */ +#define PPA_BLEND1_CLUT_DATA_REG (DR_REG_PPA_BASE + 0x4) +/** PPA_RDWR_WORD_BLEND1_CLUT : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in foreground plane of blender engine through + * this field in fifo mode. + */ +#define PPA_RDWR_WORD_BLEND1_CLUT 0xFFFFFFFFU +#define PPA_RDWR_WORD_BLEND1_CLUT_M (PPA_RDWR_WORD_BLEND1_CLUT_V << PPA_RDWR_WORD_BLEND1_CLUT_S) +#define PPA_RDWR_WORD_BLEND1_CLUT_V 0xFFFFFFFFU +#define PPA_RDWR_WORD_BLEND1_CLUT_S 0 + +/** PPA_CLUT_CONF_REG register + * CLUT configure register + */ +#define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc) +/** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register + * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access sr clut and should be 10 to access blend0 clut and should be + * 11 to access blend 1 clut in memory mode. + */ +#define PPA_APB_FIFO_MASK (BIT(0)) +#define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S) +#define PPA_APB_FIFO_MASK_V 0x00000001U +#define PPA_APB_FIFO_MASK_S 0 +/** PPA_BLEND0_CLUT_MEM_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND0 CLUT. + */ +#define PPA_BLEND0_CLUT_MEM_RST (BIT(1)) +#define PPA_BLEND0_CLUT_MEM_RST_M (PPA_BLEND0_CLUT_MEM_RST_V << PPA_BLEND0_CLUT_MEM_RST_S) +#define PPA_BLEND0_CLUT_MEM_RST_V 0x00000001U +#define PPA_BLEND0_CLUT_MEM_RST_S 1 +/** PPA_BLEND1_CLUT_MEM_RST : R/W; bitpos: [2]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND1 CLUT. + */ +#define PPA_BLEND1_CLUT_MEM_RST (BIT(2)) +#define PPA_BLEND1_CLUT_MEM_RST_M (PPA_BLEND1_CLUT_MEM_RST_V << PPA_BLEND1_CLUT_MEM_RST_S) +#define PPA_BLEND1_CLUT_MEM_RST_V 0x00000001U +#define PPA_BLEND1_CLUT_MEM_RST_S 2 +/** PPA_BLEND0_CLUT_MEM_RDADDR_RST : R/W; bitpos: [3]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + */ +#define PPA_BLEND0_CLUT_MEM_RDADDR_RST (BIT(3)) +#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_M (PPA_BLEND0_CLUT_MEM_RDADDR_RST_V << PPA_BLEND0_CLUT_MEM_RDADDR_RST_S) +#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_V 0x00000001U +#define PPA_BLEND0_CLUT_MEM_RDADDR_RST_S 3 +/** PPA_BLEND1_CLUT_MEM_RDADDR_RST : R/W; bitpos: [4]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + */ +#define PPA_BLEND1_CLUT_MEM_RDADDR_RST (BIT(4)) +#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_M (PPA_BLEND1_CLUT_MEM_RDADDR_RST_V << PPA_BLEND1_CLUT_MEM_RDADDR_RST_S) +#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_V 0x00000001U +#define PPA_BLEND1_CLUT_MEM_RDADDR_RST_S 4 +/** PPA_BLEND0_CLUT_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; + * 1: force power down BLEND CLUT memory. + */ +#define PPA_BLEND0_CLUT_MEM_FORCE_PD (BIT(5)) +#define PPA_BLEND0_CLUT_MEM_FORCE_PD_M (PPA_BLEND0_CLUT_MEM_FORCE_PD_V << PPA_BLEND0_CLUT_MEM_FORCE_PD_S) +#define PPA_BLEND0_CLUT_MEM_FORCE_PD_V 0x00000001U +#define PPA_BLEND0_CLUT_MEM_FORCE_PD_S 5 +/** PPA_BLEND0_CLUT_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; + * 1: force power up BLEND CLUT memory. + */ +#define PPA_BLEND0_CLUT_MEM_FORCE_PU (BIT(6)) +#define PPA_BLEND0_CLUT_MEM_FORCE_PU_M (PPA_BLEND0_CLUT_MEM_FORCE_PU_V << PPA_BLEND0_CLUT_MEM_FORCE_PU_S) +#define PPA_BLEND0_CLUT_MEM_FORCE_PU_V 0x00000001U +#define PPA_BLEND0_CLUT_MEM_FORCE_PU_S 6 +/** PPA_BLEND0_CLUT_MEM_CLK_ENA : R/W; bitpos: [7]; default: 0; + * 1: Force clock on for BLEND CLUT memory. + */ +#define PPA_BLEND0_CLUT_MEM_CLK_ENA (BIT(7)) +#define PPA_BLEND0_CLUT_MEM_CLK_ENA_M (PPA_BLEND0_CLUT_MEM_CLK_ENA_V << PPA_BLEND0_CLUT_MEM_CLK_ENA_S) +#define PPA_BLEND0_CLUT_MEM_CLK_ENA_V 0x00000001U +#define PPA_BLEND0_CLUT_MEM_CLK_ENA_S 7 + +/** PPA_INT_RAW_REG register + * Raw status interrupt + */ +#define PPA_INT_RAW_REG (DR_REG_PPA_BASE + 0x10) +/** PPA_SR_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when scaling and rotating engine + * calculate one frame image. + */ +#define PPA_SR_EOF_INT_RAW (BIT(0)) +#define PPA_SR_EOF_INT_RAW_M (PPA_SR_EOF_INT_RAW_V << PPA_SR_EOF_INT_RAW_S) +#define PPA_SR_EOF_INT_RAW_V 0x00000001U +#define PPA_SR_EOF_INT_RAW_S 0 +/** PPA_BLEND_EOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when blending engine calculate one frame + * image. + */ +#define PPA_BLEND_EOF_INT_RAW (BIT(1)) +#define PPA_BLEND_EOF_INT_RAW_M (PPA_BLEND_EOF_INT_RAW_V << PPA_BLEND_EOF_INT_RAW_S) +#define PPA_BLEND_EOF_INT_RAW_V 0x00000001U +#define PPA_BLEND_EOF_INT_RAW_S 1 +/** PPA_SR_PARAM_CFG_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the configured scaling and rotating + * coefficient is wrong. User can check the reasons through register + * PPA_SR_PARAM_ERR_ST_REG. + */ +#define PPA_SR_PARAM_CFG_ERR_INT_RAW (BIT(2)) +#define PPA_SR_PARAM_CFG_ERR_INT_RAW_M (PPA_SR_PARAM_CFG_ERR_INT_RAW_V << PPA_SR_PARAM_CFG_ERR_INT_RAW_S) +#define PPA_SR_PARAM_CFG_ERR_INT_RAW_V 0x00000001U +#define PPA_SR_PARAM_CFG_ERR_INT_RAW_S 2 +/** PPA_BLEND_PARAM_CFG_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the configured blending coefficient + * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. + */ +#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW (BIT(3)) +#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_M (PPA_BLEND_PARAM_CFG_ERR_INT_RAW_V << PPA_BLEND_PARAM_CFG_ERR_INT_RAW_S) +#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_V 0x00000001U +#define PPA_BLEND_PARAM_CFG_ERR_INT_RAW_S 3 + +/** PPA_INT_ST_REG register + * Masked interrupt + */ +#define PPA_INT_ST_REG (DR_REG_PPA_BASE + 0x14) +/** PPA_SR_EOF_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + */ +#define PPA_SR_EOF_INT_ST (BIT(0)) +#define PPA_SR_EOF_INT_ST_M (PPA_SR_EOF_INT_ST_V << PPA_SR_EOF_INT_ST_S) +#define PPA_SR_EOF_INT_ST_V 0x00000001U +#define PPA_SR_EOF_INT_ST_S 0 +/** PPA_BLEND_EOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + */ +#define PPA_BLEND_EOF_INT_ST (BIT(1)) +#define PPA_BLEND_EOF_INT_ST_M (PPA_BLEND_EOF_INT_ST_V << PPA_BLEND_EOF_INT_ST_S) +#define PPA_BLEND_EOF_INT_ST_V 0x00000001U +#define PPA_BLEND_EOF_INT_ST_S 1 +/** PPA_SR_PARAM_CFG_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. + */ +#define PPA_SR_PARAM_CFG_ERR_INT_ST (BIT(2)) +#define PPA_SR_PARAM_CFG_ERR_INT_ST_M (PPA_SR_PARAM_CFG_ERR_INT_ST_V << PPA_SR_PARAM_CFG_ERR_INT_ST_S) +#define PPA_SR_PARAM_CFG_ERR_INT_ST_V 0x00000001U +#define PPA_SR_PARAM_CFG_ERR_INT_ST_S 2 +/** PPA_BLEND_PARAM_CFG_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ +#define PPA_BLEND_PARAM_CFG_ERR_INT_ST (BIT(3)) +#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_M (PPA_BLEND_PARAM_CFG_ERR_INT_ST_V << PPA_BLEND_PARAM_CFG_ERR_INT_ST_S) +#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_V 0x00000001U +#define PPA_BLEND_PARAM_CFG_ERR_INT_ST_S 3 + +/** PPA_INT_ENA_REG register + * Interrupt enable bits + */ +#define PPA_INT_ENA_REG (DR_REG_PPA_BASE + 0x18) +/** PPA_SR_EOF_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + */ +#define PPA_SR_EOF_INT_ENA (BIT(0)) +#define PPA_SR_EOF_INT_ENA_M (PPA_SR_EOF_INT_ENA_V << PPA_SR_EOF_INT_ENA_S) +#define PPA_SR_EOF_INT_ENA_V 0x00000001U +#define PPA_SR_EOF_INT_ENA_S 0 +/** PPA_BLEND_EOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + */ +#define PPA_BLEND_EOF_INT_ENA (BIT(1)) +#define PPA_BLEND_EOF_INT_ENA_M (PPA_BLEND_EOF_INT_ENA_V << PPA_BLEND_EOF_INT_ENA_S) +#define PPA_BLEND_EOF_INT_ENA_V 0x00000001U +#define PPA_BLEND_EOF_INT_ENA_S 1 +/** PPA_SR_PARAM_CFG_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. + */ +#define PPA_SR_PARAM_CFG_ERR_INT_ENA (BIT(2)) +#define PPA_SR_PARAM_CFG_ERR_INT_ENA_M (PPA_SR_PARAM_CFG_ERR_INT_ENA_V << PPA_SR_PARAM_CFG_ERR_INT_ENA_S) +#define PPA_SR_PARAM_CFG_ERR_INT_ENA_V 0x00000001U +#define PPA_SR_PARAM_CFG_ERR_INT_ENA_S 2 +/** PPA_BLEND_PARAM_CFG_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ +#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA (BIT(3)) +#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_M (PPA_BLEND_PARAM_CFG_ERR_INT_ENA_V << PPA_BLEND_PARAM_CFG_ERR_INT_ENA_S) +#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_V 0x00000001U +#define PPA_BLEND_PARAM_CFG_ERR_INT_ENA_S 3 + +/** PPA_INT_CLR_REG register + * Interrupt clear bits + */ +#define PPA_INT_CLR_REG (DR_REG_PPA_BASE + 0x1c) +/** PPA_SR_EOF_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PPA_SR_EOF_INT interrupt. + */ +#define PPA_SR_EOF_INT_CLR (BIT(0)) +#define PPA_SR_EOF_INT_CLR_M (PPA_SR_EOF_INT_CLR_V << PPA_SR_EOF_INT_CLR_S) +#define PPA_SR_EOF_INT_CLR_V 0x00000001U +#define PPA_SR_EOF_INT_CLR_S 0 +/** PPA_BLEND_EOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + */ +#define PPA_BLEND_EOF_INT_CLR (BIT(1)) +#define PPA_BLEND_EOF_INT_CLR_M (PPA_BLEND_EOF_INT_CLR_V << PPA_BLEND_EOF_INT_CLR_S) +#define PPA_BLEND_EOF_INT_CLR_V 0x00000001U +#define PPA_BLEND_EOF_INT_CLR_S 1 +/** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + */ +#define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2)) +#define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S) +#define PPA_SR_PARAM_CFG_ERR_INT_CLR_V 0x00000001U +#define PPA_SR_PARAM_CFG_ERR_INT_CLR_S 2 +/** PPA_BLEND_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ +#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR (BIT(3)) +#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_M (PPA_BLEND_PARAM_CFG_ERR_INT_CLR_V << PPA_BLEND_PARAM_CFG_ERR_INT_CLR_S) +#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_V 0x00000001U +#define PPA_BLEND_PARAM_CFG_ERR_INT_CLR_S 3 + +/** PPA_SR_COLOR_MODE_REG register + * Scaling and rotating engine color mode register + */ +#define PPA_SR_COLOR_MODE_REG (DR_REG_PPA_BASE + 0x20) +/** PPA_SR_RX_CM : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: + * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. + */ +#define PPA_SR_RX_CM 0x0000000FU +#define PPA_SR_RX_CM_M (PPA_SR_RX_CM_V << PPA_SR_RX_CM_S) +#define PPA_SR_RX_CM_V 0x0000000FU +#define PPA_SR_RX_CM_S 0 +/** PPA_SR_TX_CM : R/W; bitpos: [7:4]; default: 0; + * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. + * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. + */ +#define PPA_SR_TX_CM 0x0000000FU +#define PPA_SR_TX_CM_M (PPA_SR_TX_CM_V << PPA_SR_TX_CM_S) +#define PPA_SR_TX_CM_V 0x0000000FU +#define PPA_SR_TX_CM_S 4 +/** PPA_YUV_RX_RANGE : R/W; bitpos: [8]; default: 0; + * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + */ +#define PPA_YUV_RX_RANGE (BIT(8)) +#define PPA_YUV_RX_RANGE_M (PPA_YUV_RX_RANGE_V << PPA_YUV_RX_RANGE_S) +#define PPA_YUV_RX_RANGE_V 0x00000001U +#define PPA_YUV_RX_RANGE_S 8 +/** PPA_YUV_TX_RANGE : R/W; bitpos: [9]; default: 0; + * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + */ +#define PPA_YUV_TX_RANGE (BIT(9)) +#define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S) +#define PPA_YUV_TX_RANGE_V 0x00000001U +#define PPA_YUV_TX_RANGE_S 9 +/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0; + * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + */ +#define PPA_YUV2RGB_PROTOCAL (BIT(10)) +#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S) +#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U +#define PPA_YUV2RGB_PROTOCAL_S 10 +/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0; + * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + */ +#define PPA_RGB2YUV_PROTOCAL (BIT(11)) +#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S) +#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U +#define PPA_RGB2YUV_PROTOCAL_S 11 +/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ +#define PPA_YUV422_RX_BYTE_ORDER 0x00000003U +#define PPA_YUV422_RX_BYTE_ORDER_M (PPA_YUV422_RX_BYTE_ORDER_V << PPA_YUV422_RX_BYTE_ORDER_S) +#define PPA_YUV422_RX_BYTE_ORDER_V 0x00000003U +#define PPA_YUV422_RX_BYTE_ORDER_S 12 + +/** PPA_BLEND_COLOR_MODE_REG register + * blending engine color mode register + */ +#define PPA_BLEND_COLOR_MODE_REG (DR_REG_PPA_BASE + 0x24) +/** PPA_BLEND0_RX_CM : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY + */ +#define PPA_BLEND0_RX_CM 0x0000000FU +#define PPA_BLEND0_RX_CM_M (PPA_BLEND0_RX_CM_V << PPA_BLEND0_RX_CM_S) +#define PPA_BLEND0_RX_CM_V 0x0000000FU +#define PPA_BLEND0_RX_CM_S 0 +/** PPA_BLEND1_RX_CM : R/W; bitpos: [7:4]; default: 0; + * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + */ +#define PPA_BLEND1_RX_CM 0x0000000FU +#define PPA_BLEND1_RX_CM_M (PPA_BLEND1_RX_CM_V << PPA_BLEND1_RX_CM_S) +#define PPA_BLEND1_RX_CM_V 0x0000000FU +#define PPA_BLEND1_RX_CM_S 4 +/** PPA_BLEND_TX_CM : R/W; bitpos: [11:8]; default: 0; + * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY + */ +#define PPA_BLEND_TX_CM 0x0000000FU +#define PPA_BLEND_TX_CM_M (PPA_BLEND_TX_CM_V << PPA_BLEND_TX_CM_S) +#define PPA_BLEND_TX_CM_V 0x0000000FU +#define PPA_BLEND_TX_CM_S 8 +/** PPA_BLEND0_RX_YUV_RANGE : R/W; bitpos: [12]; default: 0; + * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range + */ +#define PPA_BLEND0_RX_YUV_RANGE (BIT(12)) +#define PPA_BLEND0_RX_YUV_RANGE_M (PPA_BLEND0_RX_YUV_RANGE_V << PPA_BLEND0_RX_YUV_RANGE_S) +#define PPA_BLEND0_RX_YUV_RANGE_V 0x00000001U +#define PPA_BLEND0_RX_YUV_RANGE_S 12 +/** PPA_BLEND_TX_YUV_RANGE : R/W; bitpos: [13]; default: 0; + * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range + */ +#define PPA_BLEND_TX_YUV_RANGE (BIT(13)) +#define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S) +#define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U +#define PPA_BLEND_TX_YUV_RANGE_S 13 +/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0; + * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 + */ +#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14)) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U +#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14 +/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0; + * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 + */ +#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15)) +#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S) +#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U +#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15 +/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ +#define PPA_BLEND0_RX_YUV422_BYTE_ORDER 0x00000003U +#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_M (PPA_BLEND0_RX_YUV422_BYTE_ORDER_V << PPA_BLEND0_RX_YUV422_BYTE_ORDER_S) +#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_V 0x00000003U +#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_S 16 + +/** PPA_SR_BYTE_ORDER_REG register + * Scaling and rotating engine byte order register + */ +#define PPA_SR_BYTE_ORDER_REG (DR_REG_PPA_BASE + 0x28) +/** PPA_SR_RX_BYTE_SWAP_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ +#define PPA_SR_RX_BYTE_SWAP_EN (BIT(0)) +#define PPA_SR_RX_BYTE_SWAP_EN_M (PPA_SR_RX_BYTE_SWAP_EN_V << PPA_SR_RX_BYTE_SWAP_EN_S) +#define PPA_SR_RX_BYTE_SWAP_EN_V 0x00000001U +#define PPA_SR_RX_BYTE_SWAP_EN_S 0 +/** PPA_SR_RX_RGB_SWAP_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ +#define PPA_SR_RX_RGB_SWAP_EN (BIT(1)) +#define PPA_SR_RX_RGB_SWAP_EN_M (PPA_SR_RX_RGB_SWAP_EN_V << PPA_SR_RX_RGB_SWAP_EN_S) +#define PPA_SR_RX_RGB_SWAP_EN_V 0x00000001U +#define PPA_SR_RX_RGB_SWAP_EN_S 1 +/** PPA_SR_MACRO_BK_RO_BYPASS : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to bypass the macro block order function. This function is used + * to improve efficient accessing external memory. + */ +#define PPA_SR_MACRO_BK_RO_BYPASS (BIT(2)) +#define PPA_SR_MACRO_BK_RO_BYPASS_M (PPA_SR_MACRO_BK_RO_BYPASS_V << PPA_SR_MACRO_BK_RO_BYPASS_S) +#define PPA_SR_MACRO_BK_RO_BYPASS_V 0x00000001U +#define PPA_SR_MACRO_BK_RO_BYPASS_S 2 +/** PPA_SR_BK_SIZE_SEL : R/W; bitpos: [3]; default: 0; + * sel srm pix_blk size, 0:32x32, 1:16x16 + */ +#define PPA_SR_BK_SIZE_SEL (BIT(3)) +#define PPA_SR_BK_SIZE_SEL_M (PPA_SR_BK_SIZE_SEL_V << PPA_SR_BK_SIZE_SEL_S) +#define PPA_SR_BK_SIZE_SEL_V 0x00000001U +#define PPA_SR_BK_SIZE_SEL_S 3 + +/** PPA_BLEND_BYTE_ORDER_REG register + * Blending engine byte order register + */ +#define PPA_BLEND_BYTE_ORDER_REG (DR_REG_PPA_BASE + 0x2c) +/** PPA_BLEND0_RX_BYTE_SWAP_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ +#define PPA_BLEND0_RX_BYTE_SWAP_EN (BIT(0)) +#define PPA_BLEND0_RX_BYTE_SWAP_EN_M (PPA_BLEND0_RX_BYTE_SWAP_EN_V << PPA_BLEND0_RX_BYTE_SWAP_EN_S) +#define PPA_BLEND0_RX_BYTE_SWAP_EN_V 0x00000001U +#define PPA_BLEND0_RX_BYTE_SWAP_EN_S 0 +/** PPA_BLEND1_RX_BYTE_SWAP_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ +#define PPA_BLEND1_RX_BYTE_SWAP_EN (BIT(1)) +#define PPA_BLEND1_RX_BYTE_SWAP_EN_M (PPA_BLEND1_RX_BYTE_SWAP_EN_V << PPA_BLEND1_RX_BYTE_SWAP_EN_S) +#define PPA_BLEND1_RX_BYTE_SWAP_EN_V 0x00000001U +#define PPA_BLEND1_RX_BYTE_SWAP_EN_S 1 +/** PPA_BLEND0_RX_RGB_SWAP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ +#define PPA_BLEND0_RX_RGB_SWAP_EN (BIT(2)) +#define PPA_BLEND0_RX_RGB_SWAP_EN_M (PPA_BLEND0_RX_RGB_SWAP_EN_V << PPA_BLEND0_RX_RGB_SWAP_EN_S) +#define PPA_BLEND0_RX_RGB_SWAP_EN_V 0x00000001U +#define PPA_BLEND0_RX_RGB_SWAP_EN_S 2 +/** PPA_BLEND1_RX_RGB_SWAP_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ +#define PPA_BLEND1_RX_RGB_SWAP_EN (BIT(3)) +#define PPA_BLEND1_RX_RGB_SWAP_EN_M (PPA_BLEND1_RX_RGB_SWAP_EN_V << PPA_BLEND1_RX_RGB_SWAP_EN_S) +#define PPA_BLEND1_RX_RGB_SWAP_EN_V 0x00000001U +#define PPA_BLEND1_RX_RGB_SWAP_EN_S 3 + +/** PPA_BLEND_TRANS_MODE_REG register + * Blending engine mode configure register + */ +#define PPA_BLEND_TRANS_MODE_REG (DR_REG_PPA_BASE + 0x34) +/** PPA_BLEND_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable alpha blending. + */ +#define PPA_BLEND_EN (BIT(0)) +#define PPA_BLEND_EN_M (PPA_BLEND_EN_V << PPA_BLEND_EN_S) +#define PPA_BLEND_EN_V 0x00000001U +#define PPA_BLEND_EN_S 0 +/** PPA_BLEND_BYPASS : R/W; bitpos: [1]; default: 0; + * Set this bit to bypass blender. Then background date would be output. + */ +#define PPA_BLEND_BYPASS (BIT(1)) +#define PPA_BLEND_BYPASS_M (PPA_BLEND_BYPASS_V << PPA_BLEND_BYPASS_S) +#define PPA_BLEND_BYPASS_V 0x00000001U +#define PPA_BLEND_BYPASS_S 1 +/** PPA_BLEND_FIX_PIXEL_FILL_EN : R/W; bitpos: [2]; default: 0; + * This bit is used to enable fix pixel filling. When this mode is enable only Tx + * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + */ +#define PPA_BLEND_FIX_PIXEL_FILL_EN (BIT(2)) +#define PPA_BLEND_FIX_PIXEL_FILL_EN_M (PPA_BLEND_FIX_PIXEL_FILL_EN_V << PPA_BLEND_FIX_PIXEL_FILL_EN_S) +#define PPA_BLEND_FIX_PIXEL_FILL_EN_V 0x00000001U +#define PPA_BLEND_FIX_PIXEL_FILL_EN_S 2 +/** PPA_BLEND_TRANS_MODE_UPDATE : WT; bitpos: [3]; default: 0; + * Set this bit to update the transfer mode. Only the bit is set the transfer mode is + * valid. + */ +#define PPA_BLEND_TRANS_MODE_UPDATE (BIT(3)) +#define PPA_BLEND_TRANS_MODE_UPDATE_M (PPA_BLEND_TRANS_MODE_UPDATE_V << PPA_BLEND_TRANS_MODE_UPDATE_S) +#define PPA_BLEND_TRANS_MODE_UPDATE_V 0x00000001U +#define PPA_BLEND_TRANS_MODE_UPDATE_S 3 +/** PPA_BLEND_RST : R/W; bitpos: [4]; default: 0; + * write 1 then write 0 to reset blending engine. + */ +#define PPA_BLEND_RST (BIT(4)) +#define PPA_BLEND_RST_M (PPA_BLEND_RST_V << PPA_BLEND_RST_S) +#define PPA_BLEND_RST_V 0x00000001U +#define PPA_BLEND_RST_S 4 +/** PPA_BLEND_TX_INF_SEL : R/W; bitpos: [6:5]; default: 0; + * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and + * ls_enc + */ +#define PPA_BLEND_TX_INF_SEL 0x00000003U +#define PPA_BLEND_TX_INF_SEL_M (PPA_BLEND_TX_INF_SEL_V << PPA_BLEND_TX_INF_SEL_S) +#define PPA_BLEND_TX_INF_SEL_V 0x00000003U +#define PPA_BLEND_TX_INF_SEL_S 5 + +/** PPA_SR_FIX_ALPHA_REG register + * Scaling and rotating engine alpha override register + */ +#define PPA_SR_FIX_ALPHA_REG (DR_REG_PPA_BASE + 0x38) +/** PPA_SR_RX_FIX_ALPHA : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for Scaling and Rotating + * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + */ +#define PPA_SR_RX_FIX_ALPHA 0x000000FFU +#define PPA_SR_RX_FIX_ALPHA_M (PPA_SR_RX_FIX_ALPHA_V << PPA_SR_RX_FIX_ALPHA_S) +#define PPA_SR_RX_FIX_ALPHA_V 0x000000FFU +#define PPA_SR_RX_FIX_ALPHA_S 0 +/** PPA_SR_RX_ALPHA_MOD : R/W; bitpos: [9:8]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ +#define PPA_SR_RX_ALPHA_MOD 0x00000003U +#define PPA_SR_RX_ALPHA_MOD_M (PPA_SR_RX_ALPHA_MOD_V << PPA_SR_RX_ALPHA_MOD_S) +#define PPA_SR_RX_ALPHA_MOD_V 0x00000003U +#define PPA_SR_RX_ALPHA_MOD_S 8 +/** PPA_SR_RX_ALPHA_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ +#define PPA_SR_RX_ALPHA_INV (BIT(10)) +#define PPA_SR_RX_ALPHA_INV_M (PPA_SR_RX_ALPHA_INV_V << PPA_SR_RX_ALPHA_INV_S) +#define PPA_SR_RX_ALPHA_INV_V 0x00000001U +#define PPA_SR_RX_ALPHA_INV_S 10 + +/** PPA_BLEND_TX_SIZE_REG register + * Fix pixel filling mode image size register + */ +#define PPA_BLEND_TX_SIZE_REG (DR_REG_PPA_BASE + 0x3c) +/** PPA_BLEND_HB : R/W; bitpos: [13:0]; default: 0; + * The horizontal width of image block that would be filled in fix pixel filling mode + * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 + */ +#define PPA_BLEND_HB 0x00003FFFU +#define PPA_BLEND_HB_M (PPA_BLEND_HB_V << PPA_BLEND_HB_S) +#define PPA_BLEND_HB_V 0x00003FFFU +#define PPA_BLEND_HB_S 0 +/** PPA_BLEND_VB : R/W; bitpos: [27:14]; default: 0; + * The vertical width of image block that would be filled in fix pixel filling mode or + * blend mode. The unit is pixel. Must be even num when YUV420 + */ +#define PPA_BLEND_VB 0x00003FFFU +#define PPA_BLEND_VB_M (PPA_BLEND_VB_V << PPA_BLEND_VB_S) +#define PPA_BLEND_VB_V 0x00003FFFU +#define PPA_BLEND_VB_S 14 + +/** PPA_BLEND_FIX_ALPHA_REG register + * Blending engine alpha override register + */ +#define PPA_BLEND_FIX_ALPHA_REG (DR_REG_PPA_BASE + 0x40) +/** PPA_BLEND0_RX_FIX_ALPHA : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for background plane of + * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + */ +#define PPA_BLEND0_RX_FIX_ALPHA 0x000000FFU +#define PPA_BLEND0_RX_FIX_ALPHA_M (PPA_BLEND0_RX_FIX_ALPHA_V << PPA_BLEND0_RX_FIX_ALPHA_S) +#define PPA_BLEND0_RX_FIX_ALPHA_V 0x000000FFU +#define PPA_BLEND0_RX_FIX_ALPHA_S 0 +/** PPA_BLEND1_RX_FIX_ALPHA : R/W; bitpos: [15:8]; default: 128; + * The value would replace the alpha value in received pixel for foreground plane of + * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + */ +#define PPA_BLEND1_RX_FIX_ALPHA 0x000000FFU +#define PPA_BLEND1_RX_FIX_ALPHA_M (PPA_BLEND1_RX_FIX_ALPHA_V << PPA_BLEND1_RX_FIX_ALPHA_S) +#define PPA_BLEND1_RX_FIX_ALPHA_V 0x000000FFU +#define PPA_BLEND1_RX_FIX_ALPHA_S 8 +/** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ +#define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U +#define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S) +#define PPA_BLEND0_RX_ALPHA_MOD_V 0x00000003U +#define PPA_BLEND0_RX_ALPHA_MOD_S 16 +/** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ +#define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U +#define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S) +#define PPA_BLEND1_RX_ALPHA_MOD_V 0x00000003U +#define PPA_BLEND1_RX_ALPHA_MOD_S 18 +/** PPA_BLEND0_RX_ALPHA_INV : R/W; bitpos: [20]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ +#define PPA_BLEND0_RX_ALPHA_INV (BIT(20)) +#define PPA_BLEND0_RX_ALPHA_INV_M (PPA_BLEND0_RX_ALPHA_INV_V << PPA_BLEND0_RX_ALPHA_INV_S) +#define PPA_BLEND0_RX_ALPHA_INV_V 0x00000001U +#define PPA_BLEND0_RX_ALPHA_INV_S 20 +/** PPA_BLEND1_RX_ALPHA_INV : R/W; bitpos: [21]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ +#define PPA_BLEND1_RX_ALPHA_INV (BIT(21)) +#define PPA_BLEND1_RX_ALPHA_INV_M (PPA_BLEND1_RX_ALPHA_INV_V << PPA_BLEND1_RX_ALPHA_INV_S) +#define PPA_BLEND1_RX_ALPHA_INV_V 0x00000001U +#define PPA_BLEND1_RX_ALPHA_INV_S 21 + +/** PPA_BLEND_RGB_REG register + * RGB color register + */ +#define PPA_BLEND_RGB_REG (DR_REG_PPA_BASE + 0x48) +/** PPA_BLEND1_RX_B : R/W; bitpos: [7:0]; default: 128; + * blue color for A4/A8 mode. + */ +#define PPA_BLEND1_RX_B 0x000000FFU +#define PPA_BLEND1_RX_B_M (PPA_BLEND1_RX_B_V << PPA_BLEND1_RX_B_S) +#define PPA_BLEND1_RX_B_V 0x000000FFU +#define PPA_BLEND1_RX_B_S 0 +/** PPA_BLEND1_RX_G : R/W; bitpos: [15:8]; default: 128; + * green color for A4/A8 mode. + */ +#define PPA_BLEND1_RX_G 0x000000FFU +#define PPA_BLEND1_RX_G_M (PPA_BLEND1_RX_G_V << PPA_BLEND1_RX_G_S) +#define PPA_BLEND1_RX_G_V 0x000000FFU +#define PPA_BLEND1_RX_G_S 8 +/** PPA_BLEND1_RX_R : R/W; bitpos: [23:16]; default: 128; + * red color for A4/A8 mode. + */ +#define PPA_BLEND1_RX_R 0x000000FFU +#define PPA_BLEND1_RX_R_M (PPA_BLEND1_RX_R_V << PPA_BLEND1_RX_R_S) +#define PPA_BLEND1_RX_R_V 0x000000FFU +#define PPA_BLEND1_RX_R_S 16 + +/** PPA_BLEND_FIX_PIXEL_REG register + * Blending engine fix pixel register + */ +#define PPA_BLEND_FIX_PIXEL_REG (DR_REG_PPA_BASE + 0x4c) +/** PPA_BLEND_TX_FIX_PIXEL : R/W; bitpos: [31:0]; default: 0; + * The configure fix pixel in fix pixel filling mode for blender engine. + */ +#define PPA_BLEND_TX_FIX_PIXEL 0xFFFFFFFFU +#define PPA_BLEND_TX_FIX_PIXEL_M (PPA_BLEND_TX_FIX_PIXEL_V << PPA_BLEND_TX_FIX_PIXEL_S) +#define PPA_BLEND_TX_FIX_PIXEL_V 0xFFFFFFFFU +#define PPA_BLEND_TX_FIX_PIXEL_S 0 + +/** PPA_CK_FG_LOW_REG register + * foreground color key lower threshold + */ +#define PPA_CK_FG_LOW_REG (DR_REG_PPA_BASE + 0x50) +/** PPA_COLORKEY_FG_B_LOW : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of foreground b channel + */ +#define PPA_COLORKEY_FG_B_LOW 0x000000FFU +#define PPA_COLORKEY_FG_B_LOW_M (PPA_COLORKEY_FG_B_LOW_V << PPA_COLORKEY_FG_B_LOW_S) +#define PPA_COLORKEY_FG_B_LOW_V 0x000000FFU +#define PPA_COLORKEY_FG_B_LOW_S 0 +/** PPA_COLORKEY_FG_G_LOW : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of foreground g channel + */ +#define PPA_COLORKEY_FG_G_LOW 0x000000FFU +#define PPA_COLORKEY_FG_G_LOW_M (PPA_COLORKEY_FG_G_LOW_V << PPA_COLORKEY_FG_G_LOW_S) +#define PPA_COLORKEY_FG_G_LOW_V 0x000000FFU +#define PPA_COLORKEY_FG_G_LOW_S 8 +/** PPA_COLORKEY_FG_R_LOW : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of foreground r channel + */ +#define PPA_COLORKEY_FG_R_LOW 0x000000FFU +#define PPA_COLORKEY_FG_R_LOW_M (PPA_COLORKEY_FG_R_LOW_V << PPA_COLORKEY_FG_R_LOW_S) +#define PPA_COLORKEY_FG_R_LOW_V 0x000000FFU +#define PPA_COLORKEY_FG_R_LOW_S 16 + +/** PPA_CK_FG_HIGH_REG register + * foreground color key higher threshold + */ +#define PPA_CK_FG_HIGH_REG (DR_REG_PPA_BASE + 0x54) +/** PPA_COLORKEY_FG_B_HIGH : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of foreground b channel + */ +#define PPA_COLORKEY_FG_B_HIGH 0x000000FFU +#define PPA_COLORKEY_FG_B_HIGH_M (PPA_COLORKEY_FG_B_HIGH_V << PPA_COLORKEY_FG_B_HIGH_S) +#define PPA_COLORKEY_FG_B_HIGH_V 0x000000FFU +#define PPA_COLORKEY_FG_B_HIGH_S 0 +/** PPA_COLORKEY_FG_G_HIGH : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of foreground g channel + */ +#define PPA_COLORKEY_FG_G_HIGH 0x000000FFU +#define PPA_COLORKEY_FG_G_HIGH_M (PPA_COLORKEY_FG_G_HIGH_V << PPA_COLORKEY_FG_G_HIGH_S) +#define PPA_COLORKEY_FG_G_HIGH_V 0x000000FFU +#define PPA_COLORKEY_FG_G_HIGH_S 8 +/** PPA_COLORKEY_FG_R_HIGH : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of foreground r channel + */ +#define PPA_COLORKEY_FG_R_HIGH 0x000000FFU +#define PPA_COLORKEY_FG_R_HIGH_M (PPA_COLORKEY_FG_R_HIGH_V << PPA_COLORKEY_FG_R_HIGH_S) +#define PPA_COLORKEY_FG_R_HIGH_V 0x000000FFU +#define PPA_COLORKEY_FG_R_HIGH_S 16 + +/** PPA_CK_BG_LOW_REG register + * background color key lower threshold + */ +#define PPA_CK_BG_LOW_REG (DR_REG_PPA_BASE + 0x58) +/** PPA_COLORKEY_BG_B_LOW : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of background b channel + */ +#define PPA_COLORKEY_BG_B_LOW 0x000000FFU +#define PPA_COLORKEY_BG_B_LOW_M (PPA_COLORKEY_BG_B_LOW_V << PPA_COLORKEY_BG_B_LOW_S) +#define PPA_COLORKEY_BG_B_LOW_V 0x000000FFU +#define PPA_COLORKEY_BG_B_LOW_S 0 +/** PPA_COLORKEY_BG_G_LOW : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of background g channel + */ +#define PPA_COLORKEY_BG_G_LOW 0x000000FFU +#define PPA_COLORKEY_BG_G_LOW_M (PPA_COLORKEY_BG_G_LOW_V << PPA_COLORKEY_BG_G_LOW_S) +#define PPA_COLORKEY_BG_G_LOW_V 0x000000FFU +#define PPA_COLORKEY_BG_G_LOW_S 8 +/** PPA_COLORKEY_BG_R_LOW : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of background r channel + */ +#define PPA_COLORKEY_BG_R_LOW 0x000000FFU +#define PPA_COLORKEY_BG_R_LOW_M (PPA_COLORKEY_BG_R_LOW_V << PPA_COLORKEY_BG_R_LOW_S) +#define PPA_COLORKEY_BG_R_LOW_V 0x000000FFU +#define PPA_COLORKEY_BG_R_LOW_S 16 + +/** PPA_CK_BG_HIGH_REG register + * background color key higher threshold + */ +#define PPA_CK_BG_HIGH_REG (DR_REG_PPA_BASE + 0x5c) +/** PPA_COLORKEY_BG_B_HIGH : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of background b channel + */ +#define PPA_COLORKEY_BG_B_HIGH 0x000000FFU +#define PPA_COLORKEY_BG_B_HIGH_M (PPA_COLORKEY_BG_B_HIGH_V << PPA_COLORKEY_BG_B_HIGH_S) +#define PPA_COLORKEY_BG_B_HIGH_V 0x000000FFU +#define PPA_COLORKEY_BG_B_HIGH_S 0 +/** PPA_COLORKEY_BG_G_HIGH : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of background g channel + */ +#define PPA_COLORKEY_BG_G_HIGH 0x000000FFU +#define PPA_COLORKEY_BG_G_HIGH_M (PPA_COLORKEY_BG_G_HIGH_V << PPA_COLORKEY_BG_G_HIGH_S) +#define PPA_COLORKEY_BG_G_HIGH_V 0x000000FFU +#define PPA_COLORKEY_BG_G_HIGH_S 8 +/** PPA_COLORKEY_BG_R_HIGH : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of background r channel + */ +#define PPA_COLORKEY_BG_R_HIGH 0x000000FFU +#define PPA_COLORKEY_BG_R_HIGH_M (PPA_COLORKEY_BG_R_HIGH_V << PPA_COLORKEY_BG_R_HIGH_S) +#define PPA_COLORKEY_BG_R_HIGH_V 0x000000FFU +#define PPA_COLORKEY_BG_R_HIGH_S 16 + +/** PPA_CK_DEFAULT_REG register + * default value when foreground and background both in color key range + */ +#define PPA_CK_DEFAULT_REG (DR_REG_PPA_BASE + 0x60) +/** PPA_COLORKEY_DEFAULT_B : R/W; bitpos: [7:0]; default: 0; + * default B channel value of color key + */ +#define PPA_COLORKEY_DEFAULT_B 0x000000FFU +#define PPA_COLORKEY_DEFAULT_B_M (PPA_COLORKEY_DEFAULT_B_V << PPA_COLORKEY_DEFAULT_B_S) +#define PPA_COLORKEY_DEFAULT_B_V 0x000000FFU +#define PPA_COLORKEY_DEFAULT_B_S 0 +/** PPA_COLORKEY_DEFAULT_G : R/W; bitpos: [15:8]; default: 0; + * default G channel value of color key + */ +#define PPA_COLORKEY_DEFAULT_G 0x000000FFU +#define PPA_COLORKEY_DEFAULT_G_M (PPA_COLORKEY_DEFAULT_G_V << PPA_COLORKEY_DEFAULT_G_S) +#define PPA_COLORKEY_DEFAULT_G_V 0x000000FFU +#define PPA_COLORKEY_DEFAULT_G_S 8 +/** PPA_COLORKEY_DEFAULT_R : R/W; bitpos: [23:16]; default: 0; + * default R channel value of color key + */ +#define PPA_COLORKEY_DEFAULT_R 0x000000FFU +#define PPA_COLORKEY_DEFAULT_R_M (PPA_COLORKEY_DEFAULT_R_V << PPA_COLORKEY_DEFAULT_R_S) +#define PPA_COLORKEY_DEFAULT_R_V 0x000000FFU +#define PPA_COLORKEY_DEFAULT_R_S 16 +/** PPA_COLORKEY_FG_BG_REVERSE : R/W; bitpos: [24]; default: 0; + * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the + * result is fg + */ +#define PPA_COLORKEY_FG_BG_REVERSE (BIT(24)) +#define PPA_COLORKEY_FG_BG_REVERSE_M (PPA_COLORKEY_FG_BG_REVERSE_V << PPA_COLORKEY_FG_BG_REVERSE_S) +#define PPA_COLORKEY_FG_BG_REVERSE_V 0x00000001U +#define PPA_COLORKEY_FG_BG_REVERSE_S 24 + +/** PPA_SR_SCAL_ROTATE_REG register + * Scaling and rotating coefficient register + */ +#define PPA_SR_SCAL_ROTATE_REG (DR_REG_PPA_BASE + 0x64) +/** PPA_SR_SCAL_X_INT : R/W; bitpos: [7:0]; default: 1; + * The integrated part of scaling coefficient in X direction. + */ +#define PPA_SR_SCAL_X_INT 0x000000FFU +#define PPA_SR_SCAL_X_INT_M (PPA_SR_SCAL_X_INT_V << PPA_SR_SCAL_X_INT_S) +#define PPA_SR_SCAL_X_INT_V 0x000000FFU +#define PPA_SR_SCAL_X_INT_S 0 +/** PPA_SR_SCAL_X_FRAG : R/W; bitpos: [11:8]; default: 0; + * The fragment part of scaling coefficient in X direction. + */ +#define PPA_SR_SCAL_X_FRAG 0x0000000FU +#define PPA_SR_SCAL_X_FRAG_M (PPA_SR_SCAL_X_FRAG_V << PPA_SR_SCAL_X_FRAG_S) +#define PPA_SR_SCAL_X_FRAG_V 0x0000000FU +#define PPA_SR_SCAL_X_FRAG_S 8 +/** PPA_SR_SCAL_Y_INT : R/W; bitpos: [19:12]; default: 1; + * The integrated part of scaling coefficient in Y direction. + */ +#define PPA_SR_SCAL_Y_INT 0x000000FFU +#define PPA_SR_SCAL_Y_INT_M (PPA_SR_SCAL_Y_INT_V << PPA_SR_SCAL_Y_INT_S) +#define PPA_SR_SCAL_Y_INT_V 0x000000FFU +#define PPA_SR_SCAL_Y_INT_S 12 +/** PPA_SR_SCAL_Y_FRAG : R/W; bitpos: [23:20]; default: 0; + * The fragment part of scaling coefficient in Y direction. + */ +#define PPA_SR_SCAL_Y_FRAG 0x0000000FU +#define PPA_SR_SCAL_Y_FRAG_M (PPA_SR_SCAL_Y_FRAG_V << PPA_SR_SCAL_Y_FRAG_S) +#define PPA_SR_SCAL_Y_FRAG_V 0x0000000FU +#define PPA_SR_SCAL_Y_FRAG_S 20 +/** PPA_SR_ROTATE_ANGLE : R/W; bitpos: [25:24]; default: 0; + * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + */ +#define PPA_SR_ROTATE_ANGLE 0x00000003U +#define PPA_SR_ROTATE_ANGLE_M (PPA_SR_ROTATE_ANGLE_V << PPA_SR_ROTATE_ANGLE_S) +#define PPA_SR_ROTATE_ANGLE_V 0x00000003U +#define PPA_SR_ROTATE_ANGLE_S 24 +/** PPA_SCAL_ROTATE_RST : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset scaling and rotating engine. + */ +#define PPA_SCAL_ROTATE_RST (BIT(26)) +#define PPA_SCAL_ROTATE_RST_M (PPA_SCAL_ROTATE_RST_V << PPA_SCAL_ROTATE_RST_S) +#define PPA_SCAL_ROTATE_RST_V 0x00000001U +#define PPA_SCAL_ROTATE_RST_S 26 +/** PPA_SCAL_ROTATE_START : WT; bitpos: [27]; default: 0; + * Write 1 to enable scaling and rotating engine after parameter is configured. + */ +#define PPA_SCAL_ROTATE_START (BIT(27)) +#define PPA_SCAL_ROTATE_START_M (PPA_SCAL_ROTATE_START_V << PPA_SCAL_ROTATE_START_S) +#define PPA_SCAL_ROTATE_START_V 0x00000001U +#define PPA_SCAL_ROTATE_START_S 27 +/** PPA_SR_MIRROR_X : R/W; bitpos: [28]; default: 0; + * Image mirror in X direction. 0: disable, 1: enable + */ +#define PPA_SR_MIRROR_X (BIT(28)) +#define PPA_SR_MIRROR_X_M (PPA_SR_MIRROR_X_V << PPA_SR_MIRROR_X_S) +#define PPA_SR_MIRROR_X_V 0x00000001U +#define PPA_SR_MIRROR_X_S 28 +/** PPA_SR_MIRROR_Y : R/W; bitpos: [29]; default: 0; + * Image mirror in Y direction. 0: disable, 1: enable + */ +#define PPA_SR_MIRROR_Y (BIT(29)) +#define PPA_SR_MIRROR_Y_M (PPA_SR_MIRROR_Y_V << PPA_SR_MIRROR_Y_S) +#define PPA_SR_MIRROR_Y_V 0x00000001U +#define PPA_SR_MIRROR_Y_S 29 + +/** PPA_SR_MEM_PD_REG register + * SR memory power done register + */ +#define PPA_SR_MEM_PD_REG (DR_REG_PPA_BASE + 0x68) +/** PPA_SR_MEM_CLK_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to force clock enable of scaling and rotating engine's data memory. + */ +#define PPA_SR_MEM_CLK_ENA (BIT(0)) +#define PPA_SR_MEM_CLK_ENA_M (PPA_SR_MEM_CLK_ENA_V << PPA_SR_MEM_CLK_ENA_S) +#define PPA_SR_MEM_CLK_ENA_V 0x00000001U +#define PPA_SR_MEM_CLK_ENA_S 0 +/** PPA_SR_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force power down scaling and rotating engine's data memory. + */ +#define PPA_SR_MEM_FORCE_PD (BIT(1)) +#define PPA_SR_MEM_FORCE_PD_M (PPA_SR_MEM_FORCE_PD_V << PPA_SR_MEM_FORCE_PD_S) +#define PPA_SR_MEM_FORCE_PD_V 0x00000001U +#define PPA_SR_MEM_FORCE_PD_S 1 +/** PPA_SR_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up scaling and rotating engine's data memory. + */ +#define PPA_SR_MEM_FORCE_PU (BIT(2)) +#define PPA_SR_MEM_FORCE_PU_M (PPA_SR_MEM_FORCE_PU_V << PPA_SR_MEM_FORCE_PU_S) +#define PPA_SR_MEM_FORCE_PU_V 0x00000001U +#define PPA_SR_MEM_FORCE_PU_S 2 + +/** PPA_REG_CONF_REG register + * Register clock enable register + */ +#define PPA_REG_CONF_REG (DR_REG_PPA_BASE + 0x6c) +/** PPA_CLK_EN : R/W; bitpos: [0]; default: 0; + * PPA register clock gate enable signal. + */ +#define PPA_CLK_EN (BIT(0)) +#define PPA_CLK_EN_M (PPA_CLK_EN_V << PPA_CLK_EN_S) +#define PPA_CLK_EN_V 0x00000001U +#define PPA_CLK_EN_S 0 + +/** PPA_CLUT_CNT_REG register + * BLEND CLUT write counter register + */ +#define PPA_CLUT_CNT_REG (DR_REG_PPA_BASE + 0x70) +/** PPA_BLEND0_CLUT_CNT : RO; bitpos: [8:0]; default: 0; + * The write data counter of BLEND0 CLUT in fifo mode. + */ +#define PPA_BLEND0_CLUT_CNT 0x000001FFU +#define PPA_BLEND0_CLUT_CNT_M (PPA_BLEND0_CLUT_CNT_V << PPA_BLEND0_CLUT_CNT_S) +#define PPA_BLEND0_CLUT_CNT_V 0x000001FFU +#define PPA_BLEND0_CLUT_CNT_S 0 +/** PPA_BLEND1_CLUT_CNT : RO; bitpos: [17:9]; default: 0; + * The write data counter of BLEND1 CLUT in fifo mode. + */ +#define PPA_BLEND1_CLUT_CNT 0x000001FFU +#define PPA_BLEND1_CLUT_CNT_M (PPA_BLEND1_CLUT_CNT_V << PPA_BLEND1_CLUT_CNT_S) +#define PPA_BLEND1_CLUT_CNT_V 0x000001FFU +#define PPA_BLEND1_CLUT_CNT_S 9 + +/** PPA_BLEND_ST_REG register + * Blending engine status register + */ +#define PPA_BLEND_ST_REG (DR_REG_PPA_BASE + 0x74) +/** PPA_BLEND_SIZE_DIFF_ST : RO; bitpos: [0]; default: 0; + * 1: indicate the size of two image is different. + */ +#define PPA_BLEND_SIZE_DIFF_ST (BIT(0)) +#define PPA_BLEND_SIZE_DIFF_ST_M (PPA_BLEND_SIZE_DIFF_ST_V << PPA_BLEND_SIZE_DIFF_ST_S) +#define PPA_BLEND_SIZE_DIFF_ST_V 0x00000001U +#define PPA_BLEND_SIZE_DIFF_ST_S 0 +/** PPA_BLEND_YUV_X_SCALE_ERR_ST : RO; bitpos: [1]; default: 0; + * Represents that x param is an odd num when enable yuv422 or yuv420 + */ +#define PPA_BLEND_YUV_X_SCALE_ERR_ST (BIT(1)) +#define PPA_BLEND_YUV_X_SCALE_ERR_ST_M (PPA_BLEND_YUV_X_SCALE_ERR_ST_V << PPA_BLEND_YUV_X_SCALE_ERR_ST_S) +#define PPA_BLEND_YUV_X_SCALE_ERR_ST_V 0x00000001U +#define PPA_BLEND_YUV_X_SCALE_ERR_ST_S 1 +/** PPA_BLEND_YUV_Y_SCALE_ERR_ST : RO; bitpos: [2]; default: 0; + * Represents that y param is an odd num when enable yuv420 + */ +#define PPA_BLEND_YUV_Y_SCALE_ERR_ST (BIT(2)) +#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_M (PPA_BLEND_YUV_Y_SCALE_ERR_ST_V << PPA_BLEND_YUV_Y_SCALE_ERR_ST_S) +#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_V 0x00000001U +#define PPA_BLEND_YUV_Y_SCALE_ERR_ST_S 2 + +/** PPA_SR_PARAM_ERR_ST_REG register + * Scaling and rotating coefficient error register + */ +#define PPA_SR_PARAM_ERR_ST_REG (DR_REG_PPA_BASE + 0x78) +/** PPA_TX_DSCR_VB_ERR_ST : RO; bitpos: [0]; default: 0; + * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive + * descriptor is larger than VA in 2DDMA receive descriptor. + */ +#define PPA_TX_DSCR_VB_ERR_ST (BIT(0)) +#define PPA_TX_DSCR_VB_ERR_ST_M (PPA_TX_DSCR_VB_ERR_ST_V << PPA_TX_DSCR_VB_ERR_ST_S) +#define PPA_TX_DSCR_VB_ERR_ST_V 0x00000001U +#define PPA_TX_DSCR_VB_ERR_ST_S 0 +/** PPA_TX_DSCR_HB_ERR_ST : RO; bitpos: [1]; default: 0; + * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive + * descriptor is larger than HA in 2DDMA receive descriptor. + */ +#define PPA_TX_DSCR_HB_ERR_ST (BIT(1)) +#define PPA_TX_DSCR_HB_ERR_ST_M (PPA_TX_DSCR_HB_ERR_ST_V << PPA_TX_DSCR_HB_ERR_ST_S) +#define PPA_TX_DSCR_HB_ERR_ST_V 0x00000001U +#define PPA_TX_DSCR_HB_ERR_ST_S 1 +/** PPA_Y_RX_SCAL_EQUAL_0_ERR_ST : RO; bitpos: [2]; default: 0; + * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + */ +#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST (BIT(2)) +#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_M (PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_V << PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_S) +#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_V 0x00000001U +#define PPA_Y_RX_SCAL_EQUAL_0_ERR_ST_S 2 +/** PPA_RX_DSCR_VB_ERR_ST : RO; bitpos: [3]; default: 0; + * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in + * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + */ +#define PPA_RX_DSCR_VB_ERR_ST (BIT(3)) +#define PPA_RX_DSCR_VB_ERR_ST_M (PPA_RX_DSCR_VB_ERR_ST_V << PPA_RX_DSCR_VB_ERR_ST_S) +#define PPA_RX_DSCR_VB_ERR_ST_V 0x00000001U +#define PPA_RX_DSCR_VB_ERR_ST_S 3 +/** PPA_YDST_LEN_TOO_SAMLL_ERR_ST : RO; bitpos: [4]; default: 0; + * The error is that the scaled image width is 0. For example. when source width is + * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as + * the result would be floored. + */ +#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST (BIT(4)) +#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_M (PPA_YDST_LEN_TOO_SAMLL_ERR_ST_V << PPA_YDST_LEN_TOO_SAMLL_ERR_ST_S) +#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_V 0x00000001U +#define PPA_YDST_LEN_TOO_SAMLL_ERR_ST_S 4 +/** PPA_YDST_LEN_TOO_LARGE_ERR_ST : RO; bitpos: [5]; default: 0; + * The error is that the scaled width is larger than (2^13 - 1). + */ +#define PPA_YDST_LEN_TOO_LARGE_ERR_ST (BIT(5)) +#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_M (PPA_YDST_LEN_TOO_LARGE_ERR_ST_V << PPA_YDST_LEN_TOO_LARGE_ERR_ST_S) +#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_V 0x00000001U +#define PPA_YDST_LEN_TOO_LARGE_ERR_ST_S 5 +/** PPA_X_RX_SCAL_EQUAL_0_ERR_ST : RO; bitpos: [6]; default: 0; + * The error is that the scaled image height is 0. + */ +#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST (BIT(6)) +#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_M (PPA_X_RX_SCAL_EQUAL_0_ERR_ST_V << PPA_X_RX_SCAL_EQUAL_0_ERR_ST_S) +#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_V 0x00000001U +#define PPA_X_RX_SCAL_EQUAL_0_ERR_ST_S 6 +/** PPA_RX_DSCR_HB_ERR_ST : RO; bitpos: [7]; default: 0; + * The error is that the HB in 2DDMA transmit descriptor plus the offset of X + * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit + * descriptor. + */ +#define PPA_RX_DSCR_HB_ERR_ST (BIT(7)) +#define PPA_RX_DSCR_HB_ERR_ST_M (PPA_RX_DSCR_HB_ERR_ST_V << PPA_RX_DSCR_HB_ERR_ST_S) +#define PPA_RX_DSCR_HB_ERR_ST_V 0x00000001U +#define PPA_RX_DSCR_HB_ERR_ST_S 7 +/** PPA_XDST_LEN_TOO_SAMLL_ERR_ST : RO; bitpos: [8]; default: 0; + * The error is that the scaled image height is 0. For example. when source height is + * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as + * the result would be floored. + */ +#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST (BIT(8)) +#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_M (PPA_XDST_LEN_TOO_SAMLL_ERR_ST_V << PPA_XDST_LEN_TOO_SAMLL_ERR_ST_S) +#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_V 0x00000001U +#define PPA_XDST_LEN_TOO_SAMLL_ERR_ST_S 8 +/** PPA_XDST_LEN_TOO_LARGE_ERR_ST : RO; bitpos: [9]; default: 0; + * The error is that the scaled image height is larger than (2^13 - 1). + */ +#define PPA_XDST_LEN_TOO_LARGE_ERR_ST (BIT(9)) +#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_M (PPA_XDST_LEN_TOO_LARGE_ERR_ST_V << PPA_XDST_LEN_TOO_LARGE_ERR_ST_S) +#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_V 0x00000001U +#define PPA_XDST_LEN_TOO_LARGE_ERR_ST_S 9 +/** PPA_X_YUV420_RX_SCALE_ERR_ST : RO; bitpos: [10]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv422 or yuv420 rx + */ +#define PPA_X_YUV420_RX_SCALE_ERR_ST (BIT(10)) +#define PPA_X_YUV420_RX_SCALE_ERR_ST_M (PPA_X_YUV420_RX_SCALE_ERR_ST_V << PPA_X_YUV420_RX_SCALE_ERR_ST_S) +#define PPA_X_YUV420_RX_SCALE_ERR_ST_V 0x00000001U +#define PPA_X_YUV420_RX_SCALE_ERR_ST_S 10 +/** PPA_Y_YUV420_RX_SCALE_ERR_ST : RO; bitpos: [11]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 rx + */ +#define PPA_Y_YUV420_RX_SCALE_ERR_ST (BIT(11)) +#define PPA_Y_YUV420_RX_SCALE_ERR_ST_M (PPA_Y_YUV420_RX_SCALE_ERR_ST_V << PPA_Y_YUV420_RX_SCALE_ERR_ST_S) +#define PPA_Y_YUV420_RX_SCALE_ERR_ST_V 0x00000001U +#define PPA_Y_YUV420_RX_SCALE_ERR_ST_S 11 +/** PPA_X_YUV420_TX_SCALE_ERR_ST : RO; bitpos: [12]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv422 or yuv420 tx + */ +#define PPA_X_YUV420_TX_SCALE_ERR_ST (BIT(12)) +#define PPA_X_YUV420_TX_SCALE_ERR_ST_M (PPA_X_YUV420_TX_SCALE_ERR_ST_V << PPA_X_YUV420_TX_SCALE_ERR_ST_S) +#define PPA_X_YUV420_TX_SCALE_ERR_ST_V 0x00000001U +#define PPA_X_YUV420_TX_SCALE_ERR_ST_S 12 +/** PPA_Y_YUV420_TX_SCALE_ERR_ST : RO; bitpos: [13]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 tx + */ +#define PPA_Y_YUV420_TX_SCALE_ERR_ST (BIT(13)) +#define PPA_Y_YUV420_TX_SCALE_ERR_ST_M (PPA_Y_YUV420_TX_SCALE_ERR_ST_V << PPA_Y_YUV420_TX_SCALE_ERR_ST_S) +#define PPA_Y_YUV420_TX_SCALE_ERR_ST_V 0x00000001U +#define PPA_Y_YUV420_TX_SCALE_ERR_ST_S 13 + +/** PPA_SR_STATUS_REG register + * SR FSM register + */ +#define PPA_SR_STATUS_REG (DR_REG_PPA_BASE + 0x7c) +/** PPA_SR_RX_DSCR_SAMPLE_STATE : RO; bitpos: [1:0]; default: 0; + * Reserved. + */ +#define PPA_SR_RX_DSCR_SAMPLE_STATE 0x00000003U +#define PPA_SR_RX_DSCR_SAMPLE_STATE_M (PPA_SR_RX_DSCR_SAMPLE_STATE_V << PPA_SR_RX_DSCR_SAMPLE_STATE_S) +#define PPA_SR_RX_DSCR_SAMPLE_STATE_V 0x00000003U +#define PPA_SR_RX_DSCR_SAMPLE_STATE_S 0 +/** PPA_SR_RX_SCAN_STATE : RO; bitpos: [3:2]; default: 0; + * Reserved. + */ +#define PPA_SR_RX_SCAN_STATE 0x00000003U +#define PPA_SR_RX_SCAN_STATE_M (PPA_SR_RX_SCAN_STATE_V << PPA_SR_RX_SCAN_STATE_S) +#define PPA_SR_RX_SCAN_STATE_V 0x00000003U +#define PPA_SR_RX_SCAN_STATE_S 2 +/** PPA_SR_TX_DSCR_SAMPLE_STATE : RO; bitpos: [5:4]; default: 0; + * Reserved. + */ +#define PPA_SR_TX_DSCR_SAMPLE_STATE 0x00000003U +#define PPA_SR_TX_DSCR_SAMPLE_STATE_M (PPA_SR_TX_DSCR_SAMPLE_STATE_V << PPA_SR_TX_DSCR_SAMPLE_STATE_S) +#define PPA_SR_TX_DSCR_SAMPLE_STATE_V 0x00000003U +#define PPA_SR_TX_DSCR_SAMPLE_STATE_S 4 +/** PPA_SR_TX_SCAN_STATE : RO; bitpos: [8:6]; default: 0; + * Reserved. + */ +#define PPA_SR_TX_SCAN_STATE 0x00000007U +#define PPA_SR_TX_SCAN_STATE_M (PPA_SR_TX_SCAN_STATE_V << PPA_SR_TX_SCAN_STATE_S) +#define PPA_SR_TX_SCAN_STATE_V 0x00000007U +#define PPA_SR_TX_SCAN_STATE_S 6 + +/** PPA_ECO_LOW_REG register + * Reserved. + */ +#define PPA_ECO_LOW_REG (DR_REG_PPA_BASE + 0x80) +/** PPA_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define PPA_RND_ECO_LOW 0xFFFFFFFFU +#define PPA_RND_ECO_LOW_M (PPA_RND_ECO_LOW_V << PPA_RND_ECO_LOW_S) +#define PPA_RND_ECO_LOW_V 0xFFFFFFFFU +#define PPA_RND_ECO_LOW_S 0 + +/** PPA_ECO_HIGH_REG register + * Reserved. + */ +#define PPA_ECO_HIGH_REG (DR_REG_PPA_BASE + 0x84) +/** PPA_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ +#define PPA_RND_ECO_HIGH 0xFFFFFFFFU +#define PPA_RND_ECO_HIGH_M (PPA_RND_ECO_HIGH_V << PPA_RND_ECO_HIGH_S) +#define PPA_RND_ECO_HIGH_V 0xFFFFFFFFU +#define PPA_RND_ECO_HIGH_S 0 + +/** PPA_ECO_CELL_CTRL_REG register + * Reserved. + */ +#define PPA_ECO_CELL_CTRL_REG (DR_REG_PPA_BASE + 0x88) +/** PPA_RDN_RESULT : RO; bitpos: [0]; default: 0; + * Reserved. + */ +#define PPA_RDN_RESULT (BIT(0)) +#define PPA_RDN_RESULT_M (PPA_RDN_RESULT_V << PPA_RDN_RESULT_S) +#define PPA_RDN_RESULT_V 0x00000001U +#define PPA_RDN_RESULT_S 0 +/** PPA_RDN_ENA : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define PPA_RDN_ENA (BIT(1)) +#define PPA_RDN_ENA_M (PPA_RDN_ENA_V << PPA_RDN_ENA_S) +#define PPA_RDN_ENA_V 0x00000001U +#define PPA_RDN_ENA_S 1 + +/** PPA_SRAM_CTRL_REG register + * PPA SRAM Control Register + */ +#define PPA_SRAM_CTRL_REG (DR_REG_PPA_BASE + 0x8c) +/** PPA_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ +#define PPA_MEM_AUX_CTRL 0x00003FFFU +#define PPA_MEM_AUX_CTRL_M (PPA_MEM_AUX_CTRL_V << PPA_MEM_AUX_CTRL_S) +#define PPA_MEM_AUX_CTRL_V 0x00003FFFU +#define PPA_MEM_AUX_CTRL_S 0 + +/** PPA_DEBUG_CTRL0_REG register + * debug register + */ +#define PPA_DEBUG_CTRL0_REG (DR_REG_PPA_BASE + 0x90) +/** PPA_DBG_REPLACE_SEL : R/W; bitpos: [2:0]; default: 0; + * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx + * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: + * blend output + */ +#define PPA_DBG_REPLACE_SEL 0x00000007U +#define PPA_DBG_REPLACE_SEL_M (PPA_DBG_REPLACE_SEL_V << PPA_DBG_REPLACE_SEL_S) +#define PPA_DBG_REPLACE_SEL_V 0x00000007U +#define PPA_DBG_REPLACE_SEL_S 0 + +/** PPA_DEBUG_CTRL1_REG register + * debug register + */ +#define PPA_DEBUG_CTRL1_REG (DR_REG_PPA_BASE + 0x94) +/** PPA_DBG_REPLACE_DATA : R/W; bitpos: [31:0]; default: 0; + * Configures the replace data + */ +#define PPA_DBG_REPLACE_DATA 0xFFFFFFFFU +#define PPA_DBG_REPLACE_DATA_M (PPA_DBG_REPLACE_DATA_V << PPA_DBG_REPLACE_DATA_S) +#define PPA_DBG_REPLACE_DATA_V 0xFFFFFFFFU +#define PPA_DBG_REPLACE_DATA_S 0 + +/** PPA_RGB2GRAY_REG register + * rgb2gray register + */ +#define PPA_RGB2GRAY_REG (DR_REG_PPA_BASE + 0x98) +/** PPA_RGB2GRAY_B : R/W; bitpos: [7:0]; default: 85; + * Configures the b parameter for rgb2gray + */ +#define PPA_RGB2GRAY_B 0x000000FFU +#define PPA_RGB2GRAY_B_M (PPA_RGB2GRAY_B_V << PPA_RGB2GRAY_B_S) +#define PPA_RGB2GRAY_B_V 0x000000FFU +#define PPA_RGB2GRAY_B_S 0 +/** PPA_RGB2GRAY_G : R/W; bitpos: [15:8]; default: 86; + * Configures the g parameter for rgb2gray + */ +#define PPA_RGB2GRAY_G 0x000000FFU +#define PPA_RGB2GRAY_G_M (PPA_RGB2GRAY_G_V << PPA_RGB2GRAY_G_S) +#define PPA_RGB2GRAY_G_V 0x000000FFU +#define PPA_RGB2GRAY_G_S 8 +/** PPA_RGB2GRAY_R : R/W; bitpos: [23:16]; default: 85; + * Configures the r parameter for rgb2gray + */ +#define PPA_RGB2GRAY_R 0x000000FFU +#define PPA_RGB2GRAY_R_M (PPA_RGB2GRAY_R_V << PPA_RGB2GRAY_R_S) +#define PPA_RGB2GRAY_R_V 0x000000FFU +#define PPA_RGB2GRAY_R_S 16 + +/** PPA_DATE_REG register + * PPA Version register + */ +#define PPA_DATE_REG (DR_REG_PPA_BASE + 0x100) +/** PPA_DATE : R/W; bitpos: [31:0]; default: 539234848; + * register version. + */ +#define PPA_DATE 0xFFFFFFFFU +#define PPA_DATE_M (PPA_DATE_V << PPA_DATE_S) +#define PPA_DATE_V 0xFFFFFFFFU +#define PPA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ppa_struct.h new file mode 100644 index 0000000000..fe85942a62 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ppa_struct.h @@ -0,0 +1,908 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of blend0_clut_data register + * CLUT sram data read/write register in background plane of blender + */ +typedef union { + struct { + /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in background plane of blender engine through + * this field in fifo mode. + */ + uint32_t rdwr_word_blend0_clut:32; + }; + uint32_t val; +} ppa_blend0_clut_data_reg_t; + +/** Type of blend1_clut_data register + * CLUT sram data read/write register in foreground plane of blender + */ +typedef union { + struct { + /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0; + * Write and read data to/from CLUT RAM in foreground plane of blender engine through + * this field in fifo mode. + */ + uint32_t rdwr_word_blend1_clut:32; + }; + uint32_t val; +} ppa_blend1_clut_data_reg_t; + +/** Type of clut_conf register + * CLUT configure register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register + * PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode. + */ + uint32_t apb_fifo_mask:1; + /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND0 CLUT. + */ + uint32_t blend0_clut_mem_rst:1; + /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0; + * Write 1 then write 0 to this bit to reset BLEND1 CLUT. + */ + uint32_t blend1_clut_mem_rst:1; + /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + */ + uint32_t blend0_clut_mem_rdaddr_rst:1; + /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0; + * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + */ + uint32_t blend1_clut_mem_rdaddr_rst:1; + /** blend_clut_mem_force_pd : R/W; bitpos: [5]; default: 0; + * 1: force power down BLEND CLUT memory. + */ + uint32_t blend_clut_mem_force_pd:1; + /** blend_clut_mem_force_pu : R/W; bitpos: [6]; default: 0; + * 1: force power up BLEND CLUT memory. + */ + uint32_t blend_clut_mem_force_pu:1; + /** blend_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0; + * 1: Force clock on for BLEND CLUT memory. + */ + uint32_t blend_clut_mem_clk_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} ppa_clut_conf_reg_t; + +/** Type of sr_color_mode register + * Scaling and rotating engine color mode register + */ +typedef union { + struct { + /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: + * RGB888. 2: RGB565. 8: YUV420. others: Reserved. + */ + uint32_t sr_rx_cm:4; + /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; + * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. + * 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + */ + uint32_t sr_tx_cm:4; + /** yuv_rx_range : R/W; bitpos: [8]; default: 0; + * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + */ + uint32_t yuv_rx_range:1; + /** yuv_tx_range : R/W; bitpos: [9]; default: 0; + * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + */ + uint32_t yuv_tx_range:1; + /** yuv2rgb_protocol : R/W; bitpos: [10]; default: 0; + * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + */ + uint32_t yuv2rgb_protocol:1; + /** rgb2yuv_protocol : R/W; bitpos: [11]; default: 0; + * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + */ + uint32_t rgb2yuv_protocol:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} ppa_sr_color_mode_reg_t; + +/** Type of blend_color_mode register + * blending engine color mode register + */ +typedef union { + struct { + /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; + * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. + */ + uint32_t blend0_rx_cm:4; + /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; + * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + */ + uint32_t blend1_rx_cm:4; + /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; + * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: + * RGB565. 3: Reserved.. + */ + uint32_t blend_tx_cm:4; + uint32_t reserved_12:20; + }; + uint32_t val; +} ppa_blend_color_mode_reg_t; + +/** Type of sr_byte_order register + * Scaling and rotating engine byte order register + */ +typedef union { + struct { + /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t sr_rx_byte_swap_en:1; + /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t sr_rx_rgb_swap_en:1; + /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to bypass the macro block order function. This function is used + * to improve efficient accessing external memory. + */ + uint32_t sr_macro_bk_ro_bypass:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_sr_byte_order_reg_t; + +/** Type of blend_byte_order register + * Blending engine byte order register + */ +typedef union { + struct { + /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t blend0_rx_byte_swap_en:1; + /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 + * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + */ + uint32_t blend1_rx_byte_swap_en:1; + /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t blend0_rx_rgb_swap_en:1; + /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb + * would be swap to bgr. + */ + uint32_t blend1_rx_rgb_swap_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ppa_blend_byte_order_reg_t; + +/** Type of blend_trans_mode register + * Blending engine mode configure register + */ +typedef union { + struct { + /** blend_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable alpha blending. + */ + uint32_t blend_en:1; + /** blend_bypass : R/W; bitpos: [1]; default: 0; + * Set this bit to bypass blender. Then background date would be output. + */ + uint32_t blend_bypass:1; + /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0; + * This bit is used to enable fix pixel filling. When this mode is enable only Tx + * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + */ + uint32_t blend_fix_pixel_fill_en:1; + /** blend_trans_mode_update : WT; bitpos: [3]; default: 0; + * Set this bit to update the transfer mode. Only the bit is set the transfer mode is + * valid. + */ + uint32_t blend_trans_mode_update:1; + /** blend_rst : R/W; bitpos: [4]; default: 0; + * write 1 then write 0 to reset blending engine. + */ + uint32_t blend_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} ppa_blend_trans_mode_reg_t; + +/** Type of sr_fix_alpha register + * Scaling and rotating engine alpha override register + */ +typedef union { + struct { + /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for Scaling and Rotating + * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t sr_rx_fix_alpha:8; + /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t sr_rx_alpha_mod:2; + /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t sr_rx_alpha_inv:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} ppa_sr_fix_alpha_reg_t; + +/** Type of blend_tx_size register + * Fix pixel filling mode image size register + */ +typedef union { + struct { + /** blend_hb : R/W; bitpos: [13:0]; default: 0; + * The horizontal width of image block that would be filled in fix pixel filling mode. + * The unit is pixel + */ + uint32_t blend_hb:14; + /** blend_vb : R/W; bitpos: [27:14]; default: 0; + * The vertical width of image block that would be filled in fix pixel filling mode. + * The unit is pixel + */ + uint32_t blend_vb:14; + uint32_t reserved_28:4; + }; + uint32_t val; +} ppa_blend_tx_size_reg_t; + +/** Type of blend_fix_alpha register + * Blending engine alpha override register + */ +typedef union { + struct { + /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; + * The value would replace the alpha value in received pixel for background plane of + * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t blend0_rx_fix_alpha:8; + /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128; + * The value would replace the alpha value in received pixel for foreground plane of + * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + */ + uint32_t blend1_rx_fix_alpha:8; + /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t blend0_rx_alpha_mod:2; + /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: + * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + */ + uint32_t blend1_rx_alpha_mod:2; + /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t blend0_rx_alpha_inv:1; + /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0; + * Set this bit to invert the original alpha value. When RX color mode is + * RGB565/RGB88. The original alpha value is 255. + */ + uint32_t blend1_rx_alpha_inv:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ppa_blend_fix_alpha_reg_t; + +/** Type of blend_rgb register + * RGB color register + */ +typedef union { + struct { + /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128; + * blue color for A4/A8 mode. + */ + uint32_t blend1_rx_b:8; + /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128; + * green color for A4/A8 mode. + */ + uint32_t blend1_rx_g:8; + /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128; + * red color for A4/A8 mode. + */ + uint32_t blend1_rx_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_blend_rgb_reg_t; + +/** Type of blend_fix_pixel register + * Blending engine fix pixel register + */ +typedef union { + struct { + /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0; + * The configure fix pixel in fix pixel filling mode for blender engine. + */ + uint32_t blend_tx_fix_pixel:32; + }; + uint32_t val; +} ppa_blend_fix_pixel_reg_t; + +/** Type of ck_fg_low register + * foreground color key lower threshold + */ +typedef union { + struct { + /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of foreground b channel + */ + uint32_t colorkey_fg_b_low:8; + /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of foreground g channel + */ + uint32_t colorkey_fg_g_low:8; + /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of foreground r channel + */ + uint32_t colorkey_fg_r_low:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_fg_low_reg_t; + +/** Type of ck_fg_high register + * foreground color key higher threshold + */ +typedef union { + struct { + /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of foreground b channel + */ + uint32_t colorkey_fg_b_high:8; + /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of foreground g channel + */ + uint32_t colorkey_fg_g_high:8; + /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of foreground r channel + */ + uint32_t colorkey_fg_r_high:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_fg_high_reg_t; + +/** Type of ck_bg_low register + * background color key lower threshold + */ +typedef union { + struct { + /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255; + * color key lower threshold of background b channel + */ + uint32_t colorkey_bg_b_low:8; + /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255; + * color key lower threshold of background g channel + */ + uint32_t colorkey_bg_g_low:8; + /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255; + * color key lower threshold of background r channel + */ + uint32_t colorkey_bg_r_low:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_bg_low_reg_t; + +/** Type of ck_bg_high register + * background color key higher threshold + */ +typedef union { + struct { + /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0; + * color key higher threshold of background b channel + */ + uint32_t colorkey_bg_b_high:8; + /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0; + * color key higher threshold of background g channel + */ + uint32_t colorkey_bg_g_high:8; + /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0; + * color key higher threshold of background r channel + */ + uint32_t colorkey_bg_r_high:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_ck_bg_high_reg_t; + +/** Type of ck_default register + * default value when foreground and background both in color key range + */ +typedef union { + struct { + /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; + * default B channel value of color key + */ + uint32_t colorkey_default_b:8; + /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; + * default G channel value of color key + */ + uint32_t colorkey_default_g:8; + /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; + * default R channel value of color key + */ + uint32_t colorkey_default_r:8; + /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; + * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the + * result is fg + */ + uint32_t colorkey_fg_bg_reverse:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} ppa_ck_default_reg_t; + +/** Type of sr_scal_rotate register + * Scaling and rotating coefficient register + */ +typedef union { + struct { + /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1; + * The integrated part of scaling coefficient in X direction. + */ + uint32_t sr_scal_x_int:8; + /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0; + * The fragment part of scaling coefficient in X direction. + */ + uint32_t sr_scal_x_frag:4; + /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1; + * The integrated part of scaling coefficient in Y direction. + */ + uint32_t sr_scal_y_int:8; + /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0; + * The fragment part of scaling coefficient in Y direction. + */ + uint32_t sr_scal_y_frag:4; + /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0; + * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + */ + uint32_t sr_rotate_angle:2; + /** scal_rotate_rst : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset scaling and rotating engine. + */ + uint32_t scal_rotate_rst:1; + /** scal_rotate_start : WT; bitpos: [27]; default: 0; + * Write 1 to enable scaling and rotating engine after parameter is configured. + */ + uint32_t scal_rotate_start:1; + /** sr_mirror_x : R/W; bitpos: [28]; default: 0; + * Image mirror in X direction. 0: disable, 1: enable + */ + uint32_t sr_mirror_x:1; + /** sr_mirror_y : R/W; bitpos: [29]; default: 0; + * Image mirror in Y direction. 0: disable, 1: enable + */ + uint32_t sr_mirror_y:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ppa_sr_scal_rotate_reg_t; + +/** Type of sr_mem_pd register + * SR memory power done register + */ +typedef union { + struct { + /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to force clock enable of scaling and rotating engine's data memory. + */ + uint32_t sr_mem_clk_ena:1; + /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force power down scaling and rotating engine's data memory. + */ + uint32_t sr_mem_force_pd:1; + /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up scaling and rotating engine's data memory. + */ + uint32_t sr_mem_force_pu:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_sr_mem_pd_reg_t; + +/** Type of reg_conf register + * Register clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * PPA register clock gate enable signal. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ppa_reg_conf_reg_t; + +/** Type of eco_low register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t rnd_eco_low:32; + }; + uint32_t val; +} ppa_eco_low_reg_t; + +/** Type of eco_high register + * Reserved. + */ +typedef union { + struct { + /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t rnd_eco_high:32; + }; + uint32_t val; +} ppa_eco_high_reg_t; + +/** Type of sram_ctrl register + * PPA SRAM Control Register + */ +typedef union { + struct { + /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ + uint32_t mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} ppa_sram_ctrl_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Raw status interrupt + */ +typedef union { + struct { + /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when scaling and rotating engine + * calculate one frame image. + */ + uint32_t sr_eof_int_raw:1; + /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when blending engine calculate one frame + * image. + */ + uint32_t blend_eof_int_raw:1; + /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the configured scaling and rotating + * coefficient is wrong. User can check the reasons through register + * PPA_SR_PARAM_ERR_ST_REG. + */ + uint32_t sr_param_cfg_err_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt + */ +typedef union { + struct { + /** sr_eof_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_st:1; + /** blend_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_st:1; + /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_ena:1; + /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_ena:1; + /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** sr_eof_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PPA_SR_EOF_INT interrupt. + */ + uint32_t sr_eof_int_clr:1; + /** blend_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + */ + uint32_t blend_eof_int_clr:1; + /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + */ + uint32_t sr_param_cfg_err_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of clut_cnt register + * BLEND CLUT write counter register + */ +typedef union { + struct { + /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0; + * The write data counter of BLEND0 CLUT in fifo mode. + */ + uint32_t blend0_clut_cnt:9; + /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0; + * The write data counter of BLEND1 CLUT in fifo mode. + */ + uint32_t blend1_clut_cnt:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} ppa_clut_cnt_reg_t; + +/** Type of blend_st register + * Blending engine status register + */ +typedef union { + struct { + /** blend_size_diff_st : RO; bitpos: [0]; default: 0; + * 1: indicate the size of two image is different. + */ + uint32_t blend_size_diff_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ppa_blend_st_reg_t; + +/** Type of sr_param_err_st register + * Scaling and rotating coefficient error register + */ +typedef union { + struct { + /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0; + * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive + * descriptor is larger than VA in 2DDMA receive descriptor. + */ + uint32_t tx_dscr_vb_err_st:1; + /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0; + * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive + * descriptor is larger than HA in 2DDMA receive descriptor. + */ + uint32_t tx_dscr_hb_err_st:1; + /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0; + * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + */ + uint32_t y_rx_scal_equal_0_err_st:1; + /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0; + * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in + * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + */ + uint32_t rx_dscr_vb_err_st:1; + /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0; + * The error is that the scaled image width is 0. For example. when source width is + * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as + * the result would be floored. + */ + uint32_t ydst_len_too_samll_err_st:1; + /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0; + * The error is that the scaled width is larger than (2^13 - 1). + */ + uint32_t ydst_len_too_large_err_st:1; + /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0; + * The error is that the scaled image height is 0. + */ + uint32_t x_rx_scal_equal_0_err_st:1; + /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0; + * The error is that the HB in 2DDMA transmit descriptor plus the offset of X + * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit + * descriptor. + */ + uint32_t rx_dscr_hb_err_st:1; + /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0; + * The error is that the scaled image height is 0. For example. when source height is + * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as + * the result would be floored. + */ + uint32_t xdst_len_too_samll_err_st:1; + /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0; + * The error is that the scaled image height is larger than (2^13 - 1). + */ + uint32_t xdst_len_too_large_err_st:1; + /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv420 rx + */ + uint32_t x_yuv420_rx_scale_err_st:1; + /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 rx + */ + uint32_t y_yuv420_rx_scale_err_st:1; + /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; + * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable + * yuv420 tx + */ + uint32_t x_yuv420_tx_scale_err_st:1; + /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; + * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable + * yuv420 tx + */ + uint32_t y_yuv420_tx_scale_err_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} ppa_sr_param_err_st_reg_t; + +/** Type of sr_status register + * SR FSM register + */ +typedef union { + struct { + /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0; + * Reserved. + */ + uint32_t sr_rx_dscr_sample_state:2; + /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0; + * Reserved. + */ + uint32_t sr_rx_scan_state:2; + /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0; + * Reserved. + */ + uint32_t sr_tx_dscr_sample_state:2; + /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0; + * Reserved. + */ + uint32_t sr_tx_scan_state:3; + uint32_t reserved_9:23; + }; + uint32_t val; +} ppa_sr_status_reg_t; + +/** Type of eco_cell_ctrl register + * Reserved. + */ +typedef union { + struct { + /** rdn_result : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t rdn_result:1; + /** rdn_ena : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t rdn_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ppa_eco_cell_ctrl_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PPA Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36716609; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} ppa_date_reg_t; + + +typedef struct ppa_dev_t { + volatile ppa_blend0_clut_data_reg_t blend0_clut_data; + volatile ppa_blend1_clut_data_reg_t blend1_clut_data; + uint32_t reserved_008; + volatile ppa_clut_conf_reg_t clut_conf; + volatile ppa_int_raw_reg_t int_raw; + volatile ppa_int_st_reg_t int_st; + volatile ppa_int_ena_reg_t int_ena; + volatile ppa_int_clr_reg_t int_clr; + volatile ppa_sr_color_mode_reg_t sr_color_mode; + volatile ppa_blend_color_mode_reg_t blend_color_mode; + volatile ppa_sr_byte_order_reg_t sr_byte_order; + volatile ppa_blend_byte_order_reg_t blend_byte_order; + uint32_t reserved_030; + volatile ppa_blend_trans_mode_reg_t blend_trans_mode; + volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha; + volatile ppa_blend_tx_size_reg_t blend_tx_size; + volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha; + uint32_t reserved_044; + volatile ppa_blend_rgb_reg_t blend_rgb; + volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel; + volatile ppa_ck_fg_low_reg_t ck_fg_low; + volatile ppa_ck_fg_high_reg_t ck_fg_high; + volatile ppa_ck_bg_low_reg_t ck_bg_low; + volatile ppa_ck_bg_high_reg_t ck_bg_high; + volatile ppa_ck_default_reg_t ck_default; + volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate; + volatile ppa_sr_mem_pd_reg_t sr_mem_pd; + volatile ppa_reg_conf_reg_t reg_conf; + volatile ppa_clut_cnt_reg_t clut_cnt; + volatile ppa_blend_st_reg_t blend_st; + volatile ppa_sr_param_err_st_reg_t sr_param_err_st; + volatile ppa_sr_status_reg_t sr_status; + volatile ppa_eco_low_reg_t eco_low; + volatile ppa_eco_high_reg_t eco_high; + volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; + volatile ppa_sram_ctrl_reg_t sram_ctrl; + uint32_t reserved_090[28]; + volatile ppa_date_reg_t date; +} ppa_dev_t; + +extern ppa_dev_t PPA; + +#ifndef __cplusplus +_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pvt_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/pvt_reg.h new file mode 100644 index 0000000000..cae14a798b --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pvt_reg.h @@ -0,0 +1,3955 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PVT_PMUP_BITMAP_HIGH0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_BASE + 0x0) +/** PVT_PUMP_BITMAP_HIGH0 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel0 + */ +#define PVT_PUMP_BITMAP_HIGH0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_M (PVT_PUMP_BITMAP_HIGH0_V << PVT_PUMP_BITMAP_HIGH0_S) +#define PVT_PUMP_BITMAP_HIGH0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_S 0 + +/** PVT_PMUP_BITMAP_HIGH1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_BASE + 0x4) +/** PVT_PUMP_BITMAP_HIGH1 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel1 + */ +#define PVT_PUMP_BITMAP_HIGH1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_M (PVT_PUMP_BITMAP_HIGH1_V << PVT_PUMP_BITMAP_HIGH1_S) +#define PVT_PUMP_BITMAP_HIGH1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_S 0 + +/** PVT_PMUP_BITMAP_HIGH2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_BASE + 0x8) +/** PVT_PUMP_BITMAP_HIGH2 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel2 + */ +#define PVT_PUMP_BITMAP_HIGH2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_M (PVT_PUMP_BITMAP_HIGH2_V << PVT_PUMP_BITMAP_HIGH2_S) +#define PVT_PUMP_BITMAP_HIGH2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_S 0 + +/** PVT_PMUP_BITMAP_HIGH3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_BASE + 0xc) +/** PVT_PUMP_BITMAP_HIGH3 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel3 + */ +#define PVT_PUMP_BITMAP_HIGH3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_M (PVT_PUMP_BITMAP_HIGH3_V << PVT_PUMP_BITMAP_HIGH3_S) +#define PVT_PUMP_BITMAP_HIGH3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_S 0 + +/** PVT_PMUP_BITMAP_HIGH4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_BASE + 0x10) +/** PVT_PUMP_BITMAP_HIGH4 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel4 + */ +#define PVT_PUMP_BITMAP_HIGH4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_M (PVT_PUMP_BITMAP_HIGH4_V << PVT_PUMP_BITMAP_HIGH4_S) +#define PVT_PUMP_BITMAP_HIGH4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_S 0 + +/** PVT_PMUP_BITMAP_LOW0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_BASE + 0x14) +/** PVT_PUMP_BITMAP_LOW0 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel0 + */ +#define PVT_PUMP_BITMAP_LOW0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_M (PVT_PUMP_BITMAP_LOW0_V << PVT_PUMP_BITMAP_LOW0_S) +#define PVT_PUMP_BITMAP_LOW0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_S 0 + +/** PVT_PMUP_BITMAP_LOW1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_BASE + 0x18) +/** PVT_PUMP_BITMAP_LOW1 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel1 + */ +#define PVT_PUMP_BITMAP_LOW1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_M (PVT_PUMP_BITMAP_LOW1_V << PVT_PUMP_BITMAP_LOW1_S) +#define PVT_PUMP_BITMAP_LOW1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_S 0 + +/** PVT_PMUP_BITMAP_LOW2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_BASE + 0x1c) +/** PVT_PUMP_BITMAP_LOW2 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel2 + */ +#define PVT_PUMP_BITMAP_LOW2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_M (PVT_PUMP_BITMAP_LOW2_V << PVT_PUMP_BITMAP_LOW2_S) +#define PVT_PUMP_BITMAP_LOW2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_S 0 + +/** PVT_PMUP_BITMAP_LOW3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_BASE + 0x20) +/** PVT_PUMP_BITMAP_LOW3 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel3 + */ +#define PVT_PUMP_BITMAP_LOW3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_M (PVT_PUMP_BITMAP_LOW3_V << PVT_PUMP_BITMAP_LOW3_S) +#define PVT_PUMP_BITMAP_LOW3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_S 0 + +/** PVT_PMUP_BITMAP_LOW4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_BASE + 0x24) +/** PVT_PUMP_BITMAP_LOW4 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel4 + */ +#define PVT_PUMP_BITMAP_LOW4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_M (PVT_PUMP_BITMAP_LOW4_V << PVT_PUMP_BITMAP_LOW4_S) +#define PVT_PUMP_BITMAP_LOW4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_S 0 + +/** PVT_PMUP_DRV_CFG_REG register + * configure pump drv + */ +#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_BASE + 0x28) +/** PVT_BYPASS_EFUSE_CTRL : R/W; bitpos: [8]; default: 1; + * needs desc + */ +#define PVT_BYPASS_EFUSE_CTRL (BIT(8)) +#define PVT_BYPASS_EFUSE_CTRL_M (PVT_BYPASS_EFUSE_CTRL_V << PVT_BYPASS_EFUSE_CTRL_S) +#define PVT_BYPASS_EFUSE_CTRL_V 0x00000001U +#define PVT_BYPASS_EFUSE_CTRL_S 8 +/** PVT_PUMP_EN : R/W; bitpos: [9]; default: 0; + * configure pvt charge xpd + */ +#define PVT_PUMP_EN (BIT(9)) +#define PVT_PUMP_EN_M (PVT_PUMP_EN_V << PVT_PUMP_EN_S) +#define PVT_PUMP_EN_V 0x00000001U +#define PVT_PUMP_EN_S 9 +/** PVT_CLK_EN : R/W; bitpos: [10]; default: 0; + * force register clken + */ +#define PVT_CLK_EN (BIT(10)) +#define PVT_CLK_EN_M (PVT_CLK_EN_V << PVT_CLK_EN_S) +#define PVT_CLK_EN_V 0x00000001U +#define PVT_CLK_EN_S 10 +/** PVT_PUMP_DRV4 : R/W; bitpos: [14:11]; default: 0; + * configure cmd4 drv + */ +#define PVT_PUMP_DRV4 0x0000000FU +#define PVT_PUMP_DRV4_M (PVT_PUMP_DRV4_V << PVT_PUMP_DRV4_S) +#define PVT_PUMP_DRV4_V 0x0000000FU +#define PVT_PUMP_DRV4_S 11 +/** PVT_PUMP_DRV3 : R/W; bitpos: [18:15]; default: 0; + * configure cmd3 drv + */ +#define PVT_PUMP_DRV3 0x0000000FU +#define PVT_PUMP_DRV3_M (PVT_PUMP_DRV3_V << PVT_PUMP_DRV3_S) +#define PVT_PUMP_DRV3_V 0x0000000FU +#define PVT_PUMP_DRV3_S 15 +/** PVT_PUMP_DRV2 : R/W; bitpos: [22:19]; default: 0; + * configure cmd2 drv + */ +#define PVT_PUMP_DRV2 0x0000000FU +#define PVT_PUMP_DRV2_M (PVT_PUMP_DRV2_V << PVT_PUMP_DRV2_S) +#define PVT_PUMP_DRV2_V 0x0000000FU +#define PVT_PUMP_DRV2_S 19 +/** PVT_PUMP_DRV1 : R/W; bitpos: [26:23]; default: 0; + * configure cmd1 drv + */ +#define PVT_PUMP_DRV1 0x0000000FU +#define PVT_PUMP_DRV1_M (PVT_PUMP_DRV1_V << PVT_PUMP_DRV1_S) +#define PVT_PUMP_DRV1_V 0x0000000FU +#define PVT_PUMP_DRV1_S 23 +/** PVT_PUMP_DRV0 : R/W; bitpos: [30:27]; default: 0; + * configure cmd0 drv + */ +#define PVT_PUMP_DRV0 0x0000000FU +#define PVT_PUMP_DRV0_M (PVT_PUMP_DRV0_V << PVT_PUMP_DRV0_S) +#define PVT_PUMP_DRV0_V 0x0000000FU +#define PVT_PUMP_DRV0_S 27 + +/** PVT_PMUP_CHANNEL_CFG_REG register + * configure the code of valid pump channel code + */ +#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_BASE + 0x2c) +/** PVT_PUMP_CHANNEL_CODE4 : R/W; bitpos: [11:7]; default: 0; + * configure cmd4 code + */ +#define PVT_PUMP_CHANNEL_CODE4 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_M (PVT_PUMP_CHANNEL_CODE4_V << PVT_PUMP_CHANNEL_CODE4_S) +#define PVT_PUMP_CHANNEL_CODE4_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_S 7 +/** PVT_PUMP_CHANNEL_CODE3 : R/W; bitpos: [16:12]; default: 0; + * configure cmd3 code + */ +#define PVT_PUMP_CHANNEL_CODE3 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_M (PVT_PUMP_CHANNEL_CODE3_V << PVT_PUMP_CHANNEL_CODE3_S) +#define PVT_PUMP_CHANNEL_CODE3_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_S 12 +/** PVT_PUMP_CHANNEL_CODE2 : R/W; bitpos: [21:17]; default: 0; + * configure cmd2 code + */ +#define PVT_PUMP_CHANNEL_CODE2 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_M (PVT_PUMP_CHANNEL_CODE2_V << PVT_PUMP_CHANNEL_CODE2_S) +#define PVT_PUMP_CHANNEL_CODE2_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_S 17 +/** PVT_PUMP_CHANNEL_CODE1 : R/W; bitpos: [26:22]; default: 0; + * configure cmd1 code + */ +#define PVT_PUMP_CHANNEL_CODE1 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_M (PVT_PUMP_CHANNEL_CODE1_V << PVT_PUMP_CHANNEL_CODE1_S) +#define PVT_PUMP_CHANNEL_CODE1_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_S 22 +/** PVT_PUMP_CHANNEL_CODE0 : R/W; bitpos: [31:27]; default: 0; + * configure cmd0 code + */ +#define PVT_PUMP_CHANNEL_CODE0 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_M (PVT_PUMP_CHANNEL_CODE0_V << PVT_PUMP_CHANNEL_CODE0_S) +#define PVT_PUMP_CHANNEL_CODE0_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_S 27 + +/** PVT_CLK_CFG_REG register + * configure pvt clk + */ +#define PVT_CLK_CFG_REG (DR_REG_PVT_BASE + 0x30) +/** PVT_PUMP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_PUMP_CLK_DIV_NUM 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_M (PVT_PUMP_CLK_DIV_NUM_V << PVT_PUMP_CLK_DIV_NUM_S) +#define PVT_PUMP_CLK_DIV_NUM_V 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_S 0 +/** PVT_MONITOR_CLK_PVT_EN : R/W; bitpos: [8]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_CLK_PVT_EN (BIT(8)) +#define PVT_MONITOR_CLK_PVT_EN_M (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S) +#define PVT_MONITOR_CLK_PVT_EN_V 0x00000001U +#define PVT_MONITOR_CLK_PVT_EN_S 8 +/** PVT_CLK_SEL : R/W; bitpos: [31]; default: 0; + * select pvt clk + */ +#define PVT_CLK_SEL (BIT(31)) +#define PVT_CLK_SEL_M (PVT_CLK_SEL_V << PVT_CLK_SEL_S) +#define PVT_CLK_SEL_V 0x00000001U +#define PVT_CLK_SEL_S 31 + +/** PVT_DBIAS_CHANNEL_SEL0_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_BASE + 0x34) +/** PVT_DBIAS_CHANNEL3_SEL : R/W; bitpos: [10:4]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_M (PVT_DBIAS_CHANNEL3_SEL_V << PVT_DBIAS_CHANNEL3_SEL_S) +#define PVT_DBIAS_CHANNEL3_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_S 4 +/** PVT_DBIAS_CHANNEL2_SEL : R/W; bitpos: [17:11]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_M (PVT_DBIAS_CHANNEL2_SEL_V << PVT_DBIAS_CHANNEL2_SEL_S) +#define PVT_DBIAS_CHANNEL2_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_S 11 +/** PVT_DBIAS_CHANNEL1_SEL : R/W; bitpos: [24:18]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_M (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S) +#define PVT_DBIAS_CHANNEL1_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_S 18 +/** PVT_DBIAS_CHANNEL0_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_M (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S) +#define PVT_DBIAS_CHANNEL0_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_S 25 + +/** PVT_DBIAS_CHANNEL_SEL1_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_BASE + 0x38) +/** PVT_DBIAS_CHANNEL4_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_M (PVT_DBIAS_CHANNEL4_SEL_V << PVT_DBIAS_CHANNEL4_SEL_S) +#define PVT_DBIAS_CHANNEL4_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_S 25 + +/** PVT_DBIAS_CHANNEL0_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_BASE + 0x3c) +/** PVT_DBIAS_CHANNEL0_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_M (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S) +#define PVT_DBIAS_CHANNEL0_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_S 0 + +/** PVT_DBIAS_CHANNEL1_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_BASE + 0x40) +/** PVT_DBIAS_CHANNEL1_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_M (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S) +#define PVT_DBIAS_CHANNEL1_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_S 0 + +/** PVT_DBIAS_CHANNEL2_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_BASE + 0x44) +/** PVT_DBIAS_CHANNEL2_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_M (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S) +#define PVT_DBIAS_CHANNEL2_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_S 0 + +/** PVT_DBIAS_CHANNEL3_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_BASE + 0x48) +/** PVT_DBIAS_CHANNEL3_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_M (PVT_DBIAS_CHANNEL3_CFG_V << PVT_DBIAS_CHANNEL3_CFG_S) +#define PVT_DBIAS_CHANNEL3_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_S 0 + +/** PVT_DBIAS_CHANNEL4_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_BASE + 0x4c) +/** PVT_DBIAS_CHANNEL4_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_M (PVT_DBIAS_CHANNEL4_CFG_V << PVT_DBIAS_CHANNEL4_CFG_S) +#define PVT_DBIAS_CHANNEL4_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_S 0 + +/** PVT_DBIAS_CMD0_REG register + * needs desc + */ +#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_BASE + 0x50) +/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD0 0x0001FFFFU +#define PVT_DBIAS_CMD0_M (PVT_DBIAS_CMD0_V << PVT_DBIAS_CMD0_S) +#define PVT_DBIAS_CMD0_V 0x0001FFFFU +#define PVT_DBIAS_CMD0_S 0 + +#define PVT_DBIAS_CMD0_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD0_PVT 0x7FF +#define PVT_DBIAS_CMD0_PVT_S 0 + +/** PVT_DBIAS_CMD1_REG register + * needs desc + */ +#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_BASE + 0x54) +/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD1 0x0001FFFFU +#define PVT_DBIAS_CMD1_M (PVT_DBIAS_CMD1_V << PVT_DBIAS_CMD1_S) +#define PVT_DBIAS_CMD1_V 0x0001FFFFU +#define PVT_DBIAS_CMD1_S 0 + +#define PVT_DBIAS_CMD1_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD1_PVT 0x7FF +#define PVT_DBIAS_CMD1_PVT_S 0 + +/** PVT_DBIAS_CMD2_REG register + * needs desc + */ +#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_BASE + 0x58) +/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD2 0x0001FFFFU +#define PVT_DBIAS_CMD2_M (PVT_DBIAS_CMD2_V << PVT_DBIAS_CMD2_S) +#define PVT_DBIAS_CMD2_V 0x0001FFFFU +#define PVT_DBIAS_CMD2_S 0 + +#define PVT_DBIAS_CMD2_OFFSET_FLAG 1 +#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16 +#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F +#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11 +#define PVT_DBIAS_CMD2_PVT 0x7FF +#define PVT_DBIAS_CMD2_PVT_S 0 + +/** PVT_DBIAS_CMD3_REG register + * needs desc + */ +#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_BASE + 0x5c) +/** PVT_DBIAS_CMD3 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD3 0x0001FFFFU +#define PVT_DBIAS_CMD3_M (PVT_DBIAS_CMD3_V << PVT_DBIAS_CMD3_S) +#define PVT_DBIAS_CMD3_V 0x0001FFFFU +#define PVT_DBIAS_CMD3_S 0 + +/** PVT_DBIAS_CMD4_REG register + * needs desc + */ +#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_BASE + 0x60) +/** PVT_DBIAS_CMD4 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD4 0x0001FFFFU +#define PVT_DBIAS_CMD4_M (PVT_DBIAS_CMD4_V << PVT_DBIAS_CMD4_S) +#define PVT_DBIAS_CMD4_V 0x0001FFFFU +#define PVT_DBIAS_CMD4_S 0 + +/** PVT_DBIAS_TIMER_REG register + * needs desc + */ +#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_BASE + 0x64) +/** PVT_TIMER_TARGET : R/W; bitpos: [30:15]; default: 65535; + * needs field desc + */ +#define PVT_TIMER_TARGET 0x0000FFFFU +#define PVT_TIMER_TARGET_M (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S) +#define PVT_TIMER_TARGET_V 0x0000FFFFU +#define PVT_TIMER_TARGET_S 15 +/** PVT_TIMER_EN : R/W; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMER_EN (BIT(31)) +#define PVT_TIMER_EN_M (PVT_TIMER_EN_V << PVT_TIMER_EN_S) +#define PVT_TIMER_EN_V 0x00000001U +#define PVT_TIMER_EN_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x68) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x6c) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x70) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x74) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x78) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x7c) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x80) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x84) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x88) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x8c) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x90) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x94) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x98) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x9c) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa0) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa4) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xa8) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xac) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb0) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb4) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xb8) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xbc) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc0) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc4) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xc8) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xcc) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd0) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd4) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xd8) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xdc) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe0) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe4) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xe8) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xec) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf0) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf4) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xf8) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xfc) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x100) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x104) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x108) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x10c) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x110) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x114) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x118) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x11c) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x120) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x124) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x128) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x12c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x130) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x134) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x138) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x13c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x140) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x144) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x148) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x14c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x150) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x154) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x158) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x15c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x160) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x164) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x168) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x16c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x170) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x174) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x178) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x17c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x180) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x184) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x188) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x18c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x190) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x194) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x198) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x19c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a0) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a4) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1a8) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1ac) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b0) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b4) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1b8) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1bc) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c0) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c4) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1c8) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1cc) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d0) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d4) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1d8) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1dc) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e0) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e4) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S 16 + +/** PVT_VALUE_UPDATE_REG register + * needs field desc + */ +#define PVT_VALUE_UPDATE_REG (DR_REG_PVT_BASE + 0x1e8) +/** PVT_VALUE_UPDATE : WT; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_VALUE_UPDATE (BIT(0)) +#define PVT_VALUE_UPDATE_M (PVT_VALUE_UPDATE_V << PVT_VALUE_UPDATE_S) +#define PVT_VALUE_UPDATE_V 0x00000001U +#define PVT_VALUE_UPDATE_S 0 +/** PVT_VALUE_UPDATE_BYPASS : R/W; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_VALUE_UPDATE_BYPASS (BIT(1)) +#define PVT_VALUE_UPDATE_BYPASS_M (PVT_VALUE_UPDATE_BYPASS_V << PVT_VALUE_UPDATE_BYPASS_S) +#define PVT_VALUE_UPDATE_BYPASS_V 0x00000001U +#define PVT_VALUE_UPDATE_BYPASS_S 1 + +/** PVT_BYPASS_CHAIN_REG register + * needs field desc + */ +#define PVT_BYPASS_CHAIN_REG (DR_REG_PVT_BASE + 0x1ec) +/** PVT_CLK_CHAIN_EN : R/W; bitpos: [31:0]; default: 4294967295; + * needs field desc + */ +#define PVT_CLK_CHAIN_EN 0xFFFFFFFFU +#define PVT_CLK_CHAIN_EN_M (PVT_CLK_CHAIN_EN_V << PVT_CLK_CHAIN_EN_S) +#define PVT_CLK_CHAIN_EN_V 0xFFFFFFFFU +#define PVT_CLK_CHAIN_EN_S 0 + +/** PVT_DLY_NUM_REC0_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC0_REG (DR_REG_PVT_BASE + 0x1f0) +/** PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_M (PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT0_MAX_RECORD_S 0 +/** PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_M (PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT1_MAX_RECORD_S 8 +/** PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_M (PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT2_MAX_RECORD_S 16 +/** PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_M (PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT3_MAX_RECORD_S 24 + +/** PVT_DLY_NUM_REC1_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC1_REG (DR_REG_PVT_BASE + 0x1f4) +/** PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_M (PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT0_MAX_RECORD_S 0 +/** PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_M (PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT1_MAX_RECORD_S 8 +/** PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_M (PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT2_MAX_RECORD_S 16 +/** PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_M (PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT3_MAX_RECORD_S 24 + +/** PVT_DLY_NUM_REC2_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC2_REG (DR_REG_PVT_BASE + 0x1f8) +/** PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_M (PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT0_MAX_RECORD_S 0 +/** PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_M (PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT1_MAX_RECORD_S 8 +/** PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_M (PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT2_MAX_RECORD_S 16 +/** PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_M (PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT3_MAX_RECORD_S 24 + +/** PVT_DLY_NUM_REC3_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC3_REG (DR_REG_PVT_BASE + 0x1fc) +/** PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_M (PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT0_MAX_RECORD_S 0 +/** PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_M (PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT1_MAX_RECORD_S 8 +/** PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_M (PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT2_MAX_RECORD_S 16 +/** PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_M (PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_V << PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT3_MAX_RECORD_S 24 + +/** PVT_DLY_NUM_REC4_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC4_REG (DR_REG_PVT_BASE + 0x200) +/** PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_M (PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT0_MIN_RECORD_S 0 +/** PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_M (PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT1_MIN_RECORD_S 8 +/** PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_M (PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT2_MIN_RECORD_S 16 +/** PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_M (PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_S) +#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_V 0x000000FFU +#define PVT_SITE0_DELAY_NUM_VT3_MIN_RECORD_S 24 + +/** PVT_DLY_NUM_REC5_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC5_REG (DR_REG_PVT_BASE + 0x204) +/** PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_M (PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT0_MIN_RECORD_S 0 +/** PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_M (PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT1_MIN_RECORD_S 8 +/** PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_M (PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT2_MIN_RECORD_S 16 +/** PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_M (PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_S) +#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_V 0x000000FFU +#define PVT_SITE1_DELAY_NUM_VT3_MIN_RECORD_S 24 + +/** PVT_DLY_NUM_REC6_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC6_REG (DR_REG_PVT_BASE + 0x208) +/** PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_M (PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT0_MIN_RECORD_S 0 +/** PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_M (PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT1_MIN_RECORD_S 8 +/** PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_M (PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT2_MIN_RECORD_S 16 +/** PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_M (PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_S) +#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_V 0x000000FFU +#define PVT_SITE2_DELAY_NUM_VT3_MIN_RECORD_S 24 + +/** PVT_DLY_NUM_REC7_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC7_REG (DR_REG_PVT_BASE + 0x20c) +/** PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_M (PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT0_MIN_RECORD_S 0 +/** PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_M (PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT1_MIN_RECORD_S 8 +/** PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_M (PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT2_MIN_RECORD_S 16 +/** PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ +#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_M (PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_V << PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_S) +#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_V 0x000000FFU +#define PVT_SITE3_DELAY_NUM_VT3_MIN_RECORD_S 24 + +/** PVT_DLY_NUM_REC_CLR_REG register + * needs field desc + */ +#define PVT_DLY_NUM_REC_CLR_REG (DR_REG_PVT_BASE + 0x210) +/** PVT_DELAY_NUM_REC_CLR : WT; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_REC_CLR (BIT(0)) +#define PVT_DELAY_NUM_REC_CLR_M (PVT_DELAY_NUM_REC_CLR_V << PVT_DELAY_NUM_REC_CLR_S) +#define PVT_DELAY_NUM_REC_CLR_V 0x00000001U +#define PVT_DELAY_NUM_REC_CLR_S 0 + +/** PVT_DATE_REG register + * version register + */ +#define PVT_DATE_REG (DR_REG_PVT_BASE + 0xffc) +/** PVT_DATE : R/W; bitpos: [31:0]; default: 34677040; + * version register + */ +#define PVT_DATE 0xFFFFFFFFU +#define PVT_DATE_M (PVT_DATE_V << PVT_DATE_S) +#define PVT_DATE_V 0xFFFFFFFFU +#define PVT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/pvt_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/pvt_struct.h new file mode 100644 index 0000000000..ffeeb40341 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/pvt_struct.h @@ -0,0 +1,3340 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure register */ +/** Type of pmup_bitmap_high0 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high0 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel0 + */ + uint32_t pump_bitmap_high0:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high0_reg_t; + +/** Type of pmup_bitmap_high1 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high1 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel1 + */ + uint32_t pump_bitmap_high1:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high1_reg_t; + +/** Type of pmup_bitmap_high2 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high2 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel2 + */ + uint32_t pump_bitmap_high2:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high2_reg_t; + +/** Type of pmup_bitmap_high3 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high3 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel3 + */ + uint32_t pump_bitmap_high3:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high3_reg_t; + +/** Type of pmup_bitmap_high4 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high4 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel4 + */ + uint32_t pump_bitmap_high4:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high4_reg_t; + +/** Type of pmup_bitmap_low0 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low0 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel0 + */ + uint32_t pump_bitmap_low0:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low0_reg_t; + +/** Type of pmup_bitmap_low1 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low1 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel1 + */ + uint32_t pump_bitmap_low1:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low1_reg_t; + +/** Type of pmup_bitmap_low2 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low2 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel2 + */ + uint32_t pump_bitmap_low2:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low2_reg_t; + +/** Type of pmup_bitmap_low3 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low3 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel3 + */ + uint32_t pump_bitmap_low3:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low3_reg_t; + +/** Type of pmup_bitmap_low4 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low4 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel4 + */ + uint32_t pump_bitmap_low4:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low4_reg_t; + +/** Type of pmup_drv_cfg register + * configure pump drv + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** bypass_efuse_ctrl : R/W; bitpos: [8]; default: 1; + * needs desc + */ + uint32_t bypass_efuse_ctrl:1; + /** pump_en : R/W; bitpos: [9]; default: 0; + * configure pvt charge xpd + */ + uint32_t pump_en:1; + /** clk_en : R/W; bitpos: [10]; default: 0; + * force register clken + */ + uint32_t clk_en:1; + /** pump_drv4 : R/W; bitpos: [14:11]; default: 0; + * configure cmd4 drv + */ + uint32_t pump_drv4:4; + /** pump_drv3 : R/W; bitpos: [18:15]; default: 0; + * configure cmd3 drv + */ + uint32_t pump_drv3:4; + /** pump_drv2 : R/W; bitpos: [22:19]; default: 0; + * configure cmd2 drv + */ + uint32_t pump_drv2:4; + /** pump_drv1 : R/W; bitpos: [26:23]; default: 0; + * configure cmd1 drv + */ + uint32_t pump_drv1:4; + /** pump_drv0 : R/W; bitpos: [30:27]; default: 0; + * configure cmd0 drv + */ + uint32_t pump_drv0:4; + uint32_t reserved_31:1; + }; + uint32_t val; +} pvt_pmup_drv_cfg_reg_t; + +/** Type of pmup_channel_cfg register + * configure the code of valid pump channel code + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** pump_channel_code4 : R/W; bitpos: [11:7]; default: 0; + * configure cmd4 code + */ + uint32_t pump_channel_code4:5; + /** pump_channel_code3 : R/W; bitpos: [16:12]; default: 0; + * configure cmd3 code + */ + uint32_t pump_channel_code3:5; + /** pump_channel_code2 : R/W; bitpos: [21:17]; default: 0; + * configure cmd2 code + */ + uint32_t pump_channel_code2:5; + /** pump_channel_code1 : R/W; bitpos: [26:22]; default: 0; + * configure cmd1 code + */ + uint32_t pump_channel_code1:5; + /** pump_channel_code0 : R/W; bitpos: [31:27]; default: 0; + * configure cmd0 code + */ + uint32_t pump_channel_code0:5; + }; + uint32_t val; +} pvt_pmup_channel_cfg_reg_t; + +/** Type of clk_cfg register + * configure pvt clk + */ +typedef union { + struct { + /** pump_clk_div_num : R/W; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t pump_clk_div_num:8; + /** monitor_clk_pvt_en : R/W; bitpos: [8]; default: 0; + * needs field desc + */ + uint32_t monitor_clk_pvt_en:1; + uint32_t reserved_9:22; + /** clk_sel : R/W; bitpos: [31]; default: 0; + * select pvt clk + */ + uint32_t clk_sel:1; + }; + uint32_t val; +} pvt_clk_cfg_reg_t; + +/** Type of dbias_channel_sel0 register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** dbias_channel3_sel : R/W; bitpos: [10:4]; default: 64; + * needs field desc + */ + uint32_t dbias_channel3_sel:7; + /** dbias_channel2_sel : R/W; bitpos: [17:11]; default: 64; + * needs field desc + */ + uint32_t dbias_channel2_sel:7; + /** dbias_channel1_sel : R/W; bitpos: [24:18]; default: 64; + * needs field desc + */ + uint32_t dbias_channel1_sel:7; + /** dbias_channel0_sel : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ + uint32_t dbias_channel0_sel:7; + }; + uint32_t val; +} pvt_dbias_channel_sel0_reg_t; + +/** Type of dbias_channel_sel1 register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** dbias_channel4_sel : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ + uint32_t dbias_channel4_sel:7; + }; + uint32_t val; +} pvt_dbias_channel_sel1_reg_t; + +/** Type of dbias_channel0_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel0_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel0_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel0_sel_reg_t; + +/** Type of dbias_channel1_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel1_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel1_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel1_sel_reg_t; + +/** Type of dbias_channel2_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel2_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel2_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel2_sel_reg_t; + +/** Type of dbias_channel3_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel3_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel3_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel3_sel_reg_t; + +/** Type of dbias_channel4_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel4_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel4_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel4_sel_reg_t; + +/** Type of dbias_cmd0 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd0 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd0:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd0_reg_t; + +/** Type of dbias_cmd1 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd1 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd1:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd1_reg_t; + +/** Type of dbias_cmd2 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd2 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd2:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd2_reg_t; + +/** Type of dbias_cmd3 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd3 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd3:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd3_reg_t; + +/** Type of dbias_cmd4 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd4 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd4:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd4_reg_t; + +/** Type of dbias_timer register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** timer_target : R/W; bitpos: [30:15]; default: 65535; + * needs field desc + */ + uint32_t timer_target:16; + /** timer_en : R/W; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timer_en:1; + }; + uint32_t val; +} pvt_dbias_timer_reg_t; + +/** Type of comb_pd_site0_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit0:1; + /** delay_limit_vt0_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit0:8; + /** timing_err_vt0_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit1:1; + /** delay_limit_vt0_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit1:8; + /** timing_err_vt0_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit2:1; + /** delay_limit_vt0_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit2:8; + /** timing_err_vt0_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit3:1; + /** delay_limit_vt0_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit3:8; + /** timing_err_vt0_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit0:1; + /** delay_limit_vt1_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit0:8; + /** timing_err_vt1_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit1:1; + /** delay_limit_vt1_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit1:8; + /** timing_err_vt1_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit2:1; + /** delay_limit_vt1_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit2:8; + /** timing_err_vt1_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit3:1; + /** delay_limit_vt1_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit3:8; + /** timing_err_vt1_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit0:1; + /** delay_limit_vt2_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit0:8; + /** timing_err_vt2_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit1:1; + /** delay_limit_vt2_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit1:8; + /** timing_err_vt2_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit2:1; + /** delay_limit_vt2_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit2:8; + /** timing_err_vt2_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit3:1; + /** delay_limit_vt2_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit3:8; + /** timing_err_vt2_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit0:1; + /** delay_limit_vt0_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit0:8; + /** timing_err_vt0_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit1:1; + /** delay_limit_vt0_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit1:8; + /** timing_err_vt0_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit2:1; + /** delay_limit_vt0_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit2:8; + /** timing_err_vt0_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit3:1; + /** delay_limit_vt0_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit3:8; + /** timing_err_vt0_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit0:1; + /** delay_limit_vt1_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit0:8; + /** timing_err_vt1_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit1:1; + /** delay_limit_vt1_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit1:8; + /** timing_err_vt1_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit2:1; + /** delay_limit_vt1_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit2:8; + /** timing_err_vt1_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit3:1; + /** delay_limit_vt1_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit3:8; + /** timing_err_vt1_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit0:1; + /** delay_limit_vt2_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit0:8; + /** timing_err_vt2_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit1:1; + /** delay_limit_vt2_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit1:8; + /** timing_err_vt2_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit2:1; + /** delay_limit_vt2_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit2:8; + /** timing_err_vt2_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit3:1; + /** delay_limit_vt2_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit3:8; + /** timing_err_vt2_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit0:1; + /** delay_limit_vt0_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit0:8; + /** timing_err_vt0_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit1:1; + /** delay_limit_vt0_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit1:8; + /** timing_err_vt0_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit2:1; + /** delay_limit_vt0_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit2:8; + /** timing_err_vt0_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit3:1; + /** delay_limit_vt0_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit3:8; + /** timing_err_vt0_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit0:1; + /** delay_limit_vt1_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit0:8; + /** timing_err_vt1_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit1:1; + /** delay_limit_vt1_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit1:8; + /** timing_err_vt1_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit2:1; + /** delay_limit_vt1_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit2:8; + /** timing_err_vt1_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit3:1; + /** delay_limit_vt1_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit3:8; + /** timing_err_vt1_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit0:1; + /** delay_limit_vt2_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit0:8; + /** timing_err_vt2_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit1:1; + /** delay_limit_vt2_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit1:8; + /** timing_err_vt2_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit2:1; + /** delay_limit_vt2_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit2:8; + /** timing_err_vt2_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit3:1; + /** delay_limit_vt2_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit3:8; + /** timing_err_vt2_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit0:1; + /** delay_limit_vt0_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit0:8; + /** timing_err_vt0_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit1:1; + /** delay_limit_vt0_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit1:8; + /** timing_err_vt0_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit2:1; + /** delay_limit_vt0_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit2:8; + /** timing_err_vt0_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit3:1; + /** delay_limit_vt0_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit3:8; + /** timing_err_vt0_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit0:1; + /** delay_limit_vt1_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit0:8; + /** timing_err_vt1_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit1:1; + /** delay_limit_vt1_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit1:8; + /** timing_err_vt1_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit2:1; + /** delay_limit_vt1_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit2:8; + /** timing_err_vt1_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit3:1; + /** delay_limit_vt1_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit3:8; + /** timing_err_vt1_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit0:1; + /** delay_limit_vt2_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit0:8; + /** timing_err_vt2_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit1:1; + /** delay_limit_vt2_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit1:8; + /** timing_err_vt2_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit2:1; + /** delay_limit_vt2_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit2:8; + /** timing_err_vt2_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit3:1; + /** delay_limit_vt2_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit3:8; + /** timing_err_vt2_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit0:1; + /** timing_err_cnt_o_vt0_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit1:1; + /** timing_err_cnt_o_vt0_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit2:1; + /** timing_err_cnt_o_vt0_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit3:1; + /** timing_err_cnt_o_vt0_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit0:1; + /** timing_err_cnt_o_vt1_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit1:1; + /** timing_err_cnt_o_vt1_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit2:1; + /** timing_err_cnt_o_vt1_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit3:1; + /** timing_err_cnt_o_vt1_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit0:1; + /** timing_err_cnt_o_vt2_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit1:1; + /** timing_err_cnt_o_vt2_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit2:1; + /** timing_err_cnt_o_vt2_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit3:1; + /** timing_err_cnt_o_vt2_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit0:1; + /** timing_err_cnt_o_vt0_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit1:1; + /** timing_err_cnt_o_vt0_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit2:1; + /** timing_err_cnt_o_vt0_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit3:1; + /** timing_err_cnt_o_vt0_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit0:1; + /** timing_err_cnt_o_vt1_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit1:1; + /** timing_err_cnt_o_vt1_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit2:1; + /** timing_err_cnt_o_vt1_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit3:1; + /** timing_err_cnt_o_vt1_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit0:1; + /** timing_err_cnt_o_vt2_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit1:1; + /** timing_err_cnt_o_vt2_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit2:1; + /** timing_err_cnt_o_vt2_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit3:1; + /** timing_err_cnt_o_vt2_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit0:1; + /** timing_err_cnt_o_vt0_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit1:1; + /** timing_err_cnt_o_vt0_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit2:1; + /** timing_err_cnt_o_vt0_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit3:1; + /** timing_err_cnt_o_vt0_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit0:1; + /** timing_err_cnt_o_vt1_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit1:1; + /** timing_err_cnt_o_vt1_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit2:1; + /** timing_err_cnt_o_vt1_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit3:1; + /** timing_err_cnt_o_vt1_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit0:1; + /** timing_err_cnt_o_vt2_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit1:1; + /** timing_err_cnt_o_vt2_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit2:1; + /** timing_err_cnt_o_vt2_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit3:1; + /** timing_err_cnt_o_vt2_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit0:1; + /** timing_err_cnt_o_vt0_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit1:1; + /** timing_err_cnt_o_vt0_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit2:1; + /** timing_err_cnt_o_vt0_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit3:1; + /** timing_err_cnt_o_vt0_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit0:1; + /** timing_err_cnt_o_vt1_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit1:1; + /** timing_err_cnt_o_vt1_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit2:1; + /** timing_err_cnt_o_vt1_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit3:1; + /** timing_err_cnt_o_vt1_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit0:1; + /** timing_err_cnt_o_vt2_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit1:1; + /** timing_err_cnt_o_vt2_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit2:1; + /** timing_err_cnt_o_vt2_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit3:1; + /** timing_err_cnt_o_vt2_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt2_conf2_reg_t; + +/** Type of value_update register + * needs field desc + */ +typedef union { + struct { + /** value_update : WT; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t value_update:1; + /** value_update_bypass : R/W; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t value_update_bypass:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pvt_value_update_reg_t; + +/** Type of bypass_chain register + * needs field desc + */ +typedef union { + struct { + /** clk_chain_en : R/W; bitpos: [31:0]; default: 4294967295; + * needs field desc + */ + uint32_t clk_chain_en:32; + }; + uint32_t val; +} pvt_bypass_chain_reg_t; + +/** Type of dly_num_rec0 register + * needs field desc + */ +typedef union { + struct { + /** site0_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt0_max_record:8; + /** site0_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt1_max_record:8; + /** site0_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt2_max_record:8; + /** site0_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt3_max_record:8; + }; + uint32_t val; +} pvt_dly_num_rec0_reg_t; + +/** Type of dly_num_rec1 register + * needs field desc + */ +typedef union { + struct { + /** site1_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt0_max_record:8; + /** site1_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt1_max_record:8; + /** site1_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt2_max_record:8; + /** site1_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt3_max_record:8; + }; + uint32_t val; +} pvt_dly_num_rec1_reg_t; + +/** Type of dly_num_rec2 register + * needs field desc + */ +typedef union { + struct { + /** site2_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt0_max_record:8; + /** site2_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt1_max_record:8; + /** site2_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt2_max_record:8; + /** site2_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt3_max_record:8; + }; + uint32_t val; +} pvt_dly_num_rec2_reg_t; + +/** Type of dly_num_rec3 register + * needs field desc + */ +typedef union { + struct { + /** site3_delay_num_vt0_max_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt0_max_record:8; + /** site3_delay_num_vt1_max_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt1_max_record:8; + /** site3_delay_num_vt2_max_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt2_max_record:8; + /** site3_delay_num_vt3_max_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt3_max_record:8; + }; + uint32_t val; +} pvt_dly_num_rec3_reg_t; + +/** Type of dly_num_rec4 register + * needs field desc + */ +typedef union { + struct { + /** site0_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt0_min_record:8; + /** site0_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt1_min_record:8; + /** site0_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt2_min_record:8; + /** site0_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site0_delay_num_vt3_min_record:8; + }; + uint32_t val; +} pvt_dly_num_rec4_reg_t; + +/** Type of dly_num_rec5 register + * needs field desc + */ +typedef union { + struct { + /** site1_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt0_min_record:8; + /** site1_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt1_min_record:8; + /** site1_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt2_min_record:8; + /** site1_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site1_delay_num_vt3_min_record:8; + }; + uint32_t val; +} pvt_dly_num_rec5_reg_t; + +/** Type of dly_num_rec6 register + * needs field desc + */ +typedef union { + struct { + /** site2_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt0_min_record:8; + /** site2_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt1_min_record:8; + /** site2_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt2_min_record:8; + /** site2_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site2_delay_num_vt3_min_record:8; + }; + uint32_t val; +} pvt_dly_num_rec6_reg_t; + +/** Type of dly_num_rec7 register + * needs field desc + */ +typedef union { + struct { + /** site3_delay_num_vt0_min_record : RO; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt0_min_record:8; + /** site3_delay_num_vt1_min_record : RO; bitpos: [15:8]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt1_min_record:8; + /** site3_delay_num_vt2_min_record : RO; bitpos: [23:16]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt2_min_record:8; + /** site3_delay_num_vt3_min_record : RO; bitpos: [31:24]; default: 0; + * needs field desc + */ + uint32_t site3_delay_num_vt3_min_record:8; + }; + uint32_t val; +} pvt_dly_num_rec7_reg_t; + +/** Type of dly_num_rec_clr register + * needs field desc + */ +typedef union { + struct { + /** delay_num_rec_clr : WT; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t delay_num_rec_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pvt_dly_num_rec_clr_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34677040; + * version register + */ + uint32_t date:32; + }; + uint32_t val; +} pvt_date_reg_t; + + +typedef struct { + volatile pvt_pmup_bitmap_high0_reg_t pmup_bitmap_high0; + volatile pvt_pmup_bitmap_high1_reg_t pmup_bitmap_high1; + volatile pvt_pmup_bitmap_high2_reg_t pmup_bitmap_high2; + volatile pvt_pmup_bitmap_high3_reg_t pmup_bitmap_high3; + volatile pvt_pmup_bitmap_high4_reg_t pmup_bitmap_high4; + volatile pvt_pmup_bitmap_low0_reg_t pmup_bitmap_low0; + volatile pvt_pmup_bitmap_low1_reg_t pmup_bitmap_low1; + volatile pvt_pmup_bitmap_low2_reg_t pmup_bitmap_low2; + volatile pvt_pmup_bitmap_low3_reg_t pmup_bitmap_low3; + volatile pvt_pmup_bitmap_low4_reg_t pmup_bitmap_low4; + volatile pvt_pmup_drv_cfg_reg_t pmup_drv_cfg; + volatile pvt_pmup_channel_cfg_reg_t pmup_channel_cfg; + volatile pvt_clk_cfg_reg_t clk_cfg; + volatile pvt_dbias_channel_sel0_reg_t dbias_channel_sel0; + volatile pvt_dbias_channel_sel1_reg_t dbias_channel_sel1; + volatile pvt_dbias_channel0_sel_reg_t dbias_channel0_sel; + volatile pvt_dbias_channel1_sel_reg_t dbias_channel1_sel; + volatile pvt_dbias_channel2_sel_reg_t dbias_channel2_sel; + volatile pvt_dbias_channel3_sel_reg_t dbias_channel3_sel; + volatile pvt_dbias_channel4_sel_reg_t dbias_channel4_sel; + volatile pvt_dbias_cmd0_reg_t dbias_cmd0; + volatile pvt_dbias_cmd1_reg_t dbias_cmd1; + volatile pvt_dbias_cmd2_reg_t dbias_cmd2; + volatile pvt_dbias_cmd3_reg_t dbias_cmd3; + volatile pvt_dbias_cmd4_reg_t dbias_cmd4; + volatile pvt_dbias_timer_reg_t dbias_timer; + volatile pvt_comb_pd_site0_unit0_vt0_conf1_reg_t comb_pd_site0_unit0_vt0_conf1; + volatile pvt_comb_pd_site0_unit1_vt0_conf1_reg_t comb_pd_site0_unit1_vt0_conf1; + volatile pvt_comb_pd_site0_unit2_vt0_conf1_reg_t comb_pd_site0_unit2_vt0_conf1; + volatile pvt_comb_pd_site0_unit3_vt0_conf1_reg_t comb_pd_site0_unit3_vt0_conf1; + volatile pvt_comb_pd_site0_unit0_vt1_conf1_reg_t comb_pd_site0_unit0_vt1_conf1; + volatile pvt_comb_pd_site0_unit1_vt1_conf1_reg_t comb_pd_site0_unit1_vt1_conf1; + volatile pvt_comb_pd_site0_unit2_vt1_conf1_reg_t comb_pd_site0_unit2_vt1_conf1; + volatile pvt_comb_pd_site0_unit3_vt1_conf1_reg_t comb_pd_site0_unit3_vt1_conf1; + volatile pvt_comb_pd_site0_unit0_vt2_conf1_reg_t comb_pd_site0_unit0_vt2_conf1; + volatile pvt_comb_pd_site0_unit1_vt2_conf1_reg_t comb_pd_site0_unit1_vt2_conf1; + volatile pvt_comb_pd_site0_unit2_vt2_conf1_reg_t comb_pd_site0_unit2_vt2_conf1; + volatile pvt_comb_pd_site0_unit3_vt2_conf1_reg_t comb_pd_site0_unit3_vt2_conf1; + volatile pvt_comb_pd_site1_unit0_vt0_conf1_reg_t comb_pd_site1_unit0_vt0_conf1; + volatile pvt_comb_pd_site1_unit1_vt0_conf1_reg_t comb_pd_site1_unit1_vt0_conf1; + volatile pvt_comb_pd_site1_unit2_vt0_conf1_reg_t comb_pd_site1_unit2_vt0_conf1; + volatile pvt_comb_pd_site1_unit3_vt0_conf1_reg_t comb_pd_site1_unit3_vt0_conf1; + volatile pvt_comb_pd_site1_unit0_vt1_conf1_reg_t comb_pd_site1_unit0_vt1_conf1; + volatile pvt_comb_pd_site1_unit1_vt1_conf1_reg_t comb_pd_site1_unit1_vt1_conf1; + volatile pvt_comb_pd_site1_unit2_vt1_conf1_reg_t comb_pd_site1_unit2_vt1_conf1; + volatile pvt_comb_pd_site1_unit3_vt1_conf1_reg_t comb_pd_site1_unit3_vt1_conf1; + volatile pvt_comb_pd_site1_unit0_vt2_conf1_reg_t comb_pd_site1_unit0_vt2_conf1; + volatile pvt_comb_pd_site1_unit1_vt2_conf1_reg_t comb_pd_site1_unit1_vt2_conf1; + volatile pvt_comb_pd_site1_unit2_vt2_conf1_reg_t comb_pd_site1_unit2_vt2_conf1; + volatile pvt_comb_pd_site1_unit3_vt2_conf1_reg_t comb_pd_site1_unit3_vt2_conf1; + volatile pvt_comb_pd_site2_unit0_vt0_conf1_reg_t comb_pd_site2_unit0_vt0_conf1; + volatile pvt_comb_pd_site2_unit1_vt0_conf1_reg_t comb_pd_site2_unit1_vt0_conf1; + volatile pvt_comb_pd_site2_unit2_vt0_conf1_reg_t comb_pd_site2_unit2_vt0_conf1; + volatile pvt_comb_pd_site2_unit3_vt0_conf1_reg_t comb_pd_site2_unit3_vt0_conf1; + volatile pvt_comb_pd_site2_unit0_vt1_conf1_reg_t comb_pd_site2_unit0_vt1_conf1; + volatile pvt_comb_pd_site2_unit1_vt1_conf1_reg_t comb_pd_site2_unit1_vt1_conf1; + volatile pvt_comb_pd_site2_unit2_vt1_conf1_reg_t comb_pd_site2_unit2_vt1_conf1; + volatile pvt_comb_pd_site2_unit3_vt1_conf1_reg_t comb_pd_site2_unit3_vt1_conf1; + volatile pvt_comb_pd_site2_unit0_vt2_conf1_reg_t comb_pd_site2_unit0_vt2_conf1; + volatile pvt_comb_pd_site2_unit1_vt2_conf1_reg_t comb_pd_site2_unit1_vt2_conf1; + volatile pvt_comb_pd_site2_unit2_vt2_conf1_reg_t comb_pd_site2_unit2_vt2_conf1; + volatile pvt_comb_pd_site2_unit3_vt2_conf1_reg_t comb_pd_site2_unit3_vt2_conf1; + volatile pvt_comb_pd_site3_unit0_vt0_conf1_reg_t comb_pd_site3_unit0_vt0_conf1; + volatile pvt_comb_pd_site3_unit1_vt0_conf1_reg_t comb_pd_site3_unit1_vt0_conf1; + volatile pvt_comb_pd_site3_unit2_vt0_conf1_reg_t comb_pd_site3_unit2_vt0_conf1; + volatile pvt_comb_pd_site3_unit3_vt0_conf1_reg_t comb_pd_site3_unit3_vt0_conf1; + volatile pvt_comb_pd_site3_unit0_vt1_conf1_reg_t comb_pd_site3_unit0_vt1_conf1; + volatile pvt_comb_pd_site3_unit1_vt1_conf1_reg_t comb_pd_site3_unit1_vt1_conf1; + volatile pvt_comb_pd_site3_unit2_vt1_conf1_reg_t comb_pd_site3_unit2_vt1_conf1; + volatile pvt_comb_pd_site3_unit3_vt1_conf1_reg_t comb_pd_site3_unit3_vt1_conf1; + volatile pvt_comb_pd_site3_unit0_vt2_conf1_reg_t comb_pd_site3_unit0_vt2_conf1; + volatile pvt_comb_pd_site3_unit1_vt2_conf1_reg_t comb_pd_site3_unit1_vt2_conf1; + volatile pvt_comb_pd_site3_unit2_vt2_conf1_reg_t comb_pd_site3_unit2_vt2_conf1; + volatile pvt_comb_pd_site3_unit3_vt2_conf1_reg_t comb_pd_site3_unit3_vt2_conf1; + volatile pvt_comb_pd_site0_unit0_vt0_conf2_reg_t comb_pd_site0_unit0_vt0_conf2; + volatile pvt_comb_pd_site0_unit1_vt0_conf2_reg_t comb_pd_site0_unit1_vt0_conf2; + volatile pvt_comb_pd_site0_unit2_vt0_conf2_reg_t comb_pd_site0_unit2_vt0_conf2; + volatile pvt_comb_pd_site0_unit3_vt0_conf2_reg_t comb_pd_site0_unit3_vt0_conf2; + volatile pvt_comb_pd_site0_unit0_vt1_conf2_reg_t comb_pd_site0_unit0_vt1_conf2; + volatile pvt_comb_pd_site0_unit1_vt1_conf2_reg_t comb_pd_site0_unit1_vt1_conf2; + volatile pvt_comb_pd_site0_unit2_vt1_conf2_reg_t comb_pd_site0_unit2_vt1_conf2; + volatile pvt_comb_pd_site0_unit3_vt1_conf2_reg_t comb_pd_site0_unit3_vt1_conf2; + volatile pvt_comb_pd_site0_unit0_vt2_conf2_reg_t comb_pd_site0_unit0_vt2_conf2; + volatile pvt_comb_pd_site0_unit1_vt2_conf2_reg_t comb_pd_site0_unit1_vt2_conf2; + volatile pvt_comb_pd_site0_unit2_vt2_conf2_reg_t comb_pd_site0_unit2_vt2_conf2; + volatile pvt_comb_pd_site0_unit3_vt2_conf2_reg_t comb_pd_site0_unit3_vt2_conf2; + volatile pvt_comb_pd_site1_unit0_vt0_conf2_reg_t comb_pd_site1_unit0_vt0_conf2; + volatile pvt_comb_pd_site1_unit1_vt0_conf2_reg_t comb_pd_site1_unit1_vt0_conf2; + volatile pvt_comb_pd_site1_unit2_vt0_conf2_reg_t comb_pd_site1_unit2_vt0_conf2; + volatile pvt_comb_pd_site1_unit3_vt0_conf2_reg_t comb_pd_site1_unit3_vt0_conf2; + volatile pvt_comb_pd_site1_unit0_vt1_conf2_reg_t comb_pd_site1_unit0_vt1_conf2; + volatile pvt_comb_pd_site1_unit1_vt1_conf2_reg_t comb_pd_site1_unit1_vt1_conf2; + volatile pvt_comb_pd_site1_unit2_vt1_conf2_reg_t comb_pd_site1_unit2_vt1_conf2; + volatile pvt_comb_pd_site1_unit3_vt1_conf2_reg_t comb_pd_site1_unit3_vt1_conf2; + volatile pvt_comb_pd_site1_unit0_vt2_conf2_reg_t comb_pd_site1_unit0_vt2_conf2; + volatile pvt_comb_pd_site1_unit1_vt2_conf2_reg_t comb_pd_site1_unit1_vt2_conf2; + volatile pvt_comb_pd_site1_unit2_vt2_conf2_reg_t comb_pd_site1_unit2_vt2_conf2; + volatile pvt_comb_pd_site1_unit3_vt2_conf2_reg_t comb_pd_site1_unit3_vt2_conf2; + volatile pvt_comb_pd_site2_unit0_vt0_conf2_reg_t comb_pd_site2_unit0_vt0_conf2; + volatile pvt_comb_pd_site2_unit1_vt0_conf2_reg_t comb_pd_site2_unit1_vt0_conf2; + volatile pvt_comb_pd_site2_unit2_vt0_conf2_reg_t comb_pd_site2_unit2_vt0_conf2; + volatile pvt_comb_pd_site2_unit3_vt0_conf2_reg_t comb_pd_site2_unit3_vt0_conf2; + volatile pvt_comb_pd_site2_unit0_vt1_conf2_reg_t comb_pd_site2_unit0_vt1_conf2; + volatile pvt_comb_pd_site2_unit1_vt1_conf2_reg_t comb_pd_site2_unit1_vt1_conf2; + volatile pvt_comb_pd_site2_unit2_vt1_conf2_reg_t comb_pd_site2_unit2_vt1_conf2; + volatile pvt_comb_pd_site2_unit3_vt1_conf2_reg_t comb_pd_site2_unit3_vt1_conf2; + volatile pvt_comb_pd_site2_unit0_vt2_conf2_reg_t comb_pd_site2_unit0_vt2_conf2; + volatile pvt_comb_pd_site2_unit1_vt2_conf2_reg_t comb_pd_site2_unit1_vt2_conf2; + volatile pvt_comb_pd_site2_unit2_vt2_conf2_reg_t comb_pd_site2_unit2_vt2_conf2; + volatile pvt_comb_pd_site2_unit3_vt2_conf2_reg_t comb_pd_site2_unit3_vt2_conf2; + volatile pvt_comb_pd_site3_unit0_vt0_conf2_reg_t comb_pd_site3_unit0_vt0_conf2; + volatile pvt_comb_pd_site3_unit1_vt0_conf2_reg_t comb_pd_site3_unit1_vt0_conf2; + volatile pvt_comb_pd_site3_unit2_vt0_conf2_reg_t comb_pd_site3_unit2_vt0_conf2; + volatile pvt_comb_pd_site3_unit3_vt0_conf2_reg_t comb_pd_site3_unit3_vt0_conf2; + volatile pvt_comb_pd_site3_unit0_vt1_conf2_reg_t comb_pd_site3_unit0_vt1_conf2; + volatile pvt_comb_pd_site3_unit1_vt1_conf2_reg_t comb_pd_site3_unit1_vt1_conf2; + volatile pvt_comb_pd_site3_unit2_vt1_conf2_reg_t comb_pd_site3_unit2_vt1_conf2; + volatile pvt_comb_pd_site3_unit3_vt1_conf2_reg_t comb_pd_site3_unit3_vt1_conf2; + volatile pvt_comb_pd_site3_unit0_vt2_conf2_reg_t comb_pd_site3_unit0_vt2_conf2; + volatile pvt_comb_pd_site3_unit1_vt2_conf2_reg_t comb_pd_site3_unit1_vt2_conf2; + volatile pvt_comb_pd_site3_unit2_vt2_conf2_reg_t comb_pd_site3_unit2_vt2_conf2; + volatile pvt_comb_pd_site3_unit3_vt2_conf2_reg_t comb_pd_site3_unit3_vt2_conf2; + volatile pvt_value_update_reg_t value_update; + volatile pvt_bypass_chain_reg_t bypass_chain; + volatile pvt_dly_num_rec0_reg_t dly_num_rec0; + volatile pvt_dly_num_rec1_reg_t dly_num_rec1; + volatile pvt_dly_num_rec2_reg_t dly_num_rec2; + volatile pvt_dly_num_rec3_reg_t dly_num_rec3; + volatile pvt_dly_num_rec4_reg_t dly_num_rec4; + volatile pvt_dly_num_rec5_reg_t dly_num_rec5; + volatile pvt_dly_num_rec6_reg_t dly_num_rec6; + volatile pvt_dly_num_rec7_reg_t dly_num_rec7; + volatile pvt_dly_num_rec_clr_reg_t dly_num_rec_clr; + uint32_t reserved_214[890]; + volatile pvt_date_reg_t date; +} pvt_dev_t; + +extern pvt_dev_t PVT; + +#ifndef __cplusplus +_Static_assert(sizeof(pvt_dev_t) == 0x1000, "Invalid size of pvt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver2/soc/reg_base.h new file mode 100644 index 0000000000..12e537ee3a --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/reg_base.h @@ -0,0 +1,205 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Basic address */ +#define DR_REG_HPCPUTCP_BASE 0x3FF00000 +#define DR_REG_HPPERIPH0_BASE 0x50000000 +#define DR_REG_HPPERIPH1_BASE 0x500C0000 +#define DR_REG_LPAON_BASE 0x50110000 +#define DR_REG_LPPERIPH_BASE 0x50120000 + +/* This is raw module base from digital team + * some of them may not be used in rom + * just keep them for a reference + */ +/* + * @module: CPU-PERIPHERAL + * + * @base: 0x3FF00000 + * + * @size: 128KB + */ +#define DR_REG_TRACE0_BASE (DR_REG_HPCPUTCP_BASE + 0x4000) +#define DR_REG_TRACE1_BASE (DR_REG_HPCPUTCP_BASE + 0x5000) +#define DR_REG_CPU_BUS_MON_BASE (DR_REG_HPCPUTCP_BASE + 0x6000) +#define DR_REG_L2MEM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xE000) +#define DR_REG_TCM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xF000) +#define DR_REG_CACHE_BASE (DR_REG_HPCPUTCP_BASE + 0x10000) + +/* + * @module: PERIPHERAL0 + * + * @base: 0x50000000 + * + * @size: 768KB + */ +#define DR_REG_USB2_BASE (DR_REG_HPPERIPH0_BASE + 0x0) +#define DR_REG_USB11_BASE (DR_REG_HPPERIPH0_BASE + 0x40000) +#define DR_REG_USB_WRAP_BASE (DR_REG_HPPERIPH0_BASE + 0x80000) +#define DR_REG_GDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x81000) +#define DR_REG_REGDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x82000) +#define DR_REG_SDMMC_BASE (DR_REG_HPPERIPH0_BASE + 0x83000) +#define DR_REG_H264_CORE_BASE (DR_REG_HPPERIPH0_BASE + 0x84000) +#define DR_REG_AHB_DMA_BASE (DR_REG_HPPERIPH0_BASE + 0x85000) +#define DR_REG_JPEG_BASE (DR_REG_HPPERIPH0_BASE + 0x86000) +#define DR_REG_PPA_BASE (DR_REG_HPPERIPH0_BASE + 0x87000) +#define DR_REG_DMA2D_BASE (DR_REG_HPPERIPH0_BASE + 0x88000) +#define DR_REG_KEYMNG_BASE (DR_REG_HPPERIPH0_BASE + 0x89000) +#define DR_REG_AXI_DMA_BASE (DR_REG_HPPERIPH0_BASE + 0x8A000) +#define DR_REG_FLASH_SPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8C000) +#define DR_REG_FLASH_SPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8D000) +#define DR_REG_PSRAM_MSPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8E000) +#define DR_REG_PSRAM_MSPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8F000) +#define DR_REG_CRYPTO_BASE (DR_REG_HPPERIPH0_BASE + 0x90000) +#define DR_REG_EMAC_BASE (DR_REG_HPPERIPH0_BASE + 0x98000) +#define DR_REG_USBPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9C000) +#define DR_REG_DDRPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9D000) +#define DR_REG_PVT_BASE (DR_REG_HPPERIPH0_BASE + 0x9E000) +#define DR_REG_CSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0x9F000) +#define DR_REG_CSI_BRG_BASE (DR_REG_HPPERIPH0_BASE + 0x9F800) +#define DR_REG_DSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0xA0000) +#define DR_REG_DSI_BRG_BASE (DR_REG_HPPERIPH0_BASE + 0xA0800) +#define DR_REG_ISP_BASE (DR_REG_HPPERIPH0_BASE + 0xA1000) +#define DR_REG_RMT_BASE (DR_REG_HPPERIPH0_BASE + 0xA2000) +#define DR_REG_BITSCRAMBLER_BASE (DR_REG_HPPERIPH0_BASE + 0xA3000) +#define DR_REG_AXI_ICM_BASE (DR_REG_HPPERIPH0_BASE + 0xA4000) +#define DR_REG_AXI_ICM_QOS_BASE (DR_REG_AXI_ICM_BASE + 0x400) +#define DR_REG_HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5000) +#define DR_REG_LP2HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5800) +#define DR_REG_DMA_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA6000) +#define DR_REG_H264_DMA_2D_BASE (DR_REG_HPPERIPH0_BASE + 0xA7000) +/* + * @module: PERIPHERAL1 + * + * @base: 0x500C0000 + * + * @size: 256KB + */ +#define DR_REG_MCPWM0_BASE (DR_REG_HPPERIPH1_BASE + 0x0) +#define DR_REG_MCPWM1_BASE (DR_REG_HPPERIPH1_BASE + 0x1000) +#define DR_REG_TIMG0_BASE (DR_REG_HPPERIPH1_BASE + 0x2000) +#define DR_REG_TIMG1_BASE (DR_REG_HPPERIPH1_BASE + 0x3000) +#define DR_REG_I2C0_BASE (DR_REG_HPPERIPH1_BASE + 0x4000) +#define DR_REG_I2C1_BASE (DR_REG_HPPERIPH1_BASE + 0x5000) +#define DR_REG_I2S0_BASE (DR_REG_HPPERIPH1_BASE + 0x6000) +#define DR_REG_I2S1_BASE (DR_REG_HPPERIPH1_BASE + 0x7000) +#define DR_REG_I2S2_BASE (DR_REG_HPPERIPH1_BASE + 0x8000) +#define DR_REG_PCNT_BASE (DR_REG_HPPERIPH1_BASE + 0x9000) +#define DR_REG_UART0_BASE (DR_REG_HPPERIPH1_BASE + 0xA000) +#define DR_REG_UART1_BASE (DR_REG_HPPERIPH1_BASE + 0xB000) +#define DR_REG_UART2_BASE (DR_REG_HPPERIPH1_BASE + 0xC000) +#define DR_REG_UART3_BASE (DR_REG_HPPERIPH1_BASE + 0xD000) +#define DR_REG_UART4_BASE (DR_REG_HPPERIPH1_BASE + 0xE000) +#define DR_REG_PARIO_BASE (DR_REG_HPPERIPH1_BASE + 0xF000) +#define DR_REG_SPI2_BASE (DR_REG_HPPERIPH1_BASE + 0x10000) +#define DR_REG_SPI3_BASE (DR_REG_HPPERIPH1_BASE + 0x11000) +#define DR_REG_USB2JTAG_BASE (DR_REG_HPPERIPH1_BASE + 0x12000) +#define DR_REG_LEDC_BASE (DR_REG_HPPERIPH1_BASE + 0x13000) +#define DR_REG_ETM_BASE (DR_REG_HPPERIPH1_BASE + 0x15000) +#define DR_REG_INTR_BASE (DR_REG_HPPERIPH1_BASE + 0x16000) +#define DR_REG_TWAI0_BASE (DR_REG_HPPERIPH1_BASE + 0x17000) +#define DR_REG_TWAI1_BASE (DR_REG_HPPERIPH1_BASE + 0x18000) +#define DR_REG_TWAI2_BASE (DR_REG_HPPERIPH1_BASE + 0x19000) +#define DR_REG_I3C_MST_BASE (DR_REG_HPPERIPH1_BASE + 0x1A000) +#define DR_REG_I3C_MST_MEM_BASE (DR_REG_I3C_MST_BASE) +#define DR_REG_I3C_SLV_BASE (DR_REG_HPPERIPH1_BASE + 0x1B000) +#define DR_REG_LCDCAM_BASE (DR_REG_HPPERIPH1_BASE + 0x1C000) +#define DR_REG_ADC_BASE (DR_REG_HPPERIPH1_BASE + 0x1E000) +#define DR_REG_UHCI_BASE (DR_REG_HPPERIPH1_BASE + 0x1F000) +#define DR_REG_GPIO_BASE (DR_REG_HPPERIPH1_BASE + 0x20000) +#define DR_REG_GPIO_EXT_BASE (DR_REG_HPPERIPH1_BASE + 0x20F00) +#define DR_REG_IO_MUX_BASE (DR_REG_HPPERIPH1_BASE + 0x21000) +#define DR_REG_IOMUX_MSPI_PIN_BASE (DR_REG_HPPERIPH1_BASE + 0x21200) +#define DR_REG_SYSTIMER_BASE (DR_REG_HPPERIPH1_BASE + 0x22000) +#define DR_REG_MEM_MON_BASE (DR_REG_HPPERIPH1_BASE + 0x23000) +#define DR_REG_AUDIO_ADDC_BASE (DR_REG_HPPERIPH1_BASE + 0x24000) +#define DR_REG_HP_SYS_BASE (DR_REG_HPPERIPH1_BASE + 0x25000) +#define DR_REG_HP_SYS_CLKRST_BASE (DR_REG_HPPERIPH1_BASE + 0x26000) + +/* + * @module: LP AON + * + * @base: 0x50110000 + * + * @size: 64KB + */ +#define DR_REG_LP_SYS_BASE (DR_REG_LPAON_BASE + 0x0) +#define DR_REG_LP_CLKRST_BASE (DR_REG_LPAON_BASE + 0x1000) +#define DR_REG_LP_TIMER_BASE (DR_REG_LPAON_BASE + 0x2000) +#define DR_REG_LP_ANALOG_PERI_BASE (DR_REG_LPAON_BASE + 0x3000) +#define DR_REG_LP_HUK_BASE (DR_REG_LPAON_BASE + 0x4000) +#define DR_REG_HUK_BASE (DR_REG_LP_HUK_BASE) +#define DR_REG_PMU_BASE (DR_REG_LPAON_BASE + 0x5000) +#define DR_REG_LP_WDT_BASE (DR_REG_LPAON_BASE + 0x6000) +#define DR_REG_LP_MB_BASE (DR_REG_LPAON_BASE + 0x8000) +#define DR_REG_RTC_BASE (DR_REG_LPAON_BASE + 0x9000) + +/* + * @module: LP PERI + * + * @base: 0x50120000 + * + * @size: 64KB + */ +#define DR_REG_LP_PERI_CLKRST_BASE (DR_REG_LPPERIPH_BASE + 0x0) +#define DR_REG_LP_PERI_BASE (DR_REG_LPPERIPH_BASE + 0x0) +#define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000) +#define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000) +#define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000) +#define DR_REG_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) +#define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000) +#define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) +#define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000) +#define DR_REG_LP_GPIO_BASE (DR_REG_LPPERIPH_BASE + 0xA000) +#define DR_REG_LP_IOMUX_BASE (DR_REG_LPPERIPH_BASE + 0xB000) +#define DR_REG_LP_INTR_BASE (DR_REG_LPPERIPH_BASE + 0xC000) +#define DR_REG_EFUSE_BASE (DR_REG_LPPERIPH_BASE + 0xD000) +#define DR_REG_LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE000) +#define DR_REG_HP2LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE800) +#define DR_REG_LP_TSENSOR_BASE (DR_REG_LPPERIPH_BASE + 0xF000) + +/** + * @brief: Special memory address + */ +#define LP_I2S_RAM_BASE 0x50125c00 +#define MIPI_CSI_BRG_MEM_BASE 0x50104000 +#define MIPI_DSI_BRG_MEM_BASE 0x50105000 + + +/** + * This are module helper MACROs for quick module reference + * including some module(renamed) address + */ +#define DR_REG_UART_BASE DR_REG_UART0_BASE +#define DR_REG_UHCI0_BASE DR_REG_UHCI_BASE +#define DR_REG_TIMERGROUP0_BASE DR_REG_TIMG0_BASE +#define DR_REG_TIMERGROUP1_BASE DR_REG_TIMG1_BASE +#define DR_REG_I2S_BASE DR_REG_I2S0_BASE +#define DR_REG_USB_SERIAL_JTAG_BASE DR_REG_USB2JTAG_BASE +#define DR_REG_INTMTX_BASE DR_REG_INTR_BASE +#define DR_REG_SOC_ETM_BASE DR_REG_ETM_BASE +#define DR_REG_MCPWM_BASE DR_REG_MCPWM0_BASE +#define DR_REG_PARL_IO_BASE DR_REG_PARIO_BASE +#define DR_REG_PVT_MONITOR_BASE DR_REG_PVT_BASE +#define DR_REG_AES_BASE (DR_REG_CRYPTO_BASE + 0x0) +#define DR_REG_SHA_BASE (DR_REG_CRYPTO_BASE + 0x1000) +#define DR_REG_RSA_BASE (DR_REG_CRYPTO_BASE + 0x2000) +#define DR_REG_ECC_MULT_BASE (DR_REG_CRYPTO_BASE + 0x3000) +#define DR_REG_DS_BASE (DR_REG_CRYPTO_BASE + 0x4000) +#define DR_REG_DIGITAL_SIGNATURE_BASE DR_REG_DS_BASE +#define DR_REG_HMAC_BASE (DR_REG_CRYPTO_BASE + 0x5000) +#define DR_REG_ECDSA_BASE (DR_REG_CRYPTO_BASE + 0x6000) +#define DR_REG_MEM_MONITOR_BASE DR_REG_L2MEM_MON_BASE +#define DR_REG_HP_CLKRST_BASE DR_REG_HP_SYS_CLKRST_BASE +#define DR_REG_DSPI_MEM_BASE DR_REG_PSRAM_MSPI0_BASE +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTR_BASE +#define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR_BASE + 0x800) +#define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE +#define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE +#define DR_REG_ASSIST_DEBUG_BASE DR_REG_CPU_BUS_MON_BASE +#define DR_REG_PAU_BASE DR_REG_REGDMA_BASE +#define DR_REG_SDHOST_BASE DR_REG_SDMMC_BASE +#define DR_REG_TRACE_BASE DR_REG_TRACE0_BASE diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rmt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/rmt_eco5_struct.h new file mode 100644 index 0000000000..bd665b84be --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rmt_eco5_struct.h @@ -0,0 +1,1077 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata:32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +typedef union { + struct { + /** chmdata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ + uint32_t chmdata:32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn:1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn:1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn:1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn:1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn:1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn:1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn:1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn:1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn:8; + /** mem_size_chn : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn:4; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn:1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn:1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn:1; + uint32_t reserved_23:1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm:8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm:15; + uint32_t reserved_23:1; + /** mem_size_chm : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm:4; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm:1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm:1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm:1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm:1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block.1'h1: Receiver is using + * the ram. 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm:1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm:1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm:8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm:1; + uint32_t reserved_14:1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm:16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm:16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu:1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + */ + uint32_t sclk_sel:2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active:1; + uint32_t reserved_27:4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0:1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1:1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2:1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3:1; + /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ + uint32_t ref_cnt_rst_ch4:1; + /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ + uint32_t ref_cnt_rst_ch5:1; + /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ + uint32_t ref_cnt_rst_ch6:1; + /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ + uint32_t ref_cnt_rst_ch7:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn:10; + uint32_t reserved_10:1; + /** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn:10; + uint32_t reserved_21:1; + /** state_chn : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn:3; + /** mem_empty_chn : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn:1; + /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm:10; + uint32_t reserved_10:1; + /** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm:10; + uint32_t reserved_21:1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm:3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm:1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm:1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw:1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw:1; + /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ + uint32_t ch2_tx_end_int_raw:1; + /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ + uint32_t ch3_tx_end_int_raw:1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw:1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw:1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw:1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw:1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw:1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw:1; + /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch2_tx_thr_event_int_raw:1; + /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch3_tx_thr_event_int_raw:1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw:1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw:1; + /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch2_tx_loop_int_raw:1; + /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch3_tx_loop_int_raw:1; + /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ + uint32_t ch4_rx_end_int_raw:1; + /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ + uint32_t ch5_rx_end_int_raw:1; + /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ + uint32_t ch6_rx_end_int_raw:1; + /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ + uint32_t ch7_rx_end_int_raw:1; + /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ + uint32_t ch4_err_int_raw:1; + /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ + uint32_t ch5_err_int_raw:1; + /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ + uint32_t ch6_err_int_raw:1; + /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ + uint32_t ch7_err_int_raw:1; + /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch4_rx_thr_event_int_raw:1; + /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch5_rx_thr_event_int_raw:1; + /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch6_rx_thr_event_int_raw:1; + /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch7_rx_thr_event_int_raw:1; + /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + */ + uint32_t ch3_dma_access_fail_int_raw:1; + /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + */ + uint32_t ch7_dma_access_fail_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st:1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st:1; + /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_st:1; + /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_st:1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_st:1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_st:1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_st:1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_st:1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st:1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st:1; + /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_st:1; + /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_st:1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st:1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st:1; + /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_st:1; + /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_st:1; + /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_st:1; + /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_st:1; + /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_st:1; + /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_st:1; + /** ch4_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_st:1; + /** ch5_err_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_st:1; + /** ch6_err_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_st:1; + /** ch7_err_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_st:1; + /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_st:1; + /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_st:1; + /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_st:1; + /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_st:1; + /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_st:1; + /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0; + * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena:1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena:1; + /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_ena:1; + /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_ena:1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_ena:1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_ena:1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_ena:1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_ena:1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena:1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena:1; + /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_ena:1; + /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_ena:1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena:1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena:1; + /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_ena:1; + /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_ena:1; + /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_ena:1; + /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_ena:1; + /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_ena:1; + /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_ena:1; + /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_ena:1; + /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_ena:1; + /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_ena:1; + /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_ena:1; + /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_ena:1; + /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_ena:1; + /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_ena:1; + /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_ena:1; + /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_ena:1; + /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0; + * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr:1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr:1; + /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ + uint32_t ch2_tx_end_int_clr:1; + /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ + uint32_t ch3_tx_end_int_clr:1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr:1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr:1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr:1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr:1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr:1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr:1; + /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_tx_thr_event_int_clr:1; + /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_tx_thr_event_int_clr:1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr:1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr:1; + /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ + uint32_t ch2_tx_loop_int_clr:1; + /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ + uint32_t ch3_tx_loop_int_clr:1; + /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ + uint32_t ch4_rx_end_int_clr:1; + /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ + uint32_t ch5_rx_end_int_clr:1; + /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ + uint32_t ch6_rx_end_int_clr:1; + /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ + uint32_t ch7_rx_end_int_clr:1; + /** ch4_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ + uint32_t ch4_err_int_clr:1; + /** ch5_err_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ + uint32_t ch5_err_int_clr:1; + /** ch6_err_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ + uint32_t ch6_err_int_clr:1; + /** ch7_err_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ + uint32_t ch7_err_int_clr:1; + /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch4_rx_thr_event_int_clr:1; + /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch5_rx_thr_event_int_clr:1; + /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch6_rx_thr_event_int_clr:1; + /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch7_rx_thr_event_int_clr:1; + /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch3_dma_access_fail_int_clr:1; + /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch7_dma_access_fail_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn:16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn:16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn:9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn:10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn:1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn:1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0:1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1:1; + /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch2:1; + /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch3:1; + /** tx_sim_en : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t chm_rx_lim_reg:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655953; + * This is the version register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct { + volatile rmt_chndata_reg_t chndata[4]; + volatile rmt_chmdata_reg_t chmdata[4]; + volatile rmt_chnconf0_reg_t chnconf0[4]; + volatile rmt_chmconf0_reg_t ch4conf0; + volatile rmt_chmconf1_reg_t ch4conf1; + volatile rmt_chmconf0_reg_t ch5conf0; + volatile rmt_chmconf1_reg_t ch5conf1; + volatile rmt_chmconf0_reg_t ch6conf0; + volatile rmt_chmconf1_reg_t ch6conf1; + volatile rmt_chmconf0_reg_t ch7conf0; + volatile rmt_chmconf1_reg_t ch7conf1; + volatile rmt_chnstatus_reg_t chnstatus[4]; + volatile rmt_chmstatus_reg_t chmstatus[4]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rmt_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/rmt_reg.h new file mode 100644 index 0000000000..772e8dd316 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rmt_reg.h @@ -0,0 +1,2799 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 + +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 + +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 + +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 + +/** RMT_CH4DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_CH4DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH4DATA 0xFFFFFFFFU +#define RMT_CH4DATA_M (RMT_CH4DATA_V << RMT_CH4DATA_S) +#define RMT_CH4DATA_V 0xFFFFFFFFU +#define RMT_CH4DATA_S 0 + +/** RMT_CH5DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_CH5DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH5DATA 0xFFFFFFFFU +#define RMT_CH5DATA_M (RMT_CH5DATA_V << RMT_CH5DATA_S) +#define RMT_CH5DATA_V 0xFFFFFFFFU +#define RMT_CH5DATA_S 0 + +/** RMT_CH6DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_CH6DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH6DATA 0xFFFFFFFFU +#define RMT_CH6DATA_M (RMT_CH6DATA_V << RMT_CH6DATA_S) +#define RMT_CH6DATA_V 0xFFFFFFFFU +#define RMT_CH6DATA_S 0 + +/** RMT_CH7DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_CH7DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH7DATA 0xFFFFFFFFU +#define RMT_CH7DATA_M (RMT_CH7DATA_V << RMT_CH7DATA_S) +#define RMT_CH7DATA_V 0xFFFFFFFFU +#define RMT_CH7DATA_S 0 + +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_CH0 0x0000000FU +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x0000000FU +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 + +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_CH1 0x0000000FU +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x0000000FU +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 + +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_TX_START_CH2 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL2. + */ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (RMT_TX_START_CH2_V << RMT_TX_START_CH2_S) +#define RMT_TX_START_CH2_V 0x00000001U +#define RMT_TX_START_CH2_S 0 +/** RMT_MEM_RD_RST_CH2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL2 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH2 (BIT(1)) +#define RMT_MEM_RD_RST_CH2_M (RMT_MEM_RD_RST_CH2_V << RMT_MEM_RD_RST_CH2_S) +#define RMT_MEM_RD_RST_CH2_V 0x00000001U +#define RMT_MEM_RD_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_TX_CONTI_MODE_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL2. + */ +#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_M (RMT_TX_CONTI_MODE_CH2_V << RMT_TX_CONTI_MODE_CH2_S) +#define RMT_TX_CONTI_MODE_CH2_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH2_S 3 +/** RMT_MEM_TX_WRAP_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_M (RMT_MEM_TX_WRAP_EN_CH2_V << RMT_MEM_TX_WRAP_EN_CH2_S) +#define RMT_MEM_TX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH2_S 4 +/** RMT_IDLE_OUT_LV_CH2 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL2 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_M (RMT_IDLE_OUT_LV_CH2_V << RMT_IDLE_OUT_LV_CH2_S) +#define RMT_IDLE_OUT_LV_CH2_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH2_S 5 +/** RMT_IDLE_OUT_EN_CH2 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL2 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_M (RMT_IDLE_OUT_EN_CH2_V << RMT_IDLE_OUT_EN_CH2_S) +#define RMT_IDLE_OUT_EN_CH2_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH2_S 6 +/** RMT_TX_STOP_CH2 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL2 sending data out. + */ +#define RMT_TX_STOP_CH2 (BIT(7)) +#define RMT_TX_STOP_CH2_M (RMT_TX_STOP_CH2_V << RMT_TX_STOP_CH2_S) +#define RMT_TX_STOP_CH2_V 0x00000001U +#define RMT_TX_STOP_CH2_S 7 +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_CH2 0x0000000FU +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x0000000FU +#define RMT_MEM_SIZE_CH2_S 16 +/** RMT_CARRIER_EFF_EN_CH2 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL2. 0: Add carrier modulation on the output signal at all state for CHANNEL2. + * Only valid when RMT_CARRIER_EN_CH2 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_M (RMT_CARRIER_EFF_EN_CH2_V << RMT_CARRIER_EFF_EN_CH2_S) +#define RMT_CARRIER_EFF_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH2_S 20 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH2 (BIT(21)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 21 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 22 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_CH2 (BIT(24)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 24 + +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_TX_START_CH3 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL3. + */ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (RMT_TX_START_CH3_V << RMT_TX_START_CH3_S) +#define RMT_TX_START_CH3_V 0x00000001U +#define RMT_TX_START_CH3_S 0 +/** RMT_MEM_RD_RST_CH3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL3 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH3 (BIT(1)) +#define RMT_MEM_RD_RST_CH3_M (RMT_MEM_RD_RST_CH3_V << RMT_MEM_RD_RST_CH3_S) +#define RMT_MEM_RD_RST_CH3_V 0x00000001U +#define RMT_MEM_RD_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_TX_CONTI_MODE_CH3 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL3. + */ +#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_M (RMT_TX_CONTI_MODE_CH3_V << RMT_TX_CONTI_MODE_CH3_S) +#define RMT_TX_CONTI_MODE_CH3_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH3_S 3 +/** RMT_MEM_TX_WRAP_EN_CH3 : R/W; bitpos: [4]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_M (RMT_MEM_TX_WRAP_EN_CH3_V << RMT_MEM_TX_WRAP_EN_CH3_S) +#define RMT_MEM_TX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH3_S 4 +/** RMT_IDLE_OUT_LV_CH3 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL3 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_M (RMT_IDLE_OUT_LV_CH3_V << RMT_IDLE_OUT_LV_CH3_S) +#define RMT_IDLE_OUT_LV_CH3_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH3_S 5 +/** RMT_IDLE_OUT_EN_CH3 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL3 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_M (RMT_IDLE_OUT_EN_CH3_V << RMT_IDLE_OUT_EN_CH3_S) +#define RMT_IDLE_OUT_EN_CH3_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH3_S 6 +/** RMT_TX_STOP_CH3 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL3 sending data out. + */ +#define RMT_TX_STOP_CH3 (BIT(7)) +#define RMT_TX_STOP_CH3_M (RMT_TX_STOP_CH3_V << RMT_TX_STOP_CH3_S) +#define RMT_TX_STOP_CH3_V 0x00000001U +#define RMT_TX_STOP_CH3_S 7 +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_CH3 0x0000000FU +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x0000000FU +#define RMT_MEM_SIZE_CH3_S 16 +/** RMT_CARRIER_EFF_EN_CH3 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL3. 0: Add carrier modulation on the output signal at all state for CHANNEL3. + * Only valid when RMT_CARRIER_EN_CH3 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_M (RMT_CARRIER_EFF_EN_CH3_V << RMT_CARRIER_EFF_EN_CH3_S) +#define RMT_CARRIER_EFF_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH3_S 20 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH3 (BIT(21)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 21 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 22 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_CH3 (BIT(24)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 24 + +/** RMT_CH4CONF0_REG register + * Channel 4 configure register 0 + */ +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_DIV_CNT_CH4 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL4. + */ +#define RMT_DIV_CNT_CH4 0x000000FFU +#define RMT_DIV_CNT_CH4_M (RMT_DIV_CNT_CH4_V << RMT_DIV_CNT_CH4_S) +#define RMT_DIV_CNT_CH4_V 0x000000FFU +#define RMT_DIV_CNT_CH4_S 0 +/** RMT_IDLE_THRES_CH4 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH4 0x00007FFFU +#define RMT_IDLE_THRES_CH4_M (RMT_IDLE_THRES_CH4_V << RMT_IDLE_THRES_CH4_S) +#define RMT_IDLE_THRES_CH4_V 0x00007FFFU +#define RMT_IDLE_THRES_CH4_S 8 +/** RMT_MEM_SIZE_CH4 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL4. + */ +#define RMT_MEM_SIZE_CH4 0x0000000FU +#define RMT_MEM_SIZE_CH4_M (RMT_MEM_SIZE_CH4_V << RMT_MEM_SIZE_CH4_S) +#define RMT_MEM_SIZE_CH4_V 0x0000000FU +#define RMT_MEM_SIZE_CH4_S 24 +/** RMT_CARRIER_EN_CH4 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL4. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (RMT_CARRIER_EN_CH4_V << RMT_CARRIER_EN_CH4_S) +#define RMT_CARRIER_EN_CH4_V 0x00000001U +#define RMT_CARRIER_EN_CH4_S 28 +/** RMT_CARRIER_OUT_LV_CH4 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL4.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (RMT_CARRIER_OUT_LV_CH4_V << RMT_CARRIER_OUT_LV_CH4_S) +#define RMT_CARRIER_OUT_LV_CH4_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH4_S 29 + +/** RMT_CH4CONF1_REG register + * Channel 4 configure register 1 + */ +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_RX_EN_CH4 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL4. + */ +#define RMT_RX_EN_CH4 (BIT(0)) +#define RMT_RX_EN_CH4_M (RMT_RX_EN_CH4_V << RMT_RX_EN_CH4_S) +#define RMT_RX_EN_CH4_V 0x00000001U +#define RMT_RX_EN_CH4_S 0 +/** RMT_MEM_WR_RST_CH4 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL4 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH4 (BIT(1)) +#define RMT_MEM_WR_RST_CH4_M (RMT_MEM_WR_RST_CH4_V << RMT_MEM_WR_RST_CH4_S) +#define RMT_MEM_WR_RST_CH4_V 0x00000001U +#define RMT_MEM_WR_RST_CH4_S 1 +/** RMT_APB_MEM_RST_CH4 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL4 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH4 (BIT(2)) +#define RMT_APB_MEM_RST_CH4_M (RMT_APB_MEM_RST_CH4_V << RMT_APB_MEM_RST_CH4_S) +#define RMT_APB_MEM_RST_CH4_V 0x00000001U +#define RMT_APB_MEM_RST_CH4_S 2 +/** RMT_MEM_OWNER_CH4 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL4's ram block.1'h1: Receiver is using + * the ram. 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH4 (BIT(3)) +#define RMT_MEM_OWNER_CH4_M (RMT_MEM_OWNER_CH4_V << RMT_MEM_OWNER_CH4_S) +#define RMT_MEM_OWNER_CH4_V 0x00000001U +#define RMT_MEM_OWNER_CH4_S 3 +/** RMT_RX_FILTER_EN_CH4 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL4. + */ +#define RMT_RX_FILTER_EN_CH4 (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_M (RMT_RX_FILTER_EN_CH4_V << RMT_RX_FILTER_EN_CH4_S) +#define RMT_RX_FILTER_EN_CH4_V 0x00000001U +#define RMT_RX_FILTER_EN_CH4_S 4 +/** RMT_RX_FILTER_THRES_CH4 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH4 0x000000FFU +#define RMT_RX_FILTER_THRES_CH4_M (RMT_RX_FILTER_THRES_CH4_V << RMT_RX_FILTER_THRES_CH4_S) +#define RMT_RX_FILTER_THRES_CH4_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH4_S 5 +/** RMT_MEM_RX_WRAP_EN_CH4 : R/W; bitpos: [13]; default: 0; + * This is the channel 4 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_M (RMT_MEM_RX_WRAP_EN_CH4_V << RMT_MEM_RX_WRAP_EN_CH4_S) +#define RMT_MEM_RX_WRAP_EN_CH4_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH4_S 13 +/** RMT_CONF_UPDATE_CH4 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL4 + */ +#define RMT_CONF_UPDATE_CH4 (BIT(15)) +#define RMT_CONF_UPDATE_CH4_M (RMT_CONF_UPDATE_CH4_V << RMT_CONF_UPDATE_CH4_S) +#define RMT_CONF_UPDATE_CH4_V 0x00000001U +#define RMT_CONF_UPDATE_CH4_S 15 + +/** RMT_CH5CONF0_REG register + * Channel 5 configure register 0 + */ +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_DIV_CNT_CH5 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL5. + */ +#define RMT_DIV_CNT_CH5 0x000000FFU +#define RMT_DIV_CNT_CH5_M (RMT_DIV_CNT_CH5_V << RMT_DIV_CNT_CH5_S) +#define RMT_DIV_CNT_CH5_V 0x000000FFU +#define RMT_DIV_CNT_CH5_S 0 +/** RMT_IDLE_THRES_CH5 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH5 0x00007FFFU +#define RMT_IDLE_THRES_CH5_M (RMT_IDLE_THRES_CH5_V << RMT_IDLE_THRES_CH5_S) +#define RMT_IDLE_THRES_CH5_V 0x00007FFFU +#define RMT_IDLE_THRES_CH5_S 8 +/** RMT_MEM_SIZE_CH5 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL5. + */ +#define RMT_MEM_SIZE_CH5 0x0000000FU +#define RMT_MEM_SIZE_CH5_M (RMT_MEM_SIZE_CH5_V << RMT_MEM_SIZE_CH5_S) +#define RMT_MEM_SIZE_CH5_V 0x0000000FU +#define RMT_MEM_SIZE_CH5_S 24 +/** RMT_CARRIER_EN_CH5 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL5. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (RMT_CARRIER_EN_CH5_V << RMT_CARRIER_EN_CH5_S) +#define RMT_CARRIER_EN_CH5_V 0x00000001U +#define RMT_CARRIER_EN_CH5_S 28 +/** RMT_CARRIER_OUT_LV_CH5 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL5.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (RMT_CARRIER_OUT_LV_CH5_V << RMT_CARRIER_OUT_LV_CH5_S) +#define RMT_CARRIER_OUT_LV_CH5_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH5_S 29 + +/** RMT_CH5CONF1_REG register + * Channel 5 configure register 1 + */ +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_RX_EN_CH5 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL5. + */ +#define RMT_RX_EN_CH5 (BIT(0)) +#define RMT_RX_EN_CH5_M (RMT_RX_EN_CH5_V << RMT_RX_EN_CH5_S) +#define RMT_RX_EN_CH5_V 0x00000001U +#define RMT_RX_EN_CH5_S 0 +/** RMT_MEM_WR_RST_CH5 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL5 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH5 (BIT(1)) +#define RMT_MEM_WR_RST_CH5_M (RMT_MEM_WR_RST_CH5_V << RMT_MEM_WR_RST_CH5_S) +#define RMT_MEM_WR_RST_CH5_V 0x00000001U +#define RMT_MEM_WR_RST_CH5_S 1 +/** RMT_APB_MEM_RST_CH5 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL5 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH5 (BIT(2)) +#define RMT_APB_MEM_RST_CH5_M (RMT_APB_MEM_RST_CH5_V << RMT_APB_MEM_RST_CH5_S) +#define RMT_APB_MEM_RST_CH5_V 0x00000001U +#define RMT_APB_MEM_RST_CH5_S 2 +/** RMT_MEM_OWNER_CH5 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL5's ram block.1'h1: Receiver is using + * the ram. 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH5 (BIT(3)) +#define RMT_MEM_OWNER_CH5_M (RMT_MEM_OWNER_CH5_V << RMT_MEM_OWNER_CH5_S) +#define RMT_MEM_OWNER_CH5_V 0x00000001U +#define RMT_MEM_OWNER_CH5_S 3 +/** RMT_RX_FILTER_EN_CH5 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL5. + */ +#define RMT_RX_FILTER_EN_CH5 (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_M (RMT_RX_FILTER_EN_CH5_V << RMT_RX_FILTER_EN_CH5_S) +#define RMT_RX_FILTER_EN_CH5_V 0x00000001U +#define RMT_RX_FILTER_EN_CH5_S 4 +/** RMT_RX_FILTER_THRES_CH5 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH5 0x000000FFU +#define RMT_RX_FILTER_THRES_CH5_M (RMT_RX_FILTER_THRES_CH5_V << RMT_RX_FILTER_THRES_CH5_S) +#define RMT_RX_FILTER_THRES_CH5_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH5_S 5 +/** RMT_MEM_RX_WRAP_EN_CH5 : R/W; bitpos: [13]; default: 0; + * This is the channel 5 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_M (RMT_MEM_RX_WRAP_EN_CH5_V << RMT_MEM_RX_WRAP_EN_CH5_S) +#define RMT_MEM_RX_WRAP_EN_CH5_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH5_S 13 +/** RMT_CONF_UPDATE_CH5 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL5 + */ +#define RMT_CONF_UPDATE_CH5 (BIT(15)) +#define RMT_CONF_UPDATE_CH5_M (RMT_CONF_UPDATE_CH5_V << RMT_CONF_UPDATE_CH5_S) +#define RMT_CONF_UPDATE_CH5_V 0x00000001U +#define RMT_CONF_UPDATE_CH5_S 15 + +/** RMT_CH6CONF0_REG register + * Channel 6 configure register 0 + */ +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_DIV_CNT_CH6 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL6. + */ +#define RMT_DIV_CNT_CH6 0x000000FFU +#define RMT_DIV_CNT_CH6_M (RMT_DIV_CNT_CH6_V << RMT_DIV_CNT_CH6_S) +#define RMT_DIV_CNT_CH6_V 0x000000FFU +#define RMT_DIV_CNT_CH6_S 0 +/** RMT_IDLE_THRES_CH6 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH6 0x00007FFFU +#define RMT_IDLE_THRES_CH6_M (RMT_IDLE_THRES_CH6_V << RMT_IDLE_THRES_CH6_S) +#define RMT_IDLE_THRES_CH6_V 0x00007FFFU +#define RMT_IDLE_THRES_CH6_S 8 +/** RMT_MEM_SIZE_CH6 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL6. + */ +#define RMT_MEM_SIZE_CH6 0x0000000FU +#define RMT_MEM_SIZE_CH6_M (RMT_MEM_SIZE_CH6_V << RMT_MEM_SIZE_CH6_S) +#define RMT_MEM_SIZE_CH6_V 0x0000000FU +#define RMT_MEM_SIZE_CH6_S 24 +/** RMT_CARRIER_EN_CH6 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL6. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (RMT_CARRIER_EN_CH6_V << RMT_CARRIER_EN_CH6_S) +#define RMT_CARRIER_EN_CH6_V 0x00000001U +#define RMT_CARRIER_EN_CH6_S 28 +/** RMT_CARRIER_OUT_LV_CH6 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL6.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (RMT_CARRIER_OUT_LV_CH6_V << RMT_CARRIER_OUT_LV_CH6_S) +#define RMT_CARRIER_OUT_LV_CH6_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH6_S 29 + +/** RMT_CH6CONF1_REG register + * Channel 6 configure register 1 + */ +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_RX_EN_CH6 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL6. + */ +#define RMT_RX_EN_CH6 (BIT(0)) +#define RMT_RX_EN_CH6_M (RMT_RX_EN_CH6_V << RMT_RX_EN_CH6_S) +#define RMT_RX_EN_CH6_V 0x00000001U +#define RMT_RX_EN_CH6_S 0 +/** RMT_MEM_WR_RST_CH6 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL6 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH6 (BIT(1)) +#define RMT_MEM_WR_RST_CH6_M (RMT_MEM_WR_RST_CH6_V << RMT_MEM_WR_RST_CH6_S) +#define RMT_MEM_WR_RST_CH6_V 0x00000001U +#define RMT_MEM_WR_RST_CH6_S 1 +/** RMT_APB_MEM_RST_CH6 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL6 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH6 (BIT(2)) +#define RMT_APB_MEM_RST_CH6_M (RMT_APB_MEM_RST_CH6_V << RMT_APB_MEM_RST_CH6_S) +#define RMT_APB_MEM_RST_CH6_V 0x00000001U +#define RMT_APB_MEM_RST_CH6_S 2 +/** RMT_MEM_OWNER_CH6 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL6's ram block.1'h1: Receiver is using + * the ram. 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH6 (BIT(3)) +#define RMT_MEM_OWNER_CH6_M (RMT_MEM_OWNER_CH6_V << RMT_MEM_OWNER_CH6_S) +#define RMT_MEM_OWNER_CH6_V 0x00000001U +#define RMT_MEM_OWNER_CH6_S 3 +/** RMT_RX_FILTER_EN_CH6 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL6. + */ +#define RMT_RX_FILTER_EN_CH6 (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_M (RMT_RX_FILTER_EN_CH6_V << RMT_RX_FILTER_EN_CH6_S) +#define RMT_RX_FILTER_EN_CH6_V 0x00000001U +#define RMT_RX_FILTER_EN_CH6_S 4 +/** RMT_RX_FILTER_THRES_CH6 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH6 0x000000FFU +#define RMT_RX_FILTER_THRES_CH6_M (RMT_RX_FILTER_THRES_CH6_V << RMT_RX_FILTER_THRES_CH6_S) +#define RMT_RX_FILTER_THRES_CH6_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH6_S 5 +/** RMT_MEM_RX_WRAP_EN_CH6 : R/W; bitpos: [13]; default: 0; + * This is the channel 6 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_M (RMT_MEM_RX_WRAP_EN_CH6_V << RMT_MEM_RX_WRAP_EN_CH6_S) +#define RMT_MEM_RX_WRAP_EN_CH6_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH6_S 13 +/** RMT_CONF_UPDATE_CH6 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL6 + */ +#define RMT_CONF_UPDATE_CH6 (BIT(15)) +#define RMT_CONF_UPDATE_CH6_M (RMT_CONF_UPDATE_CH6_V << RMT_CONF_UPDATE_CH6_S) +#define RMT_CONF_UPDATE_CH6_V 0x00000001U +#define RMT_CONF_UPDATE_CH6_S 15 + +/** RMT_CH7CONF0_REG register + * Channel 7 configure register 0 + */ +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_DIV_CNT_CH7 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL7. + */ +#define RMT_DIV_CNT_CH7 0x000000FFU +#define RMT_DIV_CNT_CH7_M (RMT_DIV_CNT_CH7_V << RMT_DIV_CNT_CH7_S) +#define RMT_DIV_CNT_CH7_V 0x000000FFU +#define RMT_DIV_CNT_CH7_S 0 +/** RMT_IDLE_THRES_CH7 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH7 0x00007FFFU +#define RMT_IDLE_THRES_CH7_M (RMT_IDLE_THRES_CH7_V << RMT_IDLE_THRES_CH7_S) +#define RMT_IDLE_THRES_CH7_V 0x00007FFFU +#define RMT_IDLE_THRES_CH7_S 8 +/** RMT_MEM_SIZE_CH7 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL7. + */ +#define RMT_MEM_SIZE_CH7 0x0000000FU +#define RMT_MEM_SIZE_CH7_M (RMT_MEM_SIZE_CH7_V << RMT_MEM_SIZE_CH7_S) +#define RMT_MEM_SIZE_CH7_V 0x0000000FU +#define RMT_MEM_SIZE_CH7_S 24 +/** RMT_CARRIER_EN_CH7 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL7. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (RMT_CARRIER_EN_CH7_V << RMT_CARRIER_EN_CH7_S) +#define RMT_CARRIER_EN_CH7_V 0x00000001U +#define RMT_CARRIER_EN_CH7_S 28 +/** RMT_CARRIER_OUT_LV_CH7 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL7.1'h0: add + * carrier wave on low level.1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (RMT_CARRIER_OUT_LV_CH7_V << RMT_CARRIER_OUT_LV_CH7_S) +#define RMT_CARRIER_OUT_LV_CH7_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH7_S 29 + +/** RMT_CH7CONF1_REG register + * Channel 7 configure register 1 + */ +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_RX_EN_CH7 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL7. + */ +#define RMT_RX_EN_CH7 (BIT(0)) +#define RMT_RX_EN_CH7_M (RMT_RX_EN_CH7_V << RMT_RX_EN_CH7_S) +#define RMT_RX_EN_CH7_V 0x00000001U +#define RMT_RX_EN_CH7_S 0 +/** RMT_MEM_WR_RST_CH7 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL7 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH7 (BIT(1)) +#define RMT_MEM_WR_RST_CH7_M (RMT_MEM_WR_RST_CH7_V << RMT_MEM_WR_RST_CH7_S) +#define RMT_MEM_WR_RST_CH7_V 0x00000001U +#define RMT_MEM_WR_RST_CH7_S 1 +/** RMT_APB_MEM_RST_CH7 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL7 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH7 (BIT(2)) +#define RMT_APB_MEM_RST_CH7_M (RMT_APB_MEM_RST_CH7_V << RMT_APB_MEM_RST_CH7_S) +#define RMT_APB_MEM_RST_CH7_V 0x00000001U +#define RMT_APB_MEM_RST_CH7_S 2 +/** RMT_MEM_OWNER_CH7 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL7's ram block.1'h1: Receiver is using + * the ram. 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH7 (BIT(3)) +#define RMT_MEM_OWNER_CH7_M (RMT_MEM_OWNER_CH7_V << RMT_MEM_OWNER_CH7_S) +#define RMT_MEM_OWNER_CH7_V 0x00000001U +#define RMT_MEM_OWNER_CH7_S 3 +/** RMT_RX_FILTER_EN_CH7 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL7. + */ +#define RMT_RX_FILTER_EN_CH7 (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_M (RMT_RX_FILTER_EN_CH7_V << RMT_RX_FILTER_EN_CH7_S) +#define RMT_RX_FILTER_EN_CH7_V 0x00000001U +#define RMT_RX_FILTER_EN_CH7_S 4 +/** RMT_RX_FILTER_THRES_CH7 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH7 0x000000FFU +#define RMT_RX_FILTER_THRES_CH7_M (RMT_RX_FILTER_THRES_CH7_V << RMT_RX_FILTER_THRES_CH7_S) +#define RMT_RX_FILTER_THRES_CH7_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH7_S 5 +/** RMT_MEM_RX_WRAP_EN_CH7 : R/W; bitpos: [13]; default: 0; + * This is the channel 7 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_M (RMT_MEM_RX_WRAP_EN_CH7_V << RMT_MEM_RX_WRAP_EN_CH7_S) +#define RMT_MEM_RX_WRAP_EN_CH7_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH7_S 13 +/** RMT_CONF_UPDATE_CH7 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL7 + */ +#define RMT_CONF_UPDATE_CH7 (BIT(15)) +#define RMT_CONF_UPDATE_CH7_M (RMT_CONF_UPDATE_CH7_V << RMT_CONF_UPDATE_CH7_S) +#define RMT_CONF_UPDATE_CH7_V 0x00000001U +#define RMT_CONF_UPDATE_CH7_S 15 + +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH0 0x000003FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH0 0x000003FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH0_S 11 +/** RMT_STATE_CH0 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 22 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH0 (BIT(25)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 25 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 26 + +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH1 0x000003FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH1 0x000003FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH1_S 11 +/** RMT_STATE_CH1 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 22 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH1 (BIT(25)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 25 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 26 + +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_MEM_RADDR_EX_CH2 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL2 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH2 0x000003FFU +#define RMT_MEM_RADDR_EX_CH2_M (RMT_MEM_RADDR_EX_CH2_V << RMT_MEM_RADDR_EX_CH2_S) +#define RMT_MEM_RADDR_EX_CH2_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH2_S 0 +/** RMT_APB_MEM_WADDR_CH2 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH2 0x000003FFU +#define RMT_APB_MEM_WADDR_CH2_M (RMT_APB_MEM_WADDR_CH2_V << RMT_APB_MEM_WADDR_CH2_S) +#define RMT_APB_MEM_WADDR_CH2_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH2_S 11 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_EMPTY_CH2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH2 (BIT(25)) +#define RMT_MEM_EMPTY_CH2_M (RMT_MEM_EMPTY_CH2_V << RMT_MEM_EMPTY_CH2_S) +#define RMT_MEM_EMPTY_CH2_V 0x00000001U +#define RMT_MEM_EMPTY_CH2_S 25 +/** RMT_APB_MEM_WR_ERR_CH2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_M (RMT_APB_MEM_WR_ERR_CH2_V << RMT_APB_MEM_WR_ERR_CH2_S) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH2_S 26 + +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_MEM_RADDR_EX_CH3 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL3 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH3 0x000003FFU +#define RMT_MEM_RADDR_EX_CH3_M (RMT_MEM_RADDR_EX_CH3_V << RMT_MEM_RADDR_EX_CH3_S) +#define RMT_MEM_RADDR_EX_CH3_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH3_S 0 +/** RMT_APB_MEM_WADDR_CH3 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH3 0x000003FFU +#define RMT_APB_MEM_WADDR_CH3_M (RMT_APB_MEM_WADDR_CH3_V << RMT_APB_MEM_WADDR_CH3_S) +#define RMT_APB_MEM_WADDR_CH3_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH3_S 11 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_EMPTY_CH3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH3 (BIT(25)) +#define RMT_MEM_EMPTY_CH3_M (RMT_MEM_EMPTY_CH3_V << RMT_MEM_EMPTY_CH3_S) +#define RMT_MEM_EMPTY_CH3_V 0x00000001U +#define RMT_MEM_EMPTY_CH3_S 25 +/** RMT_APB_MEM_WR_ERR_CH3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_M (RMT_APB_MEM_WR_ERR_CH3_V << RMT_APB_MEM_WR_ERR_CH3_S) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH3_S 26 + +/** RMT_CH4STATUS_REG register + * Channel 4 status register + */ +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_MEM_WADDR_EX_CH4 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL4 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH4 0x000003FFU +#define RMT_MEM_WADDR_EX_CH4_M (RMT_MEM_WADDR_EX_CH4_V << RMT_MEM_WADDR_EX_CH4_S) +#define RMT_MEM_WADDR_EX_CH4_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH4_S 0 +/** RMT_APB_MEM_RADDR_CH4 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH4 0x000003FFU +#define RMT_APB_MEM_RADDR_CH4_M (RMT_APB_MEM_RADDR_CH4_V << RMT_APB_MEM_RADDR_CH4_S) +#define RMT_APB_MEM_RADDR_CH4_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH4_S 11 +/** RMT_STATE_CH4 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL4. + */ +#define RMT_STATE_CH4 0x00000007U +#define RMT_STATE_CH4_M (RMT_STATE_CH4_V << RMT_STATE_CH4_S) +#define RMT_STATE_CH4_V 0x00000007U +#define RMT_STATE_CH4_S 22 +/** RMT_MEM_OWNER_ERR_CH4 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_M (RMT_MEM_OWNER_ERR_CH4_V << RMT_MEM_OWNER_ERR_CH4_S) +#define RMT_MEM_OWNER_ERR_CH4_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH4_S 25 +/** RMT_MEM_FULL_CH4 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH4 (BIT(26)) +#define RMT_MEM_FULL_CH4_M (RMT_MEM_FULL_CH4_V << RMT_MEM_FULL_CH4_S) +#define RMT_MEM_FULL_CH4_V 0x00000001U +#define RMT_MEM_FULL_CH4_S 26 +/** RMT_APB_MEM_RD_ERR_CH4 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_M (RMT_APB_MEM_RD_ERR_CH4_V << RMT_APB_MEM_RD_ERR_CH4_S) +#define RMT_APB_MEM_RD_ERR_CH4_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH4_S 27 + +/** RMT_CH5STATUS_REG register + * Channel 5 status register + */ +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_MEM_WADDR_EX_CH5 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL5 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH5 0x000003FFU +#define RMT_MEM_WADDR_EX_CH5_M (RMT_MEM_WADDR_EX_CH5_V << RMT_MEM_WADDR_EX_CH5_S) +#define RMT_MEM_WADDR_EX_CH5_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH5_S 0 +/** RMT_APB_MEM_RADDR_CH5 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH5 0x000003FFU +#define RMT_APB_MEM_RADDR_CH5_M (RMT_APB_MEM_RADDR_CH5_V << RMT_APB_MEM_RADDR_CH5_S) +#define RMT_APB_MEM_RADDR_CH5_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH5_S 11 +/** RMT_STATE_CH5 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL5. + */ +#define RMT_STATE_CH5 0x00000007U +#define RMT_STATE_CH5_M (RMT_STATE_CH5_V << RMT_STATE_CH5_S) +#define RMT_STATE_CH5_V 0x00000007U +#define RMT_STATE_CH5_S 22 +/** RMT_MEM_OWNER_ERR_CH5 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_M (RMT_MEM_OWNER_ERR_CH5_V << RMT_MEM_OWNER_ERR_CH5_S) +#define RMT_MEM_OWNER_ERR_CH5_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH5_S 25 +/** RMT_MEM_FULL_CH5 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH5 (BIT(26)) +#define RMT_MEM_FULL_CH5_M (RMT_MEM_FULL_CH5_V << RMT_MEM_FULL_CH5_S) +#define RMT_MEM_FULL_CH5_V 0x00000001U +#define RMT_MEM_FULL_CH5_S 26 +/** RMT_APB_MEM_RD_ERR_CH5 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_M (RMT_APB_MEM_RD_ERR_CH5_V << RMT_APB_MEM_RD_ERR_CH5_S) +#define RMT_APB_MEM_RD_ERR_CH5_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH5_S 27 + +/** RMT_CH6STATUS_REG register + * Channel 6 status register + */ +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_MEM_WADDR_EX_CH6 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL6 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH6 0x000003FFU +#define RMT_MEM_WADDR_EX_CH6_M (RMT_MEM_WADDR_EX_CH6_V << RMT_MEM_WADDR_EX_CH6_S) +#define RMT_MEM_WADDR_EX_CH6_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH6_S 0 +/** RMT_APB_MEM_RADDR_CH6 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH6 0x000003FFU +#define RMT_APB_MEM_RADDR_CH6_M (RMT_APB_MEM_RADDR_CH6_V << RMT_APB_MEM_RADDR_CH6_S) +#define RMT_APB_MEM_RADDR_CH6_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH6_S 11 +/** RMT_STATE_CH6 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL6. + */ +#define RMT_STATE_CH6 0x00000007U +#define RMT_STATE_CH6_M (RMT_STATE_CH6_V << RMT_STATE_CH6_S) +#define RMT_STATE_CH6_V 0x00000007U +#define RMT_STATE_CH6_S 22 +/** RMT_MEM_OWNER_ERR_CH6 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_M (RMT_MEM_OWNER_ERR_CH6_V << RMT_MEM_OWNER_ERR_CH6_S) +#define RMT_MEM_OWNER_ERR_CH6_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH6_S 25 +/** RMT_MEM_FULL_CH6 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH6 (BIT(26)) +#define RMT_MEM_FULL_CH6_M (RMT_MEM_FULL_CH6_V << RMT_MEM_FULL_CH6_S) +#define RMT_MEM_FULL_CH6_V 0x00000001U +#define RMT_MEM_FULL_CH6_S 26 +/** RMT_APB_MEM_RD_ERR_CH6 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_M (RMT_APB_MEM_RD_ERR_CH6_V << RMT_APB_MEM_RD_ERR_CH6_S) +#define RMT_APB_MEM_RD_ERR_CH6_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH6_S 27 + +/** RMT_CH7STATUS_REG register + * Channel 7 status register + */ +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_MEM_WADDR_EX_CH7 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL7 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH7 0x000003FFU +#define RMT_MEM_WADDR_EX_CH7_M (RMT_MEM_WADDR_EX_CH7_V << RMT_MEM_WADDR_EX_CH7_S) +#define RMT_MEM_WADDR_EX_CH7_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH7_S 0 +/** RMT_APB_MEM_RADDR_CH7 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH7 0x000003FFU +#define RMT_APB_MEM_RADDR_CH7_M (RMT_APB_MEM_RADDR_CH7_V << RMT_APB_MEM_RADDR_CH7_S) +#define RMT_APB_MEM_RADDR_CH7_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH7_S 11 +/** RMT_STATE_CH7 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL7. + */ +#define RMT_STATE_CH7 0x00000007U +#define RMT_STATE_CH7_M (RMT_STATE_CH7_V << RMT_STATE_CH7_S) +#define RMT_STATE_CH7_V 0x00000007U +#define RMT_STATE_CH7_S 22 +/** RMT_MEM_OWNER_ERR_CH7 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_M (RMT_MEM_OWNER_ERR_CH7_V << RMT_MEM_OWNER_ERR_CH7_S) +#define RMT_MEM_OWNER_ERR_CH7_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH7_S 25 +/** RMT_MEM_FULL_CH7 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH7 (BIT(26)) +#define RMT_MEM_FULL_CH7_M (RMT_MEM_FULL_CH7_V << RMT_MEM_FULL_CH7_S) +#define RMT_MEM_FULL_CH7_V 0x00000001U +#define RMT_MEM_FULL_CH7_S 26 +/** RMT_APB_MEM_RD_ERR_CH7 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_M (RMT_APB_MEM_RD_ERR_CH7_V << RMT_APB_MEM_RD_ERR_CH7_S) +#define RMT_APB_MEM_RD_ERR_CH7_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH7_S 27 + +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_TX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ +#define RMT_CH2_TX_END_INT_RAW (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_M (RMT_CH2_TX_END_INT_RAW_V << RMT_CH2_TX_END_INT_RAW_S) +#define RMT_CH2_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_END_INT_RAW_S 2 +/** RMT_CH3_TX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ +#define RMT_CH3_TX_END_INT_RAW (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_M (RMT_CH3_TX_END_INT_RAW_V << RMT_CH3_TX_END_INT_RAW_S) +#define RMT_CH3_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (RMT_CH2_TX_THR_EVENT_INT_RAW_V << RMT_CH2_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (RMT_CH3_TX_THR_EVENT_INT_RAW_V << RMT_CH3_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/** RMT_CH2_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_M (RMT_CH2_TX_LOOP_INT_RAW_V << RMT_CH2_TX_LOOP_INT_RAW_S) +#define RMT_CH2_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_RAW_S 14 +/** RMT_CH3_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_M (RMT_CH3_TX_LOOP_INT_RAW_V << RMT_CH3_TX_LOOP_INT_RAW_S) +#define RMT_CH3_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_RAW_S 15 +/** RMT_CH4_RX_END_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ +#define RMT_CH4_RX_END_INT_RAW (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_M (RMT_CH4_RX_END_INT_RAW_V << RMT_CH4_RX_END_INT_RAW_S) +#define RMT_CH4_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH4_RX_END_INT_RAW_S 16 +/** RMT_CH5_RX_END_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ +#define RMT_CH5_RX_END_INT_RAW (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_M (RMT_CH5_RX_END_INT_RAW_V << RMT_CH5_RX_END_INT_RAW_S) +#define RMT_CH5_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH5_RX_END_INT_RAW_S 17 +/** RMT_CH6_RX_END_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ +#define RMT_CH6_RX_END_INT_RAW (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_M (RMT_CH6_RX_END_INT_RAW_V << RMT_CH6_RX_END_INT_RAW_S) +#define RMT_CH6_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH6_RX_END_INT_RAW_S 18 +/** RMT_CH7_RX_END_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ +#define RMT_CH7_RX_END_INT_RAW (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_M (RMT_CH7_RX_END_INT_RAW_V << RMT_CH7_RX_END_INT_RAW_S) +#define RMT_CH7_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH7_RX_END_INT_RAW_S 19 +/** RMT_CH4_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ +#define RMT_CH4_ERR_INT_RAW (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_M (RMT_CH4_ERR_INT_RAW_V << RMT_CH4_ERR_INT_RAW_S) +#define RMT_CH4_ERR_INT_RAW_V 0x00000001U +#define RMT_CH4_ERR_INT_RAW_S 20 +/** RMT_CH5_ERR_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ +#define RMT_CH5_ERR_INT_RAW (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_M (RMT_CH5_ERR_INT_RAW_V << RMT_CH5_ERR_INT_RAW_S) +#define RMT_CH5_ERR_INT_RAW_V 0x00000001U +#define RMT_CH5_ERR_INT_RAW_S 21 +/** RMT_CH6_ERR_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ +#define RMT_CH6_ERR_INT_RAW (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_M (RMT_CH6_ERR_INT_RAW_V << RMT_CH6_ERR_INT_RAW_S) +#define RMT_CH6_ERR_INT_RAW_V 0x00000001U +#define RMT_CH6_ERR_INT_RAW_S 22 +/** RMT_CH7_ERR_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (RMT_CH7_ERR_INT_RAW_V << RMT_CH7_ERR_INT_RAW_S) +#define RMT_CH7_ERR_INT_RAW_V 0x00000001U +#define RMT_CH7_ERR_INT_RAW_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (RMT_CH4_RX_THR_EVENT_INT_RAW_V << RMT_CH4_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (RMT_CH5_RX_THR_EVENT_INT_RAW_V << RMT_CH5_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (RMT_CH6_RX_THR_EVENT_INT_RAW_V << RMT_CH6_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (RMT_CH7_RX_THR_EVENT_INT_RAW_V << RMT_CH7_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_M (RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_M (RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S 29 + +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_TX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ST (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_M (RMT_CH2_TX_END_INT_ST_V << RMT_CH2_TX_END_INT_ST_S) +#define RMT_CH2_TX_END_INT_ST_V 0x00000001U +#define RMT_CH2_TX_END_INT_ST_S 2 +/** RMT_CH3_TX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ST (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_M (RMT_CH3_TX_END_INT_ST_V << RMT_CH3_TX_END_INT_ST_S) +#define RMT_CH3_TX_END_INT_ST_V 0x00000001U +#define RMT_CH3_TX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (RMT_CH2_TX_THR_EVENT_INT_ST_V << RMT_CH2_TX_THR_EVENT_INT_ST_S) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (RMT_CH3_TX_THR_EVENT_INT_ST_V << RMT_CH3_TX_THR_EVENT_INT_ST_S) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/** RMT_CH2_TX_LOOP_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_M (RMT_CH2_TX_LOOP_INT_ST_V << RMT_CH2_TX_LOOP_INT_ST_S) +#define RMT_CH2_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_ST_S 14 +/** RMT_CH3_TX_LOOP_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_M (RMT_CH3_TX_LOOP_INT_ST_V << RMT_CH3_TX_LOOP_INT_ST_S) +#define RMT_CH3_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_ST_S 15 +/** RMT_CH4_RX_END_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ST (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_M (RMT_CH4_RX_END_INT_ST_V << RMT_CH4_RX_END_INT_ST_S) +#define RMT_CH4_RX_END_INT_ST_V 0x00000001U +#define RMT_CH4_RX_END_INT_ST_S 16 +/** RMT_CH5_RX_END_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ST (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_M (RMT_CH5_RX_END_INT_ST_V << RMT_CH5_RX_END_INT_ST_S) +#define RMT_CH5_RX_END_INT_ST_V 0x00000001U +#define RMT_CH5_RX_END_INT_ST_S 17 +/** RMT_CH6_RX_END_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ST (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_M (RMT_CH6_RX_END_INT_ST_V << RMT_CH6_RX_END_INT_ST_S) +#define RMT_CH6_RX_END_INT_ST_V 0x00000001U +#define RMT_CH6_RX_END_INT_ST_S 18 +/** RMT_CH7_RX_END_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ST (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_M (RMT_CH7_RX_END_INT_ST_V << RMT_CH7_RX_END_INT_ST_S) +#define RMT_CH7_RX_END_INT_ST_V 0x00000001U +#define RMT_CH7_RX_END_INT_ST_S 19 +/** RMT_CH4_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ST (BIT(20)) +#define RMT_CH4_ERR_INT_ST_M (RMT_CH4_ERR_INT_ST_V << RMT_CH4_ERR_INT_ST_S) +#define RMT_CH4_ERR_INT_ST_V 0x00000001U +#define RMT_CH4_ERR_INT_ST_S 20 +/** RMT_CH5_ERR_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ST (BIT(21)) +#define RMT_CH5_ERR_INT_ST_M (RMT_CH5_ERR_INT_ST_V << RMT_CH5_ERR_INT_ST_S) +#define RMT_CH5_ERR_INT_ST_V 0x00000001U +#define RMT_CH5_ERR_INT_ST_S 21 +/** RMT_CH6_ERR_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ST (BIT(22)) +#define RMT_CH6_ERR_INT_ST_M (RMT_CH6_ERR_INT_ST_V << RMT_CH6_ERR_INT_ST_S) +#define RMT_CH6_ERR_INT_ST_V 0x00000001U +#define RMT_CH6_ERR_INT_ST_S 22 +/** RMT_CH7_ERR_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (RMT_CH7_ERR_INT_ST_V << RMT_CH7_ERR_INT_ST_S) +#define RMT_CH7_ERR_INT_ST_V 0x00000001U +#define RMT_CH7_ERR_INT_ST_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_M (RMT_CH4_RX_THR_EVENT_INT_ST_V << RMT_CH4_RX_THR_EVENT_INT_ST_S) +#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_M (RMT_CH5_RX_THR_EVENT_INT_ST_V << RMT_CH5_RX_THR_EVENT_INT_ST_S) +#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_M (RMT_CH6_RX_THR_EVENT_INT_ST_V << RMT_CH6_RX_THR_EVENT_INT_ST_S) +#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_M (RMT_CH7_RX_THR_EVENT_INT_ST_V << RMT_CH7_RX_THR_EVENT_INT_ST_S) +#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_M (RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [29]; default: 0; + * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_M (RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S 29 + +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_TX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ENA (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_M (RMT_CH2_TX_END_INT_ENA_V << RMT_CH2_TX_END_INT_ENA_S) +#define RMT_CH2_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_END_INT_ENA_S 2 +/** RMT_CH3_TX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ENA (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_M (RMT_CH3_TX_END_INT_ENA_V << RMT_CH3_TX_END_INT_ENA_S) +#define RMT_CH3_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (RMT_CH2_TX_THR_EVENT_INT_ENA_V << RMT_CH2_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (RMT_CH3_TX_THR_EVENT_INT_ENA_V << RMT_CH3_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/** RMT_CH2_TX_LOOP_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_M (RMT_CH2_TX_LOOP_INT_ENA_V << RMT_CH2_TX_LOOP_INT_ENA_S) +#define RMT_CH2_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_ENA_S 14 +/** RMT_CH3_TX_LOOP_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_M (RMT_CH3_TX_LOOP_INT_ENA_V << RMT_CH3_TX_LOOP_INT_ENA_S) +#define RMT_CH3_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_ENA_S 15 +/** RMT_CH4_RX_END_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ENA (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_M (RMT_CH4_RX_END_INT_ENA_V << RMT_CH4_RX_END_INT_ENA_S) +#define RMT_CH4_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH4_RX_END_INT_ENA_S 16 +/** RMT_CH5_RX_END_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ENA (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_M (RMT_CH5_RX_END_INT_ENA_V << RMT_CH5_RX_END_INT_ENA_S) +#define RMT_CH5_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH5_RX_END_INT_ENA_S 17 +/** RMT_CH6_RX_END_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ENA (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_M (RMT_CH6_RX_END_INT_ENA_V << RMT_CH6_RX_END_INT_ENA_S) +#define RMT_CH6_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH6_RX_END_INT_ENA_S 18 +/** RMT_CH7_RX_END_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ENA (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_M (RMT_CH7_RX_END_INT_ENA_V << RMT_CH7_RX_END_INT_ENA_S) +#define RMT_CH7_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH7_RX_END_INT_ENA_S 19 +/** RMT_CH4_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ENA (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_M (RMT_CH4_ERR_INT_ENA_V << RMT_CH4_ERR_INT_ENA_S) +#define RMT_CH4_ERR_INT_ENA_V 0x00000001U +#define RMT_CH4_ERR_INT_ENA_S 20 +/** RMT_CH5_ERR_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ENA (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_M (RMT_CH5_ERR_INT_ENA_V << RMT_CH5_ERR_INT_ENA_S) +#define RMT_CH5_ERR_INT_ENA_V 0x00000001U +#define RMT_CH5_ERR_INT_ENA_S 21 +/** RMT_CH6_ERR_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ENA (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_M (RMT_CH6_ERR_INT_ENA_V << RMT_CH6_ERR_INT_ENA_S) +#define RMT_CH6_ERR_INT_ENA_V 0x00000001U +#define RMT_CH6_ERR_INT_ENA_S 22 +/** RMT_CH7_ERR_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (RMT_CH7_ERR_INT_ENA_V << RMT_CH7_ERR_INT_ENA_S) +#define RMT_CH7_ERR_INT_ENA_V 0x00000001U +#define RMT_CH7_ERR_INT_ENA_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (RMT_CH4_RX_THR_EVENT_INT_ENA_V << RMT_CH4_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (RMT_CH5_RX_THR_EVENT_INT_ENA_V << RMT_CH5_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (RMT_CH6_RX_THR_EVENT_INT_ENA_V << RMT_CH6_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (RMT_CH7_RX_THR_EVENT_INT_ENA_V << RMT_CH7_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_M (RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [29]; default: 0; + * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_M (RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S 29 + +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7c) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_TX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ +#define RMT_CH2_TX_END_INT_CLR (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_M (RMT_CH2_TX_END_INT_CLR_V << RMT_CH2_TX_END_INT_CLR_S) +#define RMT_CH2_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_END_INT_CLR_S 2 +/** RMT_CH3_TX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ +#define RMT_CH3_TX_END_INT_CLR (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_M (RMT_CH3_TX_END_INT_CLR_V << RMT_CH3_TX_END_INT_CLR_S) +#define RMT_CH3_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (RMT_CH2_TX_THR_EVENT_INT_CLR_V << RMT_CH2_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (RMT_CH3_TX_THR_EVENT_INT_CLR_V << RMT_CH3_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/** RMT_CH2_TX_LOOP_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ +#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_M (RMT_CH2_TX_LOOP_INT_CLR_V << RMT_CH2_TX_LOOP_INT_CLR_S) +#define RMT_CH2_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_CLR_S 14 +/** RMT_CH3_TX_LOOP_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ +#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_M (RMT_CH3_TX_LOOP_INT_CLR_V << RMT_CH3_TX_LOOP_INT_CLR_S) +#define RMT_CH3_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_CLR_S 15 +/** RMT_CH4_RX_END_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ +#define RMT_CH4_RX_END_INT_CLR (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_M (RMT_CH4_RX_END_INT_CLR_V << RMT_CH4_RX_END_INT_CLR_S) +#define RMT_CH4_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH4_RX_END_INT_CLR_S 16 +/** RMT_CH5_RX_END_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ +#define RMT_CH5_RX_END_INT_CLR (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_M (RMT_CH5_RX_END_INT_CLR_V << RMT_CH5_RX_END_INT_CLR_S) +#define RMT_CH5_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH5_RX_END_INT_CLR_S 17 +/** RMT_CH6_RX_END_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ +#define RMT_CH6_RX_END_INT_CLR (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_M (RMT_CH6_RX_END_INT_CLR_V << RMT_CH6_RX_END_INT_CLR_S) +#define RMT_CH6_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH6_RX_END_INT_CLR_S 18 +/** RMT_CH7_RX_END_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ +#define RMT_CH7_RX_END_INT_CLR (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_M (RMT_CH7_RX_END_INT_CLR_V << RMT_CH7_RX_END_INT_CLR_S) +#define RMT_CH7_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH7_RX_END_INT_CLR_S 19 +/** RMT_CH4_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ +#define RMT_CH4_ERR_INT_CLR (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_M (RMT_CH4_ERR_INT_CLR_V << RMT_CH4_ERR_INT_CLR_S) +#define RMT_CH4_ERR_INT_CLR_V 0x00000001U +#define RMT_CH4_ERR_INT_CLR_S 20 +/** RMT_CH5_ERR_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ +#define RMT_CH5_ERR_INT_CLR (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_M (RMT_CH5_ERR_INT_CLR_V << RMT_CH5_ERR_INT_CLR_S) +#define RMT_CH5_ERR_INT_CLR_V 0x00000001U +#define RMT_CH5_ERR_INT_CLR_S 21 +/** RMT_CH6_ERR_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ +#define RMT_CH6_ERR_INT_CLR (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_M (RMT_CH6_ERR_INT_CLR_V << RMT_CH6_ERR_INT_CLR_S) +#define RMT_CH6_ERR_INT_CLR_V 0x00000001U +#define RMT_CH6_ERR_INT_CLR_S 22 +/** RMT_CH7_ERR_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (RMT_CH7_ERR_INT_CLR_V << RMT_CH7_ERR_INT_CLR_S) +#define RMT_CH7_ERR_INT_CLR_V 0x00000001U +#define RMT_CH7_ERR_INT_CLR_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (RMT_CH4_RX_THR_EVENT_INT_CLR_V << RMT_CH4_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (RMT_CH5_RX_THR_EVENT_INT_CLR_V << RMT_CH5_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (RMT_CH6_RX_THR_EVENT_INT_CLR_V << RMT_CH6_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (RMT_CH7_RX_THR_EVENT_INT_CLR_V << RMT_CH7_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_M (RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_M (RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S 29 + +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 + +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 + +/** RMT_CH2CARRIER_DUTY_REG register + * Channel 2 duty cycle configuration register + */ +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88) +/** RMT_CARRIER_LOW_CH2 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_LOW_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_CH2_M (RMT_CARRIER_LOW_CH2_V << RMT_CARRIER_LOW_CH2_S) +#define RMT_CARRIER_LOW_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH2_S 0 +/** RMT_CARRIER_HIGH_CH2 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_M (RMT_CARRIER_HIGH_CH2_V << RMT_CARRIER_HIGH_CH2_S) +#define RMT_CARRIER_HIGH_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_S 16 + +/** RMT_CH3CARRIER_DUTY_REG register + * Channel 3 duty cycle configuration register + */ +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8c) +/** RMT_CARRIER_LOW_CH3 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_LOW_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_CH3_M (RMT_CARRIER_LOW_CH3_V << RMT_CARRIER_LOW_CH3_S) +#define RMT_CARRIER_LOW_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH3_S 0 +/** RMT_CARRIER_HIGH_CH3 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_M (RMT_CARRIER_HIGH_CH3_V << RMT_CARRIER_HIGH_CH3_S) +#define RMT_CARRIER_HIGH_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_S 16 + +/** RMT_CH4_RX_CARRIER_RM_REG register + * Channel 4 carrier remove register + */ +#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) +/** RMT_CARRIER_LOW_THRES_CH4 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH4_M (RMT_CARRIER_LOW_THRES_CH4_V << RMT_CARRIER_LOW_THRES_CH4_S) +#define RMT_CARRIER_LOW_THRES_CH4_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH4_S 0 +/** RMT_CARRIER_HIGH_THRES_CH4 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH4_M (RMT_CARRIER_HIGH_THRES_CH4_V << RMT_CARRIER_HIGH_THRES_CH4_S) +#define RMT_CARRIER_HIGH_THRES_CH4_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH4_S 16 + +/** RMT_CH5_RX_CARRIER_RM_REG register + * Channel 5 carrier remove register + */ +#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) +/** RMT_CARRIER_LOW_THRES_CH5 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH5_M (RMT_CARRIER_LOW_THRES_CH5_V << RMT_CARRIER_LOW_THRES_CH5_S) +#define RMT_CARRIER_LOW_THRES_CH5_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH5_S 0 +/** RMT_CARRIER_HIGH_THRES_CH5 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH5_M (RMT_CARRIER_HIGH_THRES_CH5_V << RMT_CARRIER_HIGH_THRES_CH5_S) +#define RMT_CARRIER_HIGH_THRES_CH5_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH5_S 16 + +/** RMT_CH6_RX_CARRIER_RM_REG register + * Channel 6 carrier remove register + */ +#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) +/** RMT_CARRIER_LOW_THRES_CH6 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH6_M (RMT_CARRIER_LOW_THRES_CH6_V << RMT_CARRIER_LOW_THRES_CH6_S) +#define RMT_CARRIER_LOW_THRES_CH6_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH6_S 0 +/** RMT_CARRIER_HIGH_THRES_CH6 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH6_M (RMT_CARRIER_HIGH_THRES_CH6_V << RMT_CARRIER_HIGH_THRES_CH6_S) +#define RMT_CARRIER_HIGH_THRES_CH6_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH6_S 16 + +/** RMT_CH7_RX_CARRIER_RM_REG register + * Channel 7 carrier remove register + */ +#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9c) +/** RMT_CARRIER_LOW_THRES_CH7 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH7_M (RMT_CARRIER_LOW_THRES_CH7_V << RMT_CARRIER_LOW_THRES_CH7_S) +#define RMT_CARRIER_LOW_THRES_CH7_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH7_S 0 +/** RMT_CARRIER_HIGH_THRES_CH7 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH7_M (RMT_CARRIER_HIGH_THRES_CH7_V << RMT_CARRIER_HIGH_THRES_CH7_S) +#define RMT_CARRIER_HIGH_THRES_CH7_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH7_S 16 + +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xa0) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 + +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xa4) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 + +/** RMT_CH2_TX_LIM_REG register + * Channel 2 Tx event configuration register + */ +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xa8) +/** RMT_TX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can send out. + */ +#define RMT_TX_LIM_CH2 0x000001FFU +#define RMT_TX_LIM_CH2_M (RMT_TX_LIM_CH2_V << RMT_TX_LIM_CH2_S) +#define RMT_TX_LIM_CH2_V 0x000001FFU +#define RMT_TX_LIM_CH2_S 0 +/** RMT_TX_LOOP_NUM_CH2 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH2 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_M (RMT_TX_LOOP_NUM_CH2_V << RMT_TX_LOOP_NUM_CH2_S) +#define RMT_TX_LOOP_NUM_CH2_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_S 9 +/** RMT_TX_LOOP_CNT_EN_CH2 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (RMT_TX_LOOP_CNT_EN_CH2_V << RMT_TX_LOOP_CNT_EN_CH2_S) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/** RMT_LOOP_COUNT_RESET_CH2 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (RMT_LOOP_COUNT_RESET_CH2_V << RMT_LOOP_COUNT_RESET_CH2_S) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH2_S 20 +/** RMT_LOOP_STOP_EN_CH2 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL2. + */ +#define RMT_LOOP_STOP_EN_CH2 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH2_M (RMT_LOOP_STOP_EN_CH2_V << RMT_LOOP_STOP_EN_CH2_S) +#define RMT_LOOP_STOP_EN_CH2_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH2_S 21 + +/** RMT_CH3_TX_LIM_REG register + * Channel 3 Tx event configuration register + */ +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xac) +/** RMT_TX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can send out. + */ +#define RMT_TX_LIM_CH3 0x000001FFU +#define RMT_TX_LIM_CH3_M (RMT_TX_LIM_CH3_V << RMT_TX_LIM_CH3_S) +#define RMT_TX_LIM_CH3_V 0x000001FFU +#define RMT_TX_LIM_CH3_S 0 +/** RMT_TX_LOOP_NUM_CH3 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH3 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_M (RMT_TX_LOOP_NUM_CH3_V << RMT_TX_LOOP_NUM_CH3_S) +#define RMT_TX_LOOP_NUM_CH3_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_S 9 +/** RMT_TX_LOOP_CNT_EN_CH3 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (RMT_TX_LOOP_CNT_EN_CH3_V << RMT_TX_LOOP_CNT_EN_CH3_S) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/** RMT_LOOP_COUNT_RESET_CH3 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (RMT_LOOP_COUNT_RESET_CH3_V << RMT_LOOP_COUNT_RESET_CH3_S) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH3_S 20 +/** RMT_LOOP_STOP_EN_CH3 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL3. + */ +#define RMT_LOOP_STOP_EN_CH3 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH3_M (RMT_LOOP_STOP_EN_CH3_V << RMT_LOOP_STOP_EN_CH3_S) +#define RMT_LOOP_STOP_EN_CH3_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH3_S 21 + +/** RMT_CH4_RX_LIM_REG register + * Channel 4 Rx event configuration register + */ +#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xb0) +/** RMT_CH4_RX_LIM : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL4 can receive. + */ +#define RMT_CH4_RX_LIM 0x000001FFU +#define RMT_CH4_RX_LIM_M (RMT_CH4_RX_LIM_V << RMT_CH4_RX_LIM_S) +#define RMT_CH4_RX_LIM_V 0x000001FFU +#define RMT_CH4_RX_LIM_S 0 + +/** RMT_CH5_RX_LIM_REG register + * Channel 5 Rx event configuration register + */ +#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xb4) +/** RMT_CH5_RX_LIM : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL5 can receive. + */ +#define RMT_CH5_RX_LIM 0x000001FFU +#define RMT_CH5_RX_LIM_M (RMT_CH5_RX_LIM_V << RMT_CH5_RX_LIM_S) +#define RMT_CH5_RX_LIM_V 0x000001FFU +#define RMT_CH5_RX_LIM_S 0 + +/** RMT_CH6_RX_LIM_REG register + * Channel 6 Rx event configuration register + */ +#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xb8) +/** RMT_CH6_RX_LIM : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL6 can receive. + */ +#define RMT_CH6_RX_LIM 0x000001FFU +#define RMT_CH6_RX_LIM_M (RMT_CH6_RX_LIM_V << RMT_CH6_RX_LIM_S) +#define RMT_CH6_RX_LIM_V 0x000001FFU +#define RMT_CH6_RX_LIM_S 0 + +/** RMT_CH7_RX_LIM_REG register + * Channel 7 Rx event configuration register + */ +#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xbc) +/** RMT_CH7_RX_LIM : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL7 can receive. + */ +#define RMT_CH7_RX_LIM 0x000001FFU +#define RMT_CH7_RX_LIM_M (RMT_CH7_RX_LIM_V << RMT_CH7_RX_LIM_S) +#define RMT_CH7_RX_LIM_V 0x000001FFU +#define RMT_CH7_RX_LIM_S 0 + +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xc0) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) +#define RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_MEM_FORCE_PD_S 2 +/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) +#define RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_MEM_FORCE_PU_S 3 +/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_SCLK_DIV_NUM_M (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S) +#define RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_SCLK_DIV_NUM_S 4 +/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_A 0x0000003FU +#define RMT_SCLK_DIV_A_M (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S) +#define RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_SCLK_DIV_A_S 12 +/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_B 0x0000003FU +#define RMT_SCLK_DIV_B_M (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S) +#define RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_SCLK_DIV_B_S 18 +/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + */ +#define RMT_SCLK_SEL 0x00000003U +#define RMT_SCLK_SEL_M (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S) +#define RMT_SCLK_SEL_V 0x00000003U +#define RMT_SCLK_SEL_S 24 +/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S) +#define RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 + +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xc4) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH2 (BIT(2)) +#define RMT_TX_SIM_CH2_M (RMT_TX_SIM_CH2_V << RMT_TX_SIM_CH2_S) +#define RMT_TX_SIM_CH2_V 0x00000001U +#define RMT_TX_SIM_CH2_S 2 +/** RMT_TX_SIM_CH3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH3 (BIT(3)) +#define RMT_TX_SIM_CH3_M (RMT_TX_SIM_CH3_V << RMT_TX_SIM_CH3_S) +#define RMT_TX_SIM_CH3_V 0x00000001U +#define RMT_TX_SIM_CH3_S 3 +/** RMT_TX_SIM_EN : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(4)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 4 + +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xc8) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 +/** RMT_REF_CNT_RST_CH4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ +#define RMT_REF_CNT_RST_CH4 (BIT(4)) +#define RMT_REF_CNT_RST_CH4_M (RMT_REF_CNT_RST_CH4_V << RMT_REF_CNT_RST_CH4_S) +#define RMT_REF_CNT_RST_CH4_V 0x00000001U +#define RMT_REF_CNT_RST_CH4_S 4 +/** RMT_REF_CNT_RST_CH5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ +#define RMT_REF_CNT_RST_CH5 (BIT(5)) +#define RMT_REF_CNT_RST_CH5_M (RMT_REF_CNT_RST_CH5_V << RMT_REF_CNT_RST_CH5_S) +#define RMT_REF_CNT_RST_CH5_V 0x00000001U +#define RMT_REF_CNT_RST_CH5_S 5 +/** RMT_REF_CNT_RST_CH6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ +#define RMT_REF_CNT_RST_CH6 (BIT(6)) +#define RMT_REF_CNT_RST_CH6_M (RMT_REF_CNT_RST_CH6_V << RMT_REF_CNT_RST_CH6_S) +#define RMT_REF_CNT_RST_CH6_V 0x00000001U +#define RMT_REF_CNT_RST_CH6_S 6 +/** RMT_REF_CNT_RST_CH7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ +#define RMT_REF_CNT_RST_CH7 (BIT(7)) +#define RMT_REF_CNT_RST_CH7_M (RMT_REF_CNT_RST_CH7_V << RMT_REF_CNT_RST_CH7_S) +#define RMT_REF_CNT_RST_CH7_V 0x00000001U +#define RMT_REF_CNT_RST_CH7_S 7 + +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_DATE : R/W; bitpos: [27:0]; default: 35655953; + * This is the version register. + */ +#define RMT_DATE 0x0FFFFFFFU +#define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) +#define RMT_DATE_V 0x0FFFFFFFU +#define RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rmt_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/rmt_struct.h new file mode 100644 index 0000000000..b6d21840aa --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rmt_struct.h @@ -0,0 +1,1082 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata: 32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +typedef union { + struct { + /** chmdata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ + uint32_t chmdata: 32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn: 1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn: 1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn: 1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn: 1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn: 1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn: 1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn: 1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn: 1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn: 8; + /** mem_size_chn : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn: 4; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn: 1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn: 1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * 1'h0: add carrier wave on low level. + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn: 1; + /** afifo_rst_chn : WT; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chn: 1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn: 1; + /** dma_access_en_chn : WT; bitpos: [25]; default: 0; + * DMA access control bit for CHANNELn (only CHANNEL3 has this control bit) + */ + uint32_t dma_access_en_chn: 1; + uint32_t reserved_26: 6; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm: 8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm: 15; + /** dma_access_en_m : WT; bitpos: [23]; default: 0; + * DMA access control bit for CHANNELm (only channel7 has this control bit) + */ + uint32_t dma_access_en_chm: 1; + /** mem_size_chm : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm: 4; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm: 1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * 1'h0: add carrier wave on low level. + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm: 1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm: 1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm: 1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * 1'h1: Receiver is using the ram. + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm: 1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm: 1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm: 8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm: 1; + /** afifo_rst_chm : WT; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chm: 1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm: 1; + uint32_t reserved_16: 16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm: 16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm: 16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask: 1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on: 1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd: 1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu: 1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num: 8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a: 6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b: 6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + */ + uint32_t sclk_sel: 2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active: 1; + uint32_t reserved_27: 4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0: 1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1: 1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2: 1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3: 1; + /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ + uint32_t ref_cnt_rst_ch4: 1; + /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ + uint32_t ref_cnt_rst_ch5: 1; + /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ + uint32_t ref_cnt_rst_ch6: 1; + /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ + uint32_t ref_cnt_rst_ch7: 1; + uint32_t reserved_8: 24; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn: 10; + uint32_t reserved_10: 1; + /** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn: 10; + uint32_t reserved_21: 1; + /** state_chn : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn: 3; + /** mem_empty_chn : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn: 1; + /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn: 1; + uint32_t reserved_27: 5; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm: 10; + uint32_t reserved_10: 1; + /** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm: 10; + uint32_t reserved_21: 1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm: 3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm: 1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm: 1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm: 1; + uint32_t reserved_28: 4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw: 1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw: 1; + /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ + uint32_t ch2_tx_end_int_raw: 1; + /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ + uint32_t ch3_tx_end_int_raw: 1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw: 1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw: 1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw: 1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw: 1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw: 1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw: 1; + /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch2_tx_thr_event_int_raw: 1; + /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch3_tx_thr_event_int_raw: 1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw: 1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw: 1; + /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch2_tx_loop_int_raw: 1; + /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch3_tx_loop_int_raw: 1; + /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ + uint32_t ch4_rx_end_int_raw: 1; + /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ + uint32_t ch5_rx_end_int_raw: 1; + /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ + uint32_t ch6_rx_end_int_raw: 1; + /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ + uint32_t ch7_rx_end_int_raw: 1; + /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ + uint32_t ch4_err_int_raw: 1; + /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ + uint32_t ch5_err_int_raw: 1; + /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ + uint32_t ch6_err_int_raw: 1; + /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ + uint32_t ch7_err_int_raw: 1; + /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch4_rx_thr_event_int_raw: 1; + /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch5_rx_thr_event_int_raw: 1; + /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch6_rx_thr_event_int_raw: 1; + /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch7_rx_thr_event_int_raw: 1; + /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + */ + uint32_t ch3_dma_access_fail_int_raw: 1; + /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + */ + uint32_t ch7_dma_access_fail_int_raw: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st: 1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st: 1; + /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_st: 1; + /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_st: 1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_st: 1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_st: 1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_st: 1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_st: 1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st: 1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st: 1; + /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_st: 1; + /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_st: 1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st: 1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st: 1; + /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_st: 1; + /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_st: 1; + /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_st: 1; + /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_st: 1; + /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_st: 1; + /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_st: 1; + /** ch4_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_st: 1; + /** ch5_err_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_st: 1; + /** ch6_err_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_st: 1; + /** ch7_err_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_st: 1; + /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_st: 1; + /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_st: 1; + /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_st: 1; + /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_st: 1; + /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_st: 1; + /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0; + * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_st: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena: 1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena: 1; + /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_ena: 1; + /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_ena: 1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_ena: 1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_ena: 1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_ena: 1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_ena: 1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena: 1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena: 1; + /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_ena: 1; + /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_ena: 1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena: 1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena: 1; + /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_ena: 1; + /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_ena: 1; + /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_ena: 1; + /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_ena: 1; + /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_ena: 1; + /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_ena: 1; + /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_ena: 1; + /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_ena: 1; + /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_ena: 1; + /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_ena: 1; + /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_ena: 1; + /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_ena: 1; + /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_ena: 1; + /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_ena: 1; + /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_ena: 1; + /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0; + * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_ena: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr: 1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr: 1; + /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ + uint32_t ch2_tx_end_int_clr: 1; + /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ + uint32_t ch3_tx_end_int_clr: 1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr: 1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr: 1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr: 1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr: 1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr: 1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr: 1; + /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_tx_thr_event_int_clr: 1; + /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_tx_thr_event_int_clr: 1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr: 1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr: 1; + /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ + uint32_t ch2_tx_loop_int_clr: 1; + /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ + uint32_t ch3_tx_loop_int_clr: 1; + /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ + uint32_t ch4_rx_end_int_clr: 1; + /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ + uint32_t ch5_rx_end_int_clr: 1; + /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ + uint32_t ch6_rx_end_int_clr: 1; + /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ + uint32_t ch7_rx_end_int_clr: 1; + /** ch4_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ + uint32_t ch4_err_int_clr: 1; + /** ch5_err_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ + uint32_t ch5_err_int_clr: 1; + /** ch6_err_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ + uint32_t ch6_err_int_clr: 1; + /** ch7_err_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ + uint32_t ch7_err_int_clr: 1; + /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch4_rx_thr_event_int_clr: 1; + /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch5_rx_thr_event_int_clr: 1; + /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch6_rx_thr_event_int_clr: 1; + /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch7_rx_thr_event_int_clr: 1; + /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch3_dma_access_fail_int_clr: 1; + /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch7_dma_access_fail_int_clr: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_clr_reg_t; + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn: 16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn: 16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn: 9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn: 10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn: 1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn: 1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn: 1; + uint32_t reserved_22: 10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0: 1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1: 1; + /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch2: 1; + /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch3: 1; + /** tx_sim_en : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** rx_lim_chm : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t rx_lim_chm: 9; + uint32_t reserved_9: 23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655953; + * This is the version register. + */ + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} rmt_date_reg_t; + +typedef struct rmt_dev_t { + volatile rmt_chndata_reg_t chndata[4]; + volatile rmt_chmdata_reg_t chmdata[4]; + volatile rmt_chnconf0_reg_t chnconf0[4]; + volatile struct { + rmt_chmconf0_reg_t conf0; + rmt_chmconf1_reg_t conf1; + } chmconf[4]; + volatile rmt_chnstatus_reg_t chnstatus[4]; + volatile rmt_chmstatus_reg_t chmstatus[4]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rsa_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/rsa_reg.h new file mode 100644 index 0000000000..c100dbdbaa --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rsa_reg.h @@ -0,0 +1,212 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RSA_M_MEM register + * Represents M + */ +#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0) +#define RSA_M_MEM_SIZE_BYTES 16 + +/** RSA_Z_MEM register + * Represents Z + */ +#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200) +#define RSA_Z_MEM_SIZE_BYTES 16 + +/** RSA_Y_MEM register + * Represents Y + */ +#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400) +#define RSA_Y_MEM_SIZE_BYTES 16 + +/** RSA_X_MEM register + * Represents X + */ +#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600) +#define RSA_X_MEM_SIZE_BYTES 16 + +/** RSA_M_PRIME_REG register + * Represents M' + */ +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) +/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Represents M' + */ +#define RSA_M_PRIME 0xFFFFFFFFU +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFFU +#define RSA_M_PRIME_S 0 + +/** RSA_MODE_REG register + * Configures RSA length + */ +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) +/** RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ +#define RSA_MODE 0x0000007FU +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007FU +#define RSA_MODE_S 0 + +/** RSA_QUERY_CLEAN_REG register + * RSA initialization status + */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) +/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * 0: Not complete + * 1: Completed + */ +#define RSA_QUERY_CLEAN (BIT(0)) +#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) +#define RSA_QUERY_CLEAN_V 0x00000001U +#define RSA_QUERY_CLEAN_S 0 + +/** RSA_SET_START_MODEXP_REG register + * Starts modular exponentiation + */ +#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) +/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; + * Configures whether or not to starts the modular exponentiation. + * 0: No effect + * 1: Start + */ +#define RSA_SET_START_MODEXP (BIT(0)) +#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) +#define RSA_SET_START_MODEXP_V 0x00000001U +#define RSA_SET_START_MODEXP_S 0 + +/** RSA_SET_START_MODMULT_REG register + * Starts modular multiplication + */ +#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) +/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; + * Configures whether or not to start the modular multiplication. + * 0: No effect + * 1: Start + */ +#define RSA_SET_START_MODMULT (BIT(0)) +#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) +#define RSA_SET_START_MODMULT_V 0x00000001U +#define RSA_SET_START_MODMULT_S 0 + +/** RSA_SET_START_MULT_REG register + * Starts multiplication + */ +#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) +/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; + * Configures whether or not to start the multiplication. + * 0: No effect + * 1: Start + */ +#define RSA_SET_START_MULT (BIT(0)) +#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) +#define RSA_SET_START_MULT_V 0x00000001U +#define RSA_SET_START_MULT_S 0 + +/** RSA_QUERY_IDLE_REG register + * Represents the RSA status + */ +#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) +/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * 0: Busy + * 1: Idle + */ +#define RSA_QUERY_IDLE (BIT(0)) +#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) +#define RSA_QUERY_IDLE_V 0x00000001U +#define RSA_QUERY_IDLE_S 0 + +/** RSA_INT_CLR_REG register + * Clears RSA interrupt + */ +#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) +/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001U +#define RSA_CLEAR_INTERRUPT_S 0 + +/** RSA_CONSTANT_TIME_REG register + * Configures the constant_time option + */ +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * 0: Acceleration + * 1: No acceleration (default) + */ +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001U +#define RSA_CONSTANT_TIME_S 0 + +/** RSA_SEARCH_ENABLE_REG register + * Configures the search option + */ +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Configures the search option. + * 0: No acceleration (default) + * 1: Acceleration + * This option should be used together with RSA_SEARCH_POS_REG. + */ +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001U +#define RSA_SEARCH_ENABLE_S 0 + +/** RSA_SEARCH_POS_REG register + * Configures the search position + */ +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) +/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high. + */ +#define RSA_SEARCH_POS 0x00000FFFU +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFFU +#define RSA_SEARCH_POS_S 0 + +/** RSA_INT_ENA_REG register + * Enables the RSA interrupt + */ +#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) +/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ +#define RSA_INT_ENA (BIT(0)) +#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) +#define RSA_INT_ENA_V 0x00000001U +#define RSA_INT_ENA_S 0 + +/** RSA_DATE_REG register + * Version control register + */ +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) +/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ +#define RSA_DATE 0x3FFFFFFFU +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFFU +#define RSA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rsa_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/rsa_struct.h new file mode 100644 index 0000000000..44f1d9ea58 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rsa_struct.h @@ -0,0 +1,252 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory */ + +/** Group: Control / Configuration Registers */ +/** Type of m_prime register + * Represents M' + */ +typedef union { + struct { + /** m_prime : R/W; bitpos: [31:0]; default: 0; + * Represents M' + */ + uint32_t m_prime:32; + }; + uint32_t val; +} rsa_m_prime_reg_t; + +/** Type of mode register + * Configures RSA length + */ +typedef union { + struct { + /** mode : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ + uint32_t mode:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} rsa_mode_reg_t; + +/** Type of set_start_modexp register + * Starts modular exponentiation + */ +typedef union { + struct { + /** set_start_modexp : WT; bitpos: [0]; default: 0; + * Configures whether or not to starts the modular exponentiation. + * 0: No effect + * 1: Start + */ + uint32_t set_start_modexp:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modexp_reg_t; + +/** Type of set_start_modmult register + * Starts modular multiplication + */ +typedef union { + struct { + /** set_start_modmult : WT; bitpos: [0]; default: 0; + * Configures whether or not to start the modular multiplication. + * 0: No effect + * 1: Start + */ + uint32_t set_start_modmult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modmult_reg_t; + +/** Type of set_start_mult register + * Starts multiplication + */ +typedef union { + struct { + /** set_start_mult : WT; bitpos: [0]; default: 0; + * Configures whether or not to start the multiplication. + * 0: No effect + * 1: Start + */ + uint32_t set_start_mult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_mult_reg_t; + +/** Type of query_idle register + * Represents the RSA status + */ +typedef union { + struct { + /** query_idle : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * 0: Busy + * 1: Idle + */ + uint32_t query_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_idle_reg_t; + +/** Type of constant_time register + * Configures the constant_time option + */ +typedef union { + struct { + /** constant_time : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * 0: Acceleration + * 1: No acceleration (default) + */ + uint32_t constant_time:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_constant_time_reg_t; + +/** Type of search_enable register + * Configures the search option + */ +typedef union { + struct { + /** search_enable : R/W; bitpos: [0]; default: 0; + * Configures the search option. + * 0: No acceleration (default) + * 1: Acceleration + * This option should be used together with RSA_SEARCH_POS_REG. + */ + uint32_t search_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_search_enable_reg_t; + +/** Type of search_pos register + * Configures the search position + */ +typedef union { + struct { + /** search_pos : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high. + */ + uint32_t search_pos:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} rsa_search_pos_reg_t; + + +/** Group: Status Register */ +/** Type of query_clean register + * RSA initialization status + */ +typedef union { + struct { + /** query_clean : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * 0: Not complete + * 1: Completed + */ + uint32_t query_clean:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_clean_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_clr register + * Clears RSA interrupt + */ +typedef union { + struct { + /** clear_interrupt : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_clr_reg_t; + +/** Type of int_ena register + * Enables the RSA interrupt + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_ena_reg_t; + + +/** Group: Version Control Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} rsa_date_reg_t; + + +typedef struct { + volatile uint32_t m[4]; + uint32_t reserved_010[124]; + volatile uint32_t z[4]; + uint32_t reserved_210[124]; + volatile uint32_t y[4]; + uint32_t reserved_410[124]; + volatile uint32_t x[4]; + uint32_t reserved_610[124]; + volatile rsa_m_prime_reg_t m_prime; + volatile rsa_mode_reg_t mode; + volatile rsa_query_clean_reg_t query_clean; + volatile rsa_set_start_modexp_reg_t set_start_modexp; + volatile rsa_set_start_modmult_reg_t set_start_modmult; + volatile rsa_set_start_mult_reg_t set_start_mult; + volatile rsa_query_idle_reg_t query_idle; + volatile rsa_int_clr_reg_t int_clr; + volatile rsa_constant_time_reg_t constant_time; + volatile rsa_search_enable_reg_t search_enable; + volatile rsa_search_pos_reg_t search_pos; + volatile rsa_int_ena_reg_t int_ena; + volatile rsa_date_reg_t date; +} rsa_dev_t; + +extern rsa_dev_t RSA; + +#ifndef __cplusplus +_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_reg.h new file mode 100644 index 0000000000..dbf69d31a2 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_reg.h @@ -0,0 +1,578 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RTCLOCKCALI_LP_CALI_TIMER_REG register + * need_des + */ +#define RTCLOCKCALI_LP_CALI_TIMER_REG (DR_REG_RTCLOCKCALI_BASE + 0x0) +/** RTCLOCKCALI_TIMER_TARGET : R/W; bitpos: [29:0]; default: 4095; + * need_des + */ +#define RTCLOCKCALI_TIMER_TARGET 0x3FFFFFFFU +#define RTCLOCKCALI_TIMER_TARGET_M (RTCLOCKCALI_TIMER_TARGET_V << RTCLOCKCALI_TIMER_TARGET_S) +#define RTCLOCKCALI_TIMER_TARGET_V 0x3FFFFFFFU +#define RTCLOCKCALI_TIMER_TARGET_S 0 +/** RTCLOCKCALI_TIMER_STOP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define RTCLOCKCALI_TIMER_STOP (BIT(30)) +#define RTCLOCKCALI_TIMER_STOP_M (RTCLOCKCALI_TIMER_STOP_V << RTCLOCKCALI_TIMER_STOP_S) +#define RTCLOCKCALI_TIMER_STOP_V 0x00000001U +#define RTCLOCKCALI_TIMER_STOP_S 30 +/** RTCLOCKCALI_TIMER_START : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTCLOCKCALI_TIMER_START (BIT(31)) +#define RTCLOCKCALI_TIMER_START_M (RTCLOCKCALI_TIMER_START_V << RTCLOCKCALI_TIMER_START_S) +#define RTCLOCKCALI_TIMER_START_V 0x00000001U +#define RTCLOCKCALI_TIMER_START_S 31 + +/** RTCLOCKCALI_RTCCALICFG_SLOW_REG register + * RTC calibration configure register + */ +#define RTCLOCKCALI_RTCCALICFG_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x4) +/** RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW (BIT(12)) +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_M (RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S 12 +/** RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW 0x00000003U +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_M (RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V 0x00000003U +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S 13 +/** RTCLOCKCALI_RTC_CALI_RDY_SLOW : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define RTCLOCKCALI_RTC_CALI_RDY_SLOW (BIT(15)) +#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_M (RTCLOCKCALI_RTC_CALI_RDY_SLOW_V << RTCLOCKCALI_RTC_CALI_RDY_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_S 15 +/** RTCLOCKCALI_RTC_CALI_MAX_SLOW : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define RTCLOCKCALI_RTC_CALI_MAX_SLOW 0x00007FFFU +#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_M (RTCLOCKCALI_RTC_CALI_MAX_SLOW_V << RTCLOCKCALI_RTC_CALI_MAX_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_V 0x00007FFFU +#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_S 16 +/** RTCLOCKCALI_RTC_CALI_START_SLOW : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define RTCLOCKCALI_RTC_CALI_START_SLOW (BIT(31)) +#define RTCLOCKCALI_RTC_CALI_START_SLOW_M (RTCLOCKCALI_RTC_CALI_START_SLOW_V << RTCLOCKCALI_RTC_CALI_START_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_START_SLOW_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_START_SLOW_S 31 + +/** RTCLOCKCALI_RTCCALICFG_FAST_REG register + * RTC calibration configure register + */ +#define RTCLOCKCALI_RTCCALICFG_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x8) +/** RTCLOCKCALI_FOSC_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * fosc clock divider number + */ +#define RTCLOCKCALI_FOSC_DIV_NUM 0x000000FFU +#define RTCLOCKCALI_FOSC_DIV_NUM_M (RTCLOCKCALI_FOSC_DIV_NUM_V << RTCLOCKCALI_FOSC_DIV_NUM_S) +#define RTCLOCKCALI_FOSC_DIV_NUM_V 0x000000FFU +#define RTCLOCKCALI_FOSC_DIV_NUM_S 4 +/** RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST (BIT(12)) +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_M (RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S) +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S 12 +/** RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST 0x00000003U +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_M (RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S) +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V 0x00000003U +#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S 13 +/** RTCLOCKCALI_RTC_CALI_RDY_FAST : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define RTCLOCKCALI_RTC_CALI_RDY_FAST (BIT(15)) +#define RTCLOCKCALI_RTC_CALI_RDY_FAST_M (RTCLOCKCALI_RTC_CALI_RDY_FAST_V << RTCLOCKCALI_RTC_CALI_RDY_FAST_S) +#define RTCLOCKCALI_RTC_CALI_RDY_FAST_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_RDY_FAST_S 15 +/** RTCLOCKCALI_RTC_CALI_MAX_FAST : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define RTCLOCKCALI_RTC_CALI_MAX_FAST 0x00007FFFU +#define RTCLOCKCALI_RTC_CALI_MAX_FAST_M (RTCLOCKCALI_RTC_CALI_MAX_FAST_V << RTCLOCKCALI_RTC_CALI_MAX_FAST_S) +#define RTCLOCKCALI_RTC_CALI_MAX_FAST_V 0x00007FFFU +#define RTCLOCKCALI_RTC_CALI_MAX_FAST_S 16 +/** RTCLOCKCALI_RTC_CALI_START_FAST : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define RTCLOCKCALI_RTC_CALI_START_FAST (BIT(31)) +#define RTCLOCKCALI_RTC_CALI_START_FAST_M (RTCLOCKCALI_RTC_CALI_START_FAST_V << RTCLOCKCALI_RTC_CALI_START_FAST_S) +#define RTCLOCKCALI_RTC_CALI_START_FAST_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_START_FAST_S 31 + +/** RTCLOCKCALI_RTCCALICFG1_SLOW_REG register + * RTC calibration configure1 register + */ +#define RTCLOCKCALI_RTCCALICFG1_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0xc) +/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW (BIT(0)) +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_M (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S 0 +/** RTCLOCKCALI_RTC_CALI_VALUE_SLOW : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_M (RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V << RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S) +#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S 7 + +/** RTCLOCKCALI_RTCCALICFG1_FAST_REG register + * RTC calibration configure1 register + */ +#define RTCLOCKCALI_RTCCALICFG1_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x10) +/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST (BIT(0)) +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_M (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S) +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S 0 +/** RTCLOCKCALI_RTC_CALI_VALUE_FAST : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define RTCLOCKCALI_RTC_CALI_VALUE_FAST 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_M (RTCLOCKCALI_RTC_CALI_VALUE_FAST_V << RTCLOCKCALI_RTC_CALI_VALUE_FAST_S) +#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_V 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_S 7 + +/** RTCLOCKCALI_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define RTCLOCKCALI_RTCCALICFG2_REG (DR_REG_RTCLOCKCALI_BASE + 0x14) +/** RTCLOCKCALI_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define RTCLOCKCALI_RTC_CALI_TIMEOUT (BIT(0)) +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_S) +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_V 0x00000001U +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_S 0 +/** RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S) +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_M (RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S) +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S 7 + +/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG register + * RTC slow clock dfreq high limit. + */ +#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x18) +/** RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW : R/W; bitpos: [7:0]; default: 16; + * When rtc_cali_value upper/lower than reg_high/low_limit +/- + * reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step. + */ +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW 0x000000FFU +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_M (RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S) +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V 0x000000FFU +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S 0 +/** RTCLOCKCALI_HIGH_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 267; + * when rtc_cali_value upper than reg_high_limit,frequency of osc will increase . + */ +#define RTCLOCKCALI_HIGH_LIMIT_SLOW 0x00FFFFFFU +#define RTCLOCKCALI_HIGH_LIMIT_SLOW_M (RTCLOCKCALI_HIGH_LIMIT_SLOW_V << RTCLOCKCALI_HIGH_LIMIT_SLOW_S) +#define RTCLOCKCALI_HIGH_LIMIT_SLOW_V 0x00FFFFFFU +#define RTCLOCKCALI_HIGH_LIMIT_SLOW_S 8 + +/** RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG register + * RTC slow clock dfreq low limit. + */ +#define RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x1c) +/** RTCLOCKCALI_LOW_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 266; + * when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease . + */ +#define RTCLOCKCALI_LOW_LIMIT_SLOW 0x00FFFFFFU +#define RTCLOCKCALI_LOW_LIMIT_SLOW_M (RTCLOCKCALI_LOW_LIMIT_SLOW_V << RTCLOCKCALI_LOW_LIMIT_SLOW_S) +#define RTCLOCKCALI_LOW_LIMIT_SLOW_V 0x00FFFFFFU +#define RTCLOCKCALI_LOW_LIMIT_SLOW_S 8 + +/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG register + * RTC fast clock dfreq high limit. + */ +#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x20) +/** RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST : R/W; bitpos: [7:0]; default: 16; + * When rtc_cali_value upper/lower than reg_high/low_limit +/- + * reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step. + */ +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST 0x000000FFU +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_M (RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S) +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V 0x000000FFU +#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S 0 +/** RTCLOCKCALI_HIGH_LIMIT_FAST : R/W; bitpos: [31:8]; default: 267; + * when rtc_cali_value upper than reg_high_limit,frequency of osc will increase . + */ +#define RTCLOCKCALI_HIGH_LIMIT_FAST 0x00FFFFFFU +#define RTCLOCKCALI_HIGH_LIMIT_FAST_M (RTCLOCKCALI_HIGH_LIMIT_FAST_V << RTCLOCKCALI_HIGH_LIMIT_FAST_S) +#define RTCLOCKCALI_HIGH_LIMIT_FAST_V 0x00FFFFFFU +#define RTCLOCKCALI_HIGH_LIMIT_FAST_S 8 + +/** RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG register + * RTC fast clock dfreq low limit. + */ +#define RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x24) +/** RTCLOCKCALI_LOW_LIMIT_FAST : R/W; bitpos: [31:8]; default: 266; + * when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease . + */ +#define RTCLOCKCALI_LOW_LIMIT_FAST 0x00FFFFFFU +#define RTCLOCKCALI_LOW_LIMIT_FAST_M (RTCLOCKCALI_LOW_LIMIT_FAST_V << RTCLOCKCALI_LOW_LIMIT_FAST_S) +#define RTCLOCKCALI_LOW_LIMIT_FAST_V 0x00FFFFFFU +#define RTCLOCKCALI_LOW_LIMIT_FAST_S 8 + +/** RTCLOCKCALI_DFREQ_CONF2_REG register + * RTC DFREQ CONF2 + */ +#define RTCLOCKCALI_DFREQ_CONF2_REG (DR_REG_RTCLOCKCALI_BASE + 0x28) +/** RTCLOCKCALI_DREQ_UPDATE : WT; bitpos: [0]; default: 0; + * need_des + */ +#define RTCLOCKCALI_DREQ_UPDATE (BIT(0)) +#define RTCLOCKCALI_DREQ_UPDATE_M (RTCLOCKCALI_DREQ_UPDATE_V << RTCLOCKCALI_DREQ_UPDATE_S) +#define RTCLOCKCALI_DREQ_UPDATE_V 0x00000001U +#define RTCLOCKCALI_DREQ_UPDATE_S 0 +/** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0; + * Initialize the value of 32K OSC dfreq setting. + */ +#define RTCLOCKCALI_DREQ_INIT_32K (BIT(2)) +#define RTCLOCKCALI_DREQ_INIT_32K_M (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S) +#define RTCLOCKCALI_DREQ_INIT_32K_V 0x00000001U +#define RTCLOCKCALI_DREQ_INIT_32K_S 2 +/** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0; + * Initialize the value of FOSC dfreq setting. + */ +#define RTCLOCKCALI_DREQ_INIT_FOSC (BIT(3)) +#define RTCLOCKCALI_DREQ_INIT_FOSC_M (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S) +#define RTCLOCKCALI_DREQ_INIT_FOSC_V 0x00000001U +#define RTCLOCKCALI_DREQ_INIT_FOSC_S 3 +/** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0; + * Initialize the value of SOSC dfreq setting. + */ +#define RTCLOCKCALI_DREQ_INIT_SOSC (BIT(4)) +#define RTCLOCKCALI_DREQ_INIT_SOSC_M (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S) +#define RTCLOCKCALI_DREQ_INIT_SOSC_V 0x00000001U +#define RTCLOCKCALI_DREQ_INIT_SOSC_S 4 +/** RTCLOCKCALI_32K_DFREQ_SEL : R/W; bitpos: [5]; default: 0; + * 1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled + * by register from system-register bank + */ +#define RTCLOCKCALI_32K_DFREQ_SEL (BIT(5)) +#define RTCLOCKCALI_32K_DFREQ_SEL_M (RTCLOCKCALI_32K_DFREQ_SEL_V << RTCLOCKCALI_32K_DFREQ_SEL_S) +#define RTCLOCKCALI_32K_DFREQ_SEL_V 0x00000001U +#define RTCLOCKCALI_32K_DFREQ_SEL_S 5 +/** RTCLOCKCALI_FOSC_DFREQ_SEL : R/W; bitpos: [6]; default: 0; + * 1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled + * by register from system-register bank + */ +#define RTCLOCKCALI_FOSC_DFREQ_SEL (BIT(6)) +#define RTCLOCKCALI_FOSC_DFREQ_SEL_M (RTCLOCKCALI_FOSC_DFREQ_SEL_V << RTCLOCKCALI_FOSC_DFREQ_SEL_S) +#define RTCLOCKCALI_FOSC_DFREQ_SEL_V 0x00000001U +#define RTCLOCKCALI_FOSC_DFREQ_SEL_S 6 +/** RTCLOCKCALI_SOSC_DFREQ_SEL : R/W; bitpos: [7]; default: 0; + * 1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled + * by register from system-register bank + */ +#define RTCLOCKCALI_SOSC_DFREQ_SEL (BIT(7)) +#define RTCLOCKCALI_SOSC_DFREQ_SEL_M (RTCLOCKCALI_SOSC_DFREQ_SEL_V << RTCLOCKCALI_SOSC_DFREQ_SEL_S) +#define RTCLOCKCALI_SOSC_DFREQ_SEL_V 0x00000001U +#define RTCLOCKCALI_SOSC_DFREQ_SEL_S 7 +/** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1; + * Frequency fine step. + */ +#define RTCLOCKCALI_FINE_STEP 0x000000FFU +#define RTCLOCKCALI_FINE_STEP_M (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S) +#define RTCLOCKCALI_FINE_STEP_V 0x000000FFU +#define RTCLOCKCALI_FINE_STEP_S 8 +/** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8; + * Frequency coarse step,use to decrease calibration time. + */ +#define RTCLOCKCALI_COARSE_STEP_FAST 0x000000FFU +#define RTCLOCKCALI_COARSE_STEP_FAST_M (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S) +#define RTCLOCKCALI_COARSE_STEP_FAST_V 0x000000FFU +#define RTCLOCKCALI_COARSE_STEP_FAST_S 16 +/** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8; + * Frequency coarse step,use to decrease calibration time. + */ +#define RTCLOCKCALI_COARSE_STEP_SLOW 0x000000FFU +#define RTCLOCKCALI_COARSE_STEP_SLOW_M (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S) +#define RTCLOCKCALI_COARSE_STEP_SLOW_V 0x000000FFU +#define RTCLOCKCALI_COARSE_STEP_SLOW_S 24 + +/** RTCLOCKCALI_CALI_EN_REG register + * Configure register. + */ +#define RTCLOCKCALI_CALI_EN_REG (DR_REG_RTCLOCKCALI_BASE + 0x2c) +/** RTCLOCKCALI_CALI_EN_32K : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define RTCLOCKCALI_CALI_EN_32K (BIT(0)) +#define RTCLOCKCALI_CALI_EN_32K_M (RTCLOCKCALI_CALI_EN_32K_V << RTCLOCKCALI_CALI_EN_32K_S) +#define RTCLOCKCALI_CALI_EN_32K_V 0x00000001U +#define RTCLOCKCALI_CALI_EN_32K_S 0 +/** RTCLOCKCALI_CALI_EN_FOSC : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define RTCLOCKCALI_CALI_EN_FOSC (BIT(1)) +#define RTCLOCKCALI_CALI_EN_FOSC_M (RTCLOCKCALI_CALI_EN_FOSC_V << RTCLOCKCALI_CALI_EN_FOSC_S) +#define RTCLOCKCALI_CALI_EN_FOSC_V 0x00000001U +#define RTCLOCKCALI_CALI_EN_FOSC_S 1 +/** RTCLOCKCALI_CALI_EN_SOSC : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define RTCLOCKCALI_CALI_EN_SOSC (BIT(2)) +#define RTCLOCKCALI_CALI_EN_SOSC_M (RTCLOCKCALI_CALI_EN_SOSC_V << RTCLOCKCALI_CALI_EN_SOSC_S) +#define RTCLOCKCALI_CALI_EN_SOSC_V 0x00000001U +#define RTCLOCKCALI_CALI_EN_SOSC_S 2 + +/** RTCLOCKCALI_DFREQ_VALUE_REG register + * Configure register. + */ +#define RTCLOCKCALI_DFREQ_VALUE_REG (DR_REG_RTCLOCKCALI_BASE + 0x30) +/** RTCLOCKCALI_DREQ_32K : RO; bitpos: [11:2]; default: 172; + * The value of dfreq num of 32k. + */ +#define RTCLOCKCALI_DREQ_32K 0x000003FFU +#define RTCLOCKCALI_DREQ_32K_M (RTCLOCKCALI_DREQ_32K_V << RTCLOCKCALI_DREQ_32K_S) +#define RTCLOCKCALI_DREQ_32K_V 0x000003FFU +#define RTCLOCKCALI_DREQ_32K_S 2 +/** RTCLOCKCALI_DREQ_FOSC : RO; bitpos: [21:12]; default: 512; + * The value of dfreq num of FOSC. + */ +#define RTCLOCKCALI_DREQ_FOSC 0x000003FFU +#define RTCLOCKCALI_DREQ_FOSC_M (RTCLOCKCALI_DREQ_FOSC_V << RTCLOCKCALI_DREQ_FOSC_S) +#define RTCLOCKCALI_DREQ_FOSC_V 0x000003FFU +#define RTCLOCKCALI_DREQ_FOSC_S 12 +/** RTCLOCKCALI_DREQ_SOSC : RO; bitpos: [31:22]; default: 512; + * The value of dfreq num of SOSC. + */ +#define RTCLOCKCALI_DREQ_SOSC 0x000003FFU +#define RTCLOCKCALI_DREQ_SOSC_M (RTCLOCKCALI_DREQ_SOSC_V << RTCLOCKCALI_DREQ_SOSC_S) +#define RTCLOCKCALI_DREQ_SOSC_V 0x000003FFU +#define RTCLOCKCALI_DREQ_SOSC_S 22 + +/** RTCLOCKCALI_BYPASS_REG register + * Configure register. + */ +#define RTCLOCKCALI_BYPASS_REG (DR_REG_RTCLOCKCALI_BASE + 0x34) +/** RTCLOCKCALI_HP_SLEEP_AUTOCALI : R/W; bitpos: [30]; default: 0; + * 1:Chip begin to calibrating,when into hp_sleep.0:Disable this function. + */ +#define RTCLOCKCALI_HP_SLEEP_AUTOCALI (BIT(30)) +#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_M (RTCLOCKCALI_HP_SLEEP_AUTOCALI_V << RTCLOCKCALI_HP_SLEEP_AUTOCALI_S) +#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_V 0x00000001U +#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_S 30 +/** RTCLOCKCALI_LP_SLEEP_AUTOCALI : R/W; bitpos: [31]; default: 0; + * 1:Chip begin to calibrating,when into lp_sleep.0:Disable this function. + */ +#define RTCLOCKCALI_LP_SLEEP_AUTOCALI (BIT(31)) +#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_M (RTCLOCKCALI_LP_SLEEP_AUTOCALI_V << RTCLOCKCALI_LP_SLEEP_AUTOCALI_S) +#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_V 0x00000001U +#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_S 31 + +/** RTCLOCKCALI_INT_RAW_REG register + * Configure register. + */ +#define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38) +/** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * Indicate the xtal timeout once happened . + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW (BIT(29)) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S 29 +/** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Indicate the calibration timeout once happened . + */ +#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW (BIT(30)) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V 0x00000001U +#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S 30 +/** RTCLOCKCALI_CALI_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Indicate the finish of once calibration . + */ +#define RTCLOCKCALI_CALI_DONE_INT_RAW (BIT(31)) +#define RTCLOCKCALI_CALI_DONE_INT_RAW_M (RTCLOCKCALI_CALI_DONE_INT_RAW_V << RTCLOCKCALI_CALI_DONE_INT_RAW_S) +#define RTCLOCKCALI_CALI_DONE_INT_RAW_V 0x00000001U +#define RTCLOCKCALI_CALI_DONE_INT_RAW_S 31 + +/** RTCLOCKCALI_INT_ST_REG register + * Interrupt state register. + */ +#define RTCLOCKCALI_INT_ST_REG (DR_REG_RTCLOCKCALI_BASE + 0x3c) +/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ST : RO; bitpos: [29]; default: 0; + * Interrupt state register. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST (BIT(29)) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S 29 +/** RTCLOCKCALI_CALI_TIMEOUT_INT_ST : RO; bitpos: [30]; default: 0; + * Interrupt state register. + */ +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST (BIT(30)) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_M (RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V 0x00000001U +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S 30 +/** RTCLOCKCALI_CALI_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * Interrupt state register. + */ +#define RTCLOCKCALI_CALI_DONE_INT_ST (BIT(31)) +#define RTCLOCKCALI_CALI_DONE_INT_ST_M (RTCLOCKCALI_CALI_DONE_INT_ST_V << RTCLOCKCALI_CALI_DONE_INT_ST_S) +#define RTCLOCKCALI_CALI_DONE_INT_ST_V 0x00000001U +#define RTCLOCKCALI_CALI_DONE_INT_ST_S 31 + +/** RTCLOCKCALI_INT_ENA_REG register + * Configure register. + */ +#define RTCLOCKCALI_INT_ENA_REG (DR_REG_RTCLOCKCALI_BASE + 0x40) +/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA : R/W; bitpos: [29]; default: 0; + * Interrupt enable signal. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA (BIT(29)) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S 29 +/** RTCLOCKCALI_CALI_TIMEOUT_INT_ENA : R/W; bitpos: [30]; default: 0; + * Interrupt enable signal. + */ +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA (BIT(30)) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_M (RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V 0x00000001U +#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S 30 +/** RTCLOCKCALI_CALI_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * Interrupt enable signal. + */ +#define RTCLOCKCALI_CALI_DONE_INT_ENA (BIT(31)) +#define RTCLOCKCALI_CALI_DONE_INT_ENA_M (RTCLOCKCALI_CALI_DONE_INT_ENA_V << RTCLOCKCALI_CALI_DONE_INT_ENA_S) +#define RTCLOCKCALI_CALI_DONE_INT_ENA_V 0x00000001U +#define RTCLOCKCALI_CALI_DONE_INT_ENA_S 31 + +/** RTCLOCKCALI_INT_CLR_REG register + * Configure register. + */ +#define RTCLOCKCALI_INT_CLR_REG (DR_REG_RTCLOCKCALI_BASE + 0x44) +/** RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR : WT; bitpos: [29]; default: 0; + * interrupt clear signal. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR (BIT(29)) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_M (RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S 29 +/** RTCLOCKCALI_CALI_TIMEOUT_INT_CLR : WT; bitpos: [30]; default: 0; + * interrupt clear signal. + */ +#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR (BIT(30)) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_M (RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V << RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S) +#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V 0x00000001U +#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S 30 +/** RTCLOCKCALI_CALI_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * interrupt clear signal. + */ +#define RTCLOCKCALI_CALI_DONE_INT_CLR (BIT(31)) +#define RTCLOCKCALI_CALI_DONE_INT_CLR_M (RTCLOCKCALI_CALI_DONE_INT_CLR_V << RTCLOCKCALI_CALI_DONE_INT_CLR_S) +#define RTCLOCKCALI_CALI_DONE_INT_CLR_V 0x00000001U +#define RTCLOCKCALI_CALI_DONE_INT_CLR_S 31 + +/** RTCLOCKCALI_TIMEOUT_REG register + * Configure register. + */ +#define RTCLOCKCALI_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x48) +/** RTCLOCKCALI_TIMEOUT_TARGET : R/W; bitpos: [29:0]; default: 0; + * use to setting max calibration time . + */ +#define RTCLOCKCALI_TIMEOUT_TARGET 0x3FFFFFFFU +#define RTCLOCKCALI_TIMEOUT_TARGET_M (RTCLOCKCALI_TIMEOUT_TARGET_V << RTCLOCKCALI_TIMEOUT_TARGET_S) +#define RTCLOCKCALI_TIMEOUT_TARGET_V 0x3FFFFFFFU +#define RTCLOCKCALI_TIMEOUT_TARGET_S 0 +/** RTCLOCKCALI_TIMEOUT_EN : R/W; bitpos: [31]; default: 0; + * use to enable calibration time-out function ,the calibration force stopping,when + * timeout. + */ +#define RTCLOCKCALI_TIMEOUT_EN (BIT(31)) +#define RTCLOCKCALI_TIMEOUT_EN_M (RTCLOCKCALI_TIMEOUT_EN_V << RTCLOCKCALI_TIMEOUT_EN_S) +#define RTCLOCKCALI_TIMEOUT_EN_V 0x00000001U +#define RTCLOCKCALI_TIMEOUT_EN_S 31 + +/** RTCLOCKCALI_XTAL_TIMEOUT_REG register + * Configure register. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x4c) +/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET : R/W; bitpos: [29:14]; default: 65535; + * use to setting max xtal monitor time . + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET 0x0000FFFFU +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V 0x0000FFFFU +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S 14 +/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP : WT; bitpos: [30]; default: 0; + * use to stop XTAL time-out function ,timeout happened when xtal invalid. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP (BIT(30)) +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S 30 +/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_START : WT; bitpos: [31]; default: 0; + * use to start XTAL time-out function ,timeout happened when xtal invalid. + */ +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START (BIT(31)) +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_M (RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S) +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V 0x00000001U +#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S 31 + +/** RTCLOCKCALI_DATE_REG register + * Configure register. + */ +#define RTCLOCKCALI_DATE_REG (DR_REG_RTCLOCKCALI_BASE + 0x3fc) +/** RTCLOCKCALI_RTCLOCKCALI_DATE : R/W; bitpos: [30:0]; default: 36708448; + * need_des + */ +#define RTCLOCKCALI_RTCLOCKCALI_DATE 0x7FFFFFFFU +#define RTCLOCKCALI_RTCLOCKCALI_DATE_M (RTCLOCKCALI_RTCLOCKCALI_DATE_V << RTCLOCKCALI_RTCLOCKCALI_DATE_S) +#define RTCLOCKCALI_RTCLOCKCALI_DATE_V 0x7FFFFFFFU +#define RTCLOCKCALI_RTCLOCKCALI_DATE_S 0 +/** RTCLOCKCALI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTCLOCKCALI_CLK_EN (BIT(31)) +#define RTCLOCKCALI_CLK_EN_M (RTCLOCKCALI_CLK_EN_V << RTCLOCKCALI_CLK_EN_S) +#define RTCLOCKCALI_CLK_EN_V 0x00000001U +#define RTCLOCKCALI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_struct.h new file mode 100644 index 0000000000..56c9c4533d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_struct.h @@ -0,0 +1,521 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_cali_timer register + * need_des + */ +typedef union { + struct { + /** timer_target : R/W; bitpos: [29:0]; default: 4095; + * need_des + */ + uint32_t timer_target:30; + /** timer_stop : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_stop:1; + /** timer_start : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_start:1; + }; + uint32_t val; +} rtclockcali_lp_cali_timer_reg_t; + +/** Type of dfreq_high_limit_slow register + * RTC slow clock dfreq high limit. + */ +typedef union { + struct { + /** coarse_limit_diff_slow : R/W; bitpos: [7:0]; default: 16; + * When rtc_cali_value upper/lower than reg_high/low_limit +/- + * reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step. + */ + uint32_t coarse_limit_diff_slow:8; + /** high_limit_slow : R/W; bitpos: [31:8]; default: 267; + * when rtc_cali_value upper than reg_high_limit,frequency of osc will increase . + */ + uint32_t high_limit_slow:24; + }; + uint32_t val; +} rtclockcali_dfreq_high_limit_slow_reg_t; + +/** Type of dfreq_low_limit_slow register + * RTC slow clock dfreq low limit. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** low_limit_slow : R/W; bitpos: [31:8]; default: 266; + * when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease . + */ + uint32_t low_limit_slow:24; + }; + uint32_t val; +} rtclockcali_dfreq_low_limit_slow_reg_t; + +/** Type of dfreq_high_limit_fast register + * RTC fast clock dfreq high limit. + */ +typedef union { + struct { + /** coarse_limit_diff_fast : R/W; bitpos: [7:0]; default: 16; + * When rtc_cali_value upper/lower than reg_high/low_limit +/- + * reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step. + */ + uint32_t coarse_limit_diff_fast:8; + /** high_limit_fast : R/W; bitpos: [31:8]; default: 267; + * when rtc_cali_value upper than reg_high_limit,frequency of osc will increase . + */ + uint32_t high_limit_fast:24; + }; + uint32_t val; +} rtclockcali_dfreq_high_limit_fast_reg_t; + +/** Type of dfreq_low_limit_fast register + * RTC fast clock dfreq low limit. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** low_limit_fast : R/W; bitpos: [31:8]; default: 266; + * when rtc_cali_value lower than reg_low_limit,frequency of osc will decrease . + */ + uint32_t low_limit_fast:24; + }; + uint32_t val; +} rtclockcali_dfreq_low_limit_fast_reg_t; + +/** Type of dfreq_conf2 register + * RTC DFREQ CONF2 + */ +typedef union { + struct { + /** dreq_update : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t dreq_update:1; + uint32_t reserved_1:1; + /** dreq_init_32k : WT; bitpos: [2]; default: 0; + * Initialize the value of 32K OSC dfreq setting. + */ + uint32_t dreq_init_32k:1; + /** dreq_init_fosc : WT; bitpos: [3]; default: 0; + * Initialize the value of FOSC dfreq setting. + */ + uint32_t dreq_init_fosc:1; + /** dreq_init_sosc : WT; bitpos: [4]; default: 0; + * Initialize the value of SOSC dfreq setting. + */ + uint32_t dreq_init_sosc:1; + /** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0; + * 1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled + * by register from system-register bank + */ + uint32_t rc32k_dfreq_sel:1; + /** fosc_dfreq_sel : R/W; bitpos: [6]; default: 0; + * 1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled + * by register from system-register bank + */ + uint32_t fosc_dfreq_sel:1; + /** sosc_dfreq_sel : R/W; bitpos: [7]; default: 0; + * 1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled + * by register from system-register bank + */ + uint32_t sosc_dfreq_sel:1; + /** fine_step : R/W; bitpos: [15:8]; default: 1; + * Frequency fine step. + */ + uint32_t fine_step:8; + /** coarse_step_fast : R/W; bitpos: [23:16]; default: 8; + * Frequency coarse step,use to decrease calibration time. + */ + uint32_t coarse_step_fast:8; + /** coarse_step_slow : R/W; bitpos: [31:24]; default: 8; + * Frequency coarse step,use to decrease calibration time. + */ + uint32_t coarse_step_slow:8; + }; + uint32_t val; +} rtclockcali_dfreq_conf2_reg_t; + +/** Type of cali_en register + * Configure register. + */ +typedef union { + struct { + /** cali_en_32k : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t cali_en_32k:1; + /** cali_en_fosc : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t cali_en_fosc:1; + /** cali_en_sosc : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t cali_en_sosc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} rtclockcali_cali_en_reg_t; + +/** Type of dfreq_value register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** dreq_32k : RO; bitpos: [11:2]; default: 172; + * The value of dfreq num of 32k. + */ + uint32_t dreq_32k:10; + /** dreq_fosc : RO; bitpos: [21:12]; default: 512; + * The value of dfreq num of FOSC. + */ + uint32_t dreq_fosc:10; + /** dreq_sosc : RO; bitpos: [31:22]; default: 512; + * The value of dfreq num of SOSC. + */ + uint32_t dreq_sosc:10; + }; + uint32_t val; +} rtclockcali_dfreq_value_reg_t; + +/** Type of bypass register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_autocali : R/W; bitpos: [30]; default: 0; + * 1:Chip begin to calibrating,when into hp_sleep.0:Disable this function. + */ + uint32_t hp_sleep_autocali:1; + /** lp_sleep_autocali : R/W; bitpos: [31]; default: 0; + * 1:Chip begin to calibrating,when into lp_sleep.0:Disable this function. + */ + uint32_t lp_sleep_autocali:1; + }; + uint32_t val; +} rtclockcali_bypass_reg_t; + +/** Type of int_raw register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * Indicate the xtal timeout once happened . + */ + uint32_t xtal_timeout_int_raw:1; + /** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Indicate the calibration timeout once happened . + */ + uint32_t cali_timeout_int_raw:1; + /** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Indicate the finish of once calibration . + */ + uint32_t cali_done_int_raw:1; + }; + uint32_t val; +} rtclockcali_int_raw_reg_t; + +/** Type of int_st register + * Interrupt state register. + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** xtal_timeout_int_st : RO; bitpos: [29]; default: 0; + * Interrupt state register. + */ + uint32_t xtal_timeout_int_st:1; + /** cali_timeout_int_st : RO; bitpos: [30]; default: 0; + * Interrupt state register. + */ + uint32_t cali_timeout_int_st:1; + /** cali_done_int_st : RO; bitpos: [31]; default: 0; + * Interrupt state register. + */ + uint32_t cali_done_int_st:1; + }; + uint32_t val; +} rtclockcali_int_st_reg_t; + +/** Type of int_ena register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** xtal_timeout_int_ena : R/W; bitpos: [29]; default: 0; + * Interrupt enable signal. + */ + uint32_t xtal_timeout_int_ena:1; + /** cali_timeout_int_ena : R/W; bitpos: [30]; default: 0; + * Interrupt enable signal. + */ + uint32_t cali_timeout_int_ena:1; + /** cali_done_int_ena : R/W; bitpos: [31]; default: 0; + * Interrupt enable signal. + */ + uint32_t cali_done_int_ena:1; + }; + uint32_t val; +} rtclockcali_int_ena_reg_t; + +/** Type of int_clr register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** xtal_timeout_int_clr : WT; bitpos: [29]; default: 0; + * interrupt clear signal. + */ + uint32_t xtal_timeout_int_clr:1; + /** cali_timeout_int_clr : WT; bitpos: [30]; default: 0; + * interrupt clear signal. + */ + uint32_t cali_timeout_int_clr:1; + /** cali_done_int_clr : WT; bitpos: [31]; default: 0; + * interrupt clear signal. + */ + uint32_t cali_done_int_clr:1; + }; + uint32_t val; +} rtclockcali_int_clr_reg_t; + +/** Type of timeout register + * Configure register. + */ +typedef union { + struct { + /** timeout_target : R/W; bitpos: [29:0]; default: 0; + * use to setting max calibration time . + */ + uint32_t timeout_target:30; + uint32_t reserved_30:1; + /** timeout_en : R/W; bitpos: [31]; default: 0; + * use to enable calibration time-out function ,the calibration force stopping,when + * timeout. + */ + uint32_t timeout_en:1; + }; + uint32_t val; +} rtclockcali_timeout_reg_t; + +/** Type of xtal_timeout register + * Configure register. + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** xtal_timeout_cnt_target : R/W; bitpos: [29:14]; default: 65535; + * use to setting max xtal monitor time . + */ + uint32_t xtal_timeout_cnt_target:16; + /** xtal_timeout_cnt_stop : WT; bitpos: [30]; default: 0; + * use to stop XTAL time-out function ,timeout happened when xtal invalid. + */ + uint32_t xtal_timeout_cnt_stop:1; + /** xtal_timeout_cnt_start : WT; bitpos: [31]; default: 0; + * use to start XTAL time-out function ,timeout happened when xtal invalid. + */ + uint32_t xtal_timeout_cnt_start:1; + }; + uint32_t val; +} rtclockcali_xtal_timeout_reg_t; + +/** Type of date register + * Configure register. + */ +typedef union { + struct { + /** rtclockcali_date : R/W; bitpos: [30:0]; default: 36708448; + * need_des + */ + uint32_t rtclockcali_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rtclockcali_date_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg_slow register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling_slow : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling_slow:1; + /** rtc_cali_clk_sel_slow : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel_slow:2; + /** rtc_cali_rdy_slow : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy_slow:1; + /** rtc_cali_max_slow : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max_slow:15; + /** rtc_cali_start_slow : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start_slow:1; + }; + uint32_t val; +} rtclockcali_rtccalicfg_slow_reg_t; + +/** Type of rtccalicfg_fast register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** fosc_div_num : R/W; bitpos: [11:4]; default: 0; + * fosc clock divider number + */ + uint32_t fosc_div_num:8; + /** rtc_cali_start_cycling_fast : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling_fast:1; + /** rtc_cali_clk_sel_fast : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel_fast:2; + /** rtc_cali_rdy_fast : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy_fast:1; + /** rtc_cali_max_fast : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max_fast:15; + /** rtc_cali_start_fast : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start_fast:1; + }; + uint32_t val; +} rtclockcali_rtccalicfg_fast_reg_t; + +/** Type of rtccalicfg1_slow register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld_slow : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld_slow:1; + uint32_t reserved_1:6; + /** rtc_cali_value_slow : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value_slow:25; + }; + uint32_t val; +} rtclockcali_rtccalicfg1_slow_reg_t; + +/** Type of rtccalicfg1_fast register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld_fast : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld_fast:1; + uint32_t reserved_1:6; + /** rtc_cali_value_fast : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value_fast:25; + }; + uint32_t val; +} rtclockcali_rtccalicfg1_fast_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} rtclockcali_rtccalicfg2_reg_t; + + +typedef struct { + volatile rtclockcali_lp_cali_timer_reg_t lp_cali_timer; + volatile rtclockcali_rtccalicfg_slow_reg_t rtccalicfg_slow; + volatile rtclockcali_rtccalicfg_fast_reg_t rtccalicfg_fast; + volatile rtclockcali_rtccalicfg1_slow_reg_t rtccalicfg1_slow; + volatile rtclockcali_rtccalicfg1_fast_reg_t rtccalicfg1_fast; + volatile rtclockcali_rtccalicfg2_reg_t rtccalicfg2; + volatile rtclockcali_dfreq_high_limit_slow_reg_t dfreq_high_limit_slow; + volatile rtclockcali_dfreq_low_limit_slow_reg_t dfreq_low_limit_slow; + volatile rtclockcali_dfreq_high_limit_fast_reg_t dfreq_high_limit_fast; + volatile rtclockcali_dfreq_low_limit_fast_reg_t dfreq_low_limit_fast; + volatile rtclockcali_dfreq_conf2_reg_t dfreq_conf2; + volatile rtclockcali_cali_en_reg_t cali_en; + volatile rtclockcali_dfreq_value_reg_t dfreq_value; + volatile rtclockcali_bypass_reg_t bypass; + volatile rtclockcali_int_raw_reg_t int_raw; + volatile rtclockcali_int_st_reg_t int_st; + volatile rtclockcali_int_ena_reg_t int_ena; + volatile rtclockcali_int_clr_reg_t int_clr; + volatile rtclockcali_timeout_reg_t timeout; + volatile rtclockcali_xtal_timeout_reg_t xtal_timeout; + uint32_t reserved_050[235]; + volatile rtclockcali_date_reg_t date; +} rtclockcali_dev_t; + +extern rtclockcali_dev_t RTCLOCKCALI; + +#ifndef __cplusplus +_Static_assert(sizeof(rtclockcali_dev_t) == 0x400, "Invalid size of rtclockcali_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_eco5_struct.h new file mode 100644 index 0000000000..c719683228 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_eco5_struct.h @@ -0,0 +1,1457 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control register */ +/** Type of ctrl register + * Control register + */ +typedef union { + struct { + /** controller_reset : R/W; bitpos: [0]; default: 0; + * To reset controller, firmware should set this bit. This bit is auto-cleared after + * two AHB and two sdhost_cclk_in clock cycles. + */ + uint32_t controller_reset:1; + /** fifo_reset : R/W; bitpos: [1]; default: 0; + * To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after + * completion of reset operation. + * Note: FIFO pointers will be out of reset after 2 cycles of system clocks in + * addition to synchronization delay (2 cycles of card clock), after the fifo_reset is + * cleared. + */ + uint32_t fifo_reset:1; + /** dma_reset : R/W; bitpos: [2]; default: 0; + * To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared + * after two AHB clocks. + */ + uint32_t dma_reset:1; + uint32_t reserved_3:1; + /** int_enable : R/W; bitpos: [4]; default: 0; + * Global interrupt enable/disable bit. 0: Disable; 1: Enable. + */ + uint32_t int_enable:1; + uint32_t reserved_5:1; + /** read_wait : R/W; bitpos: [6]; default: 0; + * For sending read-wait to SDIO cards. + */ + uint32_t read_wait:1; + /** send_irq_response : R/W; bitpos: [7]; default: 0; + * Bit automatically clears once response is sent. To wait for MMC card interrupts, + * host issues CMD40 and waits for interrupt response from MMC card(s). In the + * meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this + * bit, at which time SD/MMC command state-machine sends CMD40 response on bus and + * returns to idle state. + */ + uint32_t send_irq_response:1; + /** abort_read_data : R/W; bitpos: [8]; default: 0; + * After a suspend-command is issued during a read-operation, software polls the card + * to find when the suspend-event occurred. Once the suspend-event has occurred, + * software sets the bit which will reset the data state machine that is waiting for + * the next block of data. This bit is automatically cleared once the data state + * machine is reset to idle. + */ + uint32_t abort_read_data:1; + /** send_ccsd : R/W; bitpos: [9]; default: 0; + * When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if + * the current command is expecting CCS (that is, RW_BLK), and if interrupts are + * enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC + * automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) + * bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, + * in case the Command Done interrupt is not masked. + * NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive + * the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may + * be sent to the CE-ATA device, even if the device has signalled CCS. + */ + uint32_t send_ccsd:1; + /** send_auto_stop_ccsd : R/W; bitpos: [10]; default: 0; + * Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; + * SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, + * SD/MMC automatically sends an internally-generated STOP command (CMD12) to the + * CE-ATA device. After sending this internally-generated STOP command, the Auto + * Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated + * for the host, in case the ACD interrupt is not masked. After sending the Command + * Completion Signal Disable (CCSD), SD/MMC automatically clears the + * SDHOST_SEND_AUTO_STOP_CCSD bit. + */ + uint32_t send_auto_stop_ccsd:1; + /** ceata_device_interrupt_status : R/W; bitpos: [11]; default: 0; + * Software should appropriately write to this bit after the power-on reset or any + * other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is + * usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, + * then software should set this bit. + */ + uint32_t ceata_device_interrupt_status:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} sdhost_ctrl_reg_t; + + +/** Group: Clock divider configuration register */ +/** Type of clkdiv register + * Clock divider configuration register + */ +typedef union { + struct { + /** clk_divider0 : R/W; bitpos: [7:0]; default: 0; + * Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider0:8; + /** clk_divider1 : R/W; bitpos: [15:8]; default: 0; + * Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider1:8; + /** clk_divider2 : R/W; bitpos: [23:16]; default: 0; + * Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider2:8; + /** clk_divider3 : R/W; bitpos: [31:24]; default: 0; + * Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider3:8; + }; + uint32_t val; +} sdhost_clkdiv_reg_t; + + +/** Group: Clock source selection register */ +/** Type of clksrc register + * Clock source selection register + */ +typedef union { + struct { + /** clksrc_reg : R/W; bitpos: [3:0]; default: 0; + * Clock divider source for two SD cards is supported. Each card has two bits assigned + * to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for + * card 1. Card 0 maps and internally routes clock divider[0:3] outputs to + * cclk_out[1:0] pins, depending on bit value. + * 00 : Clock divider 0; + * 01 : Clock divider 1; + * 10 : Clock divider 2; + * 11 : Clock divider 3. + */ + uint32_t clksrc_reg:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdhost_clksrc_reg_t; + + +/** Group: Clock enable register */ +/** Type of clkena register + * Clock enable register + */ +typedef union { + struct { + /** cclk_enable : R/W; bitpos: [1:0]; default: 0; + * Clock-enable control for two SD card clocks and one MMC card clock is supported. + * One bit per card. + * 0: Clock disabled; + * 1: Clock enabled. + */ + uint32_t cclk_enable:2; + uint32_t reserved_2:14; + /** lp_enable : R/W; bitpos: [17:16]; default: 0; + * Disable clock when the card is in IDLE state. One bit per card. + * 0: clock disabled; + * 1: clock enabled. + */ + uint32_t lp_enable:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_clkena_reg_t; + + +/** Group: Data and response timeout configuration register */ +/** Type of tmout register + * Data and response timeout configuration register + */ +typedef union { + struct { + /** response_timeout : R/W; bitpos: [7:0]; default: 64; + * Response timeout value. Value is specified in terms of number of card output + * clocks, i.e., sdhost_cclk_out. + */ + uint32_t response_timeout:8; + /** data_timeout : R/W; bitpos: [31:8]; default: 16777215; + * Value for card data read timeout. This value is also used for data starvation by + * host timeout. The timeout counter is started only after the card clock is stopped. + * This value is specified in number of card output clocks, i.e. sdhost_cclk_out of + * the selected card. + * NOTE: The software timer should be used if the timeout value is in the order of 100 + * ms. In this case, read data timeout interrupt needs to be disabled. + */ + uint32_t data_timeout:24; + }; + uint32_t val; +} sdhost_tmout_reg_t; + + +/** Group: Card bus width configuration register */ +/** Type of ctype register + * Card bus width configuration register + */ +typedef union { + struct { + /** card_width4 : R/W; bitpos: [1:0]; default: 0; + * One bit per card indicates if card is 1-bit or 4-bit mode. + * 0: 1-bit mode; + * 1: 4-bit mode. + * Bit[1:0] correspond to card[1:0] respectively. + */ + uint32_t card_width4:2; + uint32_t reserved_2:14; + /** card_width8 : R/W; bitpos: [17:16]; default: 0; + * One bit per card indicates if card is in 8-bit mode. + * 0: Non 8-bit mode; + * 1: 8-bit mode. + * Bit[17:16] correspond to card[1:0] respectively. + */ + uint32_t card_width8:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_ctype_reg_t; + + +/** Group: Card data block size configuration register */ +/** Type of blksiz register + * Card data block size configuration register + */ +typedef union { + struct { + /** block_size : R/W; bitpos: [15:0]; default: 512; + * Block size. + */ + uint32_t block_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdhost_blksiz_reg_t; + + +/** Group: Data transfer length configuration register */ +/** Type of bytcnt register + * Data transfer length configuration register + */ +typedef union { + struct { + /** byte_count : R/W; bitpos: [31:0]; default: 512; + * Number of bytes to be transferred, should be an integral multiple of Block Size for + * block transfers. For data transfers of undefined byte lengths, byte count should be + * set to 0. When byte count is set to 0, it is the responsibility of host to + * explicitly send stop/abort command to terminate data transfer. + */ + uint32_t byte_count:32; + }; + uint32_t val; +} sdhost_bytcnt_reg_t; + + +/** Group: SDIO interrupt mask register */ +/** Type of intmask register + * SDIO interrupt mask register + */ +typedef union { + struct { + /** int_mask : R/W; bitpos: [15:0]; default: 0; + * These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a + * value of 1 enables the interrupt. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): Rx Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation-by-host timeout; + * Bit 9 (DRTO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t int_mask:16; + /** sdio_int_mask : R/W; bitpos: [17:16]; default: 0; + * SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] + * respectively. When masked, SDIO interrupt detection for that card is disabled. 0 + * masks an interrupt, and 1 enables an interrupt. + */ + uint32_t sdio_int_mask:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_intmask_reg_t; + + +/** Group: Command argument data register */ +/** Type of cmdarg register + * Command argument data register + */ +typedef union { + struct { + /** cmdarg_reg : R/W; bitpos: [31:0]; default: 0; + * Value indicates command argument to be passed to the card. + */ + uint32_t cmdarg_reg:32; + }; + uint32_t val; +} sdhost_cmdarg_reg_t; + + +/** Group: Command and boot configuration register */ +/** Type of cmd register + * Command and boot configuration register + */ +typedef union { + struct { + /** cmd_index : R/W; bitpos: [5:0]; default: 0; + * Command index. + */ + uint32_t cmd_index:6; + /** response_expect : R/W; bitpos: [6]; default: 0; + * 0: No response expected from card; 1: Response expected from card. + */ + uint32_t response_expect:1; + /** response_length : R/W; bitpos: [7]; default: 0; + * 0: Short response expected from card; 1: Long response expected from card. + */ + uint32_t response_length:1; + /** check_response_crc : R/W; bitpos: [8]; default: 0; + * 0: Do not check; 1: Check response CRC. + * Some of command responses do not return valid CRC bits. Software should disable CRC + * checks for those commands in order to disable CRC checking by controller. + */ + uint32_t check_response_crc:1; + /** data_expected : R/W; bitpos: [9]; default: 0; + * 0: No data transfer expected; 1: Data transfer expected. + */ + uint32_t data_expected:1; + /** read_write : R/W; bitpos: [10]; default: 0; + * 0: Read from card; 1: Write to card. + * Don't care if no data is expected from card. + */ + uint32_t read_write:1; + /** transfer_mode : R/W; bitpos: [11]; default: 0; + * 0: Block data transfer command; 1: Stream data transfer command. + * Don't care if no data expected. + */ + uint32_t transfer_mode:1; + /** send_auto_stop : R/W; bitpos: [12]; default: 0; + * 0: No stop command is sent at the end of data transfer; 1: Send stop command at the + * end of data transfer. + */ + uint32_t send_auto_stop:1; + /** wait_prvdata_complete : R/W; bitpos: [13]; default: 0; + * 0: Send command at once, even if previous data transfer has not completed; 1: Wait + * for previous data transfer to complete before sending Command. + * The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of + * card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr + * should be same as in previous command. + */ + uint32_t wait_prvdata_complete:1; + /** stop_abort_cmd : R/W; bitpos: [14]; default: 0; + * 0: Neither stop nor abort command can stop current data transfer. If abort is sent + * to function-number currently selected or not in data-transfer mode, then bit should + * be set to 0; 1: Stop or abort command intended to stop current data transfer in + * progress. + * When open-ended or predefined data transfer is in progress, and host issues stop or + * abort command to stop data transfer, bit should be set so that command/data + * state-machines of CIU can return correctly to idle state. + */ + uint32_t stop_abort_cmd:1; + /** send_initialization : R/W; bitpos: [15]; default: 0; + * 0: Do not send initialization sequence (80 clocks of 1) before sending this + * command; 1: Send initialization sequence before sending this command. + * After powered on, 80 clocks must be sent to card for initialization before sending + * any commands to card. Bit should be set while sending first command to card so that + * controller will initialize clocks before sending command to card. + */ + uint32_t send_initialization:1; + /** card_number : R/W; bitpos: [20:16]; default: 0; + * Card number in use. Represents physical slot number of card being accessed. In + * SD-only mode, up to two cards are supported. + */ + uint32_t card_number:5; + /** update_clock_registers_only : R/W; bitpos: [21]; default: 0; + * 0: Normal command sequence; 1: Do not send commands, just update clock register + * value into card clock domain. + * Following register values are transferred into card clock domain: CLKDIV, CLRSRC, + * and CLKENA. + * Changes card clocks (change frequency, truncate off or on, and set low-frequency + * mode). This is provided in order to change clock frequency or stop clock without + * having to send command to cards. During normal command sequence, when + * sdhost_update_clock_registers_only = 0, following control registers are transferred + * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new + * register values for new command sequence to card(s). When bit is set, there are no + * Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + */ + uint32_t update_clock_registers_only:1; + /** read_ceata_device : R/W; bitpos: [22]; default: 0; + * Read access flag. + * 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; + * 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. + * Software should set this bit to indicate that CE-ATA device is being accessed for + * read transfer. This bit is used to disable read data timeout indication while + * performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no + * less than 10 seconds. SD/MMC should not indicate read data timeout while waiting + * for data from CE-ATA device. + */ + uint32_t read_ceata_device:1; + /** ccs_expected : R/W; bitpos: [23]; default: 0; + * Expected Command Completion Signal (CCS) configuration. + * 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), + * or command does not expect CCS from device; + * 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects + * command completion signal from CE-ATA device. + * If the command expects Command Completion Signal (CCS) from the CE-ATA device, the + * software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in + * RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is + * not masked. + */ + uint32_t ccs_expected:1; + uint32_t reserved_24:5; + /** use_hole_reg : R/W; bitpos: [29]; default: 1; + * Use Hold Register. + * 0: CMD and DATA sent to card bypassing HOLD Register; + * 1: CMD and DATA sent to card through the HOLD Register. + */ + uint32_t use_hole_reg:1; + uint32_t reserved_30:1; + /** start_cmd : R/W; bitpos: [31]; default: 0; + * Start command. Once command is served by the CIU, this bit is automatically + * cleared. When this bit is set, host should not attempt to write to any command + * registers. If a write is attempted, hardware lock error is set in raw interrupt + * register. Once command is sent and a response is received from SD_MMC_CEATA cards, + * Command Done bit is set in the raw interrupt Register. + */ + uint32_t start_cmd:1; + }; + uint32_t val; +} sdhost_cmd_reg_t; + + +/** Group: Response data register */ +/** Type of resp0 register + * Response data register + */ +typedef union { + struct { + /** response0_reg : RO; bitpos: [31:0]; default: 0; + * Bit[31:0] of response. + */ + uint32_t response0_reg:32; + }; + uint32_t val; +} sdhost_resp0_reg_t; + + +/** Group: Long response data register */ +/** Type of resp1 register + * Long response data register + */ +typedef union { + struct { + /** response1_reg : RO; bitpos: [31:0]; default: 0; + * Bit[63:32] of long response. + */ + uint32_t response1_reg:32; + }; + uint32_t val; +} sdhost_resp1_reg_t; + +/** Type of resp2 register + * Long response data register + */ +typedef union { + struct { + /** response2_reg : RO; bitpos: [31:0]; default: 0; + * Bit[95:64] of long response. + */ + uint32_t response2_reg:32; + }; + uint32_t val; +} sdhost_resp2_reg_t; + +/** Type of resp3 register + * Long response data register + */ +typedef union { + struct { + /** response3_reg : RO; bitpos: [31:0]; default: 0; + * Bit[127:96] of long response. + */ + uint32_t response3_reg:32; + }; + uint32_t val; +} sdhost_resp3_reg_t; + + +/** Group: Masked interrupt status register */ +/** Type of mintsts register + * Masked interrupt status register + */ +typedef union { + struct { + /** int_status_msk : RO; bitpos: [15:0]; default: 0; + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t int_status_msk:16; + /** sdio_interrupt_msk : RO; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. SDIO interrupt for card is enabled only if corresponding + * sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit + * enables interrupt). + */ + uint32_t sdio_interrupt_msk:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_mintsts_reg_t; + + +/** Group: Raw interrupt status register */ +/** Type of rintsts register + * Raw interrupt status register + */ +typedef union { + struct { + /** int_status_raw : R/W; bitpos: [15:0]; default: 0; + * Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits + * are logged regardless of interrupt mask status. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t int_status_raw:16; + /** sdio_interrupt_raw : R/W; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. Setting a bit clears the corresponding interrupt bit and + * writing 0 has no effect. + * 0: No SDIO interrupt from card; + * 1: SDIO interrupt from card. + */ + uint32_t sdio_interrupt_raw:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_rintsts_reg_t; + + +/** Group: SD/MMC status register */ +/** Type of status register + * SD/MMC status register + */ +typedef union { + struct { + /** fifo_rx_watermark : RO; bitpos: [0]; default: 0; + * FIFO reached Receive watermark level, not qualified with data transfer. + */ + uint32_t fifo_rx_watermark:1; + /** fifo_tx_watermark : RO; bitpos: [1]; default: 1; + * FIFO reached Transmit watermark level, not qualified with data transfer. + */ + uint32_t fifo_tx_watermark:1; + /** fifo_empty : RO; bitpos: [2]; default: 1; + * FIFO is empty status. + */ + uint32_t fifo_empty:1; + /** fifo_full : RO; bitpos: [3]; default: 0; + * FIFO is full status. + */ + uint32_t fifo_full:1; + /** command_fsm_states : RO; bitpos: [7:4]; default: 1; + * Command FSM states. + * 0: Idle; + * 1: Send init sequence; + * 2: Send cmd start bit; + * 3: Send cmd tx bit; + * 4: Send cmd index + arg; + * 5: Send cmd crc7; + * 6: Send cmd end bit; + * 7: Receive resp start bit; + * 8: Receive resp IRQ response; + * 9: Receive resp tx bit; + * 10: Receive resp cmd idx; + * 11: Receive resp data; + * 12: Receive resp crc7; + * 13: Receive resp end bit; + * 14: Cmd path wait NCC; + * 15: Wait, cmd-to-response turnaround. + */ + uint32_t command_fsm_states:4; + /** data_3_status : RO; bitpos: [8]; default: 1; + * Raw selected sdhost_card_data[3], checks whether card is present. + * 0: card not present; + * 1: card present. + */ + uint32_t data_3_status:1; + /** data_busy : RO; bitpos: [9]; default: 1; + * Inverted version of raw selected sdhost_card_data[0]. + * 0: Card data not busy; + * 1: Card data busy. + */ + uint32_t data_busy:1; + /** data_state_mc_busy : RO; bitpos: [10]; default: 1; + * Data transmit or receive state-machine is busy. + */ + uint32_t data_state_mc_busy:1; + /** response_index : RO; bitpos: [16:11]; default: 0; + * Index of previous response, including any auto-stop sent by core. + */ + uint32_t response_index:6; + /** fifo_count : RO; bitpos: [29:17]; default: 0; + * FIFO count, number of filled locations in FIFO. + */ + uint32_t fifo_count:13; + uint32_t reserved_30:2; + }; + uint32_t val; +} sdhost_status_reg_t; + + +/** Group: FIFO configuration register */ +/** Type of fifoth register + * FIFO configuration register + */ +typedef union { + struct { + /** tx_wmark : R/W; bitpos: [11:0]; default: 0; + * FIFO threshold watermark level when transmitting data to card. When FIFO data count + * is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is + * enabled, then interrupt occurs. During end of packet, request or interrupt is + * generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO + * threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA + * request. During end of packet, on last interrupt, host is responsible for filling + * FIFO with only required remaining bytes (not before FIFO is full or after CIU + * completes data transfers, because FIFO may not be empty). In DMA mode, at end of + * packet, if last transfer is less than burst size, DMA controller does single + * cycles until required bytes are transferred. + */ + uint32_t tx_wmark:12; + uint32_t reserved_12:4; + /** rx_wmark : R/W; bitpos: [26:16]; default: 0; + * FIFO threshold watermark level when receiving data to card.When FIFO data count + * reaches greater than this number , DMA/FIFO request is raised. During end of + * packet, request is generated regardless of threshold programming in order to + * complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) + * interrupt is enabled, then interrupt is generated instead of DMA request.During end + * of packet, interrupt is not generated if threshold programming is larger than any + * remaining data. It is responsibility of host to read remaining bytes on seeing Data + * Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are + * less than threshold, DMA request does single transfers to flush out any remaining + * bytes before Data Transfer Done interrupt is set. + */ + uint32_t rx_wmark:11; + uint32_t reserved_27:1; + /** dma_multiple_transaction_size : R/W; bitpos: [30:28]; default: 0; + * Burst size of multiple transaction, should be programmed same as DMA controller + * multiple-transaction-size SDHOST_SRC/DEST_MSIZE. + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + */ + uint32_t dma_multiple_transaction_size:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdhost_fifoth_reg_t; + + +/** Group: Card detect register */ +/** Type of cdetect register + * Card detect register + */ +typedef union { + struct { + /** card_detect_n : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 + * represents presence of card. Only NUM_CARDS number of bits are implemented. + */ + uint32_t card_detect_n:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_cdetect_reg_t; + + +/** Group: Card write protection (WP) status register */ +/** Type of wrtprt register + * Card write protection (WP) status register + */ +typedef union { + struct { + /** write_protect : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write + * protection. Only NUM_CARDS number of bits are implemented. + */ + uint32_t write_protect:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_wrtprt_reg_t; + + +/** Group: Transferred byte count register */ +/** Type of tcbcnt register + * Transferred byte count register + */ +typedef union { + struct { + /** tcbcnt_reg : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred by CIU unit to card. + */ + uint32_t tcbcnt_reg:32; + }; + uint32_t val; +} sdhost_tcbcnt_reg_t; + +/** Type of tbbcnt register + * Transferred byte count register + */ +typedef union { + struct { + /** tbbcnt_reg : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ + uint32_t tbbcnt_reg:32; + }; + uint32_t val; +} sdhost_tbbcnt_reg_t; + + +/** Group: Debounce filter time configuration register */ +/** Type of debnce register + * Debounce filter time configuration register + */ +typedef union { + struct { + /** debounce_count : R/W; bitpos: [23:0]; default: 0; + * Number of host clocks (clk) used by debounce filter logic. The typical debounce + * time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted + * or removed. + */ + uint32_t debounce_count:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdhost_debnce_reg_t; + + +/** Group: User ID (scratchpad) register */ +/** Type of usrid register + * User ID (scratchpad) register + */ +typedef union { + struct { + /** usrid_reg : R/W; bitpos: [31:0]; default: 0; + * User identification register, value set by user. Can also be used as a scratchpad + * register by user. + */ + uint32_t usrid_reg:32; + }; + uint32_t val; +} sdhost_usrid_reg_t; + + +/** Group: Version ID (scratchpad) register */ +/** Type of verid register + * Version ID (scratchpad) register + */ +typedef union { + struct { + /** versionid_reg : RO; bitpos: [31:0]; default: 1412572938; + * Hardware version register. Can also be read by fireware. + */ + uint32_t versionid_reg:32; + }; + uint32_t val; +} sdhost_verid_reg_t; + + +/** Group: Hardware feature register */ +/** Type of hcon register + * Hardware feature register + */ +typedef union { + struct { + /** card_type_reg : RO; bitpos: [0]; default: 1; + * Hardware support SDIO and MMC. + */ + uint32_t card_type_reg:1; + /** card_num_reg : RO; bitpos: [5:1]; default: 1; + * Support card number is 2. + */ + uint32_t card_num_reg:5; + /** bus_type_reg : RO; bitpos: [6]; default: 1; + * Register config is APB bus. + */ + uint32_t bus_type_reg:1; + /** data_width_reg : RO; bitpos: [9:7]; default: 1; + * Regisger data width is 32. + */ + uint32_t data_width_reg:3; + /** addr_width_reg : RO; bitpos: [15:10]; default: 19; + * Register address width is 32. + */ + uint32_t addr_width_reg:6; + uint32_t reserved_16:2; + /** dma_width_reg : RO; bitpos: [20:18]; default: 1; + * DMA data width is 32. + */ + uint32_t dma_width_reg:3; + /** ram_indise_reg : RO; bitpos: [21]; default: 0; + * Inside RAM in SDMMC module. + */ + uint32_t ram_indise_reg:1; + /** hold_reg : RO; bitpos: [22]; default: 1; + * Have a hold register in data path . + */ + uint32_t hold_reg:1; + uint32_t reserved_23:1; + /** num_clk_div_reg : RO; bitpos: [25:24]; default: 3; + * Have 4 clk divider in design . + */ + uint32_t num_clk_div_reg:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdhost_hcon_reg_t; + + +/** Group: UHS-1 register */ +/** Type of uhs register + * UHS-1 register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ddr_reg : R/W; bitpos: [17:16]; default: 0; + * DDR mode selection,1 bit for each card. + * 0-Non-DDR mode. + * 1-DDR mode. + */ + uint32_t ddr_reg:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_uhs_reg_t; + + +/** Group: Card reset register */ +/** Type of rst_n register + * Card reset register + */ +typedef union { + struct { + /** card_reset : R/W; bitpos: [1:0]; default: 1; + * Hardware reset. + * 1: Active mode; + * 0: Reset. + * These bits cause the cards to enter pre-idle state, which requires them to be + * re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, + * SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + */ + uint32_t card_reset:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_rst_n_reg_t; + + +/** Group: Burst mode transfer configuration register */ +/** Type of bmod register + * Burst mode transfer configuration register + */ +typedef union { + struct { + /** bmod_swr : R/W; bitpos: [0]; default: 0; + * Software Reset. When set, the DMA Controller resets all its internal registers. It + * is automatically cleared after one clock cycle. + */ + uint32_t bmod_swr:1; + /** bmod_fb : R/W; bitpos: [1]; default: 0; + * Fixed Burst. Controls whether the AHB Master interface performs fixed burst + * transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 + * during start of normal burst transfers. When reset, the AHB will use SINGLE and + * INCR burst transfer operations. + */ + uint32_t bmod_fb:1; + uint32_t reserved_2:5; + /** bmod_de : R/W; bitpos: [7]; default: 0; + * IDMAC Enable. When set, the IDMAC is enabled. + */ + uint32_t bmod_de:1; + /** bmod_pbl : R/W; bitpos: [10:8]; default: 0; + * Programmable Burst Length. These bits indicate the maximum number of beats to be + * performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always + * attempt to burst as specified in PBL each time it starts a burst transfer on the + * host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value + * is the mirror of MSIZE of FIFOTH register. In order to change this value, write the + * required value to FIFOTH register. This is an encode value as follows: + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + * PBL is a read-only value and is applicable only for data access, it does not apply + * to descriptor access. + */ + uint32_t bmod_pbl:3; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdhost_bmod_reg_t; + + +/** Group: Poll demand configuration register */ +/** Type of pldmnd register + * Poll demand configuration register + */ +typedef union { + struct { + /** pldmnd_pd : WO; bitpos: [31:0]; default: 0; + * Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the + * Suspend state. The host needs to write any value into this register for the IDMAC + * FSM to resume normal descriptor fetch operation. This is a write only . + */ + uint32_t pldmnd_pd:32; + }; + uint32_t val; +} sdhost_pldmnd_reg_t; + + +/** Group: Descriptor base address register */ +/** Type of dbaddr register + * Descriptor base address register + */ +typedef union { + struct { + /** dbaddr_reg : R/W; bitpos: [31:0]; default: 0; + * Start of Descriptor List. Contains the base address of the First Descriptor. The + * LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence + * these LSB bits may be treated as read-only. + */ + uint32_t dbaddr_reg:32; + }; + uint32_t val; +} sdhost_dbaddr_reg_t; + + +/** Group: IDMAC status register */ +/** Type of idsts register + * IDMAC status register + */ +typedef union { + struct { + /** idsts_ti : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt. Indicates that data transmission is finished for a descriptor. + * Writing 1 clears this bit. + */ + uint32_t idsts_ti:1; + /** idsts_ri : R/W; bitpos: [1]; default: 0; + * Receive Interrupt. Indicates the completion of data reception for a descriptor. + * Writing 1 clears this bit. + */ + uint32_t idsts_ri:1; + /** idsts_fbe : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . + * When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this + * bit. + */ + uint32_t idsts_fbe:1; + uint32_t reserved_3:1; + /** idsts_du : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. This bit is set when the descriptor is + * unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + */ + uint32_t idsts_du:1; + /** idsts_ces : R/W; bitpos: [5]; default: 0; + * Card Error Summary. Indicates the status of the transaction to/from the card, also + * present in RINTSTS. Indicates the logical OR of the following bits: + * EBE : End Bit Error; + * RTO : Response Timeout/Boot Ack Timeout; + * RCRC : Response CRC; + * SBE : Start Bit Error; + * DRTO : Data Read Timeout/BDS timeout; + * DCRC : Data CRC for Receive; + * RE : Response Error. + * Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting + * of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response + * error. + */ + uint32_t idsts_ces:1; + uint32_t reserved_6:2; + /** idsts_nis : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit + * Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This + * is a sticky bit and must be cleared each time a corresponding bit that causes NIS + * to be set is cleared. Writing 1 clears this bit. + */ + uint32_t idsts_nis:1; + /** idsts_ais : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus + * Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is + * a sticky bit and must be cleared each time a corresponding bit that causes AIS to + * be set is cleared. Writing 1 clears this bit. + */ + uint32_t idsts_ais:1; + /** idsts_fbe_code : R/W; bitpos: [12:10]; default: 0; + * Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid + * only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an + * interrupt. + * 001: Host Abort received during transmission; + * 010: Host Abort received during reception; + * Others: Reserved. + */ + uint32_t idsts_fbe_code:3; + /** idsts_fsm : R/W; bitpos: [16:13]; default: 0; + * DMAC FSM present state. + * 0: DMA_IDLE (idle state); + * 1: DMA_SUSPEND (suspend state); + * 2: DESC_RD (descriptor reading state); + * 3: DESC_CHK (descriptor checking state); + * 4: DMA_RD_REQ_WAIT (read-data request waiting state); + * 5: DMA_WR_REQ_WAIT (write-data request waiting state); + * 6: DMA_RD (data-read state); + * 7: DMA_WR (data-write state); + * 8: DESC_CLOSE (descriptor close state). + */ + uint32_t idsts_fsm:4; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdhost_idsts_reg_t; + + +/** Group: IDMAC interrupt enable register */ +/** Type of idinten register + * IDMAC interrupt enable register + */ +typedef union { + struct { + /** idinten_ti : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit + * Interrupt is enabled. When reset, Transmit Interrupt is disabled. + */ + uint32_t idinten_ti:1; + /** idinten_ri : R/W; bitpos: [1]; default: 0; + * Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive + * Interrupt is enabled. When reset, Receive Interrupt is disabled. + */ + uint32_t idinten_ri:1; + /** idinten_fbe : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal + * Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is + * disabled. + */ + uint32_t idinten_fbe:1; + uint32_t reserved_3:1; + /** idinten_du : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary + * Enable, the DU interrupt is enabled. + */ + uint32_t idinten_du:1; + /** idinten_ces : R/W; bitpos: [5]; default: 0; + * Card Error summary Interrupt Enable. When set, it enables the Card Interrupt + * summary. + */ + uint32_t idinten_ces:1; + uint32_t reserved_6:2; + /** idinten_ni : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When + * reset, a normal interrupt is disabled. This bit enables the following bits: + * IDINTEN[0]: Transmit Interrupt; + * IDINTEN[1]: Receive Interrupt. + */ + uint32_t idinten_ni:1; + /** idinten_ai : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This + * bit enables the following bits: + * IDINTEN[2]: Fatal Bus Error Interrupt; + * IDINTEN[4]: DU Interrupt. + */ + uint32_t idinten_ai:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdhost_idinten_reg_t; + + +/** Group: Host descriptor address pointer */ +/** Type of dscaddr register + * Host descriptor address pointer + */ +typedef union { + struct { + /** dscaddr_reg : RO; bitpos: [31:0]; default: 0; + * Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the start address of the current descriptor read by + * the IDMAC. + */ + uint32_t dscaddr_reg:32; + }; + uint32_t val; +} sdhost_dscaddr_reg_t; + + +/** Group: Host buffer address pointer register */ +/** Type of bufaddr register + * Host buffer address pointer register + */ +typedef union { + struct { + /** bufaddr_reg : RO; bitpos: [31:0]; default: 0; + * Host Buffer Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the current Data Buffer Address being accessed by + * the IDMAC. + */ + uint32_t bufaddr_reg:32; + }; + uint32_t val; +} sdhost_bufaddr_reg_t; + + +/** Group: Card Threshold Control register */ +/** Type of cardthrctl register + * Card Threshold Control register + */ +typedef union { + struct { + /** cardrdthren_reg : R/W; bitpos: [0]; default: 0; + * Card read threshold enable. + * 1'b0-Card read threshold disabled. + * 1'b1-Card read threshold enabled. + */ + uint32_t cardrdthren_reg:1; + /** cardclrinten_reg : R/W; bitpos: [1]; default: 0; + * Busy clear interrupt generation: + * 1'b0-Busy clear interrypt disabled. + * 1'b1-Busy clear interrypt enabled. + */ + uint32_t cardclrinten_reg:1; + /** cardwrthren_reg : R/W; bitpos: [2]; default: 0; + * Applicable when HS400 mode is enabled. + * 1'b0-Card write Threshold disabled. + * 1'b1-Card write Threshold enabled. + */ + uint32_t cardwrthren_reg:1; + uint32_t reserved_3:13; + /** cardthreshold_reg : R/W; bitpos: [31:16]; default: 0; + * The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG + * is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + */ + uint32_t cardthreshold_reg:16; + }; + uint32_t val; +} sdhost_cardthrctl_reg_t; + + +/** Group: eMMC DDR register */ +/** Type of emmcddr register + * eMMC DDR register + */ +typedef union { + struct { + /** halfstartbit_reg : R/W; bitpos: [1:0]; default: 0; + * Control for start bit detection mechanism duration of start bit.Each bit refers to + * one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For + * eMMC4.5,start bit can be: + * 1'b0-Full cycle. + * 1'b1-less than one full cycle. + */ + uint32_t halfstartbit_reg:2; + uint32_t reserved_2:29; + /** hs400_mode_reg : R/W; bitpos: [31]; default: 0; + * Set 1 to enable HS400 mode. + */ + uint32_t hs400_mode_reg:1; + }; + uint32_t val; +} sdhost_emmcddr_reg_t; + + +/** Group: Enable Phase Shift register */ +/** Type of enshift register + * Enable Phase Shift register + */ +typedef union { + struct { + /** enable_shift_reg : R/W; bitpos: [3:0]; default: 0; + * Control for the amount of phase shift provided on the default enables in the + * design.Two bits assigned for each card. + * 2'b00-Default phase shift. + * 2'b01-Enables shifted to next immediate positive edge. + * 2'b10-Enables shifted to next immediate negative edge. + * 2'b11-Reserved. + */ + uint32_t enable_shift_reg:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdhost_enshift_reg_t; + + +/** Group: CPU write and read transmit data by FIFO */ +/** Type of buffifo register + * CPU write and read transmit data by FIFO + */ +typedef union { + struct { + /** buffifo_reg : R/W; bitpos: [31:0]; default: 0; + * CPU write and read transmit data by FIFO. This register points to the current Data + * FIFO . + */ + uint32_t buffifo_reg:32; + }; + uint32_t val; +} sdhost_buffifo_reg_t; + + +/** Group: SDIO Control and configuration registers */ +/** Type of clk_edge_sel register + * SDIO control register. + */ +typedef union { + struct { + /** cclkin_edge_drv_sel : R/W; bitpos: [2:0]; default: 0; + * It's used to select the clock phase of the output signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_drv_sel:3; + /** cclkin_edge_sam_sel : R/W; bitpos: [5:3]; default: 0; + * It's used to select the clock phase of the input signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_sam_sel:3; + /** cclkin_edge_slf_sel : R/W; bitpos: [8:6]; default: 0; + * It's used to select the clock phase of the internal signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_slf_sel:3; + /** ccllkin_edge_h : R/W; bitpos: [12:9]; default: 1; + * The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + */ + uint32_t ccllkin_edge_h:4; + /** ccllkin_edge_l : R/W; bitpos: [16:13]; default: 0; + * The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + */ + uint32_t ccllkin_edge_l:4; + /** ccllkin_edge_n : R/W; bitpos: [20:17]; default: 1; + * The clock division of cclk_in. + */ + uint32_t ccllkin_edge_n:4; + /** esdio_mode : R/W; bitpos: [21]; default: 0; + * Enable esdio mode. + */ + uint32_t esdio_mode:1; + /** esd_mode : R/W; bitpos: [22]; default: 0; + * Enable esd mode. + */ + uint32_t esd_mode:1; + /** cclk_en : R/W; bitpos: [23]; default: 1; + * Sdio clock enable. + */ + uint32_t cclk_en:1; + /** ultra_high_speed_mode : R/W; bitpos: [24]; default: 0; + * Enable ultra high speed mode, use dll to generate clk. + */ + uint32_t ultra_high_speed_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdhost_clk_edge_sel_reg_t; + + +/** Group: SDIO raw ints registers */ +/** Type of raw_ints register + * SDIO raw ints register. + */ +typedef union { + struct { + /** raw_ints : RO; bitpos: [31:0]; default: 0; + * It indicates raw ints. + */ + uint32_t raw_ints:32; + }; + uint32_t val; +} sdhost_raw_ints_reg_t; + + +/** Group: SDIO dll clock control registers */ +/** Type of dll_clk_conf register + * SDIO DLL clock control register. + */ +typedef union { + struct { + /** dll_cclk_in_slf_en : R/W; bitpos: [0]; default: 0; + * Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_slf_en:1; + /** dll_cclk_in_drv_en : R/W; bitpos: [1]; default: 0; + * Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_drv_en:1; + /** dll_cclk_in_sam_en : R/W; bitpos: [2]; default: 0; + * Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_sam_en:1; + /** dll_cclk_in_slf_phase : R/W; bitpos: [8:3]; default: 0; + * It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_slf_phase:6; + /** dll_cclk_in_drv_phase : R/W; bitpos: [14:9]; default: 0; + * It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_drv_phase:6; + /** dll_cclk_in_sam_phase : R/W; bitpos: [20:15]; default: 0; + * It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_sam_phase:6; + uint32_t reserved_21:11; + }; + uint32_t val; +} sdhost_dll_clk_conf_reg_t; + + +/** Group: SDIO dll configuration registers */ +/** Type of dll_conf register + * SDIO DLL configuration register. + */ +typedef union { + struct { + /** dll_cal_stop : R/W; bitpos: [0]; default: 0; + * Set 1 to stop calibration. + */ + uint32_t dll_cal_stop:1; + /** dll_cal_end : RO; bitpos: [1]; default: 0; + * 1 means calibration finished. + */ + uint32_t dll_cal_end:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_dll_conf_reg_t; + + +typedef struct { + volatile sdhost_ctrl_reg_t ctrl; + uint32_t reserved_004; + volatile sdhost_clkdiv_reg_t clkdiv; + volatile sdhost_clksrc_reg_t clksrc; + volatile sdhost_clkena_reg_t clkena; + volatile sdhost_tmout_reg_t tmout; + volatile sdhost_ctype_reg_t ctype; + volatile sdhost_blksiz_reg_t blksiz; + volatile sdhost_bytcnt_reg_t bytcnt; + volatile sdhost_intmask_reg_t intmask; + volatile sdhost_cmdarg_reg_t cmdarg; + volatile sdhost_cmd_reg_t cmd; + volatile sdhost_resp0_reg_t resp0; + volatile sdhost_resp1_reg_t resp1; + volatile sdhost_resp2_reg_t resp2; + volatile sdhost_resp3_reg_t resp3; + volatile sdhost_mintsts_reg_t mintsts; + volatile sdhost_rintsts_reg_t rintsts; + volatile sdhost_status_reg_t status; + volatile sdhost_fifoth_reg_t fifoth; + volatile sdhost_cdetect_reg_t cdetect; + volatile sdhost_wrtprt_reg_t wrtprt; + uint32_t reserved_058; + volatile sdhost_tcbcnt_reg_t tcbcnt; + volatile sdhost_tbbcnt_reg_t tbbcnt; + volatile sdhost_debnce_reg_t debnce; + volatile sdhost_usrid_reg_t usrid; + volatile sdhost_verid_reg_t verid; + volatile sdhost_hcon_reg_t hcon; + volatile sdhost_uhs_reg_t uhs; + volatile sdhost_rst_n_reg_t rst_n; + uint32_t reserved_07c; + volatile sdhost_bmod_reg_t bmod; + volatile sdhost_pldmnd_reg_t pldmnd; + volatile sdhost_dbaddr_reg_t dbaddr; + volatile sdhost_idsts_reg_t idsts; + volatile sdhost_idinten_reg_t idinten; + volatile sdhost_dscaddr_reg_t dscaddr; + volatile sdhost_bufaddr_reg_t bufaddr; + uint32_t reserved_09c[25]; + volatile sdhost_cardthrctl_reg_t cardthrctl; + uint32_t reserved_104[2]; + volatile sdhost_emmcddr_reg_t emmcddr; + volatile sdhost_enshift_reg_t enshift; + uint32_t reserved_114[59]; + volatile sdhost_buffifo_reg_t buffifo; + uint32_t reserved_204[383]; + volatile sdhost_clk_edge_sel_reg_t clk_edge_sel; + volatile sdhost_raw_ints_reg_t raw_ints; + volatile sdhost_dll_clk_conf_reg_t dll_clk_conf; + volatile sdhost_dll_conf_reg_t dll_conf; +} sdhost_dev_t; + +extern sdhost_dev_t SDMMC; + +#ifndef __cplusplus +_Static_assert(sizeof(sdhost_dev_t) == 0x810, "Invalid size of sdhost_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_reg.h new file mode 100644 index 0000000000..29edf36547 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_reg.h @@ -0,0 +1,1498 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDHOST_CTRL_REG register + * Control register + */ +#define SDHOST_CTRL_REG (DR_REG_SDHOST_BASE + 0x0) +/** SDHOST_CONTROLLER_RESET : R/W; bitpos: [0]; default: 0; + * To reset controller, firmware should set this bit. This bit is auto-cleared after + * two AHB and two sdhost_cclk_in clock cycles. + */ +#define SDHOST_CONTROLLER_RESET (BIT(0)) +#define SDHOST_CONTROLLER_RESET_M (SDHOST_CONTROLLER_RESET_V << SDHOST_CONTROLLER_RESET_S) +#define SDHOST_CONTROLLER_RESET_V 0x00000001U +#define SDHOST_CONTROLLER_RESET_S 0 +/** SDHOST_FIFO_RESET : R/W; bitpos: [1]; default: 0; + * To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after + * completion of reset operation. + * Note: FIFO pointers will be out of reset after 2 cycles of system clocks in + * addition to synchronization delay (2 cycles of card clock), after the fifo_reset is + * cleared. + */ +#define SDHOST_FIFO_RESET (BIT(1)) +#define SDHOST_FIFO_RESET_M (SDHOST_FIFO_RESET_V << SDHOST_FIFO_RESET_S) +#define SDHOST_FIFO_RESET_V 0x00000001U +#define SDHOST_FIFO_RESET_S 1 +/** SDHOST_DMA_RESET : R/W; bitpos: [2]; default: 0; + * To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared + * after two AHB clocks. + */ +#define SDHOST_DMA_RESET (BIT(2)) +#define SDHOST_DMA_RESET_M (SDHOST_DMA_RESET_V << SDHOST_DMA_RESET_S) +#define SDHOST_DMA_RESET_V 0x00000001U +#define SDHOST_DMA_RESET_S 2 +/** SDHOST_INT_ENABLE : R/W; bitpos: [4]; default: 0; + * Global interrupt enable/disable bit. 0: Disable; 1: Enable. + */ +#define SDHOST_INT_ENABLE (BIT(4)) +#define SDHOST_INT_ENABLE_M (SDHOST_INT_ENABLE_V << SDHOST_INT_ENABLE_S) +#define SDHOST_INT_ENABLE_V 0x00000001U +#define SDHOST_INT_ENABLE_S 4 +/** SDHOST_READ_WAIT : R/W; bitpos: [6]; default: 0; + * For sending read-wait to SDIO cards. + */ +#define SDHOST_READ_WAIT (BIT(6)) +#define SDHOST_READ_WAIT_M (SDHOST_READ_WAIT_V << SDHOST_READ_WAIT_S) +#define SDHOST_READ_WAIT_V 0x00000001U +#define SDHOST_READ_WAIT_S 6 +/** SDHOST_SEND_IRQ_RESPONSE : R/W; bitpos: [7]; default: 0; + * Bit automatically clears once response is sent. To wait for MMC card interrupts, + * host issues CMD40 and waits for interrupt response from MMC card(s). In the + * meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this + * bit, at which time SD/MMC command state-machine sends CMD40 response on bus and + * returns to idle state. + */ +#define SDHOST_SEND_IRQ_RESPONSE (BIT(7)) +#define SDHOST_SEND_IRQ_RESPONSE_M (SDHOST_SEND_IRQ_RESPONSE_V << SDHOST_SEND_IRQ_RESPONSE_S) +#define SDHOST_SEND_IRQ_RESPONSE_V 0x00000001U +#define SDHOST_SEND_IRQ_RESPONSE_S 7 +/** SDHOST_ABORT_READ_DATA : R/W; bitpos: [8]; default: 0; + * After a suspend-command is issued during a read-operation, software polls the card + * to find when the suspend-event occurred. Once the suspend-event has occurred, + * software sets the bit which will reset the data state machine that is waiting for + * the next block of data. This bit is automatically cleared once the data state + * machine is reset to idle. + */ +#define SDHOST_ABORT_READ_DATA (BIT(8)) +#define SDHOST_ABORT_READ_DATA_M (SDHOST_ABORT_READ_DATA_V << SDHOST_ABORT_READ_DATA_S) +#define SDHOST_ABORT_READ_DATA_V 0x00000001U +#define SDHOST_ABORT_READ_DATA_S 8 +/** SDHOST_SEND_CCSD : R/W; bitpos: [9]; default: 0; + * When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if + * the current command is expecting CCS (that is, RW_BLK), and if interrupts are + * enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC + * automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) + * bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, + * in case the Command Done interrupt is not masked. + * NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive + * the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may + * be sent to the CE-ATA device, even if the device has signalled CCS. + */ +#define SDHOST_SEND_CCSD (BIT(9)) +#define SDHOST_SEND_CCSD_M (SDHOST_SEND_CCSD_V << SDHOST_SEND_CCSD_S) +#define SDHOST_SEND_CCSD_V 0x00000001U +#define SDHOST_SEND_CCSD_S 9 +/** SDHOST_SEND_AUTO_STOP_CCSD : R/W; bitpos: [10]; default: 0; + * Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; + * SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, + * SD/MMC automatically sends an internally-generated STOP command (CMD12) to the + * CE-ATA device. After sending this internally-generated STOP command, the Auto + * Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated + * for the host, in case the ACD interrupt is not masked. After sending the Command + * Completion Signal Disable (CCSD), SD/MMC automatically clears the + * SDHOST_SEND_AUTO_STOP_CCSD bit. + */ +#define SDHOST_SEND_AUTO_STOP_CCSD (BIT(10)) +#define SDHOST_SEND_AUTO_STOP_CCSD_M (SDHOST_SEND_AUTO_STOP_CCSD_V << SDHOST_SEND_AUTO_STOP_CCSD_S) +#define SDHOST_SEND_AUTO_STOP_CCSD_V 0x00000001U +#define SDHOST_SEND_AUTO_STOP_CCSD_S 10 +/** SDHOST_CEATA_DEVICE_INTERRUPT_STATUS : R/W; bitpos: [11]; default: 0; + * Software should appropriately write to this bit after the power-on reset or any + * other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is + * usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, + * then software should set this bit. + */ +#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS (BIT(11)) +#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_M (SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V << SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S) +#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V 0x00000001U +#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S 11 + +/** SDHOST_CLKDIV_REG register + * Clock divider configuration register + */ +#define SDHOST_CLKDIV_REG (DR_REG_SDHOST_BASE + 0x8) +/** SDHOST_CLK_DIVIDER0 : R/W; bitpos: [7:0]; default: 0; + * Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ +#define SDHOST_CLK_DIVIDER0 0x000000FFU +#define SDHOST_CLK_DIVIDER0_M (SDHOST_CLK_DIVIDER0_V << SDHOST_CLK_DIVIDER0_S) +#define SDHOST_CLK_DIVIDER0_V 0x000000FFU +#define SDHOST_CLK_DIVIDER0_S 0 +/** SDHOST_CLK_DIVIDER1 : R/W; bitpos: [15:8]; default: 0; + * Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ +#define SDHOST_CLK_DIVIDER1 0x000000FFU +#define SDHOST_CLK_DIVIDER1_M (SDHOST_CLK_DIVIDER1_V << SDHOST_CLK_DIVIDER1_S) +#define SDHOST_CLK_DIVIDER1_V 0x000000FFU +#define SDHOST_CLK_DIVIDER1_S 8 +/** SDHOST_CLK_DIVIDER2 : R/W; bitpos: [23:16]; default: 0; + * Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ +#define SDHOST_CLK_DIVIDER2 0x000000FFU +#define SDHOST_CLK_DIVIDER2_M (SDHOST_CLK_DIVIDER2_V << SDHOST_CLK_DIVIDER2_S) +#define SDHOST_CLK_DIVIDER2_V 0x000000FFU +#define SDHOST_CLK_DIVIDER2_S 16 +/** SDHOST_CLK_DIVIDER3 : R/W; bitpos: [31:24]; default: 0; + * Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ +#define SDHOST_CLK_DIVIDER3 0x000000FFU +#define SDHOST_CLK_DIVIDER3_M (SDHOST_CLK_DIVIDER3_V << SDHOST_CLK_DIVIDER3_S) +#define SDHOST_CLK_DIVIDER3_V 0x000000FFU +#define SDHOST_CLK_DIVIDER3_S 24 + +/** SDHOST_CLKSRC_REG register + * Clock source selection register + */ +#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc) +/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0; + * Clock divider source for two SD cards is supported. Each card has two bits assigned + * to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for + * card 1. Card 0 maps and internally routes clock divider[0:3] outputs to + * cclk_out[1:0] pins, depending on bit value. + * 00 : Clock divider 0; + * 01 : Clock divider 1; + * 10 : Clock divider 2; + * 11 : Clock divider 3. + */ +#define SDHOST_CLKSRC 0x0000000FU +#define SDHOST_CLKSRC_M (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S) +#define SDHOST_CLKSRC_V 0x0000000FU +#define SDHOST_CLKSRC_S 0 + +/** SDHOST_CLKENA_REG register + * Clock enable register + */ +#define SDHOST_CLKENA_REG (DR_REG_SDHOST_BASE + 0x10) +/** SDHOST_CCLK_ENABLE : R/W; bitpos: [1:0]; default: 0; + * Clock-enable control for two SD card clocks and one MMC card clock is supported. + * One bit per card. + * 0: Clock disabled; + * 1: Clock enabled. + */ +#define SDHOST_CCLK_ENABLE 0x00000003U +#define SDHOST_CCLK_ENABLE_M (SDHOST_CCLK_ENABLE_V << SDHOST_CCLK_ENABLE_S) +#define SDHOST_CCLK_ENABLE_V 0x00000003U +#define SDHOST_CCLK_ENABLE_S 0 +/** SDHOST_LP_ENABLE : R/W; bitpos: [17:16]; default: 0; + * Disable clock when the card is in IDLE state. One bit per card. + * 0: clock disabled; + * 1: clock enabled. + */ +#define SDHOST_LP_ENABLE 0x00000003U +#define SDHOST_LP_ENABLE_M (SDHOST_LP_ENABLE_V << SDHOST_LP_ENABLE_S) +#define SDHOST_LP_ENABLE_V 0x00000003U +#define SDHOST_LP_ENABLE_S 16 + +/** SDHOST_TMOUT_REG register + * Data and response timeout configuration register + */ +#define SDHOST_TMOUT_REG (DR_REG_SDHOST_BASE + 0x14) +/** SDHOST_RESPONSE_TIMEOUT : R/W; bitpos: [7:0]; default: 64; + * Response timeout value. Value is specified in terms of number of card output + * clocks, i.e., sdhost_cclk_out. + */ +#define SDHOST_RESPONSE_TIMEOUT 0x000000FFU +#define SDHOST_RESPONSE_TIMEOUT_M (SDHOST_RESPONSE_TIMEOUT_V << SDHOST_RESPONSE_TIMEOUT_S) +#define SDHOST_RESPONSE_TIMEOUT_V 0x000000FFU +#define SDHOST_RESPONSE_TIMEOUT_S 0 +/** SDHOST_DATA_TIMEOUT : R/W; bitpos: [31:8]; default: 16777215; + * Value for card data read timeout. This value is also used for data starvation by + * host timeout. The timeout counter is started only after the card clock is stopped. + * This value is specified in number of card output clocks, i.e. sdhost_cclk_out of + * the selected card. + * NOTE: The software timer should be used if the timeout value is in the order of 100 + * ms. In this case, read data timeout interrupt needs to be disabled. + */ +#define SDHOST_DATA_TIMEOUT 0x00FFFFFFU +#define SDHOST_DATA_TIMEOUT_M (SDHOST_DATA_TIMEOUT_V << SDHOST_DATA_TIMEOUT_S) +#define SDHOST_DATA_TIMEOUT_V 0x00FFFFFFU +#define SDHOST_DATA_TIMEOUT_S 8 + +/** SDHOST_CTYPE_REG register + * Card bus width configuration register + */ +#define SDHOST_CTYPE_REG (DR_REG_SDHOST_BASE + 0x18) +/** SDHOST_CARD_WIDTH4 : R/W; bitpos: [1:0]; default: 0; + * One bit per card indicates if card is 1-bit or 4-bit mode. + * 0: 1-bit mode; + * 1: 4-bit mode. + * Bit[1:0] correspond to card[1:0] respectively. + */ +#define SDHOST_CARD_WIDTH4 0x00000003U +#define SDHOST_CARD_WIDTH4_M (SDHOST_CARD_WIDTH4_V << SDHOST_CARD_WIDTH4_S) +#define SDHOST_CARD_WIDTH4_V 0x00000003U +#define SDHOST_CARD_WIDTH4_S 0 +/** SDHOST_CARD_WIDTH8 : R/W; bitpos: [17:16]; default: 0; + * One bit per card indicates if card is in 8-bit mode. + * 0: Non 8-bit mode; + * 1: 8-bit mode. + * Bit[17:16] correspond to card[1:0] respectively. + */ +#define SDHOST_CARD_WIDTH8 0x00000003U +#define SDHOST_CARD_WIDTH8_M (SDHOST_CARD_WIDTH8_V << SDHOST_CARD_WIDTH8_S) +#define SDHOST_CARD_WIDTH8_V 0x00000003U +#define SDHOST_CARD_WIDTH8_S 16 + +/** SDHOST_BLKSIZ_REG register + * Card data block size configuration register + */ +#define SDHOST_BLKSIZ_REG (DR_REG_SDHOST_BASE + 0x1c) +/** SDHOST_BLOCK_SIZE : R/W; bitpos: [15:0]; default: 512; + * Block size. + */ +#define SDHOST_BLOCK_SIZE 0x0000FFFFU +#define SDHOST_BLOCK_SIZE_M (SDHOST_BLOCK_SIZE_V << SDHOST_BLOCK_SIZE_S) +#define SDHOST_BLOCK_SIZE_V 0x0000FFFFU +#define SDHOST_BLOCK_SIZE_S 0 + +/** SDHOST_BYTCNT_REG register + * Data transfer length configuration register + */ +#define SDHOST_BYTCNT_REG (DR_REG_SDHOST_BASE + 0x20) +/** SDHOST_BYTE_COUNT : R/W; bitpos: [31:0]; default: 512; + * Number of bytes to be transferred, should be an integral multiple of Block Size for + * block transfers. For data transfers of undefined byte lengths, byte count should be + * set to 0. When byte count is set to 0, it is the responsibility of host to + * explicitly send stop/abort command to terminate data transfer. + */ +#define SDHOST_BYTE_COUNT 0xFFFFFFFFU +#define SDHOST_BYTE_COUNT_M (SDHOST_BYTE_COUNT_V << SDHOST_BYTE_COUNT_S) +#define SDHOST_BYTE_COUNT_V 0xFFFFFFFFU +#define SDHOST_BYTE_COUNT_S 0 + +/** SDHOST_INTMASK_REG register + * SDIO interrupt mask register + */ +#define SDHOST_INTMASK_REG (DR_REG_SDHOST_BASE + 0x24) +/** SDHOST_INT_MASK : R/W; bitpos: [15:0]; default: 0; + * These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a + * value of 1 enables the interrupt. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): Rx Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation-by-host timeout; + * Bit 9 (DRTO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ +#define SDHOST_INT_MASK 0x0000FFFFU +#define SDHOST_INT_MASK_M (SDHOST_INT_MASK_V << SDHOST_INT_MASK_S) +#define SDHOST_INT_MASK_V 0x0000FFFFU +#define SDHOST_INT_MASK_S 0 +/** SDHOST_SDIO_INT_MASK : R/W; bitpos: [17:16]; default: 0; + * SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] + * respectively. When masked, SDIO interrupt detection for that card is disabled. 0 + * masks an interrupt, and 1 enables an interrupt. + */ +#define SDHOST_SDIO_INT_MASK 0x00000003U +#define SDHOST_SDIO_INT_MASK_M (SDHOST_SDIO_INT_MASK_V << SDHOST_SDIO_INT_MASK_S) +#define SDHOST_SDIO_INT_MASK_V 0x00000003U +#define SDHOST_SDIO_INT_MASK_S 16 + +/** SDHOST_CMDARG_REG register + * Command argument data register + */ +#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28) +/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0; + * Value indicates command argument to be passed to the card. + */ +#define SDHOST_CMDARG 0xFFFFFFFFU +#define SDHOST_CMDARG_M (SDHOST_CMDARG_V << SDHOST_CMDARG_S) +#define SDHOST_CMDARG_V 0xFFFFFFFFU +#define SDHOST_CMDARG_S 0 + +/** SDHOST_CMD_REG register + * Command and boot configuration register + */ +#define SDHOST_CMD_REG (DR_REG_SDHOST_BASE + 0x2c) +/** SDHOST_CMD_INDEX : R/W; bitpos: [5:0]; default: 0; + * Command index. + */ +#define SDHOST_CMD_INDEX 0x0000003FU +#define SDHOST_CMD_INDEX_M (SDHOST_CMD_INDEX_V << SDHOST_CMD_INDEX_S) +#define SDHOST_CMD_INDEX_V 0x0000003FU +#define SDHOST_CMD_INDEX_S 0 +/** SDHOST_RESPONSE_EXPECT : R/W; bitpos: [6]; default: 0; + * 0: No response expected from card; 1: Response expected from card. + */ +#define SDHOST_RESPONSE_EXPECT (BIT(6)) +#define SDHOST_RESPONSE_EXPECT_M (SDHOST_RESPONSE_EXPECT_V << SDHOST_RESPONSE_EXPECT_S) +#define SDHOST_RESPONSE_EXPECT_V 0x00000001U +#define SDHOST_RESPONSE_EXPECT_S 6 +/** SDHOST_RESPONSE_LENGTH : R/W; bitpos: [7]; default: 0; + * 0: Short response expected from card; 1: Long response expected from card. + */ +#define SDHOST_RESPONSE_LENGTH (BIT(7)) +#define SDHOST_RESPONSE_LENGTH_M (SDHOST_RESPONSE_LENGTH_V << SDHOST_RESPONSE_LENGTH_S) +#define SDHOST_RESPONSE_LENGTH_V 0x00000001U +#define SDHOST_RESPONSE_LENGTH_S 7 +/** SDHOST_CHECK_RESPONSE_CRC : R/W; bitpos: [8]; default: 0; + * 0: Do not check; 1: Check response CRC. + * Some of command responses do not return valid CRC bits. Software should disable CRC + * checks for those commands in order to disable CRC checking by controller. + */ +#define SDHOST_CHECK_RESPONSE_CRC (BIT(8)) +#define SDHOST_CHECK_RESPONSE_CRC_M (SDHOST_CHECK_RESPONSE_CRC_V << SDHOST_CHECK_RESPONSE_CRC_S) +#define SDHOST_CHECK_RESPONSE_CRC_V 0x00000001U +#define SDHOST_CHECK_RESPONSE_CRC_S 8 +/** SDHOST_DATA_EXPECTED : R/W; bitpos: [9]; default: 0; + * 0: No data transfer expected; 1: Data transfer expected. + */ +#define SDHOST_DATA_EXPECTED (BIT(9)) +#define SDHOST_DATA_EXPECTED_M (SDHOST_DATA_EXPECTED_V << SDHOST_DATA_EXPECTED_S) +#define SDHOST_DATA_EXPECTED_V 0x00000001U +#define SDHOST_DATA_EXPECTED_S 9 +/** SDHOST_READ_WRITE : R/W; bitpos: [10]; default: 0; + * 0: Read from card; 1: Write to card. + * Don't care if no data is expected from card. + */ +#define SDHOST_READ_WRITE (BIT(10)) +#define SDHOST_READ_WRITE_M (SDHOST_READ_WRITE_V << SDHOST_READ_WRITE_S) +#define SDHOST_READ_WRITE_V 0x00000001U +#define SDHOST_READ_WRITE_S 10 +/** SDHOST_TRANSFER_MODE : R/W; bitpos: [11]; default: 0; + * 0: Block data transfer command; 1: Stream data transfer command. + * Don't care if no data expected. + */ +#define SDHOST_TRANSFER_MODE (BIT(11)) +#define SDHOST_TRANSFER_MODE_M (SDHOST_TRANSFER_MODE_V << SDHOST_TRANSFER_MODE_S) +#define SDHOST_TRANSFER_MODE_V 0x00000001U +#define SDHOST_TRANSFER_MODE_S 11 +/** SDHOST_SEND_AUTO_STOP : R/W; bitpos: [12]; default: 0; + * 0: No stop command is sent at the end of data transfer; 1: Send stop command at the + * end of data transfer. + */ +#define SDHOST_SEND_AUTO_STOP (BIT(12)) +#define SDHOST_SEND_AUTO_STOP_M (SDHOST_SEND_AUTO_STOP_V << SDHOST_SEND_AUTO_STOP_S) +#define SDHOST_SEND_AUTO_STOP_V 0x00000001U +#define SDHOST_SEND_AUTO_STOP_S 12 +/** SDHOST_WAIT_PRVDATA_COMPLETE : R/W; bitpos: [13]; default: 0; + * 0: Send command at once, even if previous data transfer has not completed; 1: Wait + * for previous data transfer to complete before sending Command. + * The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of + * card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr + * should be same as in previous command. + */ +#define SDHOST_WAIT_PRVDATA_COMPLETE (BIT(13)) +#define SDHOST_WAIT_PRVDATA_COMPLETE_M (SDHOST_WAIT_PRVDATA_COMPLETE_V << SDHOST_WAIT_PRVDATA_COMPLETE_S) +#define SDHOST_WAIT_PRVDATA_COMPLETE_V 0x00000001U +#define SDHOST_WAIT_PRVDATA_COMPLETE_S 13 +/** SDHOST_STOP_ABORT_CMD : R/W; bitpos: [14]; default: 0; + * 0: Neither stop nor abort command can stop current data transfer. If abort is sent + * to function-number currently selected or not in data-transfer mode, then bit should + * be set to 0; 1: Stop or abort command intended to stop current data transfer in + * progress. + * When open-ended or predefined data transfer is in progress, and host issues stop or + * abort command to stop data transfer, bit should be set so that command/data + * state-machines of CIU can return correctly to idle state. + */ +#define SDHOST_STOP_ABORT_CMD (BIT(14)) +#define SDHOST_STOP_ABORT_CMD_M (SDHOST_STOP_ABORT_CMD_V << SDHOST_STOP_ABORT_CMD_S) +#define SDHOST_STOP_ABORT_CMD_V 0x00000001U +#define SDHOST_STOP_ABORT_CMD_S 14 +/** SDHOST_SEND_INITIALIZATION : R/W; bitpos: [15]; default: 0; + * 0: Do not send initialization sequence (80 clocks of 1) before sending this + * command; 1: Send initialization sequence before sending this command. + * After powered on, 80 clocks must be sent to card for initialization before sending + * any commands to card. Bit should be set while sending first command to card so that + * controller will initialize clocks before sending command to card. + */ +#define SDHOST_SEND_INITIALIZATION (BIT(15)) +#define SDHOST_SEND_INITIALIZATION_M (SDHOST_SEND_INITIALIZATION_V << SDHOST_SEND_INITIALIZATION_S) +#define SDHOST_SEND_INITIALIZATION_V 0x00000001U +#define SDHOST_SEND_INITIALIZATION_S 15 +/** SDHOST_CARD_NUMBER : R/W; bitpos: [20:16]; default: 0; + * Card number in use. Represents physical slot number of card being accessed. In + * SD-only mode, up to two cards are supported. + */ +#define SDHOST_CARD_NUMBER 0x0000001FU +#define SDHOST_CARD_NUMBER_M (SDHOST_CARD_NUMBER_V << SDHOST_CARD_NUMBER_S) +#define SDHOST_CARD_NUMBER_V 0x0000001FU +#define SDHOST_CARD_NUMBER_S 16 +/** SDHOST_UPDATE_CLOCK_REGISTERS_ONLY : R/W; bitpos: [21]; default: 0; + * 0: Normal command sequence; 1: Do not send commands, just update clock register + * value into card clock domain. + * Following register values are transferred into card clock domain: CLKDIV, CLRSRC, + * and CLKENA. + * Changes card clocks (change frequency, truncate off or on, and set low-frequency + * mode). This is provided in order to change clock frequency or stop clock without + * having to send command to cards. During normal command sequence, when + * sdhost_update_clock_registers_only = 0, following control registers are transferred + * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new + * register values for new command sequence to card(s). When bit is set, there are no + * Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + */ +#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY (BIT(21)) +#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_M (SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V << SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S) +#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V 0x00000001U +#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S 21 +/** SDHOST_READ_CEATA_DEVICE : R/W; bitpos: [22]; default: 0; + * Read access flag. + * 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; + * 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. + * Software should set this bit to indicate that CE-ATA device is being accessed for + * read transfer. This bit is used to disable read data timeout indication while + * performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no + * less than 10 seconds. SD/MMC should not indicate read data timeout while waiting + * for data from CE-ATA device. + */ +#define SDHOST_READ_CEATA_DEVICE (BIT(22)) +#define SDHOST_READ_CEATA_DEVICE_M (SDHOST_READ_CEATA_DEVICE_V << SDHOST_READ_CEATA_DEVICE_S) +#define SDHOST_READ_CEATA_DEVICE_V 0x00000001U +#define SDHOST_READ_CEATA_DEVICE_S 22 +/** SDHOST_CCS_EXPECTED : R/W; bitpos: [23]; default: 0; + * Expected Command Completion Signal (CCS) configuration. + * 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), + * or command does not expect CCS from device; + * 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects + * command completion signal from CE-ATA device. + * If the command expects Command Completion Signal (CCS) from the CE-ATA device, the + * software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in + * RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is + * not masked. + */ +#define SDHOST_CCS_EXPECTED (BIT(23)) +#define SDHOST_CCS_EXPECTED_M (SDHOST_CCS_EXPECTED_V << SDHOST_CCS_EXPECTED_S) +#define SDHOST_CCS_EXPECTED_V 0x00000001U +#define SDHOST_CCS_EXPECTED_S 23 +/** SDHOST_USE_HOLE_REG : R/W; bitpos: [29]; default: 1; + * Use Hold Register. + * 0: CMD and DATA sent to card bypassing HOLD Register; + * 1: CMD and DATA sent to card through the HOLD Register. + */ +#define SDHOST_USE_HOLE_REG (BIT(29)) +#define SDHOST_USE_HOLE_REG_M (SDHOST_USE_HOLE_REG_V << SDHOST_USE_HOLE_REG_S) +#define SDHOST_USE_HOLE_REG_V 0x00000001U +#define SDHOST_USE_HOLE_REG_S 29 +/** SDHOST_START_CMD : R/W; bitpos: [31]; default: 0; + * Start command. Once command is served by the CIU, this bit is automatically + * cleared. When this bit is set, host should not attempt to write to any command + * registers. If a write is attempted, hardware lock error is set in raw interrupt + * register. Once command is sent and a response is received from SD_MMC_CEATA cards, + * Command Done bit is set in the raw interrupt Register. + */ +#define SDHOST_START_CMD (BIT(31)) +#define SDHOST_START_CMD_M (SDHOST_START_CMD_V << SDHOST_START_CMD_S) +#define SDHOST_START_CMD_V 0x00000001U +#define SDHOST_START_CMD_S 31 + +/** SDHOST_RESP0_REG register + * Response data register + */ +#define SDHOST_RESP0_REG (DR_REG_SDHOST_BASE + 0x30) +/** SDHOST_RESPONSE0_REG : RO; bitpos: [31:0]; default: 0; + * Bit[31:0] of response. + */ +#define SDHOST_RESPONSE0_REG 0xFFFFFFFFU +#define SDHOST_RESPONSE0_REG_M (SDHOST_RESPONSE0_REG_V << SDHOST_RESPONSE0_REG_S) +#define SDHOST_RESPONSE0_REG_V 0xFFFFFFFFU +#define SDHOST_RESPONSE0_REG_S 0 + +/** SDHOST_RESP1_REG register + * Long response data register + */ +#define SDHOST_RESP1_REG (DR_REG_SDHOST_BASE + 0x34) +/** SDHOST_RESPONSE1_REG : RO; bitpos: [31:0]; default: 0; + * Bit[63:32] of long response. + */ +#define SDHOST_RESPONSE1_REG 0xFFFFFFFFU +#define SDHOST_RESPONSE1_REG_M (SDHOST_RESPONSE1_REG_V << SDHOST_RESPONSE1_REG_S) +#define SDHOST_RESPONSE1_REG_V 0xFFFFFFFFU +#define SDHOST_RESPONSE1_REG_S 0 + +/** SDHOST_RESP2_REG register + * Long response data register + */ +#define SDHOST_RESP2_REG (DR_REG_SDHOST_BASE + 0x38) +/** SDHOST_RESPONSE2_REG : RO; bitpos: [31:0]; default: 0; + * Bit[95:64] of long response. + */ +#define SDHOST_RESPONSE2_REG 0xFFFFFFFFU +#define SDHOST_RESPONSE2_REG_M (SDHOST_RESPONSE2_REG_V << SDHOST_RESPONSE2_REG_S) +#define SDHOST_RESPONSE2_REG_V 0xFFFFFFFFU +#define SDHOST_RESPONSE2_REG_S 0 + +/** SDHOST_RESP3_REG register + * Long response data register + */ +#define SDHOST_RESP3_REG (DR_REG_SDHOST_BASE + 0x3c) +/** SDHOST_RESPONSE3_REG : RO; bitpos: [31:0]; default: 0; + * Bit[127:96] of long response. + */ +#define SDHOST_RESPONSE3_REG 0xFFFFFFFFU +#define SDHOST_RESPONSE3_REG_M (SDHOST_RESPONSE3_REG_V << SDHOST_RESPONSE3_REG_S) +#define SDHOST_RESPONSE3_REG_V 0xFFFFFFFFU +#define SDHOST_RESPONSE3_REG_S 0 + +/** SDHOST_MINTSTS_REG register + * Masked interrupt status register + */ +#define SDHOST_MINTSTS_REG (DR_REG_SDHOST_BASE + 0x40) +/** SDHOST_INT_STATUS_MSK : RO; bitpos: [15:0]; default: 0; + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ +#define SDHOST_INT_STATUS_MSK 0x0000FFFFU +#define SDHOST_INT_STATUS_MSK_M (SDHOST_INT_STATUS_MSK_V << SDHOST_INT_STATUS_MSK_S) +#define SDHOST_INT_STATUS_MSK_V 0x0000FFFFU +#define SDHOST_INT_STATUS_MSK_S 0 +/** SDHOST_SDIO_INTERRUPT_MSK : RO; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. SDIO interrupt for card is enabled only if corresponding + * sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit + * enables interrupt). + */ +#define SDHOST_SDIO_INTERRUPT_MSK 0x00000003U +#define SDHOST_SDIO_INTERRUPT_MSK_M (SDHOST_SDIO_INTERRUPT_MSK_V << SDHOST_SDIO_INTERRUPT_MSK_S) +#define SDHOST_SDIO_INTERRUPT_MSK_V 0x00000003U +#define SDHOST_SDIO_INTERRUPT_MSK_S 16 + +/** SDHOST_RINTSTS_REG register + * Raw interrupt status register + */ +#define SDHOST_RINTSTS_REG (DR_REG_SDHOST_BASE + 0x44) +/** SDHOST_INT_STATUS_RAW : R/W; bitpos: [15:0]; default: 0; + * Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits + * are logged regardless of interrupt mask status. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ +#define SDHOST_INT_STATUS_RAW 0x0000FFFFU +#define SDHOST_INT_STATUS_RAW_M (SDHOST_INT_STATUS_RAW_V << SDHOST_INT_STATUS_RAW_S) +#define SDHOST_INT_STATUS_RAW_V 0x0000FFFFU +#define SDHOST_INT_STATUS_RAW_S 0 +/** SDHOST_SDIO_INTERRUPT_RAW : R/W; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. Setting a bit clears the corresponding interrupt bit and + * writing 0 has no effect. + * 0: No SDIO interrupt from card; + * 1: SDIO interrupt from card. + */ +#define SDHOST_SDIO_INTERRUPT_RAW 0x00000003U +#define SDHOST_SDIO_INTERRUPT_RAW_M (SDHOST_SDIO_INTERRUPT_RAW_V << SDHOST_SDIO_INTERRUPT_RAW_S) +#define SDHOST_SDIO_INTERRUPT_RAW_V 0x00000003U +#define SDHOST_SDIO_INTERRUPT_RAW_S 16 + +/** SDHOST_STATUS_REG register + * SD/MMC status register + */ +#define SDHOST_STATUS_REG (DR_REG_SDHOST_BASE + 0x48) +/** SDHOST_FIFO_RX_WATERMARK : RO; bitpos: [0]; default: 0; + * FIFO reached Receive watermark level, not qualified with data transfer. + */ +#define SDHOST_FIFO_RX_WATERMARK (BIT(0)) +#define SDHOST_FIFO_RX_WATERMARK_M (SDHOST_FIFO_RX_WATERMARK_V << SDHOST_FIFO_RX_WATERMARK_S) +#define SDHOST_FIFO_RX_WATERMARK_V 0x00000001U +#define SDHOST_FIFO_RX_WATERMARK_S 0 +/** SDHOST_FIFO_TX_WATERMARK : RO; bitpos: [1]; default: 1; + * FIFO reached Transmit watermark level, not qualified with data transfer. + */ +#define SDHOST_FIFO_TX_WATERMARK (BIT(1)) +#define SDHOST_FIFO_TX_WATERMARK_M (SDHOST_FIFO_TX_WATERMARK_V << SDHOST_FIFO_TX_WATERMARK_S) +#define SDHOST_FIFO_TX_WATERMARK_V 0x00000001U +#define SDHOST_FIFO_TX_WATERMARK_S 1 +/** SDHOST_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * FIFO is empty status. + */ +#define SDHOST_FIFO_EMPTY (BIT(2)) +#define SDHOST_FIFO_EMPTY_M (SDHOST_FIFO_EMPTY_V << SDHOST_FIFO_EMPTY_S) +#define SDHOST_FIFO_EMPTY_V 0x00000001U +#define SDHOST_FIFO_EMPTY_S 2 +/** SDHOST_FIFO_FULL : RO; bitpos: [3]; default: 0; + * FIFO is full status. + */ +#define SDHOST_FIFO_FULL (BIT(3)) +#define SDHOST_FIFO_FULL_M (SDHOST_FIFO_FULL_V << SDHOST_FIFO_FULL_S) +#define SDHOST_FIFO_FULL_V 0x00000001U +#define SDHOST_FIFO_FULL_S 3 +/** SDHOST_COMMAND_FSM_STATES : RO; bitpos: [7:4]; default: 1; + * Command FSM states. + * 0: Idle; + * 1: Send init sequence; + * 2: Send cmd start bit; + * 3: Send cmd tx bit; + * 4: Send cmd index + arg; + * 5: Send cmd crc7; + * 6: Send cmd end bit; + * 7: Receive resp start bit; + * 8: Receive resp IRQ response; + * 9: Receive resp tx bit; + * 10: Receive resp cmd idx; + * 11: Receive resp data; + * 12: Receive resp crc7; + * 13: Receive resp end bit; + * 14: Cmd path wait NCC; + * 15: Wait, cmd-to-response turnaround. + */ +#define SDHOST_COMMAND_FSM_STATES 0x0000000FU +#define SDHOST_COMMAND_FSM_STATES_M (SDHOST_COMMAND_FSM_STATES_V << SDHOST_COMMAND_FSM_STATES_S) +#define SDHOST_COMMAND_FSM_STATES_V 0x0000000FU +#define SDHOST_COMMAND_FSM_STATES_S 4 +/** SDHOST_DATA_3_STATUS : RO; bitpos: [8]; default: 1; + * Raw selected sdhost_card_data[3], checks whether card is present. + * 0: card not present; + * 1: card present. + */ +#define SDHOST_DATA_3_STATUS (BIT(8)) +#define SDHOST_DATA_3_STATUS_M (SDHOST_DATA_3_STATUS_V << SDHOST_DATA_3_STATUS_S) +#define SDHOST_DATA_3_STATUS_V 0x00000001U +#define SDHOST_DATA_3_STATUS_S 8 +/** SDHOST_DATA_BUSY : RO; bitpos: [9]; default: 1; + * Inverted version of raw selected sdhost_card_data[0]. + * 0: Card data not busy; + * 1: Card data busy. + */ +#define SDHOST_DATA_BUSY (BIT(9)) +#define SDHOST_DATA_BUSY_M (SDHOST_DATA_BUSY_V << SDHOST_DATA_BUSY_S) +#define SDHOST_DATA_BUSY_V 0x00000001U +#define SDHOST_DATA_BUSY_S 9 +/** SDHOST_DATA_STATE_MC_BUSY : RO; bitpos: [10]; default: 1; + * Data transmit or receive state-machine is busy. + */ +#define SDHOST_DATA_STATE_MC_BUSY (BIT(10)) +#define SDHOST_DATA_STATE_MC_BUSY_M (SDHOST_DATA_STATE_MC_BUSY_V << SDHOST_DATA_STATE_MC_BUSY_S) +#define SDHOST_DATA_STATE_MC_BUSY_V 0x00000001U +#define SDHOST_DATA_STATE_MC_BUSY_S 10 +/** SDHOST_RESPONSE_INDEX : RO; bitpos: [16:11]; default: 0; + * Index of previous response, including any auto-stop sent by core. + */ +#define SDHOST_RESPONSE_INDEX 0x0000003FU +#define SDHOST_RESPONSE_INDEX_M (SDHOST_RESPONSE_INDEX_V << SDHOST_RESPONSE_INDEX_S) +#define SDHOST_RESPONSE_INDEX_V 0x0000003FU +#define SDHOST_RESPONSE_INDEX_S 11 +/** SDHOST_FIFO_COUNT : RO; bitpos: [29:17]; default: 0; + * FIFO count, number of filled locations in FIFO. + */ +#define SDHOST_FIFO_COUNT 0x00001FFFU +#define SDHOST_FIFO_COUNT_M (SDHOST_FIFO_COUNT_V << SDHOST_FIFO_COUNT_S) +#define SDHOST_FIFO_COUNT_V 0x00001FFFU +#define SDHOST_FIFO_COUNT_S 17 + +/** SDHOST_FIFOTH_REG register + * FIFO configuration register + */ +#define SDHOST_FIFOTH_REG (DR_REG_SDHOST_BASE + 0x4c) +/** SDHOST_TX_WMARK : R/W; bitpos: [11:0]; default: 0; + * FIFO threshold watermark level when transmitting data to card. When FIFO data count + * is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is + * enabled, then interrupt occurs. During end of packet, request or interrupt is + * generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO + * threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA + * request. During end of packet, on last interrupt, host is responsible for filling + * FIFO with only required remaining bytes (not before FIFO is full or after CIU + * completes data transfers, because FIFO may not be empty). In DMA mode, at end of + * packet, if last transfer is less than burst size, DMA controller does single + * cycles until required bytes are transferred. + */ +#define SDHOST_TX_WMARK 0x00000FFFU +#define SDHOST_TX_WMARK_M (SDHOST_TX_WMARK_V << SDHOST_TX_WMARK_S) +#define SDHOST_TX_WMARK_V 0x00000FFFU +#define SDHOST_TX_WMARK_S 0 +/** SDHOST_RX_WMARK : R/W; bitpos: [26:16]; default: 0; + * FIFO threshold watermark level when receiving data to card.When FIFO data count + * reaches greater than this number , DMA/FIFO request is raised. During end of + * packet, request is generated regardless of threshold programming in order to + * complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) + * interrupt is enabled, then interrupt is generated instead of DMA request.During end + * of packet, interrupt is not generated if threshold programming is larger than any + * remaining data. It is responsibility of host to read remaining bytes on seeing Data + * Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are + * less than threshold, DMA request does single transfers to flush out any remaining + * bytes before Data Transfer Done interrupt is set. + */ +#define SDHOST_RX_WMARK 0x000007FFU +#define SDHOST_RX_WMARK_M (SDHOST_RX_WMARK_V << SDHOST_RX_WMARK_S) +#define SDHOST_RX_WMARK_V 0x000007FFU +#define SDHOST_RX_WMARK_S 16 +/** SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE : R/W; bitpos: [30:28]; default: 0; + * Burst size of multiple transaction, should be programmed same as DMA controller + * multiple-transaction-size SDHOST_SRC/DEST_MSIZE. + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + */ +#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE 0x00000007U +#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_M (SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V << SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S) +#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V 0x00000007U +#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S 28 + +/** SDHOST_CDETECT_REG register + * Card detect register + */ +#define SDHOST_CDETECT_REG (DR_REG_SDHOST_BASE + 0x50) +/** SDHOST_CARD_DETECT_N : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 + * represents presence of card. Only NUM_CARDS number of bits are implemented. + */ +#define SDHOST_CARD_DETECT_N 0x00000003U +#define SDHOST_CARD_DETECT_N_M (SDHOST_CARD_DETECT_N_V << SDHOST_CARD_DETECT_N_S) +#define SDHOST_CARD_DETECT_N_V 0x00000003U +#define SDHOST_CARD_DETECT_N_S 0 + +/** SDHOST_WRTPRT_REG register + * Card write protection (WP) status register + */ +#define SDHOST_WRTPRT_REG (DR_REG_SDHOST_BASE + 0x54) +/** SDHOST_WRITE_PROTECT : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write + * protection. Only NUM_CARDS number of bits are implemented. + */ +#define SDHOST_WRITE_PROTECT 0x00000003U +#define SDHOST_WRITE_PROTECT_M (SDHOST_WRITE_PROTECT_V << SDHOST_WRITE_PROTECT_S) +#define SDHOST_WRITE_PROTECT_V 0x00000003U +#define SDHOST_WRITE_PROTECT_S 0 + +/** SDHOST_TCBCNT_REG register + * Transferred byte count register + */ +#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c) +/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred by CIU unit to card. + */ +#define SDHOST_TCBCNT 0xFFFFFFFFU +#define SDHOST_TCBCNT_M (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S) +#define SDHOST_TCBCNT_V 0xFFFFFFFFU +#define SDHOST_TCBCNT_S 0 + +/** SDHOST_TBBCNT_REG register + * Transferred byte count register + */ +#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60) +/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ +#define SDHOST_TBBCNT 0xFFFFFFFFU +#define SDHOST_TBBCNT_M (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S) +#define SDHOST_TBBCNT_V 0xFFFFFFFFU +#define SDHOST_TBBCNT_S 0 + +/** SDHOST_DEBNCE_REG register + * Debounce filter time configuration register + */ +#define SDHOST_DEBNCE_REG (DR_REG_SDHOST_BASE + 0x64) +/** SDHOST_DEBOUNCE_COUNT : R/W; bitpos: [23:0]; default: 0; + * Number of host clocks (clk) used by debounce filter logic. The typical debounce + * time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted + * or removed. + */ +#define SDHOST_DEBOUNCE_COUNT 0x00FFFFFFU +#define SDHOST_DEBOUNCE_COUNT_M (SDHOST_DEBOUNCE_COUNT_V << SDHOST_DEBOUNCE_COUNT_S) +#define SDHOST_DEBOUNCE_COUNT_V 0x00FFFFFFU +#define SDHOST_DEBOUNCE_COUNT_S 0 + +/** SDHOST_USRID_REG register + * User ID (scratchpad) register + */ +#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68) +/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0; + * User identification register, value set by user. Can also be used as a scratchpad + * register by user. + */ +#define SDHOST_USRID 0xFFFFFFFFU +#define SDHOST_USRID_M (SDHOST_USRID_V << SDHOST_USRID_S) +#define SDHOST_USRID_V 0xFFFFFFFFU +#define SDHOST_USRID_S 0 + +/** SDHOST_VERID_REG register + * Version ID (scratchpad) register + */ +#define SDHOST_VERID_REG (DR_REG_SDHOST_BASE + 0x6c) +/** SDHOST_VERSIONID_REG : RO; bitpos: [31:0]; default: 1412572938; + * Hardware version register. Can also be read by fireware. + */ +#define SDHOST_VERSIONID_REG 0xFFFFFFFFU +#define SDHOST_VERSIONID_REG_M (SDHOST_VERSIONID_REG_V << SDHOST_VERSIONID_REG_S) +#define SDHOST_VERSIONID_REG_V 0xFFFFFFFFU +#define SDHOST_VERSIONID_REG_S 0 + +/** SDHOST_HCON_REG register + * Hardware feature register + */ +#define SDHOST_HCON_REG (DR_REG_SDHOST_BASE + 0x70) +/** SDHOST_CARD_TYPE_REG : RO; bitpos: [0]; default: 1; + * Hardware support SDIO and MMC. + */ +#define SDHOST_CARD_TYPE_REG (BIT(0)) +#define SDHOST_CARD_TYPE_REG_M (SDHOST_CARD_TYPE_REG_V << SDHOST_CARD_TYPE_REG_S) +#define SDHOST_CARD_TYPE_REG_V 0x00000001U +#define SDHOST_CARD_TYPE_REG_S 0 +/** SDHOST_CARD_NUM_REG : RO; bitpos: [5:1]; default: 1; + * Support card number is 2. + */ +#define SDHOST_CARD_NUM_REG 0x0000001FU +#define SDHOST_CARD_NUM_REG_M (SDHOST_CARD_NUM_REG_V << SDHOST_CARD_NUM_REG_S) +#define SDHOST_CARD_NUM_REG_V 0x0000001FU +#define SDHOST_CARD_NUM_REG_S 1 +/** SDHOST_BUS_TYPE_REG : RO; bitpos: [6]; default: 1; + * Register config is APB bus. + */ +#define SDHOST_BUS_TYPE_REG (BIT(6)) +#define SDHOST_BUS_TYPE_REG_M (SDHOST_BUS_TYPE_REG_V << SDHOST_BUS_TYPE_REG_S) +#define SDHOST_BUS_TYPE_REG_V 0x00000001U +#define SDHOST_BUS_TYPE_REG_S 6 +/** SDHOST_DATA_WIDTH_REG : RO; bitpos: [9:7]; default: 1; + * Regisger data width is 32. + */ +#define SDHOST_DATA_WIDTH_REG 0x00000007U +#define SDHOST_DATA_WIDTH_REG_M (SDHOST_DATA_WIDTH_REG_V << SDHOST_DATA_WIDTH_REG_S) +#define SDHOST_DATA_WIDTH_REG_V 0x00000007U +#define SDHOST_DATA_WIDTH_REG_S 7 +/** SDHOST_ADDR_WIDTH_REG : RO; bitpos: [15:10]; default: 19; + * Register address width is 32. + */ +#define SDHOST_ADDR_WIDTH_REG 0x0000003FU +#define SDHOST_ADDR_WIDTH_REG_M (SDHOST_ADDR_WIDTH_REG_V << SDHOST_ADDR_WIDTH_REG_S) +#define SDHOST_ADDR_WIDTH_REG_V 0x0000003FU +#define SDHOST_ADDR_WIDTH_REG_S 10 +/** SDHOST_DMA_WIDTH_REG : RO; bitpos: [20:18]; default: 1; + * DMA data width is 32. + */ +#define SDHOST_DMA_WIDTH_REG 0x00000007U +#define SDHOST_DMA_WIDTH_REG_M (SDHOST_DMA_WIDTH_REG_V << SDHOST_DMA_WIDTH_REG_S) +#define SDHOST_DMA_WIDTH_REG_V 0x00000007U +#define SDHOST_DMA_WIDTH_REG_S 18 +/** SDHOST_RAM_INDISE_REG : RO; bitpos: [21]; default: 0; + * Inside RAM in SDMMC module. + */ +#define SDHOST_RAM_INDISE_REG (BIT(21)) +#define SDHOST_RAM_INDISE_REG_M (SDHOST_RAM_INDISE_REG_V << SDHOST_RAM_INDISE_REG_S) +#define SDHOST_RAM_INDISE_REG_V 0x00000001U +#define SDHOST_RAM_INDISE_REG_S 21 +/** SDHOST_HOLD_REG : RO; bitpos: [22]; default: 1; + * Have a hold register in data path . + */ +#define SDHOST_HOLD_REG (BIT(22)) +#define SDHOST_HOLD_REG_M (SDHOST_HOLD_REG_V << SDHOST_HOLD_REG_S) +#define SDHOST_HOLD_REG_V 0x00000001U +#define SDHOST_HOLD_REG_S 22 +/** SDHOST_NUM_CLK_DIV_REG : RO; bitpos: [25:24]; default: 3; + * Have 4 clk divider in design . + */ +#define SDHOST_NUM_CLK_DIV_REG 0x00000003U +#define SDHOST_NUM_CLK_DIV_REG_M (SDHOST_NUM_CLK_DIV_REG_V << SDHOST_NUM_CLK_DIV_REG_S) +#define SDHOST_NUM_CLK_DIV_REG_V 0x00000003U +#define SDHOST_NUM_CLK_DIV_REG_S 24 + +/** SDHOST_UHS_REG register + * UHS-1 register + */ +#define SDHOST_UHS_REG (DR_REG_SDHOST_BASE + 0x74) +/** SDHOST_DDR_REG : R/W; bitpos: [17:16]; default: 0; + * DDR mode selection,1 bit for each card. + * 0-Non-DDR mode. + * 1-DDR mode. + */ +#define SDHOST_DDR_REG 0x00000003U +#define SDHOST_DDR_REG_M (SDHOST_DDR_REG_V << SDHOST_DDR_REG_S) +#define SDHOST_DDR_REG_V 0x00000003U +#define SDHOST_DDR_REG_S 16 + +/** SDHOST_RST_N_REG register + * Card reset register + */ +#define SDHOST_RST_N_REG (DR_REG_SDHOST_BASE + 0x78) +/** SDHOST_CARD_RESET : R/W; bitpos: [1:0]; default: 1; + * Hardware reset. + * 1: Active mode; + * 0: Reset. + * These bits cause the cards to enter pre-idle state, which requires them to be + * re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, + * SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + */ +#define SDHOST_CARD_RESET 0x00000003U +#define SDHOST_CARD_RESET_M (SDHOST_CARD_RESET_V << SDHOST_CARD_RESET_S) +#define SDHOST_CARD_RESET_V 0x00000003U +#define SDHOST_CARD_RESET_S 0 + +/** SDHOST_BMOD_REG register + * Burst mode transfer configuration register + */ +#define SDHOST_BMOD_REG (DR_REG_SDHOST_BASE + 0x80) +/** SDHOST_BMOD_SWR : R/W; bitpos: [0]; default: 0; + * Software Reset. When set, the DMA Controller resets all its internal registers. It + * is automatically cleared after one clock cycle. + */ +#define SDHOST_BMOD_SWR (BIT(0)) +#define SDHOST_BMOD_SWR_M (SDHOST_BMOD_SWR_V << SDHOST_BMOD_SWR_S) +#define SDHOST_BMOD_SWR_V 0x00000001U +#define SDHOST_BMOD_SWR_S 0 +/** SDHOST_BMOD_FB : R/W; bitpos: [1]; default: 0; + * Fixed Burst. Controls whether the AHB Master interface performs fixed burst + * transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 + * during start of normal burst transfers. When reset, the AHB will use SINGLE and + * INCR burst transfer operations. + */ +#define SDHOST_BMOD_FB (BIT(1)) +#define SDHOST_BMOD_FB_M (SDHOST_BMOD_FB_V << SDHOST_BMOD_FB_S) +#define SDHOST_BMOD_FB_V 0x00000001U +#define SDHOST_BMOD_FB_S 1 +/** SDHOST_BMOD_DE : R/W; bitpos: [7]; default: 0; + * IDMAC Enable. When set, the IDMAC is enabled. + */ +#define SDHOST_BMOD_DE (BIT(7)) +#define SDHOST_BMOD_DE_M (SDHOST_BMOD_DE_V << SDHOST_BMOD_DE_S) +#define SDHOST_BMOD_DE_V 0x00000001U +#define SDHOST_BMOD_DE_S 7 +/** SDHOST_BMOD_PBL : R/W; bitpos: [10:8]; default: 0; + * Programmable Burst Length. These bits indicate the maximum number of beats to be + * performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always + * attempt to burst as specified in PBL each time it starts a burst transfer on the + * host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value + * is the mirror of MSIZE of FIFOTH register. In order to change this value, write the + * required value to FIFOTH register. This is an encode value as follows: + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + * PBL is a read-only value and is applicable only for data access, it does not apply + * to descriptor access. + */ +#define SDHOST_BMOD_PBL 0x00000007U +#define SDHOST_BMOD_PBL_M (SDHOST_BMOD_PBL_V << SDHOST_BMOD_PBL_S) +#define SDHOST_BMOD_PBL_V 0x00000007U +#define SDHOST_BMOD_PBL_S 8 + +/** SDHOST_PLDMND_REG register + * Poll demand configuration register + */ +#define SDHOST_PLDMND_REG (DR_REG_SDHOST_BASE + 0x84) +/** SDHOST_PLDMND_PD : WO; bitpos: [31:0]; default: 0; + * Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the + * Suspend state. The host needs to write any value into this register for the IDMAC + * FSM to resume normal descriptor fetch operation. This is a write only . + */ +#define SDHOST_PLDMND_PD 0xFFFFFFFFU +#define SDHOST_PLDMND_PD_M (SDHOST_PLDMND_PD_V << SDHOST_PLDMND_PD_S) +#define SDHOST_PLDMND_PD_V 0xFFFFFFFFU +#define SDHOST_PLDMND_PD_S 0 + +/** SDHOST_DBADDR_REG register + * Descriptor base address register + */ +#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88) +/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0; + * Start of Descriptor List. Contains the base address of the First Descriptor. The + * LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence + * these LSB bits may be treated as read-only. + */ +#define SDHOST_DBADDR 0xFFFFFFFFU +#define SDHOST_DBADDR_M (SDHOST_DBADDR_V << SDHOST_DBADDR_S) +#define SDHOST_DBADDR_V 0xFFFFFFFFU +#define SDHOST_DBADDR_S 0 + +/** SDHOST_IDSTS_REG register + * IDMAC status register + */ +#define SDHOST_IDSTS_REG (DR_REG_SDHOST_BASE + 0x8c) +/** SDHOST_IDSTS_TI : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt. Indicates that data transmission is finished for a descriptor. + * Writing 1 clears this bit. + */ +#define SDHOST_IDSTS_TI (BIT(0)) +#define SDHOST_IDSTS_TI_M (SDHOST_IDSTS_TI_V << SDHOST_IDSTS_TI_S) +#define SDHOST_IDSTS_TI_V 0x00000001U +#define SDHOST_IDSTS_TI_S 0 +/** SDHOST_IDSTS_RI : R/W; bitpos: [1]; default: 0; + * Receive Interrupt. Indicates the completion of data reception for a descriptor. + * Writing 1 clears this bit. + */ +#define SDHOST_IDSTS_RI (BIT(1)) +#define SDHOST_IDSTS_RI_M (SDHOST_IDSTS_RI_V << SDHOST_IDSTS_RI_S) +#define SDHOST_IDSTS_RI_V 0x00000001U +#define SDHOST_IDSTS_RI_S 1 +/** SDHOST_IDSTS_FBE : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . + * When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this + * bit. + */ +#define SDHOST_IDSTS_FBE (BIT(2)) +#define SDHOST_IDSTS_FBE_M (SDHOST_IDSTS_FBE_V << SDHOST_IDSTS_FBE_S) +#define SDHOST_IDSTS_FBE_V 0x00000001U +#define SDHOST_IDSTS_FBE_S 2 +/** SDHOST_IDSTS_DU : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. This bit is set when the descriptor is + * unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + */ +#define SDHOST_IDSTS_DU (BIT(4)) +#define SDHOST_IDSTS_DU_M (SDHOST_IDSTS_DU_V << SDHOST_IDSTS_DU_S) +#define SDHOST_IDSTS_DU_V 0x00000001U +#define SDHOST_IDSTS_DU_S 4 +/** SDHOST_IDSTS_CES : R/W; bitpos: [5]; default: 0; + * Card Error Summary. Indicates the status of the transaction to/from the card, also + * present in RINTSTS. Indicates the logical OR of the following bits: + * EBE : End Bit Error; + * RTO : Response Timeout/Boot Ack Timeout; + * RCRC : Response CRC; + * SBE : Start Bit Error; + * DRTO : Data Read Timeout/BDS timeout; + * DCRC : Data CRC for Receive; + * RE : Response Error. + * Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting + * of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response + * error. + */ +#define SDHOST_IDSTS_CES (BIT(5)) +#define SDHOST_IDSTS_CES_M (SDHOST_IDSTS_CES_V << SDHOST_IDSTS_CES_S) +#define SDHOST_IDSTS_CES_V 0x00000001U +#define SDHOST_IDSTS_CES_S 5 +/** SDHOST_IDSTS_NIS : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit + * Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This + * is a sticky bit and must be cleared each time a corresponding bit that causes NIS + * to be set is cleared. Writing 1 clears this bit. + */ +#define SDHOST_IDSTS_NIS (BIT(8)) +#define SDHOST_IDSTS_NIS_M (SDHOST_IDSTS_NIS_V << SDHOST_IDSTS_NIS_S) +#define SDHOST_IDSTS_NIS_V 0x00000001U +#define SDHOST_IDSTS_NIS_S 8 +/** SDHOST_IDSTS_AIS : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus + * Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is + * a sticky bit and must be cleared each time a corresponding bit that causes AIS to + * be set is cleared. Writing 1 clears this bit. + */ +#define SDHOST_IDSTS_AIS (BIT(9)) +#define SDHOST_IDSTS_AIS_M (SDHOST_IDSTS_AIS_V << SDHOST_IDSTS_AIS_S) +#define SDHOST_IDSTS_AIS_V 0x00000001U +#define SDHOST_IDSTS_AIS_S 9 +/** SDHOST_IDSTS_FBE_CODE : R/W; bitpos: [12:10]; default: 0; + * Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid + * only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an + * interrupt. + * 001: Host Abort received during transmission; + * 010: Host Abort received during reception; + * Others: Reserved. + */ +#define SDHOST_IDSTS_FBE_CODE 0x00000007U +#define SDHOST_IDSTS_FBE_CODE_M (SDHOST_IDSTS_FBE_CODE_V << SDHOST_IDSTS_FBE_CODE_S) +#define SDHOST_IDSTS_FBE_CODE_V 0x00000007U +#define SDHOST_IDSTS_FBE_CODE_S 10 +/** SDHOST_IDSTS_FSM : R/W; bitpos: [16:13]; default: 0; + * DMAC FSM present state. + * 0: DMA_IDLE (idle state); + * 1: DMA_SUSPEND (suspend state); + * 2: DESC_RD (descriptor reading state); + * 3: DESC_CHK (descriptor checking state); + * 4: DMA_RD_REQ_WAIT (read-data request waiting state); + * 5: DMA_WR_REQ_WAIT (write-data request waiting state); + * 6: DMA_RD (data-read state); + * 7: DMA_WR (data-write state); + * 8: DESC_CLOSE (descriptor close state). + */ +#define SDHOST_IDSTS_FSM 0x0000000FU +#define SDHOST_IDSTS_FSM_M (SDHOST_IDSTS_FSM_V << SDHOST_IDSTS_FSM_S) +#define SDHOST_IDSTS_FSM_V 0x0000000FU +#define SDHOST_IDSTS_FSM_S 13 + +/** SDHOST_IDINTEN_REG register + * IDMAC interrupt enable register + */ +#define SDHOST_IDINTEN_REG (DR_REG_SDHOST_BASE + 0x90) +/** SDHOST_IDINTEN_TI : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit + * Interrupt is enabled. When reset, Transmit Interrupt is disabled. + */ +#define SDHOST_IDINTEN_TI (BIT(0)) +#define SDHOST_IDINTEN_TI_M (SDHOST_IDINTEN_TI_V << SDHOST_IDINTEN_TI_S) +#define SDHOST_IDINTEN_TI_V 0x00000001U +#define SDHOST_IDINTEN_TI_S 0 +/** SDHOST_IDINTEN_RI : R/W; bitpos: [1]; default: 0; + * Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive + * Interrupt is enabled. When reset, Receive Interrupt is disabled. + */ +#define SDHOST_IDINTEN_RI (BIT(1)) +#define SDHOST_IDINTEN_RI_M (SDHOST_IDINTEN_RI_V << SDHOST_IDINTEN_RI_S) +#define SDHOST_IDINTEN_RI_V 0x00000001U +#define SDHOST_IDINTEN_RI_S 1 +/** SDHOST_IDINTEN_FBE : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal + * Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is + * disabled. + */ +#define SDHOST_IDINTEN_FBE (BIT(2)) +#define SDHOST_IDINTEN_FBE_M (SDHOST_IDINTEN_FBE_V << SDHOST_IDINTEN_FBE_S) +#define SDHOST_IDINTEN_FBE_V 0x00000001U +#define SDHOST_IDINTEN_FBE_S 2 +/** SDHOST_IDINTEN_DU : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary + * Enable, the DU interrupt is enabled. + */ +#define SDHOST_IDINTEN_DU (BIT(4)) +#define SDHOST_IDINTEN_DU_M (SDHOST_IDINTEN_DU_V << SDHOST_IDINTEN_DU_S) +#define SDHOST_IDINTEN_DU_V 0x00000001U +#define SDHOST_IDINTEN_DU_S 4 +/** SDHOST_IDINTEN_CES : R/W; bitpos: [5]; default: 0; + * Card Error summary Interrupt Enable. When set, it enables the Card Interrupt + * summary. + */ +#define SDHOST_IDINTEN_CES (BIT(5)) +#define SDHOST_IDINTEN_CES_M (SDHOST_IDINTEN_CES_V << SDHOST_IDINTEN_CES_S) +#define SDHOST_IDINTEN_CES_V 0x00000001U +#define SDHOST_IDINTEN_CES_S 5 +/** SDHOST_IDINTEN_NI : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When + * reset, a normal interrupt is disabled. This bit enables the following bits: + * IDINTEN[0]: Transmit Interrupt; + * IDINTEN[1]: Receive Interrupt. + */ +#define SDHOST_IDINTEN_NI (BIT(8)) +#define SDHOST_IDINTEN_NI_M (SDHOST_IDINTEN_NI_V << SDHOST_IDINTEN_NI_S) +#define SDHOST_IDINTEN_NI_V 0x00000001U +#define SDHOST_IDINTEN_NI_S 8 +/** SDHOST_IDINTEN_AI : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This + * bit enables the following bits: + * IDINTEN[2]: Fatal Bus Error Interrupt; + * IDINTEN[4]: DU Interrupt. + */ +#define SDHOST_IDINTEN_AI (BIT(9)) +#define SDHOST_IDINTEN_AI_M (SDHOST_IDINTEN_AI_V << SDHOST_IDINTEN_AI_S) +#define SDHOST_IDINTEN_AI_V 0x00000001U +#define SDHOST_IDINTEN_AI_S 9 + +/** SDHOST_DSCADDR_REG register + * Host descriptor address pointer + */ +#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94) +/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0; + * Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the start address of the current descriptor read by + * the IDMAC. + */ +#define SDHOST_DSCADDR 0xFFFFFFFFU +#define SDHOST_DSCADDR_M (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S) +#define SDHOST_DSCADDR_V 0xFFFFFFFFU +#define SDHOST_DSCADDR_S 0 + +/** SDHOST_BUFADDR_REG register + * Host buffer address pointer register + */ +#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98) +/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0; + * Host Buffer Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the current Data Buffer Address being accessed by + * the IDMAC. + */ +#define SDHOST_BUFADDR 0xFFFFFFFFU +#define SDHOST_BUFADDR_M (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S) +#define SDHOST_BUFADDR_V 0xFFFFFFFFU +#define SDHOST_BUFADDR_S 0 + +/** SDHOST_CARDTHRCTL_REG register + * Card Threshold Control register + */ +#define SDHOST_CARDTHRCTL_REG (DR_REG_SDHOST_BASE + 0x100) +/** SDHOST_CARDRDTHREN_REG : R/W; bitpos: [0]; default: 0; + * Card read threshold enable. + * 1'b0-Card read threshold disabled. + * 1'b1-Card read threshold enabled. + */ +#define SDHOST_CARDRDTHREN_REG (BIT(0)) +#define SDHOST_CARDRDTHREN_REG_M (SDHOST_CARDRDTHREN_REG_V << SDHOST_CARDRDTHREN_REG_S) +#define SDHOST_CARDRDTHREN_REG_V 0x00000001U +#define SDHOST_CARDRDTHREN_REG_S 0 +/** SDHOST_CARDCLRINTEN_REG : R/W; bitpos: [1]; default: 0; + * Busy clear interrupt generation: + * 1'b0-Busy clear interrypt disabled. + * 1'b1-Busy clear interrypt enabled. + */ +#define SDHOST_CARDCLRINTEN_REG (BIT(1)) +#define SDHOST_CARDCLRINTEN_REG_M (SDHOST_CARDCLRINTEN_REG_V << SDHOST_CARDCLRINTEN_REG_S) +#define SDHOST_CARDCLRINTEN_REG_V 0x00000001U +#define SDHOST_CARDCLRINTEN_REG_S 1 +/** SDHOST_CARDWRTHREN_REG : R/W; bitpos: [2]; default: 0; + * Applicable when HS400 mode is enabled. + * 1'b0-Card write Threshold disabled. + * 1'b1-Card write Threshold enabled. + */ +#define SDHOST_CARDWRTHREN_REG (BIT(2)) +#define SDHOST_CARDWRTHREN_REG_M (SDHOST_CARDWRTHREN_REG_V << SDHOST_CARDWRTHREN_REG_S) +#define SDHOST_CARDWRTHREN_REG_V 0x00000001U +#define SDHOST_CARDWRTHREN_REG_S 2 +/** SDHOST_CARDTHRESHOLD_REG : R/W; bitpos: [31:16]; default: 0; + * The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG + * is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + */ +#define SDHOST_CARDTHRESHOLD_REG 0x0000FFFFU +#define SDHOST_CARDTHRESHOLD_REG_M (SDHOST_CARDTHRESHOLD_REG_V << SDHOST_CARDTHRESHOLD_REG_S) +#define SDHOST_CARDTHRESHOLD_REG_V 0x0000FFFFU +#define SDHOST_CARDTHRESHOLD_REG_S 16 + +/** SDHOST_EMMCDDR_REG register + * eMMC DDR register + */ +#define SDHOST_EMMCDDR_REG (DR_REG_SDHOST_BASE + 0x10c) +/** SDHOST_HALFSTARTBIT_REG : R/W; bitpos: [1:0]; default: 0; + * Control for start bit detection mechanism duration of start bit.Each bit refers to + * one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For + * eMMC4.5,start bit can be: + * 1'b0-Full cycle. + * 1'b1-less than one full cycle. + */ +#define SDHOST_HALFSTARTBIT_REG 0x00000003U +#define SDHOST_HALFSTARTBIT_REG_M (SDHOST_HALFSTARTBIT_REG_V << SDHOST_HALFSTARTBIT_REG_S) +#define SDHOST_HALFSTARTBIT_REG_V 0x00000003U +#define SDHOST_HALFSTARTBIT_REG_S 0 +/** SDHOST_HS400_MODE_REG : R/W; bitpos: [31]; default: 0; + * Set 1 to enable HS400 mode. + */ +#define SDHOST_HS400_MODE_REG (BIT(31)) +#define SDHOST_HS400_MODE_REG_M (SDHOST_HS400_MODE_REG_V << SDHOST_HS400_MODE_REG_S) +#define SDHOST_HS400_MODE_REG_V 0x00000001U +#define SDHOST_HS400_MODE_REG_S 31 + +/** SDHOST_ENSHIFT_REG register + * Enable Phase Shift register + */ +#define SDHOST_ENSHIFT_REG (DR_REG_SDHOST_BASE + 0x110) +/** SDHOST_ENABLE_SHIFT_REG : R/W; bitpos: [3:0]; default: 0; + * Control for the amount of phase shift provided on the default enables in the + * design.Two bits assigned for each card. + * 2'b00-Default phase shift. + * 2'b01-Enables shifted to next immediate positive edge. + * 2'b10-Enables shifted to next immediate negative edge. + * 2'b11-Reserved. + */ +#define SDHOST_ENABLE_SHIFT_REG 0x0000000FU +#define SDHOST_ENABLE_SHIFT_REG_M (SDHOST_ENABLE_SHIFT_REG_V << SDHOST_ENABLE_SHIFT_REG_S) +#define SDHOST_ENABLE_SHIFT_REG_V 0x0000000FU +#define SDHOST_ENABLE_SHIFT_REG_S 0 + +/** SDHOST_BUFFIFO_REG register + * CPU write and read transmit data by FIFO + */ +#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200) +/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0; + * CPU write and read transmit data by FIFO. This register points to the current Data + * FIFO . + */ +#define SDHOST_BUFFIFO 0xFFFFFFFFU +#define SDHOST_BUFFIFO_M (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S) +#define SDHOST_BUFFIFO_V 0xFFFFFFFFU +#define SDHOST_BUFFIFO_S 0 + +/** SDHOST_CLK_EDGE_SEL_REG register + * SDIO control register. + */ +#define SDHOST_CLK_EDGE_SEL_REG (DR_REG_SDHOST_BASE + 0x800) +/** SDHOST_CCLKIN_EDGE_DRV_SEL : R/W; bitpos: [2:0]; default: 0; + * It's used to select the clock phase of the output signal from phase 0, phase 90, + * phase 180, phase 270. + */ +#define SDHOST_CCLKIN_EDGE_DRV_SEL 0x00000007U +#define SDHOST_CCLKIN_EDGE_DRV_SEL_M (SDHOST_CCLKIN_EDGE_DRV_SEL_V << SDHOST_CCLKIN_EDGE_DRV_SEL_S) +#define SDHOST_CCLKIN_EDGE_DRV_SEL_V 0x00000007U +#define SDHOST_CCLKIN_EDGE_DRV_SEL_S 0 +/** SDHOST_CCLKIN_EDGE_SAM_SEL : R/W; bitpos: [5:3]; default: 0; + * It's used to select the clock phase of the input signal from phase 0, phase 90, + * phase 180, phase 270. + */ +#define SDHOST_CCLKIN_EDGE_SAM_SEL 0x00000007U +#define SDHOST_CCLKIN_EDGE_SAM_SEL_M (SDHOST_CCLKIN_EDGE_SAM_SEL_V << SDHOST_CCLKIN_EDGE_SAM_SEL_S) +#define SDHOST_CCLKIN_EDGE_SAM_SEL_V 0x00000007U +#define SDHOST_CCLKIN_EDGE_SAM_SEL_S 3 +/** SDHOST_CCLKIN_EDGE_SLF_SEL : R/W; bitpos: [8:6]; default: 0; + * It's used to select the clock phase of the internal signal from phase 0, phase 90, + * phase 180, phase 270. + */ +#define SDHOST_CCLKIN_EDGE_SLF_SEL 0x00000007U +#define SDHOST_CCLKIN_EDGE_SLF_SEL_M (SDHOST_CCLKIN_EDGE_SLF_SEL_V << SDHOST_CCLKIN_EDGE_SLF_SEL_S) +#define SDHOST_CCLKIN_EDGE_SLF_SEL_V 0x00000007U +#define SDHOST_CCLKIN_EDGE_SLF_SEL_S 6 +/** SDHOST_CCLLKIN_EDGE_H : R/W; bitpos: [12:9]; default: 1; + * The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + */ +#define SDHOST_CCLLKIN_EDGE_H 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_H_M (SDHOST_CCLLKIN_EDGE_H_V << SDHOST_CCLLKIN_EDGE_H_S) +#define SDHOST_CCLLKIN_EDGE_H_V 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_H_S 9 +/** SDHOST_CCLLKIN_EDGE_L : R/W; bitpos: [16:13]; default: 0; + * The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + */ +#define SDHOST_CCLLKIN_EDGE_L 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_L_M (SDHOST_CCLLKIN_EDGE_L_V << SDHOST_CCLLKIN_EDGE_L_S) +#define SDHOST_CCLLKIN_EDGE_L_V 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_L_S 13 +/** SDHOST_CCLLKIN_EDGE_N : R/W; bitpos: [20:17]; default: 1; + * The clock division of cclk_in. + */ +#define SDHOST_CCLLKIN_EDGE_N 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_N_M (SDHOST_CCLLKIN_EDGE_N_V << SDHOST_CCLLKIN_EDGE_N_S) +#define SDHOST_CCLLKIN_EDGE_N_V 0x0000000FU +#define SDHOST_CCLLKIN_EDGE_N_S 17 +/** SDHOST_ESDIO_MODE : R/W; bitpos: [21]; default: 0; + * Enable esdio mode. + */ +#define SDHOST_ESDIO_MODE (BIT(21)) +#define SDHOST_ESDIO_MODE_M (SDHOST_ESDIO_MODE_V << SDHOST_ESDIO_MODE_S) +#define SDHOST_ESDIO_MODE_V 0x00000001U +#define SDHOST_ESDIO_MODE_S 21 +/** SDHOST_ESD_MODE : R/W; bitpos: [22]; default: 0; + * Enable esd mode. + */ +#define SDHOST_ESD_MODE (BIT(22)) +#define SDHOST_ESD_MODE_M (SDHOST_ESD_MODE_V << SDHOST_ESD_MODE_S) +#define SDHOST_ESD_MODE_V 0x00000001U +#define SDHOST_ESD_MODE_S 22 +/** SDHOST_CCLK_EN : R/W; bitpos: [23]; default: 1; + * Sdio clock enable. + */ +#define SDHOST_CCLK_EN (BIT(23)) +#define SDHOST_CCLK_EN_M (SDHOST_CCLK_EN_V << SDHOST_CCLK_EN_S) +#define SDHOST_CCLK_EN_V 0x00000001U +#define SDHOST_CCLK_EN_S 23 +/** SDHOST_ULTRA_HIGH_SPEED_MODE : R/W; bitpos: [24]; default: 0; + * Enable ultra high speed mode, use dll to generate clk. + */ +#define SDHOST_ULTRA_HIGH_SPEED_MODE (BIT(24)) +#define SDHOST_ULTRA_HIGH_SPEED_MODE_M (SDHOST_ULTRA_HIGH_SPEED_MODE_V << SDHOST_ULTRA_HIGH_SPEED_MODE_S) +#define SDHOST_ULTRA_HIGH_SPEED_MODE_V 0x00000001U +#define SDHOST_ULTRA_HIGH_SPEED_MODE_S 24 + +/** SDHOST_RAW_INTS_REG register + * SDIO raw ints register. + */ +#define SDHOST_RAW_INTS_REG (DR_REG_SDHOST_BASE + 0x804) +/** SDHOST_RAW_INTS : RO; bitpos: [31:0]; default: 0; + * It indicates raw ints. + */ +#define SDHOST_RAW_INTS 0xFFFFFFFFU +#define SDHOST_RAW_INTS_M (SDHOST_RAW_INTS_V << SDHOST_RAW_INTS_S) +#define SDHOST_RAW_INTS_V 0xFFFFFFFFU +#define SDHOST_RAW_INTS_S 0 + +/** SDHOST_DLL_CLK_CONF_REG register + * SDIO DLL clock control register. + */ +#define SDHOST_DLL_CLK_CONF_REG (DR_REG_SDHOST_BASE + 0x808) +/** SDHOST_DLL_CCLK_IN_SLF_EN : R/W; bitpos: [0]; default: 0; + * Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_SLF_EN (BIT(0)) +#define SDHOST_DLL_CCLK_IN_SLF_EN_M (SDHOST_DLL_CCLK_IN_SLF_EN_V << SDHOST_DLL_CCLK_IN_SLF_EN_S) +#define SDHOST_DLL_CCLK_IN_SLF_EN_V 0x00000001U +#define SDHOST_DLL_CCLK_IN_SLF_EN_S 0 +/** SDHOST_DLL_CCLK_IN_DRV_EN : R/W; bitpos: [1]; default: 0; + * Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_DRV_EN (BIT(1)) +#define SDHOST_DLL_CCLK_IN_DRV_EN_M (SDHOST_DLL_CCLK_IN_DRV_EN_V << SDHOST_DLL_CCLK_IN_DRV_EN_S) +#define SDHOST_DLL_CCLK_IN_DRV_EN_V 0x00000001U +#define SDHOST_DLL_CCLK_IN_DRV_EN_S 1 +/** SDHOST_DLL_CCLK_IN_SAM_EN : R/W; bitpos: [2]; default: 0; + * Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_SAM_EN (BIT(2)) +#define SDHOST_DLL_CCLK_IN_SAM_EN_M (SDHOST_DLL_CCLK_IN_SAM_EN_V << SDHOST_DLL_CCLK_IN_SAM_EN_S) +#define SDHOST_DLL_CCLK_IN_SAM_EN_V 0x00000001U +#define SDHOST_DLL_CCLK_IN_SAM_EN_S 2 +/** SDHOST_DLL_CCLK_IN_SLF_PHASE : R/W; bitpos: [8:3]; default: 0; + * It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_SLF_PHASE 0x0000003FU +#define SDHOST_DLL_CCLK_IN_SLF_PHASE_M (SDHOST_DLL_CCLK_IN_SLF_PHASE_V << SDHOST_DLL_CCLK_IN_SLF_PHASE_S) +#define SDHOST_DLL_CCLK_IN_SLF_PHASE_V 0x0000003FU +#define SDHOST_DLL_CCLK_IN_SLF_PHASE_S 3 +/** SDHOST_DLL_CCLK_IN_DRV_PHASE : R/W; bitpos: [14:9]; default: 0; + * It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_DRV_PHASE 0x0000003FU +#define SDHOST_DLL_CCLK_IN_DRV_PHASE_M (SDHOST_DLL_CCLK_IN_DRV_PHASE_V << SDHOST_DLL_CCLK_IN_DRV_PHASE_S) +#define SDHOST_DLL_CCLK_IN_DRV_PHASE_V 0x0000003FU +#define SDHOST_DLL_CCLK_IN_DRV_PHASE_S 9 +/** SDHOST_DLL_CCLK_IN_SAM_PHASE : R/W; bitpos: [20:15]; default: 0; + * It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ +#define SDHOST_DLL_CCLK_IN_SAM_PHASE 0x0000003FU +#define SDHOST_DLL_CCLK_IN_SAM_PHASE_M (SDHOST_DLL_CCLK_IN_SAM_PHASE_V << SDHOST_DLL_CCLK_IN_SAM_PHASE_S) +#define SDHOST_DLL_CCLK_IN_SAM_PHASE_V 0x0000003FU +#define SDHOST_DLL_CCLK_IN_SAM_PHASE_S 15 + +/** SDHOST_DLL_CONF_REG register + * SDIO DLL configuration register. + */ +#define SDHOST_DLL_CONF_REG (DR_REG_SDHOST_BASE + 0x80c) +/** SDHOST_DLL_CAL_STOP : R/W; bitpos: [0]; default: 0; + * Set 1 to stop calibration. + */ +#define SDHOST_DLL_CAL_STOP (BIT(0)) +#define SDHOST_DLL_CAL_STOP_M (SDHOST_DLL_CAL_STOP_V << SDHOST_DLL_CAL_STOP_S) +#define SDHOST_DLL_CAL_STOP_V 0x00000001U +#define SDHOST_DLL_CAL_STOP_S 0 +/** SDHOST_DLL_CAL_END : RO; bitpos: [1]; default: 0; + * 1 means calibration finished. + */ +#define SDHOST_DLL_CAL_END (BIT(1)) +#define SDHOST_DLL_CAL_END_M (SDHOST_DLL_CAL_END_V << SDHOST_DLL_CAL_END_S) +#define SDHOST_DLL_CAL_END_V 0x00000001U +#define SDHOST_DLL_CAL_END_S 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_struct.h new file mode 100644 index 0000000000..fded1e9eb1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sdmmc_struct.h @@ -0,0 +1,1495 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct sdmmc_desc_s { + struct { + uint32_t reserved1: 1; + uint32_t disable_int_on_completion: 1; + uint32_t last_descriptor: 1; + uint32_t first_descriptor: 1; + uint32_t second_address_chained: 1; + uint32_t end_of_ring: 1; + uint32_t reserved2: 24; + uint32_t card_error_summary: 1; + uint32_t owned_by_idmac: 1; + }; + struct { + uint32_t buffer1_size: 13; + uint32_t buffer2_size: 13; + uint32_t reserved3: 6; + }; + void* buffer1_ptr; + union { + void* buffer2_ptr; + void* next_desc_ptr; + }; + /** + * These `reserved[12]` are for cache alignment. On P4, L1 Cache alignment is 64B. + * For those who want to access the DMA descriptor in a non-cacheable way, you can + * consider remove these `reserved[12]` bytes. + */ + uint32_t reserved[12]; +} sdmmc_desc_t; + +#define SDMMC_DMA_MAX_BUF_LEN 4096 + +#ifndef __cplusplus +_Static_assert(sizeof(sdmmc_desc_t) == 64, "invalid size of sdmmc_desc_t structure"); +#endif + +/** Group: Control register */ +/** Type of ctrl register + * Control register + */ +typedef union { + struct { + /** controller_reset : R/W; bitpos: [0]; default: 0; + * To reset controller, firmware should set this bit. This bit is auto-cleared after + * two AHB and two sdhost_cclk_in clock cycles. + */ + uint32_t controller_reset:1; + /** fifo_reset : R/W; bitpos: [1]; default: 0; + * To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after + * completion of reset operation. + * Note: FIFO pointers will be out of reset after 2 cycles of system clocks in + * addition to synchronization delay (2 cycles of card clock), after the fifo_reset is + * cleared. + */ + uint32_t fifo_reset:1; + /** dma_reset : R/W; bitpos: [2]; default: 0; + * To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared + * after two AHB clocks. + */ + uint32_t dma_reset:1; + uint32_t reserved_3:1; + /** int_enable : R/W; bitpos: [4]; default: 0; + * Global interrupt enable/disable bit. 0: Disable; 1: Enable. + */ + uint32_t int_enable:1; + uint32_t dma_enable:1; + /** read_wait : R/W; bitpos: [6]; default: 0; + * For sending read-wait to SDIO cards. + */ + uint32_t read_wait:1; + /** send_irq_response : R/W; bitpos: [7]; default: 0; + * Bit automatically clears once response is sent. To wait for MMC card interrupts, + * host issues CMD40 and waits for interrupt response from MMC card(s). In the + * meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this + * bit, at which time SD/MMC command state-machine sends CMD40 response on bus and + * returns to idle state. + */ + uint32_t send_irq_response:1; + /** abort_read_data : R/W; bitpos: [8]; default: 0; + * After a suspend-command is issued during a read-operation, software polls the card + * to find when the suspend-event occurred. Once the suspend-event has occurred, + * software sets the bit which will reset the data state machine that is waiting for + * the next block of data. This bit is automatically cleared once the data state + * machine is reset to idle. + */ + uint32_t abort_read_data:1; + /** send_ccsd : R/W; bitpos: [9]; default: 0; + * When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if + * the current command is expecting CCS (that is, RW_BLK), and if interrupts are + * enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC + * automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) + * bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, + * in case the Command Done interrupt is not masked. + * NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive + * the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may + * be sent to the CE-ATA device, even if the device has signalled CCS. + */ + uint32_t send_ccsd:1; + /** send_auto_stop_ccsd : R/W; bitpos: [10]; default: 0; + * Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; + * SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, + * SD/MMC automatically sends an internally-generated STOP command (CMD12) to the + * CE-ATA device. After sending this internally-generated STOP command, the Auto + * Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated + * for the host, in case the ACD interrupt is not masked. After sending the Command + * Completion Signal Disable (CCSD), SD/MMC automatically clears the + * SDHOST_SEND_AUTO_STOP_CCSD bit. + */ + uint32_t send_auto_stop_ccsd:1; + /** ceata_device_interrupt_status : R/W; bitpos: [11]; default: 0; + * Software should appropriately write to this bit after the power-on reset or any + * other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is + * usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, + * then software should set this bit. + */ + uint32_t ceata_device_interrupt_status:1; + uint32_t reserved2:4; + uint32_t card_voltage_a:4; + uint32_t card_voltage_b:4; + uint32_t enable_od_pullup:1; + uint32_t use_internal_dma:1; + uint32_t reserved3:6; + }; + uint32_t val; +} sdhost_ctrl_reg_t; + + +/** Group: Clock divider configuration register */ +/** Type of clkdiv register + * Clock divider configuration register + */ +typedef union { + struct { + /** clk_divider0 : R/W; bitpos: [7:0]; default: 0; + * Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider0:8; + /** clk_divider1 : R/W; bitpos: [15:8]; default: 0; + * Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider1:8; + /** clk_divider2 : R/W; bitpos: [23:16]; default: 0; + * Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider2:8; + /** clk_divider3 : R/W; bitpos: [31:24]; default: 0; + * Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider + * (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF + * means divided by 2*255 = 510, and so on. + */ + uint32_t clk_divider3:8; + }; + uint32_t val; +} sdhost_clkdiv_reg_t; + + +/** Group: Clock source selection register */ +/** Type of clksrc register + * Clock source selection register + */ +typedef union { + struct { + /** clksrc_reg : R/W; bitpos: [3:0]; default: 0; + * Clock divider source for two SD cards is supported. Each card has two bits assigned + * to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for + * card 1. Card 0 maps and internally routes clock divider[0:3] outputs to + * cclk_out[1:0] pins, depending on bit value. + * 00 : Clock divider 0; + * 01 : Clock divider 1; + * 10 : Clock divider 2; + * 11 : Clock divider 3. + */ + uint32_t card0:2; + uint32_t card1:2; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdhost_clksrc_reg_t; + + +/** Group: Clock enable register */ +/** Type of clkena register + * Clock enable register + */ +typedef union { + struct { + /** cclk_enable : R/W; bitpos: [1:0]; default: 0; + * Clock-enable control for two SD card clocks and one MMC card clock is supported. + * One bit per card. + * 0: Clock disabled; + * 1: Clock enabled. + */ + uint32_t cclk_enable:2; + uint32_t reserved_2:14; + /** lp_enable : R/W; bitpos: [17:16]; default: 0; + * Disable clock when the card is in IDLE state. One bit per card. + * 0: clock disabled; + * 1: clock enabled. + */ + uint32_t lp_enable:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_clkena_reg_t; + + +/** Group: Data and response timeout configuration register */ +/** Type of tmout register + * Data and response timeout configuration register + */ +typedef union { + struct { + /** response_timeout : R/W; bitpos: [7:0]; default: 64; + * Response timeout value. Value is specified in terms of number of card output + * clocks, i.e., sdhost_cclk_out. + */ + uint32_t response_timeout:8; + /** data_timeout : R/W; bitpos: [31:8]; default: 16777215; + * Value for card data read timeout. This value is also used for data starvation by + * host timeout. The timeout counter is started only after the card clock is stopped. + * This value is specified in number of card output clocks, i.e. sdhost_cclk_out of + * the selected card. + * NOTE: The software timer should be used if the timeout value is in the order of 100 + * ms. In this case, read data timeout interrupt needs to be disabled. + */ + uint32_t data_timeout:24; + }; + uint32_t val; +} sdhost_tmout_reg_t; + + +/** Group: Card bus width configuration register */ +/** Type of ctype register + * Card bus width configuration register + */ +typedef union { + struct { + /** card_width : R/W; bitpos: [1:0]; default: 0; + * One bit per card indicates if card is 1-bit or 4-bit mode. + * 0: 1-bit mode; + * 1: 4-bit mode. + * Bit[1:0] correspond to card[1:0] respectively. + */ + uint32_t card_width:2; + uint32_t reserved_2:14; + /** card_width_8 : R/W; bitpos: [17:16]; default: 0; + * One bit per card indicates if card is in 8-bit mode. + * 0: Non 8-bit mode; + * 1: 8-bit mode. + * Bit[17:16] correspond to card[1:0] respectively. + */ + uint32_t card_width_8:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_ctype_reg_t; + + +/** Group: Card data block size configuration register */ +/** Type of blksiz register + * Card data block size configuration register + */ +typedef union { + struct { + /** block_size : R/W; bitpos: [15:0]; default: 512; + * Block size. + */ + uint32_t block_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdhost_blksiz_reg_t; + + +/** Group: Data transfer length configuration register */ +/** Type of bytcnt register + * Data transfer length configuration register + */ +typedef union { + struct { + /** byte_count : R/W; bitpos: [31:0]; default: 512; + * Number of bytes to be transferred, should be an integral multiple of Block Size for + * block transfers. For data transfers of undefined byte lengths, byte count should be + * set to 0. When byte count is set to 0, it is the responsibility of host to + * explicitly send stop/abort command to terminate data transfer. + */ + uint32_t byte_count:32; + }; + uint32_t val; +} sdhost_bytcnt_reg_t; + + +/** Group: SDIO interrupt mask register */ +/** Type of intmask register + * SDIO interrupt mask register + */ +typedef union { + struct { + /** int_mask : R/W; bitpos: [15:0]; default: 0; + * These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a + * value of 1 enables the interrupt. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): Rx Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation-by-host timeout; + * Bit 9 (DRTO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t int_mask:16; + /** sdio_int_mask : R/W; bitpos: [17:16]; default: 0; + * SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] + * respectively. When masked, SDIO interrupt detection for that card is disabled. 0 + * masks an interrupt, and 1 enables an interrupt. + */ + uint32_t sdio_int_mask:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_intmask_reg_t; + + +/** Group: Command and boot configuration register */ +/** Type of cmd register + * Command and boot configuration register + */ +typedef union { + struct { + /** cmd_index : R/W; bitpos: [5:0]; default: 0; + * Command index. + */ + uint32_t cmd_index:6; + /** response_expect : R/W; bitpos: [6]; default: 0; + * 0: No response expected from card; 1: Response expected from card. + */ + uint32_t response_expect:1; + /** response_long : R/W; bitpos: [7]; default: 0; + * 0: Short response expected from card; 1: Long response expected from card. + */ + uint32_t response_long:1; + /** check_response_crc : R/W; bitpos: [8]; default: 0; + * 0: Do not check; 1: Check response CRC. + * Some of command responses do not return valid CRC bits. Software should disable CRC + * checks for those commands in order to disable CRC checking by controller. + */ + uint32_t check_response_crc:1; + /** data_expected : R/W; bitpos: [9]; default: 0; + * 0: No data transfer expected; 1: Data transfer expected. + */ + uint32_t data_expected:1; + /** rw : R/W; bitpos: [10]; default: 0; + * 0: Read from card; 1: Write to card. + * Don't care if no data is expected from card. + */ + uint32_t rw:1; + /** transfer_mode : R/W; bitpos: [11]; default: 0; + * 0: Block data transfer command; 1: Stream data transfer command. + * Don't care if no data expected. + */ + uint32_t transfer_mode:1; + /** send_auto_stop : R/W; bitpos: [12]; default: 0; + * 0: No stop command is sent at the end of data transfer; 1: Send stop command at the + * end of data transfer. + */ + uint32_t send_auto_stop:1; + /** wait_complete : R/W; bitpos: [13]; default: 0; + * 0: Send command at once, even if previous data transfer has not completed; 1: Wait + * for previous data transfer to complete before sending Command. + * The SDHOST_WAIT_COMPLETE] = 0 option is typically used to query status of + * card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr + * should be same as in previous command. + */ + uint32_t wait_complete:1; + /** stop_abort_cmd : R/W; bitpos: [14]; default: 0; + * 0: Neither stop nor abort command can stop current data transfer. If abort is sent + * to function-number currently selected or not in data-transfer mode, then bit should + * be set to 0; 1: Stop or abort command intended to stop current data transfer in + * progress. + * When open-ended or predefined data transfer is in progress, and host issues stop or + * abort command to stop data transfer, bit should be set so that command/data + * state-machines of CIU can return correctly to idle state. + */ + uint32_t stop_abort_cmd:1; + /** send_init : R/W; bitpos: [15]; default: 0; + * 0: Do not send initialization sequence (80 clocks of 1) before sending this + * command; 1: Send initialization sequence before sending this command. + * After powered on, 80 clocks must be sent to card for initialization before sending + * any commands to card. Bit should be set while sending first command to card so that + * controller will initialize clocks before sending command to card. + */ + uint32_t send_init:1; + /** card_num : R/W; bitpos: [20:16]; default: 0; + * Card number in use. Represents physical slot number of card being accessed. In + * SD-only mode, up to two cards are supported. + */ + uint32_t card_num:5; + /** update_clk_reg : R/W; bitpos: [21]; default: 0; + * 0: Normal command sequence; 1: Do not send commands, just update clock register + * value into card clock domain. + * Following register values are transferred into card clock domain: CLKDIV, CLRSRC, + * and CLKENA. + * Changes card clocks (change frequency, truncate off or on, and set low-frequency + * mode). This is provided in order to change clock frequency or stop clock without + * having to send command to cards. During normal command sequence, when + * sdhost_update_clock_registers_only = 0, following control registers are transferred + * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new + * register values for new command sequence to card(s). When bit is set, there are no + * Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + */ + uint32_t update_clk_reg:1; + /** read_ceata_device : R/W; bitpos: [22]; default: 0; + * Read access flag. + * 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; + * 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. + * Software should set this bit to indicate that CE-ATA device is being accessed for + * read transfer. This bit is used to disable read data timeout indication while + * performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no + * less than 10 seconds. SD/MMC should not indicate read data timeout while waiting + * for data from CE-ATA device. + */ + uint32_t read_ceata_device:1; + /** ccs_expected : R/W; bitpos: [23]; default: 0; + * Expected Command Completion Signal (CCS) configuration. + * 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), + * or command does not expect CCS from device; + * 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects + * command completion signal from CE-ATA device. + * If the command expects Command Completion Signal (CCS) from the CE-ATA device, the + * software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in + * RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is + * not masked. + */ + uint32_t ccs_expected:1; + uint32_t reserved_24:4; + /** volt_switch : R/W; bitpos: [28]; default: 0; + * Voltage switch bit. + * 0: No voltage switching. + * 1: Voltage switching enabled; must be set for CMD11 only. + */ + uint32_t volt_switch:1; + /** use_hole_reg : R/W; bitpos: [29]; default: 1; + * Use Hold Register. + * 0: CMD and DATA sent to card bypassing HOLD Register; + * 1: CMD and DATA sent to card through the HOLD Register. + */ + uint32_t use_hold_reg:1; + uint32_t reserved_30:1; + /** start_command : R/W; bitpos: [31]; default: 0; + * Start command. Once command is served by the CIU, this bit is automatically + * cleared. When this bit is set, host should not attempt to write to any command + * registers. If a write is attempted, hardware lock error is set in raw interrupt + * register. Once command is sent and a response is received from SD_MMC_CEATA cards, + * Command Done bit is set in the raw interrupt Register. + */ + uint32_t start_command:1; + }; + uint32_t val; +} sdhost_cmd_reg_t; + + +/** Group: Response data register */ +/** Type of resp0 register + * Response data register + */ +typedef union { + struct { + /** response0_reg : RO; bitpos: [31:0]; default: 0; + * Bit[31:0] of response. + */ + uint32_t response0_reg:32; + }; + uint32_t val; +} sdhost_resp0_reg_t; + + +/** Group: Long response data register */ +/** Type of resp1 register + * Long response data register + */ +typedef union { + struct { + /** response1_reg : RO; bitpos: [31:0]; default: 0; + * Bit[63:32] of long response. + */ + uint32_t response1_reg:32; + }; + uint32_t val; +} sdhost_resp1_reg_t; + +/** Type of resp2 register + * Long response data register + */ +typedef union { + struct { + /** response2_reg : RO; bitpos: [31:0]; default: 0; + * Bit[95:64] of long response. + */ + uint32_t response2_reg:32; + }; + uint32_t val; +} sdhost_resp2_reg_t; + +/** Type of resp3 register + * Long response data register + */ +typedef union { + struct { + /** response3_reg : RO; bitpos: [31:0]; default: 0; + * Bit[127:96] of long response. + */ + uint32_t response3_reg:32; + }; + uint32_t val; +} sdhost_resp3_reg_t; + + +/** Group: Masked interrupt status register */ +/** Type of mintsts register + * Masked interrupt status register + */ +typedef union { + struct { + /** int_status_msk : RO; bitpos: [15:0]; default: 0; + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t int_status_msk:16; + /** sdio_interrupt_msk : RO; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. SDIO interrupt for card is enabled only if corresponding + * sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit + * enables interrupt). + */ + uint32_t sdio_interrupt_msk:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_mintsts_reg_t; + + +/** Group: Raw interrupt status register */ +/** Type of rintsts register + * Raw interrupt status register + */ +typedef union { + struct { + /** int_status_raw : R/W; bitpos: [15:0]; default: 0; + * Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits + * are logged regardless of interrupt mask status. + * Bit 15 (EBE): End-bit error/no CRC error; + * Bit 14 (ACD): Auto command done; + * Bit 13 (SBE/BCI): RX Start Bit Error; + * Bit 12 (HLE): Hardware locked write error; + * Bit 11 (FRUN): FIFO underrun/overrun error; + * Bit 10 (HTO): Data starvation by host timeout (HTO); + * Bit 9 (DTRO): Data read timeout; + * Bit 8 (RTO): Response timeout; + * Bit 7 (DCRC): Data CRC error; + * Bit 6 (RCRC): Response CRC error; + * Bit 5 (RXDR): Receive FIFO data request; + * Bit 4 (TXDR): Transmit FIFO data request; + * Bit 3 (DTO): Data transfer over; + * Bit 2 (CD): Command done; + * Bit 1 (RE): Response error; + * Bit 0 (CD): Card detect. + */ + uint32_t cd:1; + uint32_t re:1; + uint32_t cmd_done:1; + uint32_t dto:1; + uint32_t txdr:1; + uint32_t rxdr:1; + uint32_t rcrc:1; + uint32_t dcrc:1; + uint32_t rto:1; + uint32_t drto:1; + uint32_t hto:1; + uint32_t frun:1; + uint32_t hle:1; + uint32_t sbi_bci:1; + uint32_t acd:1; + uint32_t ebe:1; + /** sdio_interrupt_raw : R/W; bitpos: [17:16]; default: 0; + * Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and + * card0, respectively. Setting a bit clears the corresponding interrupt bit and + * writing 0 has no effect. + * 0: No SDIO interrupt from card; + * 1: SDIO interrupt from card. + */ + uint32_t sdio_interrupt_raw:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_rintsts_reg_t; + + +/** Group: SD/MMC status register */ +/** Type of status register + * SD/MMC status register + */ +typedef union { + struct { + /** fifo_rx_watermark : RO; bitpos: [0]; default: 0; + * FIFO reached Receive watermark level, not qualified with data transfer. + */ + uint32_t fifo_rx_watermark:1; + /** fifo_tx_watermark : RO; bitpos: [1]; default: 1; + * FIFO reached Transmit watermark level, not qualified with data transfer. + */ + uint32_t fifo_tx_watermark:1; + /** fifo_empty : RO; bitpos: [2]; default: 1; + * FIFO is empty status. + */ + uint32_t fifo_empty:1; + /** fifo_full : RO; bitpos: [3]; default: 0; + * FIFO is full status. + */ + uint32_t fifo_full:1; + /** command_fsm_states : RO; bitpos: [7:4]; default: 1; + * Command FSM states. + * 0: Idle; + * 1: Send init sequence; + * 2: Send cmd start bit; + * 3: Send cmd tx bit; + * 4: Send cmd index + arg; + * 5: Send cmd crc7; + * 6: Send cmd end bit; + * 7: Receive resp start bit; + * 8: Receive resp IRQ response; + * 9: Receive resp tx bit; + * 10: Receive resp cmd idx; + * 11: Receive resp data; + * 12: Receive resp crc7; + * 13: Receive resp end bit; + * 14: Cmd path wait NCC; + * 15: Wait, cmd-to-response turnaround. + */ + uint32_t command_fsm_states:4; + /** data_3_status : RO; bitpos: [8]; default: 1; + * Raw selected sdhost_card_data[3], checks whether card is present. + * 0: card not present; + * 1: card present. + */ + uint32_t data_3_status:1; + /** data_busy : RO; bitpos: [9]; default: 1; + * Inverted version of raw selected sdhost_card_data[0]. + * 0: Card data not busy; + * 1: Card data busy. + */ + uint32_t data_busy:1; + /** data_state_mc_busy : RO; bitpos: [10]; default: 1; + * Data transmit or receive state-machine is busy. + */ + uint32_t data_state_mc_busy:1; + /** response_index : RO; bitpos: [16:11]; default: 0; + * Index of previous response, including any auto-stop sent by core. + */ + uint32_t response_index:6; + /** fifo_count : RO; bitpos: [29:17]; default: 0; + * FIFO count, number of filled locations in FIFO. + */ + uint32_t fifo_count:13; + uint32_t reserved_30:2; + }; + uint32_t val; +} sdhost_status_reg_t; + + +/** Group: FIFO configuration register */ +/** Type of fifoth register + * FIFO configuration register + */ +typedef union { + struct { + /** tx_wmark : R/W; bitpos: [11:0]; default: 0; + * FIFO threshold watermark level when transmitting data to card. When FIFO data count + * is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is + * enabled, then interrupt occurs. During end of packet, request or interrupt is + * generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO + * threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA + * request. During end of packet, on last interrupt, host is responsible for filling + * FIFO with only required remaining bytes (not before FIFO is full or after CIU + * completes data transfers, because FIFO may not be empty). In DMA mode, at end of + * packet, if last transfer is less than burst size, DMA controller does single + * cycles until required bytes are transferred. + */ + uint32_t tx_wmark:12; + uint32_t reserved_12:4; + /** rx_wmark : R/W; bitpos: [26:16]; default: 0; + * FIFO threshold watermark level when receiving data to card.When FIFO data count + * reaches greater than this number , DMA/FIFO request is raised. During end of + * packet, request is generated regardless of threshold programming in order to + * complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) + * interrupt is enabled, then interrupt is generated instead of DMA request.During end + * of packet, interrupt is not generated if threshold programming is larger than any + * remaining data. It is responsibility of host to read remaining bytes on seeing Data + * Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are + * less than threshold, DMA request does single transfers to flush out any remaining + * bytes before Data Transfer Done interrupt is set. + */ + uint32_t rx_wmark:11; + uint32_t reserved_27:1; + /** dma_multiple_transaction_size : R/W; bitpos: [30:28]; default: 0; + * Burst size of multiple transaction, should be programmed same as DMA controller + * multiple-transaction-size SDHOST_SRC/DEST_MSIZE. + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + */ + uint32_t dma_multiple_transaction_size:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdhost_fifoth_reg_t; + + +/** Group: Card detect register */ +/** Type of cdetect register + * Card detect register + */ +typedef union { + struct { + /** card_detect_n : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 + * represents presence of card. Only NUM_CARDS number of bits are implemented. + */ + uint32_t card_detect_n:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_cdetect_reg_t; + + +/** Group: Card write protection (WP) status register */ +/** Type of wrtprt register + * Card write protection (WP) status register + */ +typedef union { + struct { + /** write_protect : RO; bitpos: [1:0]; default: 0; + * Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write + * protection. Only NUM_CARDS number of bits are implemented. + */ + uint32_t write_protect:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_wrtprt_reg_t; + + +/** Group: Transferred byte count register */ +/** Type of tcbcnt register + * Transferred byte count register + */ +typedef union { + struct { + /** tcbcnt_reg : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred by CIU unit to card. + */ + uint32_t tcbcnt_reg:32; + }; + uint32_t val; +} sdhost_tcbcnt_reg_t; + +/** Type of tbbcnt register + * Transferred byte count register + */ +typedef union { + struct { + /** tbbcnt_reg : RO; bitpos: [31:0]; default: 0; + * Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ + uint32_t tbbcnt_reg:32; + }; + uint32_t val; +} sdhost_tbbcnt_reg_t; + + +/** Group: Debounce filter time configuration register */ +/** Type of debnce register + * Debounce filter time configuration register + */ +typedef union { + struct { + /** debounce_count : R/W; bitpos: [23:0]; default: 0; + * Number of host clocks (clk) used by debounce filter logic. The typical debounce + * time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted + * or removed. + */ + uint32_t debounce_count:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdhost_debnce_reg_t; + + +/** Group: User ID (scratchpad) register */ +/** Type of usrid register + * User ID (scratchpad) register + */ +typedef union { + struct { + /** usrid_reg : R/W; bitpos: [31:0]; default: 0; + * User identification register, value set by user. Can also be used as a scratchpad + * register by user. + */ + uint32_t usrid_reg:32; + }; + uint32_t val; +} sdhost_usrid_reg_t; + + +/** Group: Hardware feature register */ +/** Type of hcon register + * Hardware feature register + */ +typedef union { + struct { + /** card_type_reg : RO; bitpos: [0]; default: 1; + * Hardware support SDIO and MMC. + */ + uint32_t card_type_reg:1; + /** card_num_reg : RO; bitpos: [5:1]; default: 1; + * Support card number is 2. + */ + uint32_t card_num_reg:5; + /** bus_type_reg : RO; bitpos: [6]; default: 1; + * Register config is APB bus. + */ + uint32_t bus_type_reg:1; + /** data_width_reg : RO; bitpos: [9:7]; default: 1; + * Regisger data width is 32. + */ + uint32_t data_width_reg:3; + /** addr_width_reg : RO; bitpos: [15:10]; default: 19; + * Register address width is 32. + */ + uint32_t addr_width_reg:6; + uint32_t reserved_16:2; + /** dma_width_reg : RO; bitpos: [20:18]; default: 1; + * DMA data width is 32. + */ + uint32_t dma_width_reg:3; + /** ram_indise_reg : RO; bitpos: [21]; default: 0; + * Inside RAM in SDMMC module. + */ + uint32_t ram_indise_reg:1; + /** hold_reg : RO; bitpos: [22]; default: 1; + * Have a hold register in data path . + */ + uint32_t hold_reg:1; + uint32_t reserved_23:1; + /** num_clk_div_reg : RO; bitpos: [25:24]; default: 3; + * Have 4 clk divider in design . + */ + uint32_t num_clk_div_reg:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdhost_hcon_reg_t; + + +/** Group: UHS-1 register */ +/** Type of uhs register + * UHS-1 register + */ +typedef union { + struct { + /** volt: R/W; bitpos: [1:0]; default: 0; + * Voltage mode selection, 1 bit for each card. On the ESP32-P4, this bit doesn't do anything, I/O voltage is controlled using LDO API instead. + * 0: 3.3V mode. + * 1: 1.8V mode. + */ + uint32_t volt:2; + uint32_t reserved_0:14; + /** ddr: R/W; bitpos: [17:16]; default: 0; + * DDR mode selection, 1 bit for each card. + * 0: Non-DDR mode. + * 1: DDR mode. + */ + uint32_t ddr:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdhost_uhs_reg_t; + + +/** Group: Card reset register */ +/** Type of rst_n register + * Card reset register + */ +typedef union { + struct { + /** card_reset : R/W; bitpos: [1:0]; default: 1; + * Hardware reset. + * 1: Active mode; + * 0: Reset. + * These bits cause the cards to enter pre-idle state, which requires them to be + * re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, + * SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + */ + uint32_t card_reset:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_rst_n_reg_t; + + +/** Group: Burst mode transfer configuration register */ +/** Type of bmod register + * Burst mode transfer configuration register + */ +typedef union { + struct { + /** sw_reset : R/W; bitpos: [0]; default: 0; + * Software Reset. When set, the DMA Controller resets all its internal registers. It + * is automatically cleared after one clock cycle. + */ + uint32_t sw_reset:1; + /** fb : R/W; bitpos: [1]; default: 0; + * Fixed Burst. Controls whether the AHB Master interface performs fixed burst + * transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 + * during start of normal burst transfers. When reset, the AHB will use SINGLE and + * INCR burst transfer operations. + */ + uint32_t fb:1; + uint32_t reserved_2:5; + /** enable : R/W; bitpos: [7]; default: 0; + * IDMAC Enable. When set, the IDMAC is enabled. + */ + uint32_t enable:1; + /** bmod_pbl : R/W; bitpos: [10:8]; default: 0; + * Programmable Burst Length. These bits indicate the maximum number of beats to be + * performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always + * attempt to burst as specified in PBL each time it starts a burst transfer on the + * host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value + * is the mirror of MSIZE of FIFOTH register. In order to change this value, write the + * required value to FIFOTH register. This is an encode value as follows: + * 000: 1-byte transfer; + * 001: 4-byte transfer; + * 010: 8-byte transfer; + * 011: 16-byte transfer; + * 100: 32-byte transfer; + * 101: 64-byte transfer; + * 110: 128-byte transfer; + * 111: 256-byte transfer. + * PBL is a read-only value and is applicable only for data access, it does not apply + * to descriptor access. + */ + uint32_t bmod_pbl:3; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdhost_bmod_reg_t; + + +/** Group: Poll demand configuration register */ +/** Type of pldmnd register + * Poll demand configuration register + */ +typedef union { + struct { + /** pldmnd_pd : WO; bitpos: [31:0]; default: 0; + * Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the + * Suspend state. The host needs to write any value into this register for the IDMAC + * FSM to resume normal descriptor fetch operation. This is a write only . + */ + uint32_t pldmnd_pd:32; + }; + uint32_t val; +} sdhost_pldmnd_reg_t; + + +/** Group: Descriptor base address register */ +/** Type of dbaddr register + * Descriptor base address register + */ +typedef union { + struct { + /** dbaddr_reg : R/W; bitpos: [31:0]; default: 0; + * Start of Descriptor List. Contains the base address of the First Descriptor. The + * LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence + * these LSB bits may be treated as read-only. + */ + uint32_t dbaddr_reg:32; + }; + uint32_t val; +} sdhost_dbaddr_reg_t; + + +/** Group: IDMAC status register */ +/** Type of idsts register + * IDMAC status register + */ +typedef union { + struct { + /** idsts_ti : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt. Indicates that data transmission is finished for a descriptor. + * Writing 1 clears this bit. + */ + uint32_t idsts_ti:1; + /** idsts_ri : R/W; bitpos: [1]; default: 0; + * Receive Interrupt. Indicates the completion of data reception for a descriptor. + * Writing 1 clears this bit. + */ + uint32_t idsts_ri:1; + /** idsts_fbe : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . + * When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this + * bit. + */ + uint32_t idsts_fbe:1; + uint32_t reserved_3:1; + /** idsts_du : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. This bit is set when the descriptor is + * unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + */ + uint32_t idsts_du:1; + /** idsts_ces : R/W; bitpos: [5]; default: 0; + * Card Error Summary. Indicates the status of the transaction to/from the card, also + * present in RINTSTS. Indicates the logical OR of the following bits: + * EBE : End Bit Error; + * RTO : Response Timeout/Boot Ack Timeout; + * RCRC : Response CRC; + * SBE : Start Bit Error; + * DRTO : Data Read Timeout/BDS timeout; + * DCRC : Data CRC for Receive; + * RE : Response Error. + * Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting + * of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response + * error. + */ + uint32_t idsts_ces:1; + uint32_t reserved_6:2; + /** idsts_nis : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit + * Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This + * is a sticky bit and must be cleared each time a corresponding bit that causes NIS + * to be set is cleared. Writing 1 clears this bit. + */ + uint32_t idsts_nis:1; + /** idsts_ais : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus + * Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is + * a sticky bit and must be cleared each time a corresponding bit that causes AIS to + * be set is cleared. Writing 1 clears this bit. + */ + uint32_t idsts_ais:1; + /** idsts_fbe_code : R/W; bitpos: [12:10]; default: 0; + * Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid + * only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an + * interrupt. + * 001: Host Abort received during transmission; + * 010: Host Abort received during reception; + * Others: Reserved. + */ + uint32_t idsts_fbe_code:3; + /** idsts_fsm : R/W; bitpos: [16:13]; default: 0; + * DMAC FSM present state. + * 0: DMA_IDLE (idle state); + * 1: DMA_SUSPEND (suspend state); + * 2: DESC_RD (descriptor reading state); + * 3: DESC_CHK (descriptor checking state); + * 4: DMA_RD_REQ_WAIT (read-data request waiting state); + * 5: DMA_WR_REQ_WAIT (write-data request waiting state); + * 6: DMA_RD (data-read state); + * 7: DMA_WR (data-write state); + * 8: DESC_CLOSE (descriptor close state). + */ + uint32_t idsts_fsm:4; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdhost_idsts_reg_t; + + +/** Group: IDMAC interrupt enable register */ +/** Type of idinten register + * IDMAC interrupt enable register + */ +typedef union { + struct { + /** ti : R/W; bitpos: [0]; default: 0; + * Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit + * Interrupt is enabled. When reset, Transmit Interrupt is disabled. + */ + uint32_t ti:1; + /** ri : R/W; bitpos: [1]; default: 0; + * Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive + * Interrupt is enabled. When reset, Receive Interrupt is disabled. + */ + uint32_t ri:1; + /** idinten_fbe : R/W; bitpos: [2]; default: 0; + * Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal + * Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is + * disabled. + */ + uint32_t idinten_fbe:1; + uint32_t reserved_3:1; + /** idinten_du : R/W; bitpos: [4]; default: 0; + * Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary + * Enable, the DU interrupt is enabled. + */ + uint32_t idinten_du:1; + /** idinten_ces : R/W; bitpos: [5]; default: 0; + * Card Error summary Interrupt Enable. When set, it enables the Card Interrupt + * summary. + */ + uint32_t idinten_ces:1; + uint32_t reserved_6:2; + /** ni : R/W; bitpos: [8]; default: 0; + * Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When + * reset, a normal interrupt is disabled. This bit enables the following bits: + * IDINTEN[0]: Transmit Interrupt; + * IDINTEN[1]: Receive Interrupt. + */ + uint32_t ni:1; + /** idinten_ai : R/W; bitpos: [9]; default: 0; + * Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This + * bit enables the following bits: + * IDINTEN[2]: Fatal Bus Error Interrupt; + * IDINTEN[4]: DU Interrupt. + */ + uint32_t idinten_ai:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdhost_idinten_reg_t; + + +/** Group: Host descriptor address pointer */ +/** Type of dscaddr register + * Host descriptor address pointer + */ +typedef union { + struct { + /** dscaddr_reg : RO; bitpos: [31:0]; default: 0; + * Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the start address of the current descriptor read by + * the IDMAC. + */ + uint32_t dscaddr_reg:32; + }; + uint32_t val; +} sdhost_dscaddr_reg_t; + + +/** Group: Host buffer address pointer register */ +/** Type of bufaddr register + * Host buffer address pointer register + */ +typedef union { + struct { + /** bufaddr_reg : RO; bitpos: [31:0]; default: 0; + * Host Buffer Address Pointer, updated by IDMAC during operation and cleared on + * reset. This register points to the current Data Buffer Address being accessed by + * the IDMAC. + */ + uint32_t bufaddr_reg:32; + }; + uint32_t val; +} sdhost_bufaddr_reg_t; + + +/** Group: Card Threshold Control register */ +/** Type of cardthrctl register + * Card Threshold Control register + */ +typedef union { + struct { + /** cardrdthren_reg : R/W; bitpos: [0]; default: 0; + * Card read threshold enable. + * 1'b0-Card read threshold disabled. + * 1'b1-Card read threshold enabled. + */ + uint32_t cardrdthren_reg:1; + /** busy_clr_int_en : R/W; bitpos: [1]; default: 0; + * Busy clear interrupt generation: + * 1'b0-Busy clear interrypt disabled. + * 1'b1-Busy clear interrypt enabled. + */ + uint32_t busy_clr_int_en:1; + /** cardwrthren_reg : R/W; bitpos: [2]; default: 0; + * Applicable when HS400 mode is enabled. + * 1'b0-Card write Threshold disabled. + * 1'b1-Card write Threshold enabled. + */ + uint32_t cardwrthren_reg:1; + uint32_t reserved_3:13; + /** cardthreshold_reg : R/W; bitpos: [31:16]; default: 0; + * The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG + * is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + */ + uint32_t cardthreshold_reg:16; + }; + uint32_t val; +} sdhost_cardthrctl_reg_t; + + +/** Group: eMMC DDR register */ +/** Type of emmcddr register + * eMMC DDR register + */ +typedef union { + struct { + /** halfstartbit_reg : R/W; bitpos: [1:0]; default: 0; + * Control for start bit detection mechanism duration of start bit.Each bit refers to + * one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For + * eMMC4.5,start bit can be: + * 1'b0-Full cycle. + * 1'b1-less than one full cycle. + */ + uint32_t halfstartbit_reg:2; + uint32_t reserved_2:29; + /** hs400_mode_reg : R/W; bitpos: [31]; default: 0; + * Set 1 to enable HS400 mode. + */ + uint32_t hs400_mode_reg:1; + }; + uint32_t val; +} sdhost_emmcddr_reg_t; + + +/** Group: Enable Phase Shift register */ +/** Type of enshift register + * Enable Phase Shift register + */ +typedef union { + struct { + /** enable_shift_reg : R/W; bitpos: [3:0]; default: 0; + * Control for the amount of phase shift provided on the default enables in the + * design.Two bits assigned for each card. + * 2'b00-Default phase shift. + * 2'b01-Enables shifted to next immediate positive edge. + * 2'b10-Enables shifted to next immediate negative edge. + * 2'b11-Reserved. + */ + uint32_t enable_shift_reg:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdhost_enshift_reg_t; + + +/** Group: CPU write and read transmit data by FIFO */ +/** Type of buffifo register + * CPU write and read transmit data by FIFO + */ +typedef union { + struct { + /** buffifo_reg : R/W; bitpos: [31:0]; default: 0; + * CPU write and read transmit data by FIFO. This register points to the current Data + * FIFO . + */ + uint32_t buffifo_reg:32; + }; + uint32_t val; +} sdhost_buffifo_reg_t; + + +/** Group: SDIO Control and configuration registers */ +/** Type of clk_edge_sel register + * SDIO control register. + */ +typedef union { + struct { + /** cclkin_edge_drv_sel : R/W; bitpos: [2:0]; default: 0; + * It's used to select the clock phase of the output signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_drv_sel:3; + /** cclkin_edge_sam_sel : R/W; bitpos: [5:3]; default: 0; + * It's used to select the clock phase of the input signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_sam_sel:3; + /** cclkin_edge_slf_sel : R/W; bitpos: [8:6]; default: 0; + * It's used to select the clock phase of the internal signal from phase 0, phase 90, + * phase 180, phase 270. + */ + uint32_t cclkin_edge_slf_sel:3; + /** ccllkin_edge_h : R/W; bitpos: [12:9]; default: 1; + * The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + */ + uint32_t ccllkin_edge_h:4; + /** ccllkin_edge_l : R/W; bitpos: [16:13]; default: 0; + * The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + */ + uint32_t ccllkin_edge_l:4; + /** ccllkin_edge_n : R/W; bitpos: [20:17]; default: 1; + * The clock division of cclk_in. + */ + uint32_t ccllkin_edge_n:4; + /** esdio_mode : R/W; bitpos: [21]; default: 0; + * Enable esdio mode. + */ + uint32_t esdio_mode:1; + /** esd_mode : R/W; bitpos: [22]; default: 0; + * Enable esd mode. + */ + uint32_t esd_mode:1; + /** cclk_en : R/W; bitpos: [23]; default: 1; + * Sdio clock enable. + */ + uint32_t cclk_en:1; + /** ultra_high_speed_mode : R/W; bitpos: [24]; default: 0; + * Enable ultra high speed mode, use dll to generate clk. + */ + uint32_t ultra_high_speed_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdhost_clk_edge_sel_reg_t; + + +/** Group: SDIO raw ints registers */ +/** Type of raw_ints register + * SDIO raw ints register. + */ +typedef union { + struct { + /** raw_ints : RO; bitpos: [31:0]; default: 0; + * It indicates raw ints. + */ + uint32_t raw_ints:32; + }; + uint32_t val; +} sdhost_raw_ints_reg_t; + + +/** Group: SDIO dll clock control registers */ +/** Type of dll_clk_conf register + * SDIO DLL clock control register. + */ +typedef union { + struct { + /** dll_cclk_in_slf_en : R/W; bitpos: [0]; default: 0; + * Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_slf_en:1; + /** dll_cclk_in_drv_en : R/W; bitpos: [1]; default: 0; + * Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_drv_en:1; + /** dll_cclk_in_sam_en : R/W; bitpos: [2]; default: 0; + * Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_sam_en:1; + /** dll_cclk_in_slf_phase : R/W; bitpos: [8:3]; default: 0; + * It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_slf_phase:6; + /** dll_cclk_in_drv_phase : R/W; bitpos: [14:9]; default: 0; + * It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_drv_phase:6; + /** dll_cclk_in_sam_phase : R/W; bitpos: [20:15]; default: 0; + * It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + */ + uint32_t dll_cclk_in_sam_phase:6; + uint32_t reserved_21:11; + }; + uint32_t val; +} sdhost_dll_clk_conf_reg_t; + + +/** Group: SDIO dll configuration registers */ +/** Type of dll_conf register + * SDIO DLL configuration register. + */ +typedef union { + struct { + /** dll_cal_stop : R/W; bitpos: [0]; default: 0; + * Set 1 to stop calibration. + */ + uint32_t dll_cal_stop:1; + /** dll_cal_end : RO; bitpos: [1]; default: 0; + * 1 means calibration finished. + */ + uint32_t dll_cal_end:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} sdhost_dll_conf_reg_t; + + +typedef struct sdmmc_dev_t { + volatile sdhost_ctrl_reg_t ctrl; + uint32_t reserved_004; + volatile sdhost_clkdiv_reg_t clkdiv; + volatile sdhost_clksrc_reg_t clksrc; + volatile sdhost_clkena_reg_t clkena; + volatile sdhost_tmout_reg_t tmout; + volatile sdhost_ctype_reg_t ctype; + volatile sdhost_blksiz_reg_t blksiz; + volatile sdhost_bytcnt_reg_t bytcnt; + volatile sdhost_intmask_reg_t intmask; + volatile uint32_t cmdarg; + volatile sdhost_cmd_reg_t cmd; + volatile uint32_t resp[4]; ///< Response from card + volatile sdhost_mintsts_reg_t mintsts; + volatile sdhost_rintsts_reg_t rintsts; + volatile sdhost_status_reg_t status; + volatile sdhost_fifoth_reg_t fifoth; + volatile sdhost_cdetect_reg_t cdetect; + volatile sdhost_wrtprt_reg_t wrtprt; + uint32_t reserved_058; + volatile sdhost_tcbcnt_reg_t tcbcnt; + volatile sdhost_tbbcnt_reg_t tbbcnt; + volatile sdhost_debnce_reg_t debnce; + volatile sdhost_usrid_reg_t usrid; + volatile uint32_t verid; + volatile sdhost_hcon_reg_t hcon; + volatile sdhost_uhs_reg_t uhs; + volatile sdhost_rst_n_reg_t rst_n; + uint32_t reserved_07c; + volatile sdhost_bmod_reg_t bmod; + volatile sdhost_pldmnd_reg_t pldmnd; + volatile sdhost_dbaddr_reg_t dbaddr; + volatile sdhost_idsts_reg_t idsts; + volatile sdhost_idinten_reg_t idinten; + volatile sdhost_dscaddr_reg_t dscaddr; + volatile sdhost_bufaddr_reg_t bufaddr; + uint32_t reserved_09c[25]; + volatile sdhost_cardthrctl_reg_t cardthrctl; + uint32_t reserved_104[2]; + volatile sdhost_emmcddr_reg_t emmcddr; + volatile sdhost_enshift_reg_t enshift; + uint32_t reserved_114[59]; + volatile sdhost_buffifo_reg_t buffifo; + uint32_t reserved_204[383]; + volatile sdhost_clk_edge_sel_reg_t clk_edge_sel; + volatile sdhost_raw_ints_reg_t raw_ints; + volatile sdhost_dll_clk_conf_reg_t dll_clk_conf; + volatile sdhost_dll_conf_reg_t dll_conf; +} sdmmc_dev_t; + +extern sdmmc_dev_t SDMMC; + +typedef sdhost_cmd_reg_t sdmmc_hw_cmd_t; + +#ifndef __cplusplus +_Static_assert(sizeof(sdmmc_dev_t) == 0x810, "Invalid size of sdmmc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sha_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/sha_eco5_reg.h new file mode 100644 index 0000000000..f417aadeff --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sha_eco5_reg.h @@ -0,0 +1,170 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Configures SHA algorithm + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA-224 + * 2: SHA-256 + * 3: SHA2-384 + * 4: SHA2-512 + * 5: SHA2-512/224 + * 6: SHA2-512/256 + * 7: SHA2-512/t + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0; + * Configures the DMA-SHA block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000FFFFU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start Typical SHA calculation. + */ +#define SHA_START (BIT(0)) +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x00000001U +#define SHA_START_S 0 + +/** SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ +#define SHA_CONTINUE (BIT(0)) +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x00000001U +#define SHA_CONTINUE_S 0 + +/** SHA_BUSY_REG register + * Represents if SHA Accelerator is busy or not + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * DMA-SHA interrupt clear register + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * DMA-SHA interrupt enable register + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Version control register + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291; + * Version control register. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_DMA_RX_RESET_REG register + * DMA RX FIFO Reset Signal + */ +#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30) +/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ +#define SHA_DMA_RX_RESET (BIT(0)) +#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S) +#define SHA_DMA_RX_RESET_V 0x00000001U +#define SHA_DMA_RX_RESET_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or final hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 128 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sha_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/sha_reg.h new file mode 100644 index 0000000000..add9873601 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sha_reg.h @@ -0,0 +1,172 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Initial configuration register. + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_T_STRING_REG register + * SHA 512/t configuration register 0. + */ +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) +/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ +#define SHA_T_STRING 0xFFFFFFFFU +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFFU +#define SHA_T_STRING_S 0 + +/** SHA_T_LENGTH_REG register + * SHA 512/t configuration register 1. + */ +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) +/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ +#define SHA_T_LENGTH 0x0000003FU +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003FU +#define SHA_T_LENGTH_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Typical SHA configuration register 0. + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Typical SHA configuration register 1. + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Busy register. + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * Interrupt clear register. + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * Interrupt enable register. + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Date register. + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or final hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/sha_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/sha_struct.h new file mode 100644 index 0000000000..30193aee03 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/sha_struct.h @@ -0,0 +1,213 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control/Configuration Registers */ +/** Type of mode register + * Configures SHA algorithm + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA-224 + * 2: SHA-256 + * 3: SHA2-384 + * 4: SHA2-512 + * 5: SHA2-512/224 + * 6: SHA2-512/256 + * 7: SHA2-512/t + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of dma_block_num register + * Block number register (only effective for DMA-SHA) + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [15:0]; default: 0; + * Configures the DMA-SHA block number. + */ + uint32_t dma_block_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Starts the SHA accelerator for Typical SHA operation + */ +typedef union { + struct { + /** start : WO; bitpos: [0]; default: 0; + * Write 1 to start Typical SHA calculation. + */ + uint32_t start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Continues SHA operation (only effective in Typical SHA mode) + */ +typedef union { + struct { + /** continue : WO; bitpos: [0]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ + uint32_t conti:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * Starts the SHA accelerator for DMA-SHA operation + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + +/** Type of dma_rx_reset register + * DMA RX FIFO Reset Signal + */ +typedef union { + struct { + /** dma_rx_reset : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ + uint32_t dma_rx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_rx_reset_reg_t; + + +/** Group: Status Registers */ +/** Type of busy register + * Represents if SHA Accelerator is busy or not + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of clear_irq register + * DMA-SHA interrupt clear register + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * DMA-SHA interrupt enable register + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 539232291; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct { + volatile sha_mode_reg_t mode; + uint32_t reserved_004[2]; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t conti; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + volatile sha_dma_rx_reset_reg_t dma_rx_reset; + uint32_t reserved_034[3]; + volatile uint32_t h[16]; + volatile uint32_t m[32]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_reg.h new file mode 100644 index 0000000000..caec8f065f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_reg.h @@ -0,0 +1,10710 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENA0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA0 (BIT(0)) +#define SOC_ETM_CH_ENA0_M (SOC_ETM_CH_ENA0_V << SOC_ETM_CH_ENA0_S) +#define SOC_ETM_CH_ENA0_V 0x00000001U +#define SOC_ETM_CH_ENA0_S 0 +/** SOC_ETM_CH_ENA1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA1 (BIT(1)) +#define SOC_ETM_CH_ENA1_M (SOC_ETM_CH_ENA1_V << SOC_ETM_CH_ENA1_S) +#define SOC_ETM_CH_ENA1_V 0x00000001U +#define SOC_ETM_CH_ENA1_S 1 +/** SOC_ETM_CH_ENA2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA2 (BIT(2)) +#define SOC_ETM_CH_ENA2_M (SOC_ETM_CH_ENA2_V << SOC_ETM_CH_ENA2_S) +#define SOC_ETM_CH_ENA2_V 0x00000001U +#define SOC_ETM_CH_ENA2_S 2 +/** SOC_ETM_CH_ENA3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA3 (BIT(3)) +#define SOC_ETM_CH_ENA3_M (SOC_ETM_CH_ENA3_V << SOC_ETM_CH_ENA3_S) +#define SOC_ETM_CH_ENA3_V 0x00000001U +#define SOC_ETM_CH_ENA3_S 3 +/** SOC_ETM_CH_ENA4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA4 (BIT(4)) +#define SOC_ETM_CH_ENA4_M (SOC_ETM_CH_ENA4_V << SOC_ETM_CH_ENA4_S) +#define SOC_ETM_CH_ENA4_V 0x00000001U +#define SOC_ETM_CH_ENA4_S 4 +/** SOC_ETM_CH_ENA5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA5 (BIT(5)) +#define SOC_ETM_CH_ENA5_M (SOC_ETM_CH_ENA5_V << SOC_ETM_CH_ENA5_S) +#define SOC_ETM_CH_ENA5_V 0x00000001U +#define SOC_ETM_CH_ENA5_S 5 +/** SOC_ETM_CH_ENA6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA6 (BIT(6)) +#define SOC_ETM_CH_ENA6_M (SOC_ETM_CH_ENA6_V << SOC_ETM_CH_ENA6_S) +#define SOC_ETM_CH_ENA6_V 0x00000001U +#define SOC_ETM_CH_ENA6_S 6 +/** SOC_ETM_CH_ENA7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA7 (BIT(7)) +#define SOC_ETM_CH_ENA7_M (SOC_ETM_CH_ENA7_V << SOC_ETM_CH_ENA7_S) +#define SOC_ETM_CH_ENA7_V 0x00000001U +#define SOC_ETM_CH_ENA7_S 7 +/** SOC_ETM_CH_ENA8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA8 (BIT(8)) +#define SOC_ETM_CH_ENA8_M (SOC_ETM_CH_ENA8_V << SOC_ETM_CH_ENA8_S) +#define SOC_ETM_CH_ENA8_V 0x00000001U +#define SOC_ETM_CH_ENA8_S 8 +/** SOC_ETM_CH_ENA9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA9 (BIT(9)) +#define SOC_ETM_CH_ENA9_M (SOC_ETM_CH_ENA9_V << SOC_ETM_CH_ENA9_S) +#define SOC_ETM_CH_ENA9_V 0x00000001U +#define SOC_ETM_CH_ENA9_S 9 +/** SOC_ETM_CH_ENA10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA10 (BIT(10)) +#define SOC_ETM_CH_ENA10_M (SOC_ETM_CH_ENA10_V << SOC_ETM_CH_ENA10_S) +#define SOC_ETM_CH_ENA10_V 0x00000001U +#define SOC_ETM_CH_ENA10_S 10 +/** SOC_ETM_CH_ENA11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA11 (BIT(11)) +#define SOC_ETM_CH_ENA11_M (SOC_ETM_CH_ENA11_V << SOC_ETM_CH_ENA11_S) +#define SOC_ETM_CH_ENA11_V 0x00000001U +#define SOC_ETM_CH_ENA11_S 11 +/** SOC_ETM_CH_ENA12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA12 (BIT(12)) +#define SOC_ETM_CH_ENA12_M (SOC_ETM_CH_ENA12_V << SOC_ETM_CH_ENA12_S) +#define SOC_ETM_CH_ENA12_V 0x00000001U +#define SOC_ETM_CH_ENA12_S 12 +/** SOC_ETM_CH_ENA13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA13 (BIT(13)) +#define SOC_ETM_CH_ENA13_M (SOC_ETM_CH_ENA13_V << SOC_ETM_CH_ENA13_S) +#define SOC_ETM_CH_ENA13_V 0x00000001U +#define SOC_ETM_CH_ENA13_S 13 +/** SOC_ETM_CH_ENA14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA14 (BIT(14)) +#define SOC_ETM_CH_ENA14_M (SOC_ETM_CH_ENA14_V << SOC_ETM_CH_ENA14_S) +#define SOC_ETM_CH_ENA14_V 0x00000001U +#define SOC_ETM_CH_ENA14_S 14 +/** SOC_ETM_CH_ENA15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA15 (BIT(15)) +#define SOC_ETM_CH_ENA15_M (SOC_ETM_CH_ENA15_V << SOC_ETM_CH_ENA15_S) +#define SOC_ETM_CH_ENA15_V 0x00000001U +#define SOC_ETM_CH_ENA15_S 15 +/** SOC_ETM_CH_ENA16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA16 (BIT(16)) +#define SOC_ETM_CH_ENA16_M (SOC_ETM_CH_ENA16_V << SOC_ETM_CH_ENA16_S) +#define SOC_ETM_CH_ENA16_V 0x00000001U +#define SOC_ETM_CH_ENA16_S 16 +/** SOC_ETM_CH_ENA17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA17 (BIT(17)) +#define SOC_ETM_CH_ENA17_M (SOC_ETM_CH_ENA17_V << SOC_ETM_CH_ENA17_S) +#define SOC_ETM_CH_ENA17_V 0x00000001U +#define SOC_ETM_CH_ENA17_S 17 +/** SOC_ETM_CH_ENA18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA18 (BIT(18)) +#define SOC_ETM_CH_ENA18_M (SOC_ETM_CH_ENA18_V << SOC_ETM_CH_ENA18_S) +#define SOC_ETM_CH_ENA18_V 0x00000001U +#define SOC_ETM_CH_ENA18_S 18 +/** SOC_ETM_CH_ENA19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA19 (BIT(19)) +#define SOC_ETM_CH_ENA19_M (SOC_ETM_CH_ENA19_V << SOC_ETM_CH_ENA19_S) +#define SOC_ETM_CH_ENA19_V 0x00000001U +#define SOC_ETM_CH_ENA19_S 19 +/** SOC_ETM_CH_ENA20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA20 (BIT(20)) +#define SOC_ETM_CH_ENA20_M (SOC_ETM_CH_ENA20_V << SOC_ETM_CH_ENA20_S) +#define SOC_ETM_CH_ENA20_V 0x00000001U +#define SOC_ETM_CH_ENA20_S 20 +/** SOC_ETM_CH_ENA21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA21 (BIT(21)) +#define SOC_ETM_CH_ENA21_M (SOC_ETM_CH_ENA21_V << SOC_ETM_CH_ENA21_S) +#define SOC_ETM_CH_ENA21_V 0x00000001U +#define SOC_ETM_CH_ENA21_S 21 +/** SOC_ETM_CH_ENA22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA22 (BIT(22)) +#define SOC_ETM_CH_ENA22_M (SOC_ETM_CH_ENA22_V << SOC_ETM_CH_ENA22_S) +#define SOC_ETM_CH_ENA22_V 0x00000001U +#define SOC_ETM_CH_ENA22_S 22 +/** SOC_ETM_CH_ENA23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA23 (BIT(23)) +#define SOC_ETM_CH_ENA23_M (SOC_ETM_CH_ENA23_V << SOC_ETM_CH_ENA23_S) +#define SOC_ETM_CH_ENA23_V 0x00000001U +#define SOC_ETM_CH_ENA23_S 23 +/** SOC_ETM_CH_ENA24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA24 (BIT(24)) +#define SOC_ETM_CH_ENA24_M (SOC_ETM_CH_ENA24_V << SOC_ETM_CH_ENA24_S) +#define SOC_ETM_CH_ENA24_V 0x00000001U +#define SOC_ETM_CH_ENA24_S 24 +/** SOC_ETM_CH_ENA25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA25 (BIT(25)) +#define SOC_ETM_CH_ENA25_M (SOC_ETM_CH_ENA25_V << SOC_ETM_CH_ENA25_S) +#define SOC_ETM_CH_ENA25_V 0x00000001U +#define SOC_ETM_CH_ENA25_S 25 +/** SOC_ETM_CH_ENA26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA26 (BIT(26)) +#define SOC_ETM_CH_ENA26_M (SOC_ETM_CH_ENA26_V << SOC_ETM_CH_ENA26_S) +#define SOC_ETM_CH_ENA26_V 0x00000001U +#define SOC_ETM_CH_ENA26_S 26 +/** SOC_ETM_CH_ENA27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA27 (BIT(27)) +#define SOC_ETM_CH_ENA27_M (SOC_ETM_CH_ENA27_V << SOC_ETM_CH_ENA27_S) +#define SOC_ETM_CH_ENA27_V 0x00000001U +#define SOC_ETM_CH_ENA27_S 27 +/** SOC_ETM_CH_ENA28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA28 (BIT(28)) +#define SOC_ETM_CH_ENA28_M (SOC_ETM_CH_ENA28_V << SOC_ETM_CH_ENA28_S) +#define SOC_ETM_CH_ENA28_V 0x00000001U +#define SOC_ETM_CH_ENA28_S 28 +/** SOC_ETM_CH_ENA29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA29 (BIT(29)) +#define SOC_ETM_CH_ENA29_M (SOC_ETM_CH_ENA29_V << SOC_ETM_CH_ENA29_S) +#define SOC_ETM_CH_ENA29_V 0x00000001U +#define SOC_ETM_CH_ENA29_S 29 +/** SOC_ETM_CH_ENA30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA30 (BIT(30)) +#define SOC_ETM_CH_ENA30_M (SOC_ETM_CH_ENA30_V << SOC_ETM_CH_ENA30_S) +#define SOC_ETM_CH_ENA30_V 0x00000001U +#define SOC_ETM_CH_ENA30_S 30 +/** SOC_ETM_CH_ENA31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA31 (BIT(31)) +#define SOC_ETM_CH_ENA31_M (SOC_ETM_CH_ENA31_V << SOC_ETM_CH_ENA31_S) +#define SOC_ETM_CH_ENA31_V 0x00000001U +#define SOC_ETM_CH_ENA31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_SET0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET0 (BIT(0)) +#define SOC_ETM_CH_SET0_M (SOC_ETM_CH_SET0_V << SOC_ETM_CH_SET0_S) +#define SOC_ETM_CH_SET0_V 0x00000001U +#define SOC_ETM_CH_SET0_S 0 +/** SOC_ETM_CH_SET1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET1 (BIT(1)) +#define SOC_ETM_CH_SET1_M (SOC_ETM_CH_SET1_V << SOC_ETM_CH_SET1_S) +#define SOC_ETM_CH_SET1_V 0x00000001U +#define SOC_ETM_CH_SET1_S 1 +/** SOC_ETM_CH_SET2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET2 (BIT(2)) +#define SOC_ETM_CH_SET2_M (SOC_ETM_CH_SET2_V << SOC_ETM_CH_SET2_S) +#define SOC_ETM_CH_SET2_V 0x00000001U +#define SOC_ETM_CH_SET2_S 2 +/** SOC_ETM_CH_SET3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET3 (BIT(3)) +#define SOC_ETM_CH_SET3_M (SOC_ETM_CH_SET3_V << SOC_ETM_CH_SET3_S) +#define SOC_ETM_CH_SET3_V 0x00000001U +#define SOC_ETM_CH_SET3_S 3 +/** SOC_ETM_CH_SET4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET4 (BIT(4)) +#define SOC_ETM_CH_SET4_M (SOC_ETM_CH_SET4_V << SOC_ETM_CH_SET4_S) +#define SOC_ETM_CH_SET4_V 0x00000001U +#define SOC_ETM_CH_SET4_S 4 +/** SOC_ETM_CH_SET5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET5 (BIT(5)) +#define SOC_ETM_CH_SET5_M (SOC_ETM_CH_SET5_V << SOC_ETM_CH_SET5_S) +#define SOC_ETM_CH_SET5_V 0x00000001U +#define SOC_ETM_CH_SET5_S 5 +/** SOC_ETM_CH_SET6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET6 (BIT(6)) +#define SOC_ETM_CH_SET6_M (SOC_ETM_CH_SET6_V << SOC_ETM_CH_SET6_S) +#define SOC_ETM_CH_SET6_V 0x00000001U +#define SOC_ETM_CH_SET6_S 6 +/** SOC_ETM_CH_SET7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET7 (BIT(7)) +#define SOC_ETM_CH_SET7_M (SOC_ETM_CH_SET7_V << SOC_ETM_CH_SET7_S) +#define SOC_ETM_CH_SET7_V 0x00000001U +#define SOC_ETM_CH_SET7_S 7 +/** SOC_ETM_CH_SET8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET8 (BIT(8)) +#define SOC_ETM_CH_SET8_M (SOC_ETM_CH_SET8_V << SOC_ETM_CH_SET8_S) +#define SOC_ETM_CH_SET8_V 0x00000001U +#define SOC_ETM_CH_SET8_S 8 +/** SOC_ETM_CH_SET9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET9 (BIT(9)) +#define SOC_ETM_CH_SET9_M (SOC_ETM_CH_SET9_V << SOC_ETM_CH_SET9_S) +#define SOC_ETM_CH_SET9_V 0x00000001U +#define SOC_ETM_CH_SET9_S 9 +/** SOC_ETM_CH_SET10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET10 (BIT(10)) +#define SOC_ETM_CH_SET10_M (SOC_ETM_CH_SET10_V << SOC_ETM_CH_SET10_S) +#define SOC_ETM_CH_SET10_V 0x00000001U +#define SOC_ETM_CH_SET10_S 10 +/** SOC_ETM_CH_SET11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET11 (BIT(11)) +#define SOC_ETM_CH_SET11_M (SOC_ETM_CH_SET11_V << SOC_ETM_CH_SET11_S) +#define SOC_ETM_CH_SET11_V 0x00000001U +#define SOC_ETM_CH_SET11_S 11 +/** SOC_ETM_CH_SET12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET12 (BIT(12)) +#define SOC_ETM_CH_SET12_M (SOC_ETM_CH_SET12_V << SOC_ETM_CH_SET12_S) +#define SOC_ETM_CH_SET12_V 0x00000001U +#define SOC_ETM_CH_SET12_S 12 +/** SOC_ETM_CH_SET13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET13 (BIT(13)) +#define SOC_ETM_CH_SET13_M (SOC_ETM_CH_SET13_V << SOC_ETM_CH_SET13_S) +#define SOC_ETM_CH_SET13_V 0x00000001U +#define SOC_ETM_CH_SET13_S 13 +/** SOC_ETM_CH_SET14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET14 (BIT(14)) +#define SOC_ETM_CH_SET14_M (SOC_ETM_CH_SET14_V << SOC_ETM_CH_SET14_S) +#define SOC_ETM_CH_SET14_V 0x00000001U +#define SOC_ETM_CH_SET14_S 14 +/** SOC_ETM_CH_SET15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET15 (BIT(15)) +#define SOC_ETM_CH_SET15_M (SOC_ETM_CH_SET15_V << SOC_ETM_CH_SET15_S) +#define SOC_ETM_CH_SET15_V 0x00000001U +#define SOC_ETM_CH_SET15_S 15 +/** SOC_ETM_CH_SET16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET16 (BIT(16)) +#define SOC_ETM_CH_SET16_M (SOC_ETM_CH_SET16_V << SOC_ETM_CH_SET16_S) +#define SOC_ETM_CH_SET16_V 0x00000001U +#define SOC_ETM_CH_SET16_S 16 +/** SOC_ETM_CH_SET17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET17 (BIT(17)) +#define SOC_ETM_CH_SET17_M (SOC_ETM_CH_SET17_V << SOC_ETM_CH_SET17_S) +#define SOC_ETM_CH_SET17_V 0x00000001U +#define SOC_ETM_CH_SET17_S 17 +/** SOC_ETM_CH_SET18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET18 (BIT(18)) +#define SOC_ETM_CH_SET18_M (SOC_ETM_CH_SET18_V << SOC_ETM_CH_SET18_S) +#define SOC_ETM_CH_SET18_V 0x00000001U +#define SOC_ETM_CH_SET18_S 18 +/** SOC_ETM_CH_SET19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET19 (BIT(19)) +#define SOC_ETM_CH_SET19_M (SOC_ETM_CH_SET19_V << SOC_ETM_CH_SET19_S) +#define SOC_ETM_CH_SET19_V 0x00000001U +#define SOC_ETM_CH_SET19_S 19 +/** SOC_ETM_CH_SET20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET20 (BIT(20)) +#define SOC_ETM_CH_SET20_M (SOC_ETM_CH_SET20_V << SOC_ETM_CH_SET20_S) +#define SOC_ETM_CH_SET20_V 0x00000001U +#define SOC_ETM_CH_SET20_S 20 +/** SOC_ETM_CH_SET21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET21 (BIT(21)) +#define SOC_ETM_CH_SET21_M (SOC_ETM_CH_SET21_V << SOC_ETM_CH_SET21_S) +#define SOC_ETM_CH_SET21_V 0x00000001U +#define SOC_ETM_CH_SET21_S 21 +/** SOC_ETM_CH_SET22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET22 (BIT(22)) +#define SOC_ETM_CH_SET22_M (SOC_ETM_CH_SET22_V << SOC_ETM_CH_SET22_S) +#define SOC_ETM_CH_SET22_V 0x00000001U +#define SOC_ETM_CH_SET22_S 22 +/** SOC_ETM_CH_SET23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET23 (BIT(23)) +#define SOC_ETM_CH_SET23_M (SOC_ETM_CH_SET23_V << SOC_ETM_CH_SET23_S) +#define SOC_ETM_CH_SET23_V 0x00000001U +#define SOC_ETM_CH_SET23_S 23 +/** SOC_ETM_CH_SET24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET24 (BIT(24)) +#define SOC_ETM_CH_SET24_M (SOC_ETM_CH_SET24_V << SOC_ETM_CH_SET24_S) +#define SOC_ETM_CH_SET24_V 0x00000001U +#define SOC_ETM_CH_SET24_S 24 +/** SOC_ETM_CH_SET25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET25 (BIT(25)) +#define SOC_ETM_CH_SET25_M (SOC_ETM_CH_SET25_V << SOC_ETM_CH_SET25_S) +#define SOC_ETM_CH_SET25_V 0x00000001U +#define SOC_ETM_CH_SET25_S 25 +/** SOC_ETM_CH_SET26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET26 (BIT(26)) +#define SOC_ETM_CH_SET26_M (SOC_ETM_CH_SET26_V << SOC_ETM_CH_SET26_S) +#define SOC_ETM_CH_SET26_V 0x00000001U +#define SOC_ETM_CH_SET26_S 26 +/** SOC_ETM_CH_SET27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET27 (BIT(27)) +#define SOC_ETM_CH_SET27_M (SOC_ETM_CH_SET27_V << SOC_ETM_CH_SET27_S) +#define SOC_ETM_CH_SET27_V 0x00000001U +#define SOC_ETM_CH_SET27_S 27 +/** SOC_ETM_CH_SET28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET28 (BIT(28)) +#define SOC_ETM_CH_SET28_M (SOC_ETM_CH_SET28_V << SOC_ETM_CH_SET28_S) +#define SOC_ETM_CH_SET28_V 0x00000001U +#define SOC_ETM_CH_SET28_S 28 +/** SOC_ETM_CH_SET29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET29 (BIT(29)) +#define SOC_ETM_CH_SET29_M (SOC_ETM_CH_SET29_V << SOC_ETM_CH_SET29_S) +#define SOC_ETM_CH_SET29_V 0x00000001U +#define SOC_ETM_CH_SET29_S 29 +/** SOC_ETM_CH_SET30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET30 (BIT(30)) +#define SOC_ETM_CH_SET30_M (SOC_ETM_CH_SET30_V << SOC_ETM_CH_SET30_S) +#define SOC_ETM_CH_SET30_V 0x00000001U +#define SOC_ETM_CH_SET30_S 30 +/** SOC_ETM_CH_SET31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET31 (BIT(31)) +#define SOC_ETM_CH_SET31_M (SOC_ETM_CH_SET31_V << SOC_ETM_CH_SET31_S) +#define SOC_ETM_CH_SET31_V 0x00000001U +#define SOC_ETM_CH_SET31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_CLR0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR0 (BIT(0)) +#define SOC_ETM_CH_CLR0_M (SOC_ETM_CH_CLR0_V << SOC_ETM_CH_CLR0_S) +#define SOC_ETM_CH_CLR0_V 0x00000001U +#define SOC_ETM_CH_CLR0_S 0 +/** SOC_ETM_CH_CLR1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR1 (BIT(1)) +#define SOC_ETM_CH_CLR1_M (SOC_ETM_CH_CLR1_V << SOC_ETM_CH_CLR1_S) +#define SOC_ETM_CH_CLR1_V 0x00000001U +#define SOC_ETM_CH_CLR1_S 1 +/** SOC_ETM_CH_CLR2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR2 (BIT(2)) +#define SOC_ETM_CH_CLR2_M (SOC_ETM_CH_CLR2_V << SOC_ETM_CH_CLR2_S) +#define SOC_ETM_CH_CLR2_V 0x00000001U +#define SOC_ETM_CH_CLR2_S 2 +/** SOC_ETM_CH_CLR3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR3 (BIT(3)) +#define SOC_ETM_CH_CLR3_M (SOC_ETM_CH_CLR3_V << SOC_ETM_CH_CLR3_S) +#define SOC_ETM_CH_CLR3_V 0x00000001U +#define SOC_ETM_CH_CLR3_S 3 +/** SOC_ETM_CH_CLR4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR4 (BIT(4)) +#define SOC_ETM_CH_CLR4_M (SOC_ETM_CH_CLR4_V << SOC_ETM_CH_CLR4_S) +#define SOC_ETM_CH_CLR4_V 0x00000001U +#define SOC_ETM_CH_CLR4_S 4 +/** SOC_ETM_CH_CLR5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR5 (BIT(5)) +#define SOC_ETM_CH_CLR5_M (SOC_ETM_CH_CLR5_V << SOC_ETM_CH_CLR5_S) +#define SOC_ETM_CH_CLR5_V 0x00000001U +#define SOC_ETM_CH_CLR5_S 5 +/** SOC_ETM_CH_CLR6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR6 (BIT(6)) +#define SOC_ETM_CH_CLR6_M (SOC_ETM_CH_CLR6_V << SOC_ETM_CH_CLR6_S) +#define SOC_ETM_CH_CLR6_V 0x00000001U +#define SOC_ETM_CH_CLR6_S 6 +/** SOC_ETM_CH_CLR7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR7 (BIT(7)) +#define SOC_ETM_CH_CLR7_M (SOC_ETM_CH_CLR7_V << SOC_ETM_CH_CLR7_S) +#define SOC_ETM_CH_CLR7_V 0x00000001U +#define SOC_ETM_CH_CLR7_S 7 +/** SOC_ETM_CH_CLR8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR8 (BIT(8)) +#define SOC_ETM_CH_CLR8_M (SOC_ETM_CH_CLR8_V << SOC_ETM_CH_CLR8_S) +#define SOC_ETM_CH_CLR8_V 0x00000001U +#define SOC_ETM_CH_CLR8_S 8 +/** SOC_ETM_CH_CLR9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR9 (BIT(9)) +#define SOC_ETM_CH_CLR9_M (SOC_ETM_CH_CLR9_V << SOC_ETM_CH_CLR9_S) +#define SOC_ETM_CH_CLR9_V 0x00000001U +#define SOC_ETM_CH_CLR9_S 9 +/** SOC_ETM_CH_CLR10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR10 (BIT(10)) +#define SOC_ETM_CH_CLR10_M (SOC_ETM_CH_CLR10_V << SOC_ETM_CH_CLR10_S) +#define SOC_ETM_CH_CLR10_V 0x00000001U +#define SOC_ETM_CH_CLR10_S 10 +/** SOC_ETM_CH_CLR11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR11 (BIT(11)) +#define SOC_ETM_CH_CLR11_M (SOC_ETM_CH_CLR11_V << SOC_ETM_CH_CLR11_S) +#define SOC_ETM_CH_CLR11_V 0x00000001U +#define SOC_ETM_CH_CLR11_S 11 +/** SOC_ETM_CH_CLR12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR12 (BIT(12)) +#define SOC_ETM_CH_CLR12_M (SOC_ETM_CH_CLR12_V << SOC_ETM_CH_CLR12_S) +#define SOC_ETM_CH_CLR12_V 0x00000001U +#define SOC_ETM_CH_CLR12_S 12 +/** SOC_ETM_CH_CLR13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR13 (BIT(13)) +#define SOC_ETM_CH_CLR13_M (SOC_ETM_CH_CLR13_V << SOC_ETM_CH_CLR13_S) +#define SOC_ETM_CH_CLR13_V 0x00000001U +#define SOC_ETM_CH_CLR13_S 13 +/** SOC_ETM_CH_CLR14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR14 (BIT(14)) +#define SOC_ETM_CH_CLR14_M (SOC_ETM_CH_CLR14_V << SOC_ETM_CH_CLR14_S) +#define SOC_ETM_CH_CLR14_V 0x00000001U +#define SOC_ETM_CH_CLR14_S 14 +/** SOC_ETM_CH_CLR15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR15 (BIT(15)) +#define SOC_ETM_CH_CLR15_M (SOC_ETM_CH_CLR15_V << SOC_ETM_CH_CLR15_S) +#define SOC_ETM_CH_CLR15_V 0x00000001U +#define SOC_ETM_CH_CLR15_S 15 +/** SOC_ETM_CH_CLR16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR16 (BIT(16)) +#define SOC_ETM_CH_CLR16_M (SOC_ETM_CH_CLR16_V << SOC_ETM_CH_CLR16_S) +#define SOC_ETM_CH_CLR16_V 0x00000001U +#define SOC_ETM_CH_CLR16_S 16 +/** SOC_ETM_CH_CLR17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR17 (BIT(17)) +#define SOC_ETM_CH_CLR17_M (SOC_ETM_CH_CLR17_V << SOC_ETM_CH_CLR17_S) +#define SOC_ETM_CH_CLR17_V 0x00000001U +#define SOC_ETM_CH_CLR17_S 17 +/** SOC_ETM_CH_CLR18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR18 (BIT(18)) +#define SOC_ETM_CH_CLR18_M (SOC_ETM_CH_CLR18_V << SOC_ETM_CH_CLR18_S) +#define SOC_ETM_CH_CLR18_V 0x00000001U +#define SOC_ETM_CH_CLR18_S 18 +/** SOC_ETM_CH_CLR19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR19 (BIT(19)) +#define SOC_ETM_CH_CLR19_M (SOC_ETM_CH_CLR19_V << SOC_ETM_CH_CLR19_S) +#define SOC_ETM_CH_CLR19_V 0x00000001U +#define SOC_ETM_CH_CLR19_S 19 +/** SOC_ETM_CH_CLR20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR20 (BIT(20)) +#define SOC_ETM_CH_CLR20_M (SOC_ETM_CH_CLR20_V << SOC_ETM_CH_CLR20_S) +#define SOC_ETM_CH_CLR20_V 0x00000001U +#define SOC_ETM_CH_CLR20_S 20 +/** SOC_ETM_CH_CLR21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR21 (BIT(21)) +#define SOC_ETM_CH_CLR21_M (SOC_ETM_CH_CLR21_V << SOC_ETM_CH_CLR21_S) +#define SOC_ETM_CH_CLR21_V 0x00000001U +#define SOC_ETM_CH_CLR21_S 21 +/** SOC_ETM_CH_CLR22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR22 (BIT(22)) +#define SOC_ETM_CH_CLR22_M (SOC_ETM_CH_CLR22_V << SOC_ETM_CH_CLR22_S) +#define SOC_ETM_CH_CLR22_V 0x00000001U +#define SOC_ETM_CH_CLR22_S 22 +/** SOC_ETM_CH_CLR23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR23 (BIT(23)) +#define SOC_ETM_CH_CLR23_M (SOC_ETM_CH_CLR23_V << SOC_ETM_CH_CLR23_S) +#define SOC_ETM_CH_CLR23_V 0x00000001U +#define SOC_ETM_CH_CLR23_S 23 +/** SOC_ETM_CH_CLR24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR24 (BIT(24)) +#define SOC_ETM_CH_CLR24_M (SOC_ETM_CH_CLR24_V << SOC_ETM_CH_CLR24_S) +#define SOC_ETM_CH_CLR24_V 0x00000001U +#define SOC_ETM_CH_CLR24_S 24 +/** SOC_ETM_CH_CLR25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR25 (BIT(25)) +#define SOC_ETM_CH_CLR25_M (SOC_ETM_CH_CLR25_V << SOC_ETM_CH_CLR25_S) +#define SOC_ETM_CH_CLR25_V 0x00000001U +#define SOC_ETM_CH_CLR25_S 25 +/** SOC_ETM_CH_CLR26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR26 (BIT(26)) +#define SOC_ETM_CH_CLR26_M (SOC_ETM_CH_CLR26_V << SOC_ETM_CH_CLR26_S) +#define SOC_ETM_CH_CLR26_V 0x00000001U +#define SOC_ETM_CH_CLR26_S 26 +/** SOC_ETM_CH_CLR27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR27 (BIT(27)) +#define SOC_ETM_CH_CLR27_M (SOC_ETM_CH_CLR27_V << SOC_ETM_CH_CLR27_S) +#define SOC_ETM_CH_CLR27_V 0x00000001U +#define SOC_ETM_CH_CLR27_S 27 +/** SOC_ETM_CH_CLR28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR28 (BIT(28)) +#define SOC_ETM_CH_CLR28_M (SOC_ETM_CH_CLR28_V << SOC_ETM_CH_CLR28_S) +#define SOC_ETM_CH_CLR28_V 0x00000001U +#define SOC_ETM_CH_CLR28_S 28 +/** SOC_ETM_CH_CLR29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR29 (BIT(29)) +#define SOC_ETM_CH_CLR29_M (SOC_ETM_CH_CLR29_V << SOC_ETM_CH_CLR29_S) +#define SOC_ETM_CH_CLR29_V 0x00000001U +#define SOC_ETM_CH_CLR29_S 29 +/** SOC_ETM_CH_CLR30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR30 (BIT(30)) +#define SOC_ETM_CH_CLR30_M (SOC_ETM_CH_CLR30_V << SOC_ETM_CH_CLR30_S) +#define SOC_ETM_CH_CLR30_V 0x00000001U +#define SOC_ETM_CH_CLR30_S 30 +/** SOC_ETM_CH_CLR31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR31 (BIT(31)) +#define SOC_ETM_CH_CLR31_M (SOC_ETM_CH_CLR31_V << SOC_ETM_CH_CLR31_S) +#define SOC_ETM_CH_CLR31_V 0x00000001U +#define SOC_ETM_CH_CLR31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENA32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA32 (BIT(0)) +#define SOC_ETM_CH_ENA32_M (SOC_ETM_CH_ENA32_V << SOC_ETM_CH_ENA32_S) +#define SOC_ETM_CH_ENA32_V 0x00000001U +#define SOC_ETM_CH_ENA32_S 0 +/** SOC_ETM_CH_ENA33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA33 (BIT(1)) +#define SOC_ETM_CH_ENA33_M (SOC_ETM_CH_ENA33_V << SOC_ETM_CH_ENA33_S) +#define SOC_ETM_CH_ENA33_V 0x00000001U +#define SOC_ETM_CH_ENA33_S 1 +/** SOC_ETM_CH_ENA34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA34 (BIT(2)) +#define SOC_ETM_CH_ENA34_M (SOC_ETM_CH_ENA34_V << SOC_ETM_CH_ENA34_S) +#define SOC_ETM_CH_ENA34_V 0x00000001U +#define SOC_ETM_CH_ENA34_S 2 +/** SOC_ETM_CH_ENA35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA35 (BIT(3)) +#define SOC_ETM_CH_ENA35_M (SOC_ETM_CH_ENA35_V << SOC_ETM_CH_ENA35_S) +#define SOC_ETM_CH_ENA35_V 0x00000001U +#define SOC_ETM_CH_ENA35_S 3 +/** SOC_ETM_CH_ENA36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA36 (BIT(4)) +#define SOC_ETM_CH_ENA36_M (SOC_ETM_CH_ENA36_V << SOC_ETM_CH_ENA36_S) +#define SOC_ETM_CH_ENA36_V 0x00000001U +#define SOC_ETM_CH_ENA36_S 4 +/** SOC_ETM_CH_ENA37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA37 (BIT(5)) +#define SOC_ETM_CH_ENA37_M (SOC_ETM_CH_ENA37_V << SOC_ETM_CH_ENA37_S) +#define SOC_ETM_CH_ENA37_V 0x00000001U +#define SOC_ETM_CH_ENA37_S 5 +/** SOC_ETM_CH_ENA38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA38 (BIT(6)) +#define SOC_ETM_CH_ENA38_M (SOC_ETM_CH_ENA38_V << SOC_ETM_CH_ENA38_S) +#define SOC_ETM_CH_ENA38_V 0x00000001U +#define SOC_ETM_CH_ENA38_S 6 +/** SOC_ETM_CH_ENA39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA39 (BIT(7)) +#define SOC_ETM_CH_ENA39_M (SOC_ETM_CH_ENA39_V << SOC_ETM_CH_ENA39_S) +#define SOC_ETM_CH_ENA39_V 0x00000001U +#define SOC_ETM_CH_ENA39_S 7 +/** SOC_ETM_CH_ENA40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA40 (BIT(8)) +#define SOC_ETM_CH_ENA40_M (SOC_ETM_CH_ENA40_V << SOC_ETM_CH_ENA40_S) +#define SOC_ETM_CH_ENA40_V 0x00000001U +#define SOC_ETM_CH_ENA40_S 8 +/** SOC_ETM_CH_ENA41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA41 (BIT(9)) +#define SOC_ETM_CH_ENA41_M (SOC_ETM_CH_ENA41_V << SOC_ETM_CH_ENA41_S) +#define SOC_ETM_CH_ENA41_V 0x00000001U +#define SOC_ETM_CH_ENA41_S 9 +/** SOC_ETM_CH_ENA42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA42 (BIT(10)) +#define SOC_ETM_CH_ENA42_M (SOC_ETM_CH_ENA42_V << SOC_ETM_CH_ENA42_S) +#define SOC_ETM_CH_ENA42_V 0x00000001U +#define SOC_ETM_CH_ENA42_S 10 +/** SOC_ETM_CH_ENA43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA43 (BIT(11)) +#define SOC_ETM_CH_ENA43_M (SOC_ETM_CH_ENA43_V << SOC_ETM_CH_ENA43_S) +#define SOC_ETM_CH_ENA43_V 0x00000001U +#define SOC_ETM_CH_ENA43_S 11 +/** SOC_ETM_CH_ENA44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA44 (BIT(12)) +#define SOC_ETM_CH_ENA44_M (SOC_ETM_CH_ENA44_V << SOC_ETM_CH_ENA44_S) +#define SOC_ETM_CH_ENA44_V 0x00000001U +#define SOC_ETM_CH_ENA44_S 12 +/** SOC_ETM_CH_ENA45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA45 (BIT(13)) +#define SOC_ETM_CH_ENA45_M (SOC_ETM_CH_ENA45_V << SOC_ETM_CH_ENA45_S) +#define SOC_ETM_CH_ENA45_V 0x00000001U +#define SOC_ETM_CH_ENA45_S 13 +/** SOC_ETM_CH_ENA46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA46 (BIT(14)) +#define SOC_ETM_CH_ENA46_M (SOC_ETM_CH_ENA46_V << SOC_ETM_CH_ENA46_S) +#define SOC_ETM_CH_ENA46_V 0x00000001U +#define SOC_ETM_CH_ENA46_S 14 +/** SOC_ETM_CH_ENA47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA47 (BIT(15)) +#define SOC_ETM_CH_ENA47_M (SOC_ETM_CH_ENA47_V << SOC_ETM_CH_ENA47_S) +#define SOC_ETM_CH_ENA47_V 0x00000001U +#define SOC_ETM_CH_ENA47_S 15 +/** SOC_ETM_CH_ENA48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA48 (BIT(16)) +#define SOC_ETM_CH_ENA48_M (SOC_ETM_CH_ENA48_V << SOC_ETM_CH_ENA48_S) +#define SOC_ETM_CH_ENA48_V 0x00000001U +#define SOC_ETM_CH_ENA48_S 16 +/** SOC_ETM_CH_ENA49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status. + * 0: Disable + * 1: Enable + */ +#define SOC_ETM_CH_ENA49 (BIT(17)) +#define SOC_ETM_CH_ENA49_M (SOC_ETM_CH_ENA49_V << SOC_ETM_CH_ENA49_S) +#define SOC_ETM_CH_ENA49_V 0x00000001U +#define SOC_ETM_CH_ENA49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_SET32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET32 (BIT(0)) +#define SOC_ETM_CH_SET32_M (SOC_ETM_CH_SET32_V << SOC_ETM_CH_SET32_S) +#define SOC_ETM_CH_SET32_V 0x00000001U +#define SOC_ETM_CH_SET32_S 0 +/** SOC_ETM_CH_SET33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET33 (BIT(1)) +#define SOC_ETM_CH_SET33_M (SOC_ETM_CH_SET33_V << SOC_ETM_CH_SET33_S) +#define SOC_ETM_CH_SET33_V 0x00000001U +#define SOC_ETM_CH_SET33_S 1 +/** SOC_ETM_CH_SET34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET34 (BIT(2)) +#define SOC_ETM_CH_SET34_M (SOC_ETM_CH_SET34_V << SOC_ETM_CH_SET34_S) +#define SOC_ETM_CH_SET34_V 0x00000001U +#define SOC_ETM_CH_SET34_S 2 +/** SOC_ETM_CH_SET35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET35 (BIT(3)) +#define SOC_ETM_CH_SET35_M (SOC_ETM_CH_SET35_V << SOC_ETM_CH_SET35_S) +#define SOC_ETM_CH_SET35_V 0x00000001U +#define SOC_ETM_CH_SET35_S 3 +/** SOC_ETM_CH_SET36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET36 (BIT(4)) +#define SOC_ETM_CH_SET36_M (SOC_ETM_CH_SET36_V << SOC_ETM_CH_SET36_S) +#define SOC_ETM_CH_SET36_V 0x00000001U +#define SOC_ETM_CH_SET36_S 4 +/** SOC_ETM_CH_SET37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET37 (BIT(5)) +#define SOC_ETM_CH_SET37_M (SOC_ETM_CH_SET37_V << SOC_ETM_CH_SET37_S) +#define SOC_ETM_CH_SET37_V 0x00000001U +#define SOC_ETM_CH_SET37_S 5 +/** SOC_ETM_CH_SET38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET38 (BIT(6)) +#define SOC_ETM_CH_SET38_M (SOC_ETM_CH_SET38_V << SOC_ETM_CH_SET38_S) +#define SOC_ETM_CH_SET38_V 0x00000001U +#define SOC_ETM_CH_SET38_S 6 +/** SOC_ETM_CH_SET39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET39 (BIT(7)) +#define SOC_ETM_CH_SET39_M (SOC_ETM_CH_SET39_V << SOC_ETM_CH_SET39_S) +#define SOC_ETM_CH_SET39_V 0x00000001U +#define SOC_ETM_CH_SET39_S 7 +/** SOC_ETM_CH_SET40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET40 (BIT(8)) +#define SOC_ETM_CH_SET40_M (SOC_ETM_CH_SET40_V << SOC_ETM_CH_SET40_S) +#define SOC_ETM_CH_SET40_V 0x00000001U +#define SOC_ETM_CH_SET40_S 8 +/** SOC_ETM_CH_SET41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET41 (BIT(9)) +#define SOC_ETM_CH_SET41_M (SOC_ETM_CH_SET41_V << SOC_ETM_CH_SET41_S) +#define SOC_ETM_CH_SET41_V 0x00000001U +#define SOC_ETM_CH_SET41_S 9 +/** SOC_ETM_CH_SET42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET42 (BIT(10)) +#define SOC_ETM_CH_SET42_M (SOC_ETM_CH_SET42_V << SOC_ETM_CH_SET42_S) +#define SOC_ETM_CH_SET42_V 0x00000001U +#define SOC_ETM_CH_SET42_S 10 +/** SOC_ETM_CH_SET43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET43 (BIT(11)) +#define SOC_ETM_CH_SET43_M (SOC_ETM_CH_SET43_V << SOC_ETM_CH_SET43_S) +#define SOC_ETM_CH_SET43_V 0x00000001U +#define SOC_ETM_CH_SET43_S 11 +/** SOC_ETM_CH_SET44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET44 (BIT(12)) +#define SOC_ETM_CH_SET44_M (SOC_ETM_CH_SET44_V << SOC_ETM_CH_SET44_S) +#define SOC_ETM_CH_SET44_V 0x00000001U +#define SOC_ETM_CH_SET44_S 12 +/** SOC_ETM_CH_SET45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET45 (BIT(13)) +#define SOC_ETM_CH_SET45_M (SOC_ETM_CH_SET45_V << SOC_ETM_CH_SET45_S) +#define SOC_ETM_CH_SET45_V 0x00000001U +#define SOC_ETM_CH_SET45_S 13 +/** SOC_ETM_CH_SET46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET46 (BIT(14)) +#define SOC_ETM_CH_SET46_M (SOC_ETM_CH_SET46_V << SOC_ETM_CH_SET46_S) +#define SOC_ETM_CH_SET46_V 0x00000001U +#define SOC_ETM_CH_SET46_S 14 +/** SOC_ETM_CH_SET47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET47 (BIT(15)) +#define SOC_ETM_CH_SET47_M (SOC_ETM_CH_SET47_V << SOC_ETM_CH_SET47_S) +#define SOC_ETM_CH_SET47_V 0x00000001U +#define SOC_ETM_CH_SET47_S 15 +/** SOC_ETM_CH_SET48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET48 (BIT(16)) +#define SOC_ETM_CH_SET48_M (SOC_ETM_CH_SET48_V << SOC_ETM_CH_SET48_S) +#define SOC_ETM_CH_SET48_V 0x00000001U +#define SOC_ETM_CH_SET48_S 16 +/** SOC_ETM_CH_SET49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49. + * 0: Invalid, No effect + * 1: Enable + */ +#define SOC_ETM_CH_SET49 (BIT(17)) +#define SOC_ETM_CH_SET49_M (SOC_ETM_CH_SET49_V << SOC_ETM_CH_SET49_S) +#define SOC_ETM_CH_SET49_V 0x00000001U +#define SOC_ETM_CH_SET49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_CLR32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR32 (BIT(0)) +#define SOC_ETM_CH_CLR32_M (SOC_ETM_CH_CLR32_V << SOC_ETM_CH_CLR32_S) +#define SOC_ETM_CH_CLR32_V 0x00000001U +#define SOC_ETM_CH_CLR32_S 0 +/** SOC_ETM_CH_CLR33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR33 (BIT(1)) +#define SOC_ETM_CH_CLR33_M (SOC_ETM_CH_CLR33_V << SOC_ETM_CH_CLR33_S) +#define SOC_ETM_CH_CLR33_V 0x00000001U +#define SOC_ETM_CH_CLR33_S 1 +/** SOC_ETM_CH_CLR34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR34 (BIT(2)) +#define SOC_ETM_CH_CLR34_M (SOC_ETM_CH_CLR34_V << SOC_ETM_CH_CLR34_S) +#define SOC_ETM_CH_CLR34_V 0x00000001U +#define SOC_ETM_CH_CLR34_S 2 +/** SOC_ETM_CH_CLR35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR35 (BIT(3)) +#define SOC_ETM_CH_CLR35_M (SOC_ETM_CH_CLR35_V << SOC_ETM_CH_CLR35_S) +#define SOC_ETM_CH_CLR35_V 0x00000001U +#define SOC_ETM_CH_CLR35_S 3 +/** SOC_ETM_CH_CLR36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR36 (BIT(4)) +#define SOC_ETM_CH_CLR36_M (SOC_ETM_CH_CLR36_V << SOC_ETM_CH_CLR36_S) +#define SOC_ETM_CH_CLR36_V 0x00000001U +#define SOC_ETM_CH_CLR36_S 4 +/** SOC_ETM_CH_CLR37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR37 (BIT(5)) +#define SOC_ETM_CH_CLR37_M (SOC_ETM_CH_CLR37_V << SOC_ETM_CH_CLR37_S) +#define SOC_ETM_CH_CLR37_V 0x00000001U +#define SOC_ETM_CH_CLR37_S 5 +/** SOC_ETM_CH_CLR38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR38 (BIT(6)) +#define SOC_ETM_CH_CLR38_M (SOC_ETM_CH_CLR38_V << SOC_ETM_CH_CLR38_S) +#define SOC_ETM_CH_CLR38_V 0x00000001U +#define SOC_ETM_CH_CLR38_S 6 +/** SOC_ETM_CH_CLR39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR39 (BIT(7)) +#define SOC_ETM_CH_CLR39_M (SOC_ETM_CH_CLR39_V << SOC_ETM_CH_CLR39_S) +#define SOC_ETM_CH_CLR39_V 0x00000001U +#define SOC_ETM_CH_CLR39_S 7 +/** SOC_ETM_CH_CLR40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR40 (BIT(8)) +#define SOC_ETM_CH_CLR40_M (SOC_ETM_CH_CLR40_V << SOC_ETM_CH_CLR40_S) +#define SOC_ETM_CH_CLR40_V 0x00000001U +#define SOC_ETM_CH_CLR40_S 8 +/** SOC_ETM_CH_CLR41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR41 (BIT(9)) +#define SOC_ETM_CH_CLR41_M (SOC_ETM_CH_CLR41_V << SOC_ETM_CH_CLR41_S) +#define SOC_ETM_CH_CLR41_V 0x00000001U +#define SOC_ETM_CH_CLR41_S 9 +/** SOC_ETM_CH_CLR42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR42 (BIT(10)) +#define SOC_ETM_CH_CLR42_M (SOC_ETM_CH_CLR42_V << SOC_ETM_CH_CLR42_S) +#define SOC_ETM_CH_CLR42_V 0x00000001U +#define SOC_ETM_CH_CLR42_S 10 +/** SOC_ETM_CH_CLR43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR43 (BIT(11)) +#define SOC_ETM_CH_CLR43_M (SOC_ETM_CH_CLR43_V << SOC_ETM_CH_CLR43_S) +#define SOC_ETM_CH_CLR43_V 0x00000001U +#define SOC_ETM_CH_CLR43_S 11 +/** SOC_ETM_CH_CLR44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR44 (BIT(12)) +#define SOC_ETM_CH_CLR44_M (SOC_ETM_CH_CLR44_V << SOC_ETM_CH_CLR44_S) +#define SOC_ETM_CH_CLR44_V 0x00000001U +#define SOC_ETM_CH_CLR44_S 12 +/** SOC_ETM_CH_CLR45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR45 (BIT(13)) +#define SOC_ETM_CH_CLR45_M (SOC_ETM_CH_CLR45_V << SOC_ETM_CH_CLR45_S) +#define SOC_ETM_CH_CLR45_V 0x00000001U +#define SOC_ETM_CH_CLR45_S 13 +/** SOC_ETM_CH_CLR46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR46 (BIT(14)) +#define SOC_ETM_CH_CLR46_M (SOC_ETM_CH_CLR46_V << SOC_ETM_CH_CLR46_S) +#define SOC_ETM_CH_CLR46_V 0x00000001U +#define SOC_ETM_CH_CLR46_S 14 +/** SOC_ETM_CH_CLR47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR47 (BIT(15)) +#define SOC_ETM_CH_CLR47_M (SOC_ETM_CH_CLR47_V << SOC_ETM_CH_CLR47_S) +#define SOC_ETM_CH_CLR47_V 0x00000001U +#define SOC_ETM_CH_CLR47_S 15 +/** SOC_ETM_CH_CLR48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR48 (BIT(16)) +#define SOC_ETM_CH_CLR48_M (SOC_ETM_CH_CLR48_V << SOC_ETM_CH_CLR48_S) +#define SOC_ETM_CH_CLR48_V 0x00000001U +#define SOC_ETM_CH_CLR48_S 16 +/** SOC_ETM_CH_CLR49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_CH_CLR49 (BIT(17)) +#define SOC_ETM_CH_CLR49_M (SOC_ETM_CH_CLR49_V << SOC_ETM_CH_CLR49_S) +#define SOC_ETM_CH_CLR49_V 0x00000001U +#define SOC_ETM_CH_CLR49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * Channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * Channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * Channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * Channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * Channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * Channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * Channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * Channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * Channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * Channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * Channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * Channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * Channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * Channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * Channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * Channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * Channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * Channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * Channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * Channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * Channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * Channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * Channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * Channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * Channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * Channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * Channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * Channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * Channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * Channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * Channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * Channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * Channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * Channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * Channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * Channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * Channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * Channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * Channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * Channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * Channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * Channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * Channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * Channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * Channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * Channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * Channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * Channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * Channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * Channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * Channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * Channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * Channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * Channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * Channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * Channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * Channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * Channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * Channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * Channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * Channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * Channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * Channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * Channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * Channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * Channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * Channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * Channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * Channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * Channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * Channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * Channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * Channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * Channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * Channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * Channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * Channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * Channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * Channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * Channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * Channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * Channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * Channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * Channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * Channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * Channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * Channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * Channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * Channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * Channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * Channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * Channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * Channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * Channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * Channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * Channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * Channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * Channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * Channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * Channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_EVT_ST0_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 31 + +/** SOC_ETM_EVT_ST0_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST1_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 0 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 1 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST (BIT(2)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_S 2 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST (BIT(3)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 5 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST (BIT(6)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 6 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST (BIT(7)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 7 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST (BIT(8)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 8 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST (BIT(9)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 9 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST (BIT(10)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_S 10 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST (BIT(11)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_S 11 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 12 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 13 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST (BIT(14)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 14 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST (BIT(15)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 15 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST (BIT(16)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 16 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST (BIT(17)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 17 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST (BIT(18)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 18 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST (BIT(19)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 19 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST (BIT(20)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 20 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST (BIT(21)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 21 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST (BIT(22)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 22 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST (BIT(23)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 23 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST (BIT(24)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 24 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST (BIT(25)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 25 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST (BIT(26)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S 29 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S 30 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S 31 + +/** SOC_ETM_EVT_ST1_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_S 2 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 5 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 6 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 7 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 8 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 9 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_S 10 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_S 11 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 12 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 13 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 14 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 15 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 16 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 17 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 18 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 19 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(20)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 20 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(21)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 21 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(22)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 22 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(23)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 23 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(24)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 24 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(25)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 25 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(26)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S 29 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S 30 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST2_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S 0 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S 1 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S 2 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S 3 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S 4 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S 5 +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S 6 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S 7 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S 8 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S 9 +/** SOC_ETM_MCPWM0_EVT_F0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_f0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_M (SOC_ETM_MCPWM0_EVT_F0_ST_V << SOC_ETM_MCPWM0_EVT_F0_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_S 10 +/** SOC_ETM_MCPWM0_EVT_F1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_f1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_M (SOC_ETM_MCPWM0_EVT_F1_ST_V << SOC_ETM_MCPWM0_EVT_F1_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_S 11 +/** SOC_ETM_MCPWM0_EVT_F2_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_f2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_M (SOC_ETM_MCPWM0_EVT_F2_ST_V << SOC_ETM_MCPWM0_EVT_F2_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_S 12 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S 13 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S 14 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S 15 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S 16 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S 17 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S 18 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S 19 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S 20 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S 21 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_S 22 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_S 23 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_S 24 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S 25 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S 26 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S 27 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S 28 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S 29 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S 30 +/** SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM1_evt_timer0_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST (BIT(31)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_S 31 + +/** SOC_ETM_EVT_ST2_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S 0 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S 1 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S 2 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S 5 +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S 6 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S 7 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S 8 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S 9 +/** SOC_ETM_MCPWM0_EVT_F0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S 10 +/** SOC_ETM_MCPWM0_EVT_F1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S 11 +/** SOC_ETM_MCPWM0_EVT_F2_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S 12 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S 13 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S 14 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S 25 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S 26 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S 27 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S 28 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S 29 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S 30 +/** SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_STOP_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST3_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) +/** SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM1_evt_timer1_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST (BIT(0)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_S 0 +/** SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM1_evt_timer2_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST (BIT(1)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_S 1 +/** SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM1_evt_timer0_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST (BIT(2)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_M (SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_S 2 +/** SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM1_evt_timer1_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST (BIT(3)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_M (SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_S 3 +/** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM1_evt_timer2_tez trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST (BIT(4)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_M (SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_S 4 +/** SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM1_evt_timer0_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST (BIT(5)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_S 5 +/** SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM1_evt_timer1_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST (BIT(6)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_S 6 +/** SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM1_evt_timer2_tep trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST (BIT(7)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_M (SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_S 7 +/** SOC_ETM_MCPWM1_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM1_evt_op0_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST (BIT(8)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_M (SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_S 8 +/** SOC_ETM_MCPWM1_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM1_evt_op1_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST (BIT(9)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_M (SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_S 9 +/** SOC_ETM_MCPWM1_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM1_evt_op2_tea trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST (BIT(10)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_M (SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_S 10 +/** SOC_ETM_MCPWM1_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM1_evt_op0_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST (BIT(11)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_M (SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_S 11 +/** SOC_ETM_MCPWM1_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM1_evt_op1_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST (BIT(12)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_M (SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_S 12 +/** SOC_ETM_MCPWM1_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM1_evt_op2_teb trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST (BIT(13)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_M (SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_S 13 +/** SOC_ETM_MCPWM1_EVT_F0_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM1_evt_f0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F0_ST (BIT(14)) +#define SOC_ETM_MCPWM1_EVT_F0_ST_M (SOC_ETM_MCPWM1_EVT_F0_ST_V << SOC_ETM_MCPWM1_EVT_F0_ST_S) +#define SOC_ETM_MCPWM1_EVT_F0_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F0_ST_S 14 +/** SOC_ETM_MCPWM1_EVT_F1_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM1_evt_f1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F1_ST (BIT(15)) +#define SOC_ETM_MCPWM1_EVT_F1_ST_M (SOC_ETM_MCPWM1_EVT_F1_ST_V << SOC_ETM_MCPWM1_EVT_F1_ST_S) +#define SOC_ETM_MCPWM1_EVT_F1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F1_ST_S 15 +/** SOC_ETM_MCPWM1_EVT_F2_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM1_evt_f2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F2_ST (BIT(16)) +#define SOC_ETM_MCPWM1_EVT_F2_ST_M (SOC_ETM_MCPWM1_EVT_F2_ST_V << SOC_ETM_MCPWM1_EVT_F2_ST_S) +#define SOC_ETM_MCPWM1_EVT_F2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F2_ST_S 16 +/** SOC_ETM_MCPWM1_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM1_evt_f0_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST (BIT(17)) +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_M (SOC_ETM_MCPWM1_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F0_CLR_ST_S) +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_S 17 +/** SOC_ETM_MCPWM1_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM1_evt_f1_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST (BIT(18)) +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_M (SOC_ETM_MCPWM1_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F1_CLR_ST_S) +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_S 18 +/** SOC_ETM_MCPWM1_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM1_evt_f2_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST (BIT(19)) +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_M (SOC_ETM_MCPWM1_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM1_EVT_F2_CLR_ST_S) +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_S 19 +/** SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM1_evt_tz0_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST (BIT(20)) +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_M (SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_S 20 +/** SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM1_evt_tz1_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST (BIT(21)) +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_M (SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_S 21 +/** SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM1_evt_tz2_cbc trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST (BIT(22)) +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_M (SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_S 22 +/** SOC_ETM_MCPWM1_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM1_evt_tz0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST (BIT(23)) +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_M (SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_S 23 +/** SOC_ETM_MCPWM1_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM1_evt_tz1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST (BIT(24)) +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_M (SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_S 24 +/** SOC_ETM_MCPWM1_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM1_evt_tz2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST (BIT(25)) +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_M (SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_S 25 +/** SOC_ETM_MCPWM1_EVT_CAP0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM1_evt_cap0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_CAP0_ST (BIT(26)) +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_M (SOC_ETM_MCPWM1_EVT_CAP0_ST_V << SOC_ETM_MCPWM1_EVT_CAP0_ST_S) +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_S 26 +/** SOC_ETM_MCPWM1_EVT_CAP1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM1_evt_cap1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_CAP1_ST (BIT(27)) +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_M (SOC_ETM_MCPWM1_EVT_CAP1_ST_V << SOC_ETM_MCPWM1_EVT_CAP1_ST_S) +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_S 27 +/** SOC_ETM_MCPWM1_EVT_CAP2_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM1_evt_cap2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_CAP2_ST (BIT(28)) +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_M (SOC_ETM_MCPWM1_EVT_CAP2_ST_V << SOC_ETM_MCPWM1_EVT_CAP2_ST_S) +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_S 28 +/** SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM1_evt_op0_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST (BIT(29)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_M (SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_S 29 +/** SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM1_evt_op1_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST (BIT(30)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_M (SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_S 30 +/** SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM1_evt_op2_tee1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST (BIT(31)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_M (SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_S 31 + +/** SOC_ETM_EVT_ST3_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) +/** SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_STOP_ST_CLR_S 0 +/** SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_STOP_ST_CLR_S 1 +/** SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_S 2 +/** SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR (BIT(3)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_S 3 +/** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_S 4 +/** SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER0_TEP_ST_CLR_S 5 +/** SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER1_TEP_ST_CLR_S 6 +/** SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TIMER2_TEP_ST_CLR_S 7 +/** SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEA_ST_CLR_S 8 +/** SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEA_ST_CLR_S 9 +/** SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tea trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEA_ST_CLR_S 10 +/** SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEB_ST_CLR_S 11 +/** SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEB_ST_CLR_S 12 +/** SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_teb trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEB_ST_CLR_S 13 +/** SOC_ETM_MCPWM1_EVT_F0_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F0_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F0_ST_CLR_S 14 +/** SOC_ETM_MCPWM1_EVT_F1_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F1_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F1_ST_CLR_S 15 +/** SOC_ETM_MCPWM1_EVT_F2_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F2_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F2_ST_CLR_S 16 +/** SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f0_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F0_CLR_ST_CLR_S 17 +/** SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f1_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F1_CLR_ST_CLR_S 18 +/** SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f2_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_M (SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_F2_CLR_ST_CLR_S 19 +/** SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ0_CBC_ST_CLR_S 20 +/** SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ1_CBC_ST_CLR_S 21 +/** SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ2_CBC_ST_CLR_S 22 +/** SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ0_OST_ST_CLR_S 23 +/** SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ1_OST_ST_CLR_S 24 +/** SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_TZ2_OST_ST_CLR_S 25 +/** SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_M (SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP0_ST_CLR_S 26 +/** SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_M (SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP1_ST_CLR_S 27 +/** SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_M (SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_CAP2_ST_CLR_S 28 +/** SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEE1_ST_CLR_S 29 +/** SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEE1_ST_CLR_S 30 +/** SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEE1_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST4_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8) +/** SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM1_evt_op0_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST (BIT(0)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_M (SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_S 0 +/** SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM1_evt_op1_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST (BIT(1)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_M (SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_S 1 +/** SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM1_evt_op2_tee2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST (BIT(2)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_M (SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_S 2 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST (BIT(3)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 3 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST (BIT(4)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 4 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST (BIT(5)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 5 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST (BIT(6)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 6 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST (BIT(7)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 7 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents ADC_evt_result_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST (BIT(8)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 8 +/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ADC_evt_stopped0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST (BIT(9)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_M (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_S 9 +/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ADC_evt_started0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST (BIT(10)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_S 10 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_evt_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(11)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 11 +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents REGDMA_evt_done1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(12)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 12 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents REGDMA_evt_done2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(13)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 13 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents REGDMA_evt_done3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(14)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 14 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents REGDMA_evt_err0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(15)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 15 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents REGDMA_evt_err1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(16)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 16 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents REGDMA_evt_err2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(17)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 17 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents REGDMA_evt_err3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(18)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 18 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST (BIT(19)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 19 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S0_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST (BIT(20)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 20 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S0_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST (BIT(21)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 21 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents I2S0_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST (BIT(22)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 22 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST (BIT(23)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 23 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents I2S1_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST (BIT(24)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_S 24 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents I2S1_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST (BIT(25)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_S 25 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents I2S1_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST (BIT(26)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S 26 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST (BIT(27)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S 27 +/** SOC_ETM_I2S2_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents I2S2_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_EVT_RX_DONE_ST (BIT(28)) +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_M (SOC_ETM_I2S2_EVT_RX_DONE_ST_V << SOC_ETM_I2S2_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_S 28 +/** SOC_ETM_I2S2_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents I2S2_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_EVT_TX_DONE_ST (BIT(29)) +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_M (SOC_ETM_I2S2_EVT_TX_DONE_ST_V << SOC_ETM_I2S2_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_S 29 +/** SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents I2S2_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST (BIT(30)) +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_S 30 +/** SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents I2S2_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST (BIT(31)) +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_S 31 + +/** SOC_ETM_EVT_ST4_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) +/** SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP0_TEE2_ST_CLR_S 0 +/** SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP1_TEE2_ST_CLR_S 1 +/** SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_M (SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_EVT_OP2_TEE2_ST_CLR_S 2 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(3)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 3 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(4)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 4 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(5)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 5 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(6)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 6 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(7)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 7 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(8)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 8 +/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(9)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 9 +/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(10)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 10 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(11)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 11 +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(12)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 12 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(13)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 13 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(14)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 14 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(15)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 15 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(16)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 16 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(17)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 17 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(18)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 18 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(19)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 19 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(20)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 20 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(21)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 21 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(22)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 22 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(23)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 23 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR (BIT(24)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S 24 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR (BIT(25)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S 25 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(26)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S 26 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR (BIT(27)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S 27 +/** SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear I2S2_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR (BIT(28)) +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_EVT_RX_DONE_ST_CLR_S 28 +/** SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear I2S2_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR (BIT(29)) +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_EVT_TX_DONE_ST_CLR_S 29 +/** SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear I2S2_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(30)) +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_S 30 +/** SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear I2S2_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR (BIT(31)) +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_EVT_X_WORDS_SENT_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST5_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_ETM_BASE + 0x1d0) +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ULP_evt_err_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(0)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 0 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents ULP_evt_halt trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(1)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 1 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents ULP_evt_start_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(2)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 2 +/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents RTC_evt_tick trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_EVT_TICK_ST (BIT(3)) +#define SOC_ETM_RTC_EVT_TICK_ST_M (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S) +#define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_S 3 +/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents RTC_evt_ovf trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_EVT_OVF_ST (BIT(4)) +#define SOC_ETM_RTC_EVT_OVF_ST_M (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S) +#define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_S 4 +/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents RTC_evt_cmp trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_EVT_CMP_ST (BIT(5)) +#define SOC_ETM_RTC_EVT_CMP_ST_M (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S) +#define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_S 5 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST (BIT(6)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_S 6 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST (BIT(7)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_S 7 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST (BIT(8)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_S 8 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST (BIT(9)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S 9 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST (BIT(10)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S 10 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST (BIT(11)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S 11 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST (BIT(12)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S 12 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST (BIT(13)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S 13 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(14)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S 14 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST (BIT(15)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S 15 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST (BIT(16)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S 16 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST (BIT(17)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S 17 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST (BIT(18)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_S 18 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST (BIT(19)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_S 19 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST (BIT(20)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_S 20 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST (BIT(21)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_S 21 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST (BIT(22)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_S 22 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST (BIT(23)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_S 23 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(24)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S 24 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(25)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S 25 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(26)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S 26 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST (BIT(27)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S 27 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST (BIT(28)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S 28 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(29)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S 29 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST (BIT(30)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S 30 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST (BIT(31)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S 31 + +/** SOC_ETM_EVT_ST5_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(0)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 0 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(1)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 1 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(2)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 2 +/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(3)) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 3 +/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(4)) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 4 +/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(5)) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 5 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR (BIT(6)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S 6 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR (BIT(7)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S 7 +/** SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR (BIT(8)) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S 8 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(9)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S 9 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(10)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S 10 +/** SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(11)) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S 11 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 12 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 13 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 14 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(15)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 15 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(16)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 16 +/** SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(17)) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 17 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR (BIT(18)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S 18 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR (BIT(19)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S 19 +/** SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR (BIT(20)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S 20 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR (BIT(21)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S 21 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR (BIT(22)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S 22 +/** SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR (BIT(23)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S 23 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(24)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 24 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(25)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 25 +/** SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(26)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 26 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(27)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 27 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(28)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 28 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(29)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 29 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 30 +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST6_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_ETM_BASE + 0x1d8) +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST (BIT(0)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S 0 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST (BIT(1)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_S 1 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST (BIT(2)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_S 2 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST (BIT(3)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_S 3 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST (BIT(4)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_S 4 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST (BIT(5)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_S 5 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST (BIT(6)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_S 6 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST (BIT(7)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_S 7 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST (BIT(8)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_S 8 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(9)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_S 9 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST (BIT(10)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_S 10 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST (BIT(11)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_S 11 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST (BIT(12)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_S 12 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST (BIT(13)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_S 13 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST (BIT(14)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_S 14 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST (BIT(15)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_S 15 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST (BIT(16)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_S 16 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST (BIT(17)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_S 17 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST (BIT(18)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_S 18 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(19)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_S 19 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(20)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_S 20 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(21)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_S 21 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST (BIT(22)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_S 22 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST (BIT(23)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_S 23 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(24)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_S 24 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST (BIT(25)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_S 25 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST (BIT(26)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_S 26 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST (BIT(27)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_S 27 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST (BIT(28)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 28 +/** SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents DMA2D_evt_in_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST (BIT(29)) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_M (SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_S 29 +/** SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents DMA2D_evt_in_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST (BIT(30)) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_M (SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_S 30 +/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents DMA2D_evt_in_suc_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST (BIT(31)) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_S 31 + +/** SOC_ETM_EVT_ST6_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) +/** SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 0 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR (BIT(1)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_S 1 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR (BIT(2)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_S 2 +/** SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR (BIT(3)) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_S 3 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_S 4 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_S 5 +/** SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_S 6 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(7)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 7 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(8)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 8 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(9)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 9 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(10)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 10 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(11)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 11 +/** SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(12)) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 12 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR (BIT(13)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_S 13 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR (BIT(14)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_S 14 +/** SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR (BIT(15)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_S 15 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR (BIT(16)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_S 16 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR (BIT(17)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_S 17 +/** SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR (BIT(18)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_S 18 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(19)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 19 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(20)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 20 +/** SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(21)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 21 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(22)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 22 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(23)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 23 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(24)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 24 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(25)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 25 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(26)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 26 +/** SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(27)) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 27 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(28)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 28 +/** SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR (BIT(29)) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH0_ST_CLR_S 29 +/** SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR (BIT(30)) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_DONE_CH1_ST_CLR_S 30 +/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(31)) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST7_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST7_REG (DR_REG_SOC_ETM_BASE + 0x1e0) +/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents DMA2D_evt_in_suc_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST (BIT(0)) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_S 0 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents DMA2D_evt_out_done_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST (BIT(1)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_S 1 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents DMA2D_evt_out_done_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST (BIT(2)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_S 2 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents DMA2D_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST (BIT(3)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_S 3 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents DMA2D_evt_out_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST (BIT(4)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_S 4 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents DMA2D_evt_out_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST (BIT(5)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_S 5 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents DMA2D_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST (BIT(6)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_S 6 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(7)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_S 7 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(8)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_S 8 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(9)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_S 9 + +/** SOC_ETM_EVT_ST7_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST7_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) +/** SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(0)) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_S 0 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR (BIT(1)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_S 1 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR (BIT(2)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_S 2 +/** SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR (BIT(3)) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_S 3 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_S 4 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_S 5 +/** SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_S 6 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(7)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 7 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(8)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 8 +/** SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(9)) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 9 + +/** SOC_ETM_TASK_ST0_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1e8) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 + +/** SOC_ETM_TASK_ST0_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST1_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1f0) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_duty_scale_update_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_S 2 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_duty_scale_update_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_S 3 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer0_cap trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 4 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer1_cap trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 5 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_timer2_cap trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 6 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_timer3_cap trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 11 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 12 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 13 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_sig_out_dis_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_S 14 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_sig_out_dis_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 17 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST (BIT(18)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 18 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST (BIT(19)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 19 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST (BIT(20)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 20 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST (BIT(21)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 21 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST (BIT(22)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_S 22 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST (BIT(23)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_rst trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_rst trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_rst trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_rst trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 27 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer0_resume trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 28 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer1_resume trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 29 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_timer2_resume trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 30 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_timer3_resume trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 31 + +/** SOC_ETM_TASK_ST1_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 17 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 18 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 19 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(20)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 20 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(21)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 21 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR (BIT(22)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_S 22 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR (BIT(23)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST2_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1f8) +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_timer0_pause trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 0 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_timer1_pause trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 1 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer2_pause trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 2 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer3_pause trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_restart_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_restart_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 15 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST (BIT(16)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 16 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST (BIT(17)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 17 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_gamma_pause_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST (BIT(18)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_S 18 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_gamma_pause_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST (BIT(19)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_S 19 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST (BIT(20)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 20 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST (BIT(21)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 21 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST (BIT(22)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 22 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST (BIT(23)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 23 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 24 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 25 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_gamma_resume_ch6 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_S 26 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_gamma_resume_ch7 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_S 27 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST (BIT(28)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 28 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST (BIT(29)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 29 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST (BIT(30)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 30 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST (BIT(31)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 31 + +/** SOC_ETM_TASK_ST2_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1fc) +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 15 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 16 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 17 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_S 18 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_S 19 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(20)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 20 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(21)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 21 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(22)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 22 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(23)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_S 27 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(28)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 28 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(29)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 29 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(30)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 30 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(31)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST3_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x200) +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST (BIT(0)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 0 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST (BIT(1)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 1 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST (BIT(2)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 2 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST (BIT(3)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 3 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST (BIT(4)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 4 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST (BIT(5)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 5 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST (BIT(6)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 6 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST (BIT(7)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 7 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST (BIT(8)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 8 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST (BIT(9)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 9 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST (BIT(10)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 10 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST (BIT(11)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 11 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST (BIT(12)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 12 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST (BIT(13)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 13 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST (BIT(14)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 14 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST (BIT(15)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 15 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S 16 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S 17 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S 18 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S 19 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S 20 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S 21 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S 22 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S 23 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S 24 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S 25 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST (BIT(26)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S 26 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST (BIT(27)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S 27 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST (BIT(28)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S 28 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST (BIT(29)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S 29 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST (BIT(30)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S 30 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST (BIT(31)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S 31 + +/** SOC_ETM_TASK_ST3_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x204) +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(0)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 0 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(1)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 1 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(2)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 2 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(3)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 3 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(4)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 4 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(5)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 5 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(6)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 6 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(7)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 7 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(8)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 8 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(9)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 9 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(10)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 10 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(11)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 11 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(12)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 12 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(13)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 13 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(14)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 14 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(15)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S 25 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S 26 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S 27 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S 28 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S 29 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S 30 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST4_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x208) +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST (BIT(0)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S 0 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST (BIT(1)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S 1 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST (BIT(2)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S 2 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_task_cap0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST (BIT(3)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_S 3 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cap1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_S 4 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cap2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_S 5 +/** SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM1_task_cmpr0_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST (BIT(6)) +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_S 6 +/** SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM1_task_cmpr1_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST (BIT(7)) +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_S 7 +/** SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM1_task_cmpr2_a_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST (BIT(8)) +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_S 8 +/** SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM1_task_cmpr0_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST (BIT(9)) +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_S 9 +/** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM1_task_cmpr1_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST (BIT(10)) +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_S 10 +/** SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM1_task_cmpr2_b_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST (BIT(11)) +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_M (SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_S 11 +/** SOC_ETM_MCPWM1_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM1_task_gen_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST (BIT(12)) +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_M (SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_S) +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_S 12 +/** SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM1_task_timer0_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST (BIT(13)) +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_M (SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_S 13 +/** SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM1_task_timer1_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST (BIT(14)) +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_M (SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_S 14 +/** SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM1_task_timer2_syn trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST (BIT(15)) +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_M (SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_S 15 +/** SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM1_task_timer0_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST (BIT(16)) +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_M (SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_S 16 +/** SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM1_task_timer1_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST (BIT(17)) +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_M (SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_S 17 +/** SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM1_task_timer2_period_up trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST (BIT(18)) +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_M (SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_S 18 +/** SOC_ETM_MCPWM1_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM1_task_tz0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST (BIT(19)) +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_M (SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_S 19 +/** SOC_ETM_MCPWM1_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM1_task_tz1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST (BIT(20)) +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_M (SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_S 20 +/** SOC_ETM_MCPWM1_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM1_task_tz2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST (BIT(21)) +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_M (SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_S 21 +/** SOC_ETM_MCPWM1_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM1_task_clr0_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST (BIT(22)) +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_M (SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_S 22 +/** SOC_ETM_MCPWM1_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM1_task_clr1_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST (BIT(23)) +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_M (SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_S 23 +/** SOC_ETM_MCPWM1_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM1_task_clr2_ost trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST (BIT(24)) +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_M (SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_S) +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_S 24 +/** SOC_ETM_MCPWM1_TASK_CAP0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM1_task_cap0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CAP0_ST (BIT(25)) +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_M (SOC_ETM_MCPWM1_TASK_CAP0_ST_V << SOC_ETM_MCPWM1_TASK_CAP0_ST_S) +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_S 25 +/** SOC_ETM_MCPWM1_TASK_CAP1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM1_task_cap1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CAP1_ST (BIT(26)) +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_M (SOC_ETM_MCPWM1_TASK_CAP1_ST_V << SOC_ETM_MCPWM1_TASK_CAP1_ST_S) +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_S 26 +/** SOC_ETM_MCPWM1_TASK_CAP2_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM1_task_cap2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_MCPWM1_TASK_CAP2_ST (BIT(27)) +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_M (SOC_ETM_MCPWM1_TASK_CAP2_ST_V << SOC_ETM_MCPWM1_TASK_CAP2_ST_S) +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_S 27 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_sample0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST (BIT(28)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 28 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_sample1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(29)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 29 +/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_START0_ST (BIT(30)) +#define SOC_ETM_ADC_TASK_START0_ST_M (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S) +#define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_S 30 +/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_task_stop0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_STOP0_ST (BIT(31)) +#define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_S 31 + +/** SOC_ETM_TASK_ST4_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x20c) +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S 0 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S 1 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S 2 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR (BIT(3)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S 5 +/** SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_S 6 +/** SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_S 7 +/** SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_S 8 +/** SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_S 9 +/** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_S 10 +/** SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_S 11 +/** SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM1_task_gen_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_GEN_STOP_ST_CLR_S 12 +/** SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer0_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER0_SYN_ST_CLR_S 13 +/** SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer1_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER1_SYN_ST_CLR_S 14 +/** SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer2_syn trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER2_SYN_ST_CLR_S 15 +/** SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_S 16 +/** SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_S 17 +/** SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_S 18 +/** SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ0_OST_ST_CLR_S 19 +/** SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ1_OST_ST_CLR_S 20 +/** SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_TZ2_OST_ST_CLR_S 21 +/** SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr0_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR0_OST_ST_CLR_S 22 +/** SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr1_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR1_OST_ST_CLR_S 23 +/** SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr2_ost trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CLR2_OST_ST_CLR_S 24 +/** SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP0_ST_CLR_S 25 +/** SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP1_ST_CLR_S 26 +/** SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_M (SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM1_TASK_CAP2_ST_CLR_S 27 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 28 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 29 +/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(30)) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_M (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_CLR_S 30 +/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(31)) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST5_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_ETM_BASE + 0x210) +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 0 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 1 +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_task_start2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(2)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 2 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_task_start3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(3)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 3 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST (BIT(4)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 4 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST (BIT(5)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 5 +/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST (BIT(6)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_M (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_S 6 +/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST (BIT(7)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_M (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_S 7 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST (BIT(8)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 8 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents I2S0_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST (BIT(9)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 9 +/** SOC_ETM_I2S1_TASK_START_RX_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S1_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST (BIT(10)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_M (SOC_ETM_I2S1_TASK_START_RX_ST_V << SOC_ETM_I2S1_TASK_START_RX_ST_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_S 10 +/** SOC_ETM_I2S1_TASK_START_TX_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S1_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST (BIT(11)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_M (SOC_ETM_I2S1_TASK_START_TX_ST_V << SOC_ETM_I2S1_TASK_START_TX_ST_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_S 11 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST (BIT(12)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_S 12 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST (BIT(13)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_S 13 +/** SOC_ETM_I2S2_TASK_START_RX_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S2_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_TASK_START_RX_ST (BIT(14)) +#define SOC_ETM_I2S2_TASK_START_RX_ST_M (SOC_ETM_I2S2_TASK_START_RX_ST_V << SOC_ETM_I2S2_TASK_START_RX_ST_S) +#define SOC_ETM_I2S2_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S2_TASK_START_RX_ST_S 14 +/** SOC_ETM_I2S2_TASK_START_TX_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S2_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_TASK_START_TX_ST (BIT(15)) +#define SOC_ETM_I2S2_TASK_START_TX_ST_M (SOC_ETM_I2S2_TASK_START_TX_ST_V << SOC_ETM_I2S2_TASK_START_TX_ST_S) +#define SOC_ETM_I2S2_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S2_TASK_START_TX_ST_S 15 +/** SOC_ETM_I2S2_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents I2S2_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_TASK_STOP_RX_ST (BIT(16)) +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_M (SOC_ETM_I2S2_TASK_STOP_RX_ST_V << SOC_ETM_I2S2_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_S 16 +/** SOC_ETM_I2S2_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents I2S2_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S2_TASK_STOP_TX_ST (BIT(17)) +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_M (SOC_ETM_I2S2_TASK_STOP_TX_ST_V << SOC_ETM_I2S2_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_S 17 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(18)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 18 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents ULP_task_int_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(19)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 19 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents RTC_task_start trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(20)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 20 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents RTC_task_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(21)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 21 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents RTC_task_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(22)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 22 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents RTC_task_triggerflw trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(23)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 23 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AHB_task_in_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST (BIT(24)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_S 24 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AHB_task_in_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST (BIT(25)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_S 25 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AHB_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST (BIT(26)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_S 26 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AHB_task_out_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST (BIT(27)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_S 27 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PDMA_AHB_task_out_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST (BIT(28)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_S 28 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents PDMA_AHB_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST (BIT(29)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_S 29 +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents PDMA_AXI_task_in_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST (BIT(30)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_S 30 +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents PDMA_AXI_task_in_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST (BIT(31)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_S 31 + +/** SOC_ETM_TASK_ST5_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x214) +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 0 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 1 +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 2 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 3 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(4)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 4 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(5)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 5 +/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(6)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 6 +/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(7)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 7 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(8)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 8 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(9)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 9 +/** SOC_ETM_I2S1_TASK_START_RX_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR (BIT(10)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S 10 +/** SOC_ETM_I2S1_TASK_START_TX_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR (BIT(11)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S 11 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR (BIT(12)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S 12 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR (BIT(13)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S 13 +/** SOC_ETM_I2S2_TASK_START_RX_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S2_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR (BIT(14)) +#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S2_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S2_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_TASK_START_RX_ST_CLR_S 14 +/** SOC_ETM_I2S2_TASK_START_TX_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S2_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR (BIT(15)) +#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S2_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S2_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_TASK_START_TX_ST_CLR_S 15 +/** SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear I2S2_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR (BIT(16)) +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_TASK_STOP_RX_ST_CLR_S 16 +/** SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear I2S2_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR (BIT(17)) +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S2_TASK_STOP_TX_ST_CLR_S 17 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(18)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 18 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(19)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 19 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(20)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 20 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(21)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 21 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(22)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 22 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(23)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 23 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR (BIT(24)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_S 24 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR (BIT(25)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_S 25 +/** SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR (BIT(26)) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_S 26 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR (BIT(27)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S 27 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR (BIT(28)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S 28 +/** SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR (BIT(29)) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S 29 +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_S 30 +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST6_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST6_REG (DR_REG_SOC_ETM_BASE + 0x218) +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents PDMA_AXI_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST (BIT(0)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_S 0 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents PDMA_AXI_task_out_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST (BIT(1)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_S 1 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PDMA_AXI_task_out_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST (BIT(2)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_S 2 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents PDMA_AXI_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST (BIT(3)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_S 3 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents PMU_task_sleep_req trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST (BIT(4)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 4 +/** SOC_ETM_DMA2D_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents DMA2D_task_in_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST (BIT(5)) +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_M (SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_V << SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_S 5 +/** SOC_ETM_DMA2D_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents DMA2D_task_in_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST (BIT(6)) +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_M (SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_V << SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_S 6 +/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents DMA2D_task_in_dscr_ready_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST (BIT(7)) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_M (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_S) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_S 7 +/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents DMA2D_task_in_dscr_ready_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST (BIT(8)) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_M (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_S) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_S 8 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents DMA2D_task_out_start_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST (BIT(9)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_M (SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_S 9 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents DMA2D_task_out_start_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST (BIT(10)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_M (SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_S 10 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents DMA2D_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST (BIT(11)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_M (SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_V << SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_S 11 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST (BIT(12)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_S 12 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST (BIT(13)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_S 13 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST (BIT(14)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_S 14 + +/** SOC_ETM_TASK_ST6_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x21c) +/** SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_S 0 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR (BIT(1)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_S 1 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR (BIT(2)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_S 2 +/** SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR (BIT(3)) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_S 3 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(4)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S 4 +/** SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR (BIT(5)) +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_START_CH0_ST_CLR_S 5 +/** SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR (BIT(6)) +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_START_CH1_ST_CLR_S 6 +/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR (BIT(7)) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_M (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_S 7 +/** SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR (BIT(8)) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_M (SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_S 8 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR (BIT(9)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH0_ST_CLR_S 9 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR (BIT(10)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH1_ST_CLR_S 10 +/** SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR (BIT(11)) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_START_CH2_ST_CLR_S 11 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_S 12 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_S 13 +/** SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_M (SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_V << SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_S) +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_S 14 + +/** SOC_ETM_CLK_EN_REG register + * ETM clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x220) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * ETM date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x224) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36712497; + * Configures the version. + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h new file mode 100644 index 0000000000..63d820d1c5 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h @@ -0,0 +1,5134 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13428 + +/** Group: Status register */ +/** Type of ch_ena_ad0 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena0: 1; + /** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena1: 1; + /** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena2: 1; + /** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena3: 1; + /** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena4: 1; + /** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena5: 1; + /** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena6: 1; + /** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena7: 1; + /** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena8: 1; + /** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena9: 1; + /** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena10: 1; + /** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena11: 1; + /** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena12: 1; + /** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena13: 1; + /** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena14: 1; + /** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena15: 1; + /** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena16: 1; + /** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena17: 1; + /** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena18: 1; + /** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena19: 1; + /** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena20: 1; + /** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena21: 1; + /** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena22: 1; + /** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena23: 1; + /** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena24: 1; + /** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena25: 1; + /** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena26: 1; + /** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena27: 1; + /** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena28: 1; + /** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena29: 1; + /** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena30: 1; + /** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena31: 1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad1 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena32: 1; + /** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena33: 1; + /** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena34: 1; + /** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena35: 1; + /** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena36: 1; + /** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena37: 1; + /** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena38: 1; + /** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena39: 1; + /** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena40: 1; + /** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena41: 1; + /** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena42: 1; + /** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena43: 1; + /** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena44: 1; + /** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena45: 1; + /** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena46: 1; + /** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena47: 1; + /** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena48: 1; + /** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_ena49: 1; + uint32_t reserved_18: 14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of evt_st0 register + * Events trigger status register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_rise_edge_st: 1; + /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_rise_edge_st: 1; + /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_rise_edge_st: 1; + /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_rise_edge_st: 1; + /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_rise_edge_st: 1; + /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_rise_edge_st: 1; + /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_rise_edge_st: 1; + /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_rise_edge_st: 1; + /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_fall_edge_st: 1; + /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_fall_edge_st: 1; + /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_fall_edge_st: 1; + /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_fall_edge_st: 1; + /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_fall_edge_st: 1; + /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_fall_edge_st: 1; + /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_fall_edge_st: 1; + /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_fall_edge_st: 1; + /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_any_edge_st: 1; + /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_any_edge_st: 1; + /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_any_edge_st: 1; + /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_any_edge_st: 1; + /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_any_edge_st: 1; + /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_any_edge_st: 1; + /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_any_edge_st: 1; + /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_any_edge_st: 1; + /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos0_st: 1; + /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg0_st: 1; + /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos1_st: 1; + /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg1_st: 1; + /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch0_st: 1; + /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch1_st: 1; + /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch2_st: 1; + /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch3_st: 1; + }; + uint32_t val; +} soc_etm_evt_st0_reg_t; + +/** Type of evt_st1 register + * Events trigger status register + */ +typedef union { + struct { + /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch4_st: 1; + /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch5_st: 1; + /** ledc_evt_duty_chng_end_ch6_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch6_st: 1; + /** ledc_evt_duty_chng_end_ch7_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch7_st: 1; + /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st: 1; + /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st: 1; + /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st: 1; + /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st: 1; + /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st: 1; + /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st: 1; + /** ledc_evt_ovf_cnt_pls_ch6_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch6_st: 1; + /** ledc_evt_ovf_cnt_pls_ch7_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch7_st: 1; + /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer0_st: 1; + /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer1_st: 1; + /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer2_st: 1; + /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer3_st: 1; + /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer0_cmp_st: 1; + /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer1_cmp_st: 1; + /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer2_cmp_st: 1; + /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer3_cmp_st: 1; + /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer0_st: 1; + /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer1_st: 1; + /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer0_st: 1; + /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer1_st: 1; + /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp0_st: 1; + /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp1_st: 1; + /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp2_st: 1; + /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_stop_st: 1; + /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_stop_st: 1; + /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_stop_st: 1; + /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tez_st: 1; + /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tez_st: 1; + }; + uint32_t val; +} soc_etm_evt_st1_reg_t; + +/** Type of evt_st2 register + * Events trigger status register + */ +typedef union { + struct { + /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tez_st: 1; + /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tep_st: 1; + /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tep_st: 1; + /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tep_st: 1; + /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tea_st: 1; + /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tea_st: 1; + /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tea_st: 1; + /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_teb_st: 1; + /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_teb_st: 1; + /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_teb_st: 1; + /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_st: 1; + /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_st: 1; + /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_st: 1; + /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_clr_st: 1; + /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_clr_st: 1; + /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_clr_st: 1; + /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_cbc_st: 1; + /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_cbc_st: 1; + /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_cbc_st: 1; + /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_ost_st: 1; + /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_ost_st: 1; + /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_ost_st: 1; + /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap0_st: 1; + /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap1_st: 1; + /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap2_st: 1; + /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee1_st: 1; + /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee1_st: 1; + /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee1_st: 1; + /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee2_st: 1; + /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee2_st: 1; + /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee2_st: 1; + /** mcpwm1_evt_timer0_stop_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer0_stop_st: 1; + }; + uint32_t val; +} soc_etm_evt_st2_reg_t; + +/** Type of evt_st3 register + * Events trigger status register + */ +typedef union { + struct { + /** mcpwm1_evt_timer1_stop_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer1_stop_st: 1; + /** mcpwm1_evt_timer2_stop_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer2_stop_st: 1; + /** mcpwm1_evt_timer0_tez_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer0_tez_st: 1; + /** mcpwm1_evt_timer1_tez_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer1_tez_st: 1; + /** mcpwm1_evt_timer2_tez_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer2_tez_st: 1; + /** mcpwm1_evt_timer0_tep_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer0_tep_st: 1; + /** mcpwm1_evt_timer1_tep_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer1_tep_st: 1; + /** mcpwm1_evt_timer2_tep_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_timer2_tep_st: 1; + /** mcpwm1_evt_op0_tea_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op0_tea_st: 1; + /** mcpwm1_evt_op1_tea_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op1_tea_st: 1; + /** mcpwm1_evt_op2_tea_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op2_tea_st: 1; + /** mcpwm1_evt_op0_teb_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op0_teb_st: 1; + /** mcpwm1_evt_op1_teb_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op1_teb_st: 1; + /** mcpwm1_evt_op2_teb_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op2_teb_st: 1; + /** mcpwm1_evt_f0_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f0_st: 1; + /** mcpwm1_evt_f1_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f1_st: 1; + /** mcpwm1_evt_f2_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f2_st: 1; + /** mcpwm1_evt_f0_clr_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f0_clr_st: 1; + /** mcpwm1_evt_f1_clr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f1_clr_st: 1; + /** mcpwm1_evt_f2_clr_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_f2_clr_st: 1; + /** mcpwm1_evt_tz0_cbc_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz0_cbc_st: 1; + /** mcpwm1_evt_tz1_cbc_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz1_cbc_st: 1; + /** mcpwm1_evt_tz2_cbc_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz2_cbc_st: 1; + /** mcpwm1_evt_tz0_ost_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz0_ost_st: 1; + /** mcpwm1_evt_tz1_ost_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz1_ost_st: 1; + /** mcpwm1_evt_tz2_ost_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_tz2_ost_st: 1; + /** mcpwm1_evt_cap0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_cap0_st: 1; + /** mcpwm1_evt_cap1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_cap1_st: 1; + /** mcpwm1_evt_cap2_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_cap2_st: 1; + /** mcpwm1_evt_op0_tee1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op0_tee1_st: 1; + /** mcpwm1_evt_op1_tee1_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op1_tee1_st: 1; + /** mcpwm1_evt_op2_tee1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op2_tee1_st: 1; + }; + uint32_t val; +} soc_etm_evt_st3_reg_t; + +/** Type of evt_st4 register + * Events trigger status register + */ +typedef union { + struct { + /** mcpwm1_evt_op0_tee2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op0_tee2_st: 1; + /** mcpwm1_evt_op1_tee2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op1_tee2_st: 1; + /** mcpwm1_evt_op2_tee2_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_evt_op2_tee2_st: 1; + /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_conv_cmplt0_st: 1; + /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh0_st: 1; + /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh1_st: 1; + /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh0_st: 1; + /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh1_st: 1; + /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_result_done0_st: 1; + /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_stopped0_st: 1; + /** adc_evt_started0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_started0_st: 1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done0_st: 1; + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done1_st: 1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done2_st: 1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done3_st: 1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err0_st: 1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err1_st: 1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err2_st: 1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err3_st: 1; + /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_evt_over_limit_st: 1; + /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_rx_done_st: 1; + /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_tx_done_st: 1; + /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_received_st: 1; + /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_sent_st: 1; + /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_rx_done_st: 1; + /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_tx_done_st: 1; + /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_x_words_received_st: 1; + /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_evt_x_words_sent_st: 1; + /** i2s2_evt_rx_done_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_evt_rx_done_st: 1; + /** i2s2_evt_tx_done_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_evt_tx_done_st: 1; + /** i2s2_evt_x_words_received_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_evt_x_words_received_st: 1; + /** i2s2_evt_x_words_sent_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_evt_x_words_sent_st: 1; + }; + uint32_t val; +} soc_etm_evt_st4_reg_t; + +/** Type of evt_st5 register + * Events trigger status register + */ +typedef union { + struct { + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_err_intr_st: 1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_halt_st: 1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_start_intr_st: 1; + /** rtc_evt_tick_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_tick_st: 1; + /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_ovf_st: 1; + /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_cmp_st: 1; + /** pdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_in_done_ch0_st: 1; + /** pdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_in_done_ch1_st: 1; + /** pdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_in_done_ch2_st: 1; + /** pdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch0_st: 1; + /** pdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch1_st: 1; + /** pdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch2_st: 1; + /** pdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st: 1; + /** pdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st: 1; + /** pdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st: 1; + /** pdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch0_st: 1; + /** pdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch1_st: 1; + /** pdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch2_st: 1; + /** pdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_done_ch0_st: 1; + /** pdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_done_ch1_st: 1; + /** pdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_done_ch2_st: 1; + /** pdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_eof_ch0_st: 1; + /** pdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_eof_ch1_st: 1; + /** pdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_ahb_evt_out_eof_ch2_st: 1; + /** pdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_total_eof_ch0_st: 1; + /** pdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_total_eof_ch1_st: 1; + /** pdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_total_eof_ch2_st: 1; + /** pdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st: 1; + /** pdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st: 1; + /** pdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st: 1; + /** pdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch0_st: 1; + /** pdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch1_st: 1; + }; + uint32_t val; +} soc_etm_evt_st5_reg_t; + +/** Type of evt_st6 register + * Events trigger status register + */ +typedef union { + struct { + /** pdma_ahb_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch2_st: 1; + /** pdma_axi_evt_in_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_in_done_ch0_st: 1; + /** pdma_axi_evt_in_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_in_done_ch1_st: 1; + /** pdma_axi_evt_in_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_in_done_ch2_st: 1; + /** pdma_axi_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_suc_eof_ch0_st: 1; + /** pdma_axi_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_suc_eof_ch1_st: 1; + /** pdma_axi_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_suc_eof_ch2_st: 1; + /** pdma_axi_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch0_st: 1; + /** pdma_axi_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch1_st: 1; + /** pdma_axi_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch2_st: 1; + /** pdma_axi_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_full_ch0_st: 1; + /** pdma_axi_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_full_ch1_st: 1; + /** pdma_axi_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_in_fifo_full_ch2_st: 1; + /** pdma_axi_evt_out_done_ch0_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_done_ch0_st: 1; + /** pdma_axi_evt_out_done_ch1_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_done_ch1_st: 1; + /** pdma_axi_evt_out_done_ch2_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_done_ch2_st: 1; + /** pdma_axi_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_eof_ch0_st: 1; + /** pdma_axi_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_eof_ch1_st: 1; + /** pdma_axi_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pdma_axi_evt_out_eof_ch2_st: 1; + /** pdma_axi_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_total_eof_ch0_st: 1; + /** pdma_axi_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_total_eof_ch1_st: 1; + /** pdma_axi_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_total_eof_ch2_st: 1; + /** pdma_axi_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch0_st: 1; + /** pdma_axi_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch1_st: 1; + /** pdma_axi_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch2_st: 1; + /** pdma_axi_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_full_ch0_st: 1; + /** pdma_axi_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_full_ch1_st: 1; + /** pdma_axi_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_evt_out_fifo_full_ch2_st: 1; + /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_evt_sleep_weekup_st: 1; + /** dma2d_evt_in_done_ch0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_in_done_ch0_st: 1; + /** dma2d_evt_in_done_ch1_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_in_done_ch1_st: 1; + /** dma2d_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_in_suc_eof_ch0_st: 1; + }; + uint32_t val; +} soc_etm_evt_st6_reg_t; + +/** Type of evt_st7 register + * Events trigger status register + */ +typedef union { + struct { + /** dma2d_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_in_suc_eof_ch1_st: 1; + /** dma2d_evt_out_done_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_done_ch0_st: 1; + /** dma2d_evt_out_done_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_done_ch1_st: 1; + /** dma2d_evt_out_done_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_done_ch2_st: 1; + /** dma2d_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_eof_ch0_st: 1; + /** dma2d_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_eof_ch1_st: 1; + /** dma2d_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_evt_out_eof_ch2_st: 1; + /** dma2d_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_evt_out_total_eof_ch0_st: 1; + /** dma2d_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_evt_out_total_eof_ch1_st: 1; + /** dma2d_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_evt_out_total_eof_ch2_st: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} soc_etm_evt_st7_reg_t; + +/** Type of task_st0 register + * Tasks trigger status register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_set_st: 1; + /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_set_st: 1; + /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_set_st: 1; + /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_set_st: 1; + /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_set_st: 1; + /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_set_st: 1; + /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_set_st: 1; + /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_set_st: 1; + /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_clear_st: 1; + /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_clear_st: 1; + /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_clear_st: 1; + /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_clear_st: 1; + /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_clear_st: 1; + /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_clear_st: 1; + /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_clear_st: 1; + /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_clear_st: 1; + /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_toggle_st: 1; + /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_toggle_st: 1; + /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_toggle_st: 1; + /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_toggle_st: 1; + /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_toggle_st: 1; + /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_toggle_st: 1; + /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_toggle_st: 1; + /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_toggle_st: 1; + /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer0_res_update_st: 1; + /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer1_res_update_st: 1; + /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer2_res_update_st: 1; + /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer3_res_update_st: 1; + /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch0_st: 1; + /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch1_st: 1; + /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch2_st: 1; + /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch3_st: 1; + }; + uint32_t val; +} soc_etm_task_st0_reg_t; + +/** Type of task_st1 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch4_st: 1; + /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch5_st: 1; + /** ledc_task_duty_scale_update_ch6_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch6_st: 1; + /** ledc_task_duty_scale_update_ch7_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch7_st: 1; + /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_cap_st: 1; + /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_cap_st: 1; + /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_cap_st: 1; + /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_cap_st: 1; + /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch0_st: 1; + /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch1_st: 1; + /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch2_st: 1; + /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch3_st: 1; + /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch4_st: 1; + /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch5_st: 1; + /** ledc_task_sig_out_dis_ch6_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch6_st: 1; + /** ledc_task_sig_out_dis_ch7_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch7_st: 1; + /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st: 1; + /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st: 1; + /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st: 1; + /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st: 1; + /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st: 1; + /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st: 1; + /** ledc_task_ovf_cnt_rst_ch6_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch6_st: 1; + /** ledc_task_ovf_cnt_rst_ch7_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch7_st: 1; + /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_rst_st: 1; + /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_rst_st: 1; + /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_rst_st: 1; + /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_rst_st: 1; + /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_resume_st: 1; + /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_resume_st: 1; + /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_resume_st: 1; + /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_resume_st: 1; + }; + uint32_t val; +} soc_etm_task_st1_reg_t; + +/** Type of task_st2 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_pause_st: 1; + /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_pause_st: 1; + /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_pause_st: 1; + /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_pause_st: 1; + /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch0_st: 1; + /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch1_st: 1; + /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch2_st: 1; + /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch3_st: 1; + /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch4_st: 1; + /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch5_st: 1; + /** ledc_task_gamma_restart_ch6_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch6_st: 1; + /** ledc_task_gamma_restart_ch7_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch7_st: 1; + /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch0_st: 1; + /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch1_st: 1; + /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch2_st: 1; + /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch3_st: 1; + /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch4_st: 1; + /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch5_st: 1; + /** ledc_task_gamma_pause_ch6_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch6_st: 1; + /** ledc_task_gamma_pause_ch7_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch7_st: 1; + /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch0_st: 1; + /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch1_st: 1; + /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch2_st: 1; + /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch3_st: 1; + /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch4_st: 1; + /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch5_st: 1; + /** ledc_task_gamma_resume_ch6_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch6_st: 1; + /** ledc_task_gamma_resume_ch7_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch7_st: 1; + /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer0_st: 1; + /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer0_st: 1; + /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer0_st: 1; + /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer0_st: 1; + }; + uint32_t val; +} soc_etm_task_st2_reg_t; + +/** Type of task_st3 register + * Tasks trigger status register + */ +typedef union { + struct { + /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer0_st: 1; + /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer1_st: 1; + /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer1_st: 1; + /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer1_st: 1; + /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer1_st: 1; + /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer1_st: 1; + /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer0_st: 1; + /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer0_st: 1; + /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer0_st: 1; + /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer0_st: 1; + /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer0_st: 1; + /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer1_st: 1; + /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer1_st: 1; + /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer1_st: 1; + /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer1_st: 1; + /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer1_st: 1; + /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_a_up_st: 1; + /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_a_up_st: 1; + /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_a_up_st: 1; + /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_b_up_st: 1; + /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_b_up_st: 1; + /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_b_up_st: 1; + /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_gen_stop_st: 1; + /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer0_syn_st: 1; + /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer1_syn_st: 1; + /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer2_syn_st: 1; + /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer0_period_up_st: 1; + /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer1_period_up_st: 1; + /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer2_period_up_st: 1; + /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz0_ost_st: 1; + /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz1_ost_st: 1; + /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz2_ost_st: 1; + }; + uint32_t val; +} soc_etm_task_st3_reg_t; + +/** Type of task_st4 register + * Tasks trigger status register + */ +typedef union { + struct { + /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr0_ost_st: 1; + /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr1_ost_st: 1; + /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr2_ost_st: 1; + /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap0_st: 1; + /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap1_st: 1; + /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap2_st: 1; + /** mcpwm1_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr0_a_up_st: 1; + /** mcpwm1_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr1_a_up_st: 1; + /** mcpwm1_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr2_a_up_st: 1; + /** mcpwm1_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr0_b_up_st: 1; + /** mcpwm1_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr1_b_up_st: 1; + /** mcpwm1_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cmpr2_b_up_st: 1; + /** mcpwm1_task_gen_stop_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_gen_stop_st: 1; + /** mcpwm1_task_timer0_syn_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_timer0_syn_st: 1; + /** mcpwm1_task_timer1_syn_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_timer1_syn_st: 1; + /** mcpwm1_task_timer2_syn_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_timer2_syn_st: 1; + /** mcpwm1_task_timer0_period_up_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm1_task_timer0_period_up_st: 1; + /** mcpwm1_task_timer1_period_up_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm1_task_timer1_period_up_st: 1; + /** mcpwm1_task_timer2_period_up_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm1_task_timer2_period_up_st: 1; + /** mcpwm1_task_tz0_ost_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_tz0_ost_st: 1; + /** mcpwm1_task_tz1_ost_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_tz1_ost_st: 1; + /** mcpwm1_task_tz2_ost_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_tz2_ost_st: 1; + /** mcpwm1_task_clr0_ost_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_clr0_ost_st: 1; + /** mcpwm1_task_clr1_ost_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_clr1_ost_st: 1; + /** mcpwm1_task_clr2_ost_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_clr2_ost_st: 1; + /** mcpwm1_task_cap0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cap0_st: 1; + /** mcpwm1_task_cap1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cap1_st: 1; + /** mcpwm1_task_cap2_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm1_task_cap2_st: 1; + /** adc_task_sample0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample0_st: 1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample1_st: 1; + /** adc_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_start0_st: 1; + /** adc_task_stop0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_stop0_st: 1; + }; + uint32_t val; +} soc_etm_task_st4_reg_t; + +/** Type of task_st5 register + * Tasks trigger status register + */ +typedef union { + struct { + /** regdma_task_start0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start0_st: 1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start1_st: 1; + /** regdma_task_start2_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start2_st: 1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start3_st: 1; + /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_start_sample_st: 1; + /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_stop_sample_st: 1; + /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_rx_st: 1; + /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_tx_st: 1; + /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_rx_st: 1; + /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_tx_st: 1; + /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_start_rx_st: 1; + /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_start_tx_st: 1; + /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_stop_rx_st: 1; + /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s1_task_stop_tx_st: 1; + /** i2s2_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_task_start_rx_st: 1; + /** i2s2_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_task_start_tx_st: 1; + /** i2s2_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_task_stop_rx_st: 1; + /** i2s2_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s2_task_stop_tx_st: 1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st: 1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_int_cpu_st: 1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_start_st: 1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_stop_st: 1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_clr_st: 1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_triggerflw_st: 1; + /** pdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_in_start_ch0_st: 1; + /** pdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_in_start_ch1_st: 1; + /** pdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_in_start_ch2_st: 1; + /** pdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_out_start_ch0_st: 1; + /** pdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_out_start_ch1_st: 1; + /** pdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_ahb_task_out_start_ch2_st: 1; + /** pdma_axi_task_in_start_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_in_start_ch0_st: 1; + /** pdma_axi_task_in_start_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_in_start_ch1_st: 1; + }; + uint32_t val; +} soc_etm_task_st5_reg_t; + +/** Type of task_st6 register + * Tasks trigger status register + */ +typedef union { + struct { + /** pdma_axi_task_in_start_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_in_start_ch2_st: 1; + /** pdma_axi_task_out_start_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_out_start_ch0_st: 1; + /** pdma_axi_task_out_start_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_out_start_ch1_st: 1; + /** pdma_axi_task_out_start_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t pdma_axi_task_out_start_ch2_st: 1; + /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_task_sleep_req_st: 1; + /** dma2d_task_in_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_task_in_start_ch0_st: 1; + /** dma2d_task_in_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_task_in_start_ch1_st: 1; + /** dma2d_task_in_dscr_ready_ch0_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_task_in_dscr_ready_ch0_st: 1; + /** dma2d_task_in_dscr_ready_ch1_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_task_in_dscr_ready_ch1_st: 1; + /** dma2d_task_out_start_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_task_out_start_ch0_st: 1; + /** dma2d_task_out_start_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_task_out_start_ch1_st: 1; + /** dma2d_task_out_start_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t dma2d_task_out_start_ch2_st: 1; + /** dma2d_task_out_dscr_ready_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_task_out_dscr_ready_ch0_st: 1; + /** dma2d_task_out_dscr_ready_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_task_out_dscr_ready_ch1_st: 1; + /** dma2d_task_out_dscr_ready_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t dma2d_task_out_dscr_ready_ch2_st: 1; + uint32_t reserved_15: 17; + }; + uint32_t val; +} soc_etm_task_st6_reg_t; + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_set0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set0: 1; + /** ch_set1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set1: 1; + /** ch_set2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set2: 1; + /** ch_set3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set3: 1; + /** ch_set4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set4: 1; + /** ch_set5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set5: 1; + /** ch_set6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set6: 1; + /** ch_set7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set7: 1; + /** ch_set8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set8: 1; + /** ch_set9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set9: 1; + /** ch_set10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set10: 1; + /** ch_set11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set11: 1; + /** ch_set12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set12: 1; + /** ch_set13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set13: 1; + /** ch_set14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set14: 1; + /** ch_set15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set15: 1; + /** ch_set16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set16: 1; + /** ch_set17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set17: 1; + /** ch_set18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set18: 1; + /** ch_set19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set19: 1; + /** ch_set20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set20: 1; + /** ch_set21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set21: 1; + /** ch_set22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set22: 1; + /** ch_set23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set23: 1; + /** ch_set24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set24: 1; + /** ch_set25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set25: 1; + /** ch_set26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set26: 1; + /** ch_set27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set27: 1; + /** ch_set28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set28: 1; + /** ch_set29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set29: 1; + /** ch_set30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set30: 1; + /** ch_set31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set31: 1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_clr0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr0: 1; + /** ch_clr1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr1: 1; + /** ch_clr2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr2: 1; + /** ch_clr3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr3: 1; + /** ch_clr4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr4: 1; + /** ch_clr5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr5: 1; + /** ch_clr6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr6: 1; + /** ch_clr7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr7: 1; + /** ch_clr8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr8: 1; + /** ch_clr9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr9: 1; + /** ch_clr10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr10: 1; + /** ch_clr11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr11: 1; + /** ch_clr12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr12: 1; + /** ch_clr13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr13: 1; + /** ch_clr14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr14: 1; + /** ch_clr15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr15: 1; + /** ch_clr16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr16: 1; + /** ch_clr17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr17: 1; + /** ch_clr18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr18: 1; + /** ch_clr19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr19: 1; + /** ch_clr20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr20: 1; + /** ch_clr21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr21: 1; + /** ch_clr22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr22: 1; + /** ch_clr23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr23: 1; + /** ch_clr24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr24: 1; + /** ch_clr25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr25: 1; + /** ch_clr26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr26: 1; + /** ch_clr27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr27: 1; + /** ch_clr28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr28: 1; + /** ch_clr29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr29: 1; + /** ch_clr30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr30: 1; + /** ch_clr31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr31: 1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_set32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set32: 1; + /** ch_set33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set33: 1; + /** ch_set34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set34: 1; + /** ch_set35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set35: 1; + /** ch_set36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set36: 1; + /** ch_set37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set37: 1; + /** ch_set38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set38: 1; + /** ch_set39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set39: 1; + /** ch_set40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set40: 1; + /** ch_set41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set41: 1; + /** ch_set42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set42: 1; + /** ch_set43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set43: 1; + /** ch_set44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set44: 1; + /** ch_set45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set45: 1; + /** ch_set46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set46: 1; + /** ch_set47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set47: 1; + /** ch_set48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set48: 1; + /** ch_set49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_set49: 1; + uint32_t reserved_18: 14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_clr32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr32: 1; + /** ch_clr33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr33: 1; + /** ch_clr34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr34: 1; + /** ch_clr35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr35: 1; + /** ch_clr36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr36: 1; + /** ch_clr37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr37: 1; + /** ch_clr38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr38: 1; + /** ch_clr39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr39: 1; + /** ch_clr40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr40: 1; + /** ch_clr41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr41: 1; + /** ch_clr42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr42: 1; + /** ch_clr43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr43: 1; + /** ch_clr44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr44: 1; + /** ch_clr45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr45: 1; + /** ch_clr46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr46: 1; + /** ch_clr47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr47: 1; + /** ch_clr48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr48: 1; + /** ch_clr49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_clr49: 1; + uint32_t reserved_18: 14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of chn_evt_id register + * Channeln event id register + */ +typedef union { + struct { + /** evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures chn_evt_id + */ + uint32_t evt_id: 8; + uint32_t reserved_8: 24; + }; + uint32_t val; +} soc_etm_chn_evt_id_reg_t; + +/** Type of chn_task_id register + * Channeln task id register + */ +typedef union { + struct { + /** chn_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures chn_task_id + */ + uint32_t task_id: 8; + uint32_t reserved_8: 24; + }; + uint32_t val; +} soc_etm_chn_task_id_reg_t; + +/** Type of evt_st0_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_rise_edge_st_clr: 1; + /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_rise_edge_st_clr: 1; + /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_rise_edge_st_clr: 1; + /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_rise_edge_st_clr: 1; + /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_rise_edge_st_clr: 1; + /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_rise_edge_st_clr: 1; + /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_rise_edge_st_clr: 1; + /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_rise_edge_st_clr: 1; + /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_fall_edge_st_clr: 1; + /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_fall_edge_st_clr: 1; + /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_fall_edge_st_clr: 1; + /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_fall_edge_st_clr: 1; + /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_fall_edge_st_clr: 1; + /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_fall_edge_st_clr: 1; + /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_fall_edge_st_clr: 1; + /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_fall_edge_st_clr: 1; + /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_any_edge_st_clr: 1; + /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_any_edge_st_clr: 1; + /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_any_edge_st_clr: 1; + /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_any_edge_st_clr: 1; + /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_any_edge_st_clr: 1; + /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_any_edge_st_clr: 1; + /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_any_edge_st_clr: 1; + /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_any_edge_st_clr: 1; + /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos0_st_clr: 1; + /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg0_st_clr: 1; + /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos1_st_clr: 1; + /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg1_st_clr: 1; + /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch0_st_clr: 1; + /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch1_st_clr: 1; + /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch2_st_clr: 1; + /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch3_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st0_clr_reg_t; + +/** Type of evt_st1_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch4_st_clr: 1; + /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch5_st_clr: 1; + /** ledc_evt_duty_chng_end_ch6_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch6_st_clr: 1; + /** ledc_evt_duty_chng_end_ch7_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch7_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch6_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch6_st_clr: 1; + /** ledc_evt_ovf_cnt_pls_ch7_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch7_st_clr: 1; + /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer0_st_clr: 1; + /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer1_st_clr: 1; + /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer2_st_clr: 1; + /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer3_st_clr: 1; + /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer0_cmp_st_clr: 1; + /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer1_cmp_st_clr: 1; + /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer2_cmp_st_clr: 1; + /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer3_cmp_st_clr: 1; + /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer0_st_clr: 1; + /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer1_st_clr: 1; + /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer0_st_clr: 1; + /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer1_st_clr: 1; + /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp0_st_clr: 1; + /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp1_st_clr: 1; + /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp2_st_clr: 1; + /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_stop_st_clr: 1; + /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_stop_st_clr: 1; + /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_stop_st_clr: 1; + /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tez_st_clr: 1; + /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tez_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st1_clr_reg_t; + +/** Type of evt_st2_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** mcpwm0_evt_timer2_tez_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tez_st_clr: 1; + /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tep_st_clr: 1; + /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tep_st_clr: 1; + /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tep_st_clr: 1; + /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tea_st_clr: 1; + /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tea_st_clr: 1; + /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tea_st_clr: 1; + /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_teb_st_clr: 1; + /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_teb_st_clr: 1; + /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_teb_st_clr: 1; + /** mcpwm0_evt_f0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_st_clr: 1; + /** mcpwm0_evt_f1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_st_clr: 1; + /** mcpwm0_evt_f2_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_st_clr: 1; + /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_clr_st_clr: 1; + /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_clr_st_clr: 1; + /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_clr_st_clr: 1; + /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_cbc_st_clr: 1; + /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_cbc_st_clr: 1; + /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_cbc_st_clr: 1; + /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_ost_st_clr: 1; + /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_ost_st_clr: 1; + /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_ost_st_clr: 1; + /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap0_st_clr: 1; + /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap1_st_clr: 1; + /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap2_st_clr: 1; + /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee1_st_clr: 1; + /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee1_st_clr: 1; + /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee1_st_clr: 1; + /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee2_st_clr: 1; + /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee2_st_clr: 1; + /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee2_st_clr: 1; + /** mcpwm1_evt_timer0_stop_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer0_stop_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st2_clr_reg_t; + +/** Type of evt_st3_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** mcpwm1_evt_timer1_stop_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer1_stop_st_clr: 1; + /** mcpwm1_evt_timer2_stop_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer2_stop_st_clr: 1; + /** mcpwm1_evt_timer0_tez_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer0_tez_st_clr: 1; + /** mcpwm1_evt_timer1_tez_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer1_tez_st_clr: 1; + /** mcpwm1_evt_timer2_tez_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer2_tez_st_clr: 1; + /** mcpwm1_evt_timer0_tep_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer0_tep_st_clr: 1; + /** mcpwm1_evt_timer1_tep_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer1_tep_st_clr: 1; + /** mcpwm1_evt_timer2_tep_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_evt_timer2_tep_st_clr: 1; + /** mcpwm1_evt_op0_tea_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op0_tea_st_clr: 1; + /** mcpwm1_evt_op1_tea_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op1_tea_st_clr: 1; + /** mcpwm1_evt_op2_tea_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op2_tea_st_clr: 1; + /** mcpwm1_evt_op0_teb_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op0_teb_st_clr: 1; + /** mcpwm1_evt_op1_teb_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op1_teb_st_clr: 1; + /** mcpwm1_evt_op2_teb_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op2_teb_st_clr: 1; + /** mcpwm1_evt_f0_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_f0_st_clr: 1; + /** mcpwm1_evt_f1_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_f1_st_clr: 1; + /** mcpwm1_evt_f2_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_f2_st_clr: 1; + /** mcpwm1_evt_f0_clr_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_f0_clr_st_clr: 1; + /** mcpwm1_evt_f1_clr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_f1_clr_st_clr: 1; + /** mcpwm1_evt_f2_clr_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_f2_clr_st_clr: 1; + /** mcpwm1_evt_tz0_cbc_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz0_cbc_st_clr: 1; + /** mcpwm1_evt_tz1_cbc_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz1_cbc_st_clr: 1; + /** mcpwm1_evt_tz2_cbc_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz2_cbc_st_clr: 1; + /** mcpwm1_evt_tz0_ost_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz0_ost_st_clr: 1; + /** mcpwm1_evt_tz1_ost_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz1_ost_st_clr: 1; + /** mcpwm1_evt_tz2_ost_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_tz2_ost_st_clr: 1; + /** mcpwm1_evt_cap0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_cap0_st_clr: 1; + /** mcpwm1_evt_cap1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_cap1_st_clr: 1; + /** mcpwm1_evt_cap2_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_evt_cap2_st_clr: 1; + /** mcpwm1_evt_op0_tee1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op0_tee1_st_clr: 1; + /** mcpwm1_evt_op1_tee1_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op1_tee1_st_clr: 1; + /** mcpwm1_evt_op2_tee1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op2_tee1_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st3_clr_reg_t; + +/** Type of evt_st4_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** mcpwm1_evt_op0_tee2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op0_tee2_st_clr: 1; + /** mcpwm1_evt_op1_tee2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op1_tee2_st_clr: 1; + /** mcpwm1_evt_op2_tee2_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_evt_op2_tee2_st_clr: 1; + /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t adc_evt_conv_cmplt0_st_clr: 1; + /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh0_st_clr: 1; + /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh1_st_clr: 1; + /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh0_st_clr: 1; + /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh1_st_clr: 1; + /** adc_evt_result_done0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_result_done0_st_clr: 1; + /** adc_evt_stopped0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_stopped0_st_clr: 1; + /** adc_evt_started0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_started0_st_clr: 1; + /** regdma_evt_done0_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done0_st_clr: 1; + /** regdma_evt_done1_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done1_st_clr: 1; + /** regdma_evt_done2_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done2_st_clr: 1; + /** regdma_evt_done3_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done3_st_clr: 1; + /** regdma_evt_err0_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err0_st_clr: 1; + /** regdma_evt_err1_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err1_st_clr: 1; + /** regdma_evt_err2_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err2_st_clr: 1; + /** regdma_evt_err3_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err3_st_clr: 1; + /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_evt_over_limit_st_clr: 1; + /** i2s0_evt_rx_done_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_rx_done_st_clr: 1; + /** i2s0_evt_tx_done_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_tx_done_st_clr: 1; + /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_received_st_clr: 1; + /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_sent_st_clr: 1; + /** i2s1_evt_rx_done_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s1_evt_rx_done_st_clr: 1; + /** i2s1_evt_tx_done_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s1_evt_tx_done_st_clr: 1; + /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s1_evt_x_words_received_st_clr: 1; + /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s1_evt_x_words_sent_st_clr: 1; + /** i2s2_evt_rx_done_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s2_evt_rx_done_st_clr: 1; + /** i2s2_evt_tx_done_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s2_evt_tx_done_st_clr: 1; + /** i2s2_evt_x_words_received_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s2_evt_x_words_received_st_clr: 1; + /** i2s2_evt_x_words_sent_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s2_evt_x_words_sent_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st4_clr_reg_t; + +/** Type of evt_st5_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** ulp_evt_err_intr_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr: 1; + /** ulp_evt_halt_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_halt_st_clr: 1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr: 1; + /** rtc_evt_tick_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_tick_st_clr: 1; + /** rtc_evt_ovf_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_ovf_st_clr: 1; + /** rtc_evt_cmp_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_cmp_st_clr: 1; + /** pdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_done_ch0_st_clr: 1; + /** pdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_done_ch1_st_clr: 1; + /** pdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_done_ch2_st_clr: 1; + /** pdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch0_st_clr: 1; + /** pdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch1_st_clr: 1; + /** pdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_suc_eof_ch2_st_clr: 1; + /** pdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch0_st_clr: 1; + /** pdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch1_st_clr: 1; + /** pdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_empty_ch2_st_clr: 1; + /** pdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch0_st_clr: 1; + /** pdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch1_st_clr: 1; + /** pdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_in_fifo_full_ch2_st_clr: 1; + /** pdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_done_ch0_st_clr: 1; + /** pdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_done_ch1_st_clr: 1; + /** pdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_done_ch2_st_clr: 1; + /** pdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_eof_ch0_st_clr: 1; + /** pdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_eof_ch1_st_clr: 1; + /** pdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_eof_ch2_st_clr: 1; + /** pdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_total_eof_ch0_st_clr: 1; + /** pdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_total_eof_ch1_st_clr: 1; + /** pdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_total_eof_ch2_st_clr: 1; + /** pdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch0_st_clr: 1; + /** pdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch1_st_clr: 1; + /** pdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_empty_ch2_st_clr: 1; + /** pdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch0_st_clr: 1; + /** pdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch1_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st5_clr_reg_t; + +/** Type of evt_st6_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** pdma_ahb_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_evt_out_fifo_full_ch2_st_clr: 1; + /** pdma_axi_evt_in_done_ch0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_done_ch0_st_clr: 1; + /** pdma_axi_evt_in_done_ch1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_done_ch1_st_clr: 1; + /** pdma_axi_evt_in_done_ch2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_done_ch2_st_clr: 1; + /** pdma_axi_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_suc_eof_ch0_st_clr: 1; + /** pdma_axi_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_suc_eof_ch1_st_clr: 1; + /** pdma_axi_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_suc_eof_ch2_st_clr: 1; + /** pdma_axi_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch0_st_clr: 1; + /** pdma_axi_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch1_st_clr: 1; + /** pdma_axi_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_empty_ch2_st_clr: 1; + /** pdma_axi_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_full_ch0_st_clr: 1; + /** pdma_axi_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_full_ch1_st_clr: 1; + /** pdma_axi_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_in_fifo_full_ch2_st_clr: 1; + /** pdma_axi_evt_out_done_ch0_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_done_ch0_st_clr: 1; + /** pdma_axi_evt_out_done_ch1_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_done_ch1_st_clr: 1; + /** pdma_axi_evt_out_done_ch2_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_done_ch2_st_clr: 1; + /** pdma_axi_evt_out_eof_ch0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_eof_ch0_st_clr: 1; + /** pdma_axi_evt_out_eof_ch1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_eof_ch1_st_clr: 1; + /** pdma_axi_evt_out_eof_ch2_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_eof_ch2_st_clr: 1; + /** pdma_axi_evt_out_total_eof_ch0_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_total_eof_ch0_st_clr: 1; + /** pdma_axi_evt_out_total_eof_ch1_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_total_eof_ch1_st_clr: 1; + /** pdma_axi_evt_out_total_eof_ch2_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_total_eof_ch2_st_clr: 1; + /** pdma_axi_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch0_st_clr: 1; + /** pdma_axi_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch1_st_clr: 1; + /** pdma_axi_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_empty_ch2_st_clr: 1; + /** pdma_axi_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_full_ch0_st_clr: 1; + /** pdma_axi_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_full_ch1_st_clr: 1; + /** pdma_axi_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_evt_out_fifo_full_ch2_st_clr: 1; + /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pmu_evt_sleep_weekup_st_clr: 1; + /** dma2d_evt_in_done_ch0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_in_done_ch0_st_clr: 1; + /** dma2d_evt_in_done_ch1_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_in_done_ch1_st_clr: 1; + /** dma2d_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_in_suc_eof_ch0_st_clr: 1; + }; + uint32_t val; +} soc_etm_evt_st6_clr_reg_t; + +/** Type of evt_st7_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** dma2d_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_in_suc_eof_ch1_st_clr: 1; + /** dma2d_evt_out_done_ch0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_done_ch0_st_clr: 1; + /** dma2d_evt_out_done_ch1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_done_ch1_st_clr: 1; + /** dma2d_evt_out_done_ch2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_done_ch2_st_clr: 1; + /** dma2d_evt_out_eof_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_eof_ch0_st_clr: 1; + /** dma2d_evt_out_eof_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_eof_ch1_st_clr: 1; + /** dma2d_evt_out_eof_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_eof_ch2_st_clr: 1; + /** dma2d_evt_out_total_eof_ch0_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_total_eof_ch0_st_clr: 1; + /** dma2d_evt_out_total_eof_ch1_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_total_eof_ch1_st_clr: 1; + /** dma2d_evt_out_total_eof_ch2_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_evt_out_total_eof_ch2_st_clr: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} soc_etm_evt_st7_clr_reg_t; + +/** Type of task_st0_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_set_st_clr: 1; + /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_set_st_clr: 1; + /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_set_st_clr: 1; + /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_set_st_clr: 1; + /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_set_st_clr: 1; + /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_set_st_clr: 1; + /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_set_st_clr: 1; + /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_set_st_clr: 1; + /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_clear_st_clr: 1; + /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_clear_st_clr: 1; + /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_clear_st_clr: 1; + /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_clear_st_clr: 1; + /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_clear_st_clr: 1; + /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_clear_st_clr: 1; + /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_clear_st_clr: 1; + /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_clear_st_clr: 1; + /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch0_toggle_st_clr: 1; + /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch1_toggle_st_clr: 1; + /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch2_toggle_st_clr: 1; + /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch3_toggle_st_clr: 1; + /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch4_toggle_st_clr: 1; + /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch5_toggle_st_clr: 1; + /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch6_toggle_st_clr: 1; + /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch7_toggle_st_clr: 1; + /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_res_update_st_clr: 1; + /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_res_update_st_clr: 1; + /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_res_update_st_clr: 1; + /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_res_update_st_clr: 1; + /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch0_st_clr: 1; + /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch1_st_clr: 1; + /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch2_st_clr: 1; + /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch3_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st0_clr_reg_t; + +/** Type of task_st1_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch4_st_clr: 1; + /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch5_st_clr: 1; + /** ledc_task_duty_scale_update_ch6_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch6_st_clr: 1; + /** ledc_task_duty_scale_update_ch7_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch7_st_clr: 1; + /** ledc_task_timer0_cap_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_cap_st_clr: 1; + /** ledc_task_timer1_cap_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_cap_st_clr: 1; + /** ledc_task_timer2_cap_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_cap_st_clr: 1; + /** ledc_task_timer3_cap_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_cap_st_clr: 1; + /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch0_st_clr: 1; + /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch1_st_clr: 1; + /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch2_st_clr: 1; + /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch3_st_clr: 1; + /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch4_st_clr: 1; + /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch5_st_clr: 1; + /** ledc_task_sig_out_dis_ch6_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch6_st_clr: 1; + /** ledc_task_sig_out_dis_ch7_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch7_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch6_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch6_st_clr: 1; + /** ledc_task_ovf_cnt_rst_ch7_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch7_st_clr: 1; + /** ledc_task_timer0_rst_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_rst_st_clr: 1; + /** ledc_task_timer1_rst_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_rst_st_clr: 1; + /** ledc_task_timer2_rst_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_rst_st_clr: 1; + /** ledc_task_timer3_rst_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_rst_st_clr: 1; + /** ledc_task_timer0_resume_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_resume_st_clr: 1; + /** ledc_task_timer1_resume_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_resume_st_clr: 1; + /** ledc_task_timer2_resume_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_resume_st_clr: 1; + /** ledc_task_timer3_resume_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_resume_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st1_clr_reg_t; + +/** Type of task_st2_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_timer0_pause_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_pause_st_clr: 1; + /** ledc_task_timer1_pause_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_pause_st_clr: 1; + /** ledc_task_timer2_pause_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_pause_st_clr: 1; + /** ledc_task_timer3_pause_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_pause_st_clr: 1; + /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch0_st_clr: 1; + /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch1_st_clr: 1; + /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch2_st_clr: 1; + /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch3_st_clr: 1; + /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch4_st_clr: 1; + /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch5_st_clr: 1; + /** ledc_task_gamma_restart_ch6_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch6_st_clr: 1; + /** ledc_task_gamma_restart_ch7_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch7_st_clr: 1; + /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch0_st_clr: 1; + /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch1_st_clr: 1; + /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch2_st_clr: 1; + /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch3_st_clr: 1; + /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch4_st_clr: 1; + /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch5_st_clr: 1; + /** ledc_task_gamma_pause_ch6_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch6_st_clr: 1; + /** ledc_task_gamma_pause_ch7_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch7_st_clr: 1; + /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch0_st_clr: 1; + /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch1_st_clr: 1; + /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch2_st_clr: 1; + /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch3_st_clr: 1; + /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch4_st_clr: 1; + /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch5_st_clr: 1; + /** ledc_task_gamma_resume_ch6_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch6_st_clr: 1; + /** ledc_task_gamma_resume_ch7_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch7_st_clr: 1; + /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer0_st_clr: 1; + /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer0_st_clr: 1; + /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer0_st_clr: 1; + /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer0_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st2_clr_reg_t; + +/** Type of task_st3_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer0_st_clr: 1; + /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer1_st_clr: 1; + /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer1_st_clr: 1; + /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer1_st_clr: 1; + /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer1_st_clr: 1; + /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer1_st_clr: 1; + /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer0_st_clr: 1; + /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer0_st_clr: 1; + /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer0_st_clr: 1; + /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer0_st_clr: 1; + /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer0_st_clr: 1; + /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer1_st_clr: 1; + /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer1_st_clr: 1; + /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer1_st_clr: 1; + /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer1_st_clr: 1; + /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer1_st_clr: 1; + /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_a_up_st_clr: 1; + /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_a_up_st_clr: 1; + /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_a_up_st_clr: 1; + /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_b_up_st_clr: 1; + /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_b_up_st_clr: 1; + /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_b_up_st_clr: 1; + /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_gen_stop_st_clr: 1; + /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_syn_st_clr: 1; + /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_syn_st_clr: 1; + /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_syn_st_clr: 1; + /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_period_up_st_clr: 1; + /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_period_up_st_clr: 1; + /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_period_up_st_clr: 1; + /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz0_ost_st_clr: 1; + /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz1_ost_st_clr: 1; + /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz2_ost_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st3_clr_reg_t; + +/** Type of task_st4_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** mcpwm0_task_clr0_ost_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr0_ost_st_clr: 1; + /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr1_ost_st_clr: 1; + /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr2_ost_st_clr: 1; + /** mcpwm0_task_cap0_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap0_st_clr: 1; + /** mcpwm0_task_cap1_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap1_st_clr: 1; + /** mcpwm0_task_cap2_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap2_st_clr: 1; + /** mcpwm1_task_cmpr0_a_up_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr0_a_up_st_clr: 1; + /** mcpwm1_task_cmpr1_a_up_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr1_a_up_st_clr: 1; + /** mcpwm1_task_cmpr2_a_up_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr2_a_up_st_clr: 1; + /** mcpwm1_task_cmpr0_b_up_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr0_b_up_st_clr: 1; + /** mcpwm1_task_cmpr1_b_up_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr1_b_up_st_clr: 1; + /** mcpwm1_task_cmpr2_b_up_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_cmpr2_b_up_st_clr: 1; + /** mcpwm1_task_gen_stop_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_gen_stop_st_clr: 1; + /** mcpwm1_task_timer0_syn_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer0_syn_st_clr: 1; + /** mcpwm1_task_timer1_syn_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer1_syn_st_clr: 1; + /** mcpwm1_task_timer2_syn_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer2_syn_st_clr: 1; + /** mcpwm1_task_timer0_period_up_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer0_period_up_st_clr: 1; + /** mcpwm1_task_timer1_period_up_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer1_period_up_st_clr: 1; + /** mcpwm1_task_timer2_period_up_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_timer2_period_up_st_clr: 1; + /** mcpwm1_task_tz0_ost_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_task_tz0_ost_st_clr: 1; + /** mcpwm1_task_tz1_ost_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_task_tz1_ost_st_clr: 1; + /** mcpwm1_task_tz2_ost_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm1_task_tz2_ost_st_clr: 1; + /** mcpwm1_task_clr0_ost_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_clr0_ost_st_clr: 1; + /** mcpwm1_task_clr1_ost_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_clr1_ost_st_clr: 1; + /** mcpwm1_task_clr2_ost_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm1_task_clr2_ost_st_clr: 1; + /** mcpwm1_task_cap0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_task_cap0_st_clr: 1; + /** mcpwm1_task_cap1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_task_cap1_st_clr: 1; + /** mcpwm1_task_cap2_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm1_task_cap2_st_clr: 1; + /** adc_task_sample0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample0_st_clr: 1; + /** adc_task_sample1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample1_st_clr: 1; + /** adc_task_start0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_start0_st_clr: 1; + /** adc_task_stop0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_stop0_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st4_clr_reg_t; + +/** Type of task_st5_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** regdma_task_start0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start0_st_clr: 1; + /** regdma_task_start1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start1_st_clr: 1; + /** regdma_task_start2_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start2_st_clr: 1; + /** regdma_task_start3_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start3_st_clr: 1; + /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_start_sample_st_clr: 1; + /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_stop_sample_st_clr: 1; + /** i2s0_task_start_rx_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_rx_st_clr: 1; + /** i2s0_task_start_tx_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_tx_st_clr: 1; + /** i2s0_task_stop_rx_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_rx_st_clr: 1; + /** i2s0_task_stop_tx_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_tx_st_clr: 1; + /** i2s1_task_start_rx_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_start_rx_st_clr: 1; + /** i2s1_task_start_tx_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_start_tx_st_clr: 1; + /** i2s1_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_stop_rx_st_clr: 1; + /** i2s1_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s1_task_stop_tx_st_clr: 1; + /** i2s2_task_start_rx_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s2_task_start_rx_st_clr: 1; + /** i2s2_task_start_tx_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s2_task_start_tx_st_clr: 1; + /** i2s2_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s2_task_stop_rx_st_clr: 1; + /** i2s2_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s2_task_stop_tx_st_clr: 1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr: 1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr: 1; + /** rtc_task_start_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_start_st_clr: 1; + /** rtc_task_stop_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_stop_st_clr: 1; + /** rtc_task_clr_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_clr_st_clr: 1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr: 1; + /** pdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_in_start_ch0_st_clr: 1; + /** pdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_in_start_ch1_st_clr: 1; + /** pdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_in_start_ch2_st_clr: 1; + /** pdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_out_start_ch0_st_clr: 1; + /** pdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_out_start_ch1_st_clr: 1; + /** pdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_ahb_task_out_start_ch2_st_clr: 1; + /** pdma_axi_task_in_start_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_in_start_ch0_st_clr: 1; + /** pdma_axi_task_in_start_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_in_start_ch1_st_clr: 1; + }; + uint32_t val; +} soc_etm_task_st5_clr_reg_t; + +/** Type of task_st6_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** pdma_axi_task_in_start_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_in_start_ch2_st_clr: 1; + /** pdma_axi_task_out_start_ch0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_out_start_ch0_st_clr: 1; + /** pdma_axi_task_out_start_ch1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_out_start_ch1_st_clr: 1; + /** pdma_axi_task_out_start_ch2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pdma_axi_task_out_start_ch2_st_clr: 1; + /** pmu_task_sleep_req_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t pmu_task_sleep_req_st_clr: 1; + /** dma2d_task_in_start_ch0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_in_start_ch0_st_clr: 1; + /** dma2d_task_in_start_ch1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_in_start_ch1_st_clr: 1; + /** dma2d_task_in_dscr_ready_ch0_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_in_dscr_ready_ch0_st_clr: 1; + /** dma2d_task_in_dscr_ready_ch1_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_in_dscr_ready_ch1_st_clr: 1; + /** dma2d_task_out_start_ch0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_start_ch0_st_clr: 1; + /** dma2d_task_out_start_ch1_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_start_ch1_st_clr: 1; + /** dma2d_task_out_start_ch2_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_start_ch2_st_clr: 1; + /** dma2d_task_out_dscr_ready_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_dscr_ready_ch0_st_clr: 1; + /** dma2d_task_out_dscr_ready_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_dscr_ready_ch1_st_clr: 1; + /** dma2d_task_out_dscr_ready_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t dma2d_task_out_dscr_ready_ch2_st_clr: 1; + uint32_t reserved_15: 17; + }; + uint32_t val; +} soc_etm_task_st6_clr_reg_t; + +/** Type of clk_en register + * ETM clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en: 1; + uint32_t reserved_1: 31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + +/** Group: Version Register */ +/** Type of date register + * ETM date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36712497; + * Configures the version. + */ + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} soc_etm_date_reg_t; + +typedef struct soc_etm_dev_t { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; + volatile soc_etm_evt_st0_reg_t evt_st0; + volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; + volatile soc_etm_evt_st1_reg_t evt_st1; + volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr; + volatile soc_etm_evt_st2_reg_t evt_st2; + volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr; + volatile soc_etm_evt_st3_reg_t evt_st3; + volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr; + volatile soc_etm_evt_st4_reg_t evt_st4; + volatile soc_etm_evt_st4_clr_reg_t evt_st4_clr; + volatile soc_etm_evt_st5_reg_t evt_st5; + volatile soc_etm_evt_st5_clr_reg_t evt_st5_clr; + volatile soc_etm_evt_st6_reg_t evt_st6; + volatile soc_etm_evt_st6_clr_reg_t evt_st6_clr; + volatile soc_etm_evt_st7_reg_t evt_st7; + volatile soc_etm_evt_st7_clr_reg_t evt_st7_clr; + volatile soc_etm_task_st0_reg_t task_st0; + volatile soc_etm_task_st0_clr_reg_t task_st0_clr; + volatile soc_etm_task_st1_reg_t task_st1; + volatile soc_etm_task_st1_clr_reg_t task_st1_clr; + volatile soc_etm_task_st2_reg_t task_st2; + volatile soc_etm_task_st2_clr_reg_t task_st2_clr; + volatile soc_etm_task_st3_reg_t task_st3; + volatile soc_etm_task_st3_clr_reg_t task_st3_clr; + volatile soc_etm_task_st4_reg_t task_st4; + volatile soc_etm_task_st4_clr_reg_t task_st4_clr; + volatile soc_etm_task_st5_reg_t task_st5; + volatile soc_etm_task_st5_clr_reg_t task_st5_clr; + volatile soc_etm_task_st6_reg_t task_st6; + volatile soc_etm_task_st6_clr_reg_t task_st6_clr; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x228, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_reg.h new file mode 100644 index 0000000000..e1f54ec7bb --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_reg.h @@ -0,0 +1,1481 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI1_MEM_C_CMD_REG register + * SPI1 memory command register + */ +#define SPI1_MEM_C_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0x0) +/** SPI1_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ +#define SPI1_MEM_C_MST_ST 0x0000000FU +#define SPI1_MEM_C_MST_ST_M (SPI1_MEM_C_MST_ST_V << SPI1_MEM_C_MST_ST_S) +#define SPI1_MEM_C_MST_ST_V 0x0000000FU +#define SPI1_MEM_C_MST_ST_S 0 +/** SPI1_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI1_MEM_C_SLV_ST 0x0000000FU +#define SPI1_MEM_C_SLV_ST_M (SPI1_MEM_C_SLV_ST_V << SPI1_MEM_C_SLV_ST_S) +#define SPI1_MEM_C_SLV_ST_V 0x0000000FU +#define SPI1_MEM_C_SLV_ST_S 4 +/** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_PE (BIT(17)) +#define SPI1_MEM_C_FLASH_PE_M (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S) +#define SPI1_MEM_C_FLASH_PE_V 0x00000001U +#define SPI1_MEM_C_FLASH_PE_S 17 +/** SPI1_MEM_C_USR : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_USR (BIT(18)) +#define SPI1_MEM_C_USR_M (SPI1_MEM_C_USR_V << SPI1_MEM_C_USR_S) +#define SPI1_MEM_C_USR_V 0x00000001U +#define SPI1_MEM_C_USR_S 18 +/** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_HPM (BIT(19)) +#define SPI1_MEM_C_FLASH_HPM_M (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S) +#define SPI1_MEM_C_FLASH_HPM_V 0x00000001U +#define SPI1_MEM_C_FLASH_HPM_S 19 +/** SPI1_MEM_C_FLASH_RES : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_RES (BIT(20)) +#define SPI1_MEM_C_FLASH_RES_M (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S) +#define SPI1_MEM_C_FLASH_RES_V 0x00000001U +#define SPI1_MEM_C_FLASH_RES_S 20 +/** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_DP (BIT(21)) +#define SPI1_MEM_C_FLASH_DP_M (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S) +#define SPI1_MEM_C_FLASH_DP_V 0x00000001U +#define SPI1_MEM_C_FLASH_DP_S 21 +/** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_CE (BIT(22)) +#define SPI1_MEM_C_FLASH_CE_M (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S) +#define SPI1_MEM_C_FLASH_CE_V 0x00000001U +#define SPI1_MEM_C_FLASH_CE_S 22 +/** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_BE (BIT(23)) +#define SPI1_MEM_C_FLASH_BE_M (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S) +#define SPI1_MEM_C_FLASH_BE_V 0x00000001U +#define SPI1_MEM_C_FLASH_BE_S 23 +/** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_SE (BIT(24)) +#define SPI1_MEM_C_FLASH_SE_M (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S) +#define SPI1_MEM_C_FLASH_SE_V 0x00000001U +#define SPI1_MEM_C_FLASH_SE_S 24 +/** SPI1_MEM_C_FLASH_PP : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_PP (BIT(25)) +#define SPI1_MEM_C_FLASH_PP_M (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S) +#define SPI1_MEM_C_FLASH_PP_V 0x00000001U +#define SPI1_MEM_C_FLASH_PP_S 25 +/** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_WRSR (BIT(26)) +#define SPI1_MEM_C_FLASH_WRSR_M (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S) +#define SPI1_MEM_C_FLASH_WRSR_V 0x00000001U +#define SPI1_MEM_C_FLASH_WRSR_S 26 +/** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_RDSR (BIT(27)) +#define SPI1_MEM_C_FLASH_RDSR_M (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S) +#define SPI1_MEM_C_FLASH_RDSR_V 0x00000001U +#define SPI1_MEM_C_FLASH_RDSR_S 27 +/** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_RDID (BIT(28)) +#define SPI1_MEM_C_FLASH_RDID_M (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S) +#define SPI1_MEM_C_FLASH_RDID_V 0x00000001U +#define SPI1_MEM_C_FLASH_RDID_S 28 +/** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_WRDI (BIT(29)) +#define SPI1_MEM_C_FLASH_WRDI_M (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S) +#define SPI1_MEM_C_FLASH_WRDI_V 0x00000001U +#define SPI1_MEM_C_FLASH_WRDI_S 29 +/** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_WREN (BIT(30)) +#define SPI1_MEM_C_FLASH_WREN_M (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S) +#define SPI1_MEM_C_FLASH_WREN_V 0x00000001U +#define SPI1_MEM_C_FLASH_WREN_S 30 +/** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FLASH_READ (BIT(31)) +#define SPI1_MEM_C_FLASH_READ_M (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S) +#define SPI1_MEM_C_FLASH_READ_V 0x00000001U +#define SPI1_MEM_C_FLASH_READ_S 31 + +/** SPI1_MEM_C_ADDR_REG register + * SPI1 address register + */ +#define SPI1_MEM_C_ADDR_REG (DR_REG_FLASH_SPI1_BASE + 0x4) +/** SPI1_MEM_C_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ +#define SPI1_MEM_C_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI1_MEM_C_USR_ADDR_VALUE_M (SPI1_MEM_C_USR_ADDR_VALUE_V << SPI1_MEM_C_USR_ADDR_VALUE_S) +#define SPI1_MEM_C_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI1_MEM_C_USR_ADDR_VALUE_S 0 + +/** SPI1_MEM_C_CTRL_REG register + * SPI1 control register. + */ +#define SPI1_MEM_C_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x8) +/** SPI1_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_C_FDUMMY_RIN (BIT(2)) +#define SPI1_MEM_C_FDUMMY_RIN_M (SPI1_MEM_C_FDUMMY_RIN_V << SPI1_MEM_C_FDUMMY_RIN_S) +#define SPI1_MEM_C_FDUMMY_RIN_V 0x00000001U +#define SPI1_MEM_C_FDUMMY_RIN_S 2 +/** SPI1_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_C_FDUMMY_WOUT (BIT(3)) +#define SPI1_MEM_C_FDUMMY_WOUT_M (SPI1_MEM_C_FDUMMY_WOUT_V << SPI1_MEM_C_FDUMMY_WOUT_S) +#define SPI1_MEM_C_FDUMMY_WOUT_V 0x00000001U +#define SPI1_MEM_C_FDUMMY_WOUT_S 3 +/** SPI1_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI1_MEM_C_FDOUT_OCT (BIT(4)) +#define SPI1_MEM_C_FDOUT_OCT_M (SPI1_MEM_C_FDOUT_OCT_V << SPI1_MEM_C_FDOUT_OCT_S) +#define SPI1_MEM_C_FDOUT_OCT_V 0x00000001U +#define SPI1_MEM_C_FDOUT_OCT_S 4 +/** SPI1_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI1_MEM_C_FDIN_OCT (BIT(5)) +#define SPI1_MEM_C_FDIN_OCT_M (SPI1_MEM_C_FDIN_OCT_V << SPI1_MEM_C_FDIN_OCT_S) +#define SPI1_MEM_C_FDIN_OCT_V 0x00000001U +#define SPI1_MEM_C_FDIN_OCT_S 5 +/** SPI1_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI1_MEM_C_FADDR_OCT (BIT(6)) +#define SPI1_MEM_C_FADDR_OCT_M (SPI1_MEM_C_FADDR_OCT_V << SPI1_MEM_C_FADDR_OCT_S) +#define SPI1_MEM_C_FADDR_OCT_V 0x00000001U +#define SPI1_MEM_C_FADDR_OCT_S 6 +/** SPI1_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_C_FCMD_QUAD (BIT(8)) +#define SPI1_MEM_C_FCMD_QUAD_M (SPI1_MEM_C_FCMD_QUAD_V << SPI1_MEM_C_FCMD_QUAD_S) +#define SPI1_MEM_C_FCMD_QUAD_V 0x00000001U +#define SPI1_MEM_C_FCMD_QUAD_S 8 +/** SPI1_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_C_FCMD_OCT (BIT(9)) +#define SPI1_MEM_C_FCMD_OCT_M (SPI1_MEM_C_FCMD_OCT_V << SPI1_MEM_C_FCMD_OCT_S) +#define SPI1_MEM_C_FCMD_OCT_V 0x00000001U +#define SPI1_MEM_C_FCMD_OCT_S 9 +/** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ +#define SPI1_MEM_C_FCS_CRC_EN (BIT(10)) +#define SPI1_MEM_C_FCS_CRC_EN_M (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S) +#define SPI1_MEM_C_FCS_CRC_EN_V 0x00000001U +#define SPI1_MEM_C_FCS_CRC_EN_S 10 +/** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ +#define SPI1_MEM_C_TX_CRC_EN (BIT(11)) +#define SPI1_MEM_C_TX_CRC_EN_M (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S) +#define SPI1_MEM_C_TX_CRC_EN_V 0x00000001U +#define SPI1_MEM_C_TX_CRC_EN_S 11 +/** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout + * and spi1_mem_c_fread_dout. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FASTRD_MODE (BIT(13)) +#define SPI1_MEM_C_FASTRD_MODE_M (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S) +#define SPI1_MEM_C_FASTRD_MODE_V 0x00000001U +#define SPI1_MEM_C_FASTRD_MODE_S 13 +/** SPI1_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FREAD_DUAL (BIT(14)) +#define SPI1_MEM_C_FREAD_DUAL_M (SPI1_MEM_C_FREAD_DUAL_V << SPI1_MEM_C_FREAD_DUAL_S) +#define SPI1_MEM_C_FREAD_DUAL_V 0x00000001U +#define SPI1_MEM_C_FREAD_DUAL_S 14 +/** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with + * spi1_mem_c_flash_res bit. 1: enable 0: disable. + */ +#define SPI1_MEM_C_RESANDRES (BIT(15)) +#define SPI1_MEM_C_RESANDRES_M (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S) +#define SPI1_MEM_C_RESANDRES_V 0x00000001U +#define SPI1_MEM_C_RESANDRES_S 15 +/** SPI1_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI1_MEM_C_Q_POL (BIT(18)) +#define SPI1_MEM_C_Q_POL_M (SPI1_MEM_C_Q_POL_V << SPI1_MEM_C_Q_POL_S) +#define SPI1_MEM_C_Q_POL_V 0x00000001U +#define SPI1_MEM_C_Q_POL_S 18 +/** SPI1_MEM_C_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI1_MEM_C_D_POL (BIT(19)) +#define SPI1_MEM_C_D_POL_M (SPI1_MEM_C_D_POL_V << SPI1_MEM_C_D_POL_S) +#define SPI1_MEM_C_D_POL_V 0x00000001U +#define SPI1_MEM_C_D_POL_S 19 +/** SPI1_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_C_FREAD_QUAD (BIT(20)) +#define SPI1_MEM_C_FREAD_QUAD_M (SPI1_MEM_C_FREAD_QUAD_V << SPI1_MEM_C_FREAD_QUAD_S) +#define SPI1_MEM_C_FREAD_QUAD_V 0x00000001U +#define SPI1_MEM_C_FREAD_QUAD_S 20 +/** SPI1_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI1_MEM_C_WP_REG (BIT(21)) +#define SPI1_MEM_C_WP_REG_M (SPI1_MEM_C_WP_REG_V << SPI1_MEM_C_WP_REG_S) +#define SPI1_MEM_C_WP_REG_V 0x00000001U +#define SPI1_MEM_C_WP_REG_S 21 +/** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ +#define SPI1_MEM_C_WRSR_2B (BIT(22)) +#define SPI1_MEM_C_WRSR_2B_M (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S) +#define SPI1_MEM_C_WRSR_2B_V 0x00000001U +#define SPI1_MEM_C_WRSR_2B_S 22 +/** SPI1_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_C_FREAD_DIO (BIT(23)) +#define SPI1_MEM_C_FREAD_DIO_M (SPI1_MEM_C_FREAD_DIO_V << SPI1_MEM_C_FREAD_DIO_S) +#define SPI1_MEM_C_FREAD_DIO_V 0x00000001U +#define SPI1_MEM_C_FREAD_DIO_S 23 +/** SPI1_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_C_FREAD_QIO (BIT(24)) +#define SPI1_MEM_C_FREAD_QIO_M (SPI1_MEM_C_FREAD_QIO_V << SPI1_MEM_C_FREAD_QIO_S) +#define SPI1_MEM_C_FREAD_QIO_V 0x00000001U +#define SPI1_MEM_C_FREAD_QIO_S 24 + +/** SPI1_MEM_C_CTRL1_REG register + * SPI1 control1 register. + */ +#define SPI1_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI1_BASE + 0xc) +/** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI1_MEM_C_CLK_MODE 0x00000003U +#define SPI1_MEM_C_CLK_MODE_M (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S) +#define SPI1_MEM_C_CLK_MODE_V 0x00000003U +#define SPI1_MEM_C_CLK_MODE_S 0 +/** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ +#define SPI1_MEM_C_CS_HOLD_DLY_RES 0x000003FFU +#define SPI1_MEM_C_CS_HOLD_DLY_RES_M (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S) +#define SPI1_MEM_C_CS_HOLD_DLY_RES_V 0x000003FFU +#define SPI1_MEM_C_CS_HOLD_DLY_RES_S 2 + +/** SPI1_MEM_C_CTRL2_REG register + * SPI1 control2 register. + */ +#define SPI1_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI1_BASE + 0x10) +/** SPI1_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ +#define SPI1_MEM_C_SYNC_RESET (BIT(31)) +#define SPI1_MEM_C_SYNC_RESET_M (SPI1_MEM_C_SYNC_RESET_V << SPI1_MEM_C_SYNC_RESET_S) +#define SPI1_MEM_C_SYNC_RESET_V 0x00000001U +#define SPI1_MEM_C_SYNC_RESET_S 31 + +/** SPI1_MEM_C_CLOCK_REG register + * SPI1 clock division control register. + */ +#define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14) +/** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + */ +#define SPI1_MEM_C_CLKCNT_L 0x000000FFU +#define SPI1_MEM_C_CLKCNT_L_M (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S) +#define SPI1_MEM_C_CLKCNT_L_V 0x000000FFU +#define SPI1_MEM_C_CLKCNT_L_S 0 +/** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + */ +#define SPI1_MEM_C_CLKCNT_H 0x000000FFU +#define SPI1_MEM_C_CLKCNT_H_M (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S) +#define SPI1_MEM_C_CLKCNT_H_V 0x000000FFU +#define SPI1_MEM_C_CLKCNT_H_S 8 +/** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is + * system/(spi1_mem_c_clkcnt_N+1) + */ +#define SPI1_MEM_C_CLKCNT_N 0x000000FFU +#define SPI1_MEM_C_CLKCNT_N_M (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S) +#define SPI1_MEM_C_CLKCNT_N_V 0x000000FFU +#define SPI1_MEM_C_CLKCNT_N_S 16 +/** SPI1_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SPI1_MEM_C_CLK_EQU_SYSCLK (BIT(31)) +#define SPI1_MEM_C_CLK_EQU_SYSCLK_M (SPI1_MEM_C_CLK_EQU_SYSCLK_V << SPI1_MEM_C_CLK_EQU_SYSCLK_S) +#define SPI1_MEM_C_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI1_MEM_C_CLK_EQU_SYSCLK_S 31 + +/** SPI1_MEM_C_USER_REG register + * SPI1 user register. + */ +#define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18) +/** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + */ +#define SPI1_MEM_C_CK_OUT_EDGE (BIT(9)) +#define SPI1_MEM_C_CK_OUT_EDGE_M (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S) +#define SPI1_MEM_C_CK_OUT_EDGE_V 0x00000001U +#define SPI1_MEM_C_CK_OUT_EDGE_S 9 +/** SPI1_MEM_C_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ +#define SPI1_MEM_C_FWRITE_DUAL (BIT(12)) +#define SPI1_MEM_C_FWRITE_DUAL_M (SPI1_MEM_C_FWRITE_DUAL_V << SPI1_MEM_C_FWRITE_DUAL_S) +#define SPI1_MEM_C_FWRITE_DUAL_V 0x00000001U +#define SPI1_MEM_C_FWRITE_DUAL_S 12 +/** SPI1_MEM_C_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ +#define SPI1_MEM_C_FWRITE_QUAD (BIT(13)) +#define SPI1_MEM_C_FWRITE_QUAD_M (SPI1_MEM_C_FWRITE_QUAD_V << SPI1_MEM_C_FWRITE_QUAD_S) +#define SPI1_MEM_C_FWRITE_QUAD_V 0x00000001U +#define SPI1_MEM_C_FWRITE_QUAD_S 13 +/** SPI1_MEM_C_FWRITE_DIO : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ +#define SPI1_MEM_C_FWRITE_DIO (BIT(14)) +#define SPI1_MEM_C_FWRITE_DIO_M (SPI1_MEM_C_FWRITE_DIO_V << SPI1_MEM_C_FWRITE_DIO_S) +#define SPI1_MEM_C_FWRITE_DIO_V 0x00000001U +#define SPI1_MEM_C_FWRITE_DIO_S 14 +/** SPI1_MEM_C_FWRITE_QIO : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ +#define SPI1_MEM_C_FWRITE_QIO (BIT(15)) +#define SPI1_MEM_C_FWRITE_QIO_M (SPI1_MEM_C_FWRITE_QIO_V << SPI1_MEM_C_FWRITE_QIO_S) +#define SPI1_MEM_C_FWRITE_QIO_V 0x00000001U +#define SPI1_MEM_C_FWRITE_QIO_S 15 +/** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * enable 0: disable. + */ +#define SPI1_MEM_C_USR_MISO_HIGHPART (BIT(24)) +#define SPI1_MEM_C_USR_MISO_HIGHPART_M (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S) +#define SPI1_MEM_C_USR_MISO_HIGHPART_V 0x00000001U +#define SPI1_MEM_C_USR_MISO_HIGHPART_S 24 +/** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * enable 0: disable. + */ +#define SPI1_MEM_C_USR_MOSI_HIGHPART (BIT(25)) +#define SPI1_MEM_C_USR_MOSI_HIGHPART_M (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S) +#define SPI1_MEM_C_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI1_MEM_C_USR_MOSI_HIGHPART_S 25 +/** SPI1_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ +#define SPI1_MEM_C_USR_DUMMY_IDLE (BIT(26)) +#define SPI1_MEM_C_USR_DUMMY_IDLE_M (SPI1_MEM_C_USR_DUMMY_IDLE_V << SPI1_MEM_C_USR_DUMMY_IDLE_S) +#define SPI1_MEM_C_USR_DUMMY_IDLE_V 0x00000001U +#define SPI1_MEM_C_USR_DUMMY_IDLE_S 26 +/** SPI1_MEM_C_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ +#define SPI1_MEM_C_USR_MOSI (BIT(27)) +#define SPI1_MEM_C_USR_MOSI_M (SPI1_MEM_C_USR_MOSI_V << SPI1_MEM_C_USR_MOSI_S) +#define SPI1_MEM_C_USR_MOSI_V 0x00000001U +#define SPI1_MEM_C_USR_MOSI_S 27 +/** SPI1_MEM_C_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ +#define SPI1_MEM_C_USR_MISO (BIT(28)) +#define SPI1_MEM_C_USR_MISO_M (SPI1_MEM_C_USR_MISO_V << SPI1_MEM_C_USR_MISO_S) +#define SPI1_MEM_C_USR_MISO_V 0x00000001U +#define SPI1_MEM_C_USR_MISO_S 28 +/** SPI1_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI1_MEM_C_USR_DUMMY (BIT(29)) +#define SPI1_MEM_C_USR_DUMMY_M (SPI1_MEM_C_USR_DUMMY_V << SPI1_MEM_C_USR_DUMMY_S) +#define SPI1_MEM_C_USR_DUMMY_V 0x00000001U +#define SPI1_MEM_C_USR_DUMMY_S 29 +/** SPI1_MEM_C_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ +#define SPI1_MEM_C_USR_ADDR (BIT(30)) +#define SPI1_MEM_C_USR_ADDR_M (SPI1_MEM_C_USR_ADDR_V << SPI1_MEM_C_USR_ADDR_S) +#define SPI1_MEM_C_USR_ADDR_V 0x00000001U +#define SPI1_MEM_C_USR_ADDR_S 30 +/** SPI1_MEM_C_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ +#define SPI1_MEM_C_USR_COMMAND (BIT(31)) +#define SPI1_MEM_C_USR_COMMAND_M (SPI1_MEM_C_USR_COMMAND_V << SPI1_MEM_C_USR_COMMAND_S) +#define SPI1_MEM_C_USR_COMMAND_V 0x00000001U +#define SPI1_MEM_C_USR_COMMAND_S 31 + +/** SPI1_MEM_C_USER1_REG register + * SPI1 user1 register. + */ +#define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c) +/** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI1_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_M (SPI1_MEM_C_USR_DUMMY_CYCLELEN_V << SPI1_MEM_C_USR_DUMMY_CYCLELEN_S) +#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_S 0 +/** SPI1_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_C_USR_ADDR_BITLEN 0x0000003FU +#define SPI1_MEM_C_USR_ADDR_BITLEN_M (SPI1_MEM_C_USR_ADDR_BITLEN_V << SPI1_MEM_C_USR_ADDR_BITLEN_S) +#define SPI1_MEM_C_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI1_MEM_C_USR_ADDR_BITLEN_S 26 + +/** SPI1_MEM_C_USER2_REG register + * SPI1 user2 register. + */ +#define SPI1_MEM_C_USER2_REG (DR_REG_FLASH_SPI1_BASE + 0x20) +/** SPI1_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI1_MEM_C_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI1_MEM_C_USR_COMMAND_VALUE_M (SPI1_MEM_C_USR_COMMAND_VALUE_V << SPI1_MEM_C_USR_COMMAND_VALUE_S) +#define SPI1_MEM_C_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI1_MEM_C_USR_COMMAND_VALUE_S 0 +/** SPI1_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI1_MEM_C_USR_COMMAND_BITLEN 0x0000000FU +#define SPI1_MEM_C_USR_COMMAND_BITLEN_M (SPI1_MEM_C_USR_COMMAND_BITLEN_V << SPI1_MEM_C_USR_COMMAND_BITLEN_S) +#define SPI1_MEM_C_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI1_MEM_C_USR_COMMAND_BITLEN_S 28 + +/** SPI1_MEM_C_MOSI_DLEN_REG register + * SPI1 send data bit length control register. + */ +#define SPI1_MEM_C_MOSI_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x24) +/** SPI1_MEM_C_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_C_USR_MOSI_DBITLEN 0x000003FFU +#define SPI1_MEM_C_USR_MOSI_DBITLEN_M (SPI1_MEM_C_USR_MOSI_DBITLEN_V << SPI1_MEM_C_USR_MOSI_DBITLEN_S) +#define SPI1_MEM_C_USR_MOSI_DBITLEN_V 0x000003FFU +#define SPI1_MEM_C_USR_MOSI_DBITLEN_S 0 + +/** SPI1_MEM_C_MISO_DLEN_REG register + * SPI1 receive data bit length control register. + */ +#define SPI1_MEM_C_MISO_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x28) +/** SPI1_MEM_C_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_C_USR_MISO_DBITLEN 0x000003FFU +#define SPI1_MEM_C_USR_MISO_DBITLEN_M (SPI1_MEM_C_USR_MISO_DBITLEN_V << SPI1_MEM_C_USR_MISO_DBITLEN_S) +#define SPI1_MEM_C_USR_MISO_DBITLEN_V 0x000003FFU +#define SPI1_MEM_C_USR_MISO_DBITLEN_S 0 + +/** SPI1_MEM_C_RD_STATUS_REG register + * SPI1 status register. + */ +#define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c) +/** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + */ +#define SPI1_MEM_C_STATUS 0x0000FFFFU +#define SPI1_MEM_C_STATUS_M (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S) +#define SPI1_MEM_C_STATUS_V 0x0000FFFFU +#define SPI1_MEM_C_STATUS_S 0 +/** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + */ +#define SPI1_MEM_C_WB_MODE 0x000000FFU +#define SPI1_MEM_C_WB_MODE_M (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S) +#define SPI1_MEM_C_WB_MODE_V 0x000000FFU +#define SPI1_MEM_C_WB_MODE_S 16 + +/** SPI1_MEM_C_MISC_REG register + * SPI1 misc register + */ +#define SPI1_MEM_C_MISC_REG (DR_REG_FLASH_SPI1_BASE + 0x34) +/** SPI1_MEM_C_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_C_CS0_DIS (BIT(0)) +#define SPI1_MEM_C_CS0_DIS_M (SPI1_MEM_C_CS0_DIS_V << SPI1_MEM_C_CS0_DIS_S) +#define SPI1_MEM_C_CS0_DIS_V 0x00000001U +#define SPI1_MEM_C_CS0_DIS_S 0 +/** SPI1_MEM_C_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_C_CS1_DIS (BIT(1)) +#define SPI1_MEM_C_CS1_DIS_M (SPI1_MEM_C_CS1_DIS_V << SPI1_MEM_C_CS1_DIS_S) +#define SPI1_MEM_C_CS1_DIS_V 0x00000001U +#define SPI1_MEM_C_CS1_DIS_S 1 +/** SPI1_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ +#define SPI1_MEM_C_CK_IDLE_EDGE (BIT(9)) +#define SPI1_MEM_C_CK_IDLE_EDGE_M (SPI1_MEM_C_CK_IDLE_EDGE_V << SPI1_MEM_C_CK_IDLE_EDGE_S) +#define SPI1_MEM_C_CK_IDLE_EDGE_V 0x00000001U +#define SPI1_MEM_C_CK_IDLE_EDGE_S 9 +/** SPI1_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ +#define SPI1_MEM_C_CS_KEEP_ACTIVE (BIT(10)) +#define SPI1_MEM_C_CS_KEEP_ACTIVE_M (SPI1_MEM_C_CS_KEEP_ACTIVE_V << SPI1_MEM_C_CS_KEEP_ACTIVE_S) +#define SPI1_MEM_C_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI1_MEM_C_CS_KEEP_ACTIVE_S 10 + +/** SPI1_MEM_C_TX_CRC_REG register + * SPI1 TX CRC data register. + */ +#define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38) +/** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ +#define SPI1_MEM_C_TX_CRC_DATA 0xFFFFFFFFU +#define SPI1_MEM_C_TX_CRC_DATA_M (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S) +#define SPI1_MEM_C_TX_CRC_DATA_V 0xFFFFFFFFU +#define SPI1_MEM_C_TX_CRC_DATA_S 0 + +/** SPI1_MEM_C_CACHE_FCTRL_REG register + * SPI1 bit mode control register. + */ +#define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c) +/** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ +#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S) +#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi1_mem_c_fread_dio. + */ +#define SPI1_MEM_C_FDIN_DUAL (BIT(3)) +#define SPI1_MEM_C_FDIN_DUAL_M (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S) +#define SPI1_MEM_C_FDIN_DUAL_V 0x00000001U +#define SPI1_MEM_C_FDIN_DUAL_S 3 +/** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_dio. + */ +#define SPI1_MEM_C_FDOUT_DUAL (BIT(4)) +#define SPI1_MEM_C_FDOUT_DUAL_M (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S) +#define SPI1_MEM_C_FDOUT_DUAL_V 0x00000001U +#define SPI1_MEM_C_FDOUT_DUAL_S 4 +/** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_dio. + */ +#define SPI1_MEM_C_FADDR_DUAL (BIT(5)) +#define SPI1_MEM_C_FADDR_DUAL_M (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S) +#define SPI1_MEM_C_FADDR_DUAL_V 0x00000001U +#define SPI1_MEM_C_FADDR_DUAL_S 5 +/** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ +#define SPI1_MEM_C_FDIN_QUAD (BIT(6)) +#define SPI1_MEM_C_FDIN_QUAD_M (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S) +#define SPI1_MEM_C_FDIN_QUAD_V 0x00000001U +#define SPI1_MEM_C_FDIN_QUAD_S 6 +/** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ +#define SPI1_MEM_C_FDOUT_QUAD (BIT(7)) +#define SPI1_MEM_C_FDOUT_QUAD_M (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S) +#define SPI1_MEM_C_FDOUT_QUAD_V 0x00000001U +#define SPI1_MEM_C_FDOUT_QUAD_S 7 +/** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ +#define SPI1_MEM_C_FADDR_QUAD (BIT(8)) +#define SPI1_MEM_C_FADDR_QUAD_M (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S) +#define SPI1_MEM_C_FADDR_QUAD_V 0x00000001U +#define SPI1_MEM_C_FADDR_QUAD_S 8 + +/** SPI1_MEM_C_W0_REG register + * SPI1 memory data buffer0 + */ +#define SPI1_MEM_C_W0_REG (DR_REG_FLASH_SPI1_BASE + 0x58) +/** SPI1_MEM_C_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF0 0xFFFFFFFFU +#define SPI1_MEM_C_BUF0_M (SPI1_MEM_C_BUF0_V << SPI1_MEM_C_BUF0_S) +#define SPI1_MEM_C_BUF0_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF0_S 0 + +/** SPI1_MEM_C_W1_REG register + * SPI1 memory data buffer1 + */ +#define SPI1_MEM_C_W1_REG (DR_REG_FLASH_SPI1_BASE + 0x5c) +/** SPI1_MEM_C_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF1 0xFFFFFFFFU +#define SPI1_MEM_C_BUF1_M (SPI1_MEM_C_BUF1_V << SPI1_MEM_C_BUF1_S) +#define SPI1_MEM_C_BUF1_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF1_S 0 + +/** SPI1_MEM_C_W2_REG register + * SPI1 memory data buffer2 + */ +#define SPI1_MEM_C_W2_REG (DR_REG_FLASH_SPI1_BASE + 0x60) +/** SPI1_MEM_C_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF2 0xFFFFFFFFU +#define SPI1_MEM_C_BUF2_M (SPI1_MEM_C_BUF2_V << SPI1_MEM_C_BUF2_S) +#define SPI1_MEM_C_BUF2_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF2_S 0 + +/** SPI1_MEM_C_W3_REG register + * SPI1 memory data buffer3 + */ +#define SPI1_MEM_C_W3_REG (DR_REG_FLASH_SPI1_BASE + 0x64) +/** SPI1_MEM_C_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF3 0xFFFFFFFFU +#define SPI1_MEM_C_BUF3_M (SPI1_MEM_C_BUF3_V << SPI1_MEM_C_BUF3_S) +#define SPI1_MEM_C_BUF3_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF3_S 0 + +/** SPI1_MEM_C_W4_REG register + * SPI1 memory data buffer4 + */ +#define SPI1_MEM_C_W4_REG (DR_REG_FLASH_SPI1_BASE + 0x68) +/** SPI1_MEM_C_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF4 0xFFFFFFFFU +#define SPI1_MEM_C_BUF4_M (SPI1_MEM_C_BUF4_V << SPI1_MEM_C_BUF4_S) +#define SPI1_MEM_C_BUF4_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF4_S 0 + +/** SPI1_MEM_C_W5_REG register + * SPI1 memory data buffer5 + */ +#define SPI1_MEM_C_W5_REG (DR_REG_FLASH_SPI1_BASE + 0x6c) +/** SPI1_MEM_C_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF5 0xFFFFFFFFU +#define SPI1_MEM_C_BUF5_M (SPI1_MEM_C_BUF5_V << SPI1_MEM_C_BUF5_S) +#define SPI1_MEM_C_BUF5_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF5_S 0 + +/** SPI1_MEM_C_W6_REG register + * SPI1 memory data buffer6 + */ +#define SPI1_MEM_C_W6_REG (DR_REG_FLASH_SPI1_BASE + 0x70) +/** SPI1_MEM_C_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF6 0xFFFFFFFFU +#define SPI1_MEM_C_BUF6_M (SPI1_MEM_C_BUF6_V << SPI1_MEM_C_BUF6_S) +#define SPI1_MEM_C_BUF6_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF6_S 0 + +/** SPI1_MEM_C_W7_REG register + * SPI1 memory data buffer7 + */ +#define SPI1_MEM_C_W7_REG (DR_REG_FLASH_SPI1_BASE + 0x74) +/** SPI1_MEM_C_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF7 0xFFFFFFFFU +#define SPI1_MEM_C_BUF7_M (SPI1_MEM_C_BUF7_V << SPI1_MEM_C_BUF7_S) +#define SPI1_MEM_C_BUF7_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF7_S 0 + +/** SPI1_MEM_C_W8_REG register + * SPI1 memory data buffer8 + */ +#define SPI1_MEM_C_W8_REG (DR_REG_FLASH_SPI1_BASE + 0x78) +/** SPI1_MEM_C_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF8 0xFFFFFFFFU +#define SPI1_MEM_C_BUF8_M (SPI1_MEM_C_BUF8_V << SPI1_MEM_C_BUF8_S) +#define SPI1_MEM_C_BUF8_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF8_S 0 + +/** SPI1_MEM_C_W9_REG register + * SPI1 memory data buffer9 + */ +#define SPI1_MEM_C_W9_REG (DR_REG_FLASH_SPI1_BASE + 0x7c) +/** SPI1_MEM_C_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF9 0xFFFFFFFFU +#define SPI1_MEM_C_BUF9_M (SPI1_MEM_C_BUF9_V << SPI1_MEM_C_BUF9_S) +#define SPI1_MEM_C_BUF9_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF9_S 0 + +/** SPI1_MEM_C_W10_REG register + * SPI1 memory data buffer10 + */ +#define SPI1_MEM_C_W10_REG (DR_REG_FLASH_SPI1_BASE + 0x80) +/** SPI1_MEM_C_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF10 0xFFFFFFFFU +#define SPI1_MEM_C_BUF10_M (SPI1_MEM_C_BUF10_V << SPI1_MEM_C_BUF10_S) +#define SPI1_MEM_C_BUF10_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF10_S 0 + +/** SPI1_MEM_C_W11_REG register + * SPI1 memory data buffer11 + */ +#define SPI1_MEM_C_W11_REG (DR_REG_FLASH_SPI1_BASE + 0x84) +/** SPI1_MEM_C_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF11 0xFFFFFFFFU +#define SPI1_MEM_C_BUF11_M (SPI1_MEM_C_BUF11_V << SPI1_MEM_C_BUF11_S) +#define SPI1_MEM_C_BUF11_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF11_S 0 + +/** SPI1_MEM_C_W12_REG register + * SPI1 memory data buffer12 + */ +#define SPI1_MEM_C_W12_REG (DR_REG_FLASH_SPI1_BASE + 0x88) +/** SPI1_MEM_C_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF12 0xFFFFFFFFU +#define SPI1_MEM_C_BUF12_M (SPI1_MEM_C_BUF12_V << SPI1_MEM_C_BUF12_S) +#define SPI1_MEM_C_BUF12_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF12_S 0 + +/** SPI1_MEM_C_W13_REG register + * SPI1 memory data buffer13 + */ +#define SPI1_MEM_C_W13_REG (DR_REG_FLASH_SPI1_BASE + 0x8c) +/** SPI1_MEM_C_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF13 0xFFFFFFFFU +#define SPI1_MEM_C_BUF13_M (SPI1_MEM_C_BUF13_V << SPI1_MEM_C_BUF13_S) +#define SPI1_MEM_C_BUF13_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF13_S 0 + +/** SPI1_MEM_C_W14_REG register + * SPI1 memory data buffer14 + */ +#define SPI1_MEM_C_W14_REG (DR_REG_FLASH_SPI1_BASE + 0x90) +/** SPI1_MEM_C_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF14 0xFFFFFFFFU +#define SPI1_MEM_C_BUF14_M (SPI1_MEM_C_BUF14_V << SPI1_MEM_C_BUF14_S) +#define SPI1_MEM_C_BUF14_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF14_S 0 + +/** SPI1_MEM_C_W15_REG register + * SPI1 memory data buffer15 + */ +#define SPI1_MEM_C_W15_REG (DR_REG_FLASH_SPI1_BASE + 0x94) +/** SPI1_MEM_C_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_C_BUF15 0xFFFFFFFFU +#define SPI1_MEM_C_BUF15_M (SPI1_MEM_C_BUF15_V << SPI1_MEM_C_BUF15_S) +#define SPI1_MEM_C_BUF15_V 0xFFFFFFFFU +#define SPI1_MEM_C_BUF15_S 0 + +/** SPI1_MEM_C_FLASH_WAITI_CTRL_REG register + * SPI1 wait idle control register + */ +#define SPI1_MEM_C_FLASH_WAITI_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x98) +/** SPI1_MEM_C_WAITI_EN : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ +#define SPI1_MEM_C_WAITI_EN (BIT(0)) +#define SPI1_MEM_C_WAITI_EN_M (SPI1_MEM_C_WAITI_EN_V << SPI1_MEM_C_WAITI_EN_S) +#define SPI1_MEM_C_WAITI_EN_V 0x00000001U +#define SPI1_MEM_C_WAITI_EN_S 0 +/** SPI1_MEM_C_WAITI_DUMMY : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ +#define SPI1_MEM_C_WAITI_DUMMY (BIT(1)) +#define SPI1_MEM_C_WAITI_DUMMY_M (SPI1_MEM_C_WAITI_DUMMY_V << SPI1_MEM_C_WAITI_DUMMY_S) +#define SPI1_MEM_C_WAITI_DUMMY_V 0x00000001U +#define SPI1_MEM_C_WAITI_DUMMY_S 1 +/** SPI1_MEM_C_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ +#define SPI1_MEM_C_WAITI_ADDR_EN (BIT(2)) +#define SPI1_MEM_C_WAITI_ADDR_EN_M (SPI1_MEM_C_WAITI_ADDR_EN_V << SPI1_MEM_C_WAITI_ADDR_EN_S) +#define SPI1_MEM_C_WAITI_ADDR_EN_V 0x00000001U +#define SPI1_MEM_C_WAITI_ADDR_EN_S 2 +/** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + */ +#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN 0x00000003U +#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S) +#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V 0x00000003U +#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S 3 +/** SPI1_MEM_C_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ +#define SPI1_MEM_C_WAITI_CMD_2B (BIT(9)) +#define SPI1_MEM_C_WAITI_CMD_2B_M (SPI1_MEM_C_WAITI_CMD_2B_V << SPI1_MEM_C_WAITI_CMD_2B_S) +#define SPI1_MEM_C_WAITI_CMD_2B_V 0x00000001U +#define SPI1_MEM_C_WAITI_CMD_2B_S 9 +/** SPI1_MEM_C_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ +#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_M (SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S) +#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S 10 +/** SPI1_MEM_C_WAITI_CMD : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ +#define SPI1_MEM_C_WAITI_CMD 0x0000FFFFU +#define SPI1_MEM_C_WAITI_CMD_M (SPI1_MEM_C_WAITI_CMD_V << SPI1_MEM_C_WAITI_CMD_S) +#define SPI1_MEM_C_WAITI_CMD_V 0x0000FFFFU +#define SPI1_MEM_C_WAITI_CMD_S 16 + +/** SPI1_MEM_C_FLASH_SUS_CTRL_REG register + * SPI1 flash suspend control register + */ +#define SPI1_MEM_C_FLASH_SUS_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x9c) +/** SPI1_MEM_C_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_C_FLASH_PER (BIT(0)) +#define SPI1_MEM_C_FLASH_PER_M (SPI1_MEM_C_FLASH_PER_V << SPI1_MEM_C_FLASH_PER_S) +#define SPI1_MEM_C_FLASH_PER_V 0x00000001U +#define SPI1_MEM_C_FLASH_PER_S 0 +/** SPI1_MEM_C_FLASH_PES : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_C_FLASH_PES (BIT(1)) +#define SPI1_MEM_C_FLASH_PES_M (SPI1_MEM_C_FLASH_PES_V << SPI1_MEM_C_FLASH_PES_S) +#define SPI1_MEM_C_FLASH_PES_V 0x00000001U +#define SPI1_MEM_C_FLASH_PES_S 1 +/** SPI1_MEM_C_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ +#define SPI1_MEM_C_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI1_MEM_C_FLASH_PER_WAIT_EN_M (SPI1_MEM_C_FLASH_PER_WAIT_EN_V << SPI1_MEM_C_FLASH_PER_WAIT_EN_S) +#define SPI1_MEM_C_FLASH_PER_WAIT_EN_V 0x00000001U +#define SPI1_MEM_C_FLASH_PER_WAIT_EN_S 2 +/** SPI1_MEM_C_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ +#define SPI1_MEM_C_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI1_MEM_C_FLASH_PES_WAIT_EN_M (SPI1_MEM_C_FLASH_PES_WAIT_EN_V << SPI1_MEM_C_FLASH_PES_WAIT_EN_S) +#define SPI1_MEM_C_FLASH_PES_WAIT_EN_V 0x00000001U +#define SPI1_MEM_C_FLASH_PES_WAIT_EN_S 3 +/** SPI1_MEM_C_PES_PER_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ +#define SPI1_MEM_C_PES_PER_EN (BIT(4)) +#define SPI1_MEM_C_PES_PER_EN_M (SPI1_MEM_C_PES_PER_EN_V << SPI1_MEM_C_PES_PER_EN_S) +#define SPI1_MEM_C_PES_PER_EN_V 0x00000001U +#define SPI1_MEM_C_PES_PER_EN_S 4 +/** SPI1_MEM_C_FLASH_PES_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ +#define SPI1_MEM_C_FLASH_PES_EN (BIT(5)) +#define SPI1_MEM_C_FLASH_PES_EN_M (SPI1_MEM_C_FLASH_PES_EN_V << SPI1_MEM_C_FLASH_PES_EN_S) +#define SPI1_MEM_C_FLASH_PES_EN_V 0x00000001U +#define SPI1_MEM_C_FLASH_PES_EN_S 5 +/** SPI1_MEM_C_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0]. + */ +#define SPI1_MEM_C_PESR_END_MSK 0x0000FFFFU +#define SPI1_MEM_C_PESR_END_MSK_M (SPI1_MEM_C_PESR_END_MSK_V << SPI1_MEM_C_PESR_END_MSK_S) +#define SPI1_MEM_C_PESR_END_MSK_V 0x0000FFFFU +#define SPI1_MEM_C_PESR_END_MSK_S 6 +/** SPI1_MEM_C_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ +#define SPI1_MEM_C_FMEM_RD_SUS_2B (BIT(22)) +#define SPI1_MEM_C_FMEM_RD_SUS_2B_M (SPI1_MEM_C_FMEM_RD_SUS_2B_V << SPI1_MEM_C_FMEM_RD_SUS_2B_S) +#define SPI1_MEM_C_FMEM_RD_SUS_2B_V 0x00000001U +#define SPI1_MEM_C_FMEM_RD_SUS_2B_S 22 +/** SPI1_MEM_C_PER_END_EN : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_C_PER_END_EN (BIT(23)) +#define SPI1_MEM_C_PER_END_EN_M (SPI1_MEM_C_PER_END_EN_V << SPI1_MEM_C_PER_END_EN_S) +#define SPI1_MEM_C_PER_END_EN_V 0x00000001U +#define SPI1_MEM_C_PER_END_EN_S 23 +/** SPI1_MEM_C_PES_END_EN : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_C_PES_END_EN (BIT(24)) +#define SPI1_MEM_C_PES_END_EN_M (SPI1_MEM_C_PES_END_EN_V << SPI1_MEM_C_PES_END_EN_S) +#define SPI1_MEM_C_PES_END_EN_V 0x00000001U +#define SPI1_MEM_C_PES_END_EN_S 24 +/** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ +#define SPI1_MEM_C_SUS_TIMEOUT_CNT 0x0000007FU +#define SPI1_MEM_C_SUS_TIMEOUT_CNT_M (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S) +#define SPI1_MEM_C_SUS_TIMEOUT_CNT_V 0x0000007FU +#define SPI1_MEM_C_SUS_TIMEOUT_CNT_S 25 + +/** SPI1_MEM_C_FLASH_SUS_CMD_REG register + * SPI1 flash suspend command register + */ +#define SPI1_MEM_C_FLASH_SUS_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0xa0) +/** SPI1_MEM_C_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ +#define SPI1_MEM_C_FLASH_PES_COMMAND 0x0000FFFFU +#define SPI1_MEM_C_FLASH_PES_COMMAND_M (SPI1_MEM_C_FLASH_PES_COMMAND_V << SPI1_MEM_C_FLASH_PES_COMMAND_S) +#define SPI1_MEM_C_FLASH_PES_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_C_FLASH_PES_COMMAND_S 0 +/** SPI1_MEM_C_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ +#define SPI1_MEM_C_WAIT_PESR_COMMAND 0x0000FFFFU +#define SPI1_MEM_C_WAIT_PESR_COMMAND_M (SPI1_MEM_C_WAIT_PESR_COMMAND_V << SPI1_MEM_C_WAIT_PESR_COMMAND_S) +#define SPI1_MEM_C_WAIT_PESR_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_C_WAIT_PESR_COMMAND_S 16 + +/** SPI1_MEM_C_SUS_STATUS_REG register + * SPI1 flash suspend status register + */ +#define SPI1_MEM_C_SUS_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0xa4) +/** SPI1_MEM_C_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ +#define SPI1_MEM_C_FLASH_SUS (BIT(0)) +#define SPI1_MEM_C_FLASH_SUS_M (SPI1_MEM_C_FLASH_SUS_V << SPI1_MEM_C_FLASH_SUS_S) +#define SPI1_MEM_C_FLASH_SUS_V 0x00000001U +#define SPI1_MEM_C_FLASH_SUS_S 0 +/** SPI1_MEM_C_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ +#define SPI1_MEM_C_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI1_MEM_C_WAIT_PESR_CMD_2B_M (SPI1_MEM_C_WAIT_PESR_CMD_2B_V << SPI1_MEM_C_WAIT_PESR_CMD_2B_S) +#define SPI1_MEM_C_WAIT_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_C_WAIT_PESR_CMD_2B_S 1 +/** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ +#define SPI1_MEM_C_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI1_MEM_C_FLASH_HPM_DLY_128_M (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S) +#define SPI1_MEM_C_FLASH_HPM_DLY_128_V 0x00000001U +#define SPI1_MEM_C_FLASH_HPM_DLY_128_S 2 +/** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ +#define SPI1_MEM_C_FLASH_RES_DLY_128 (BIT(3)) +#define SPI1_MEM_C_FLASH_RES_DLY_128_M (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S) +#define SPI1_MEM_C_FLASH_RES_DLY_128_V 0x00000001U +#define SPI1_MEM_C_FLASH_RES_DLY_128_S 3 +/** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ +#define SPI1_MEM_C_FLASH_DP_DLY_128 (BIT(4)) +#define SPI1_MEM_C_FLASH_DP_DLY_128_M (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S) +#define SPI1_MEM_C_FLASH_DP_DLY_128_V 0x00000001U +#define SPI1_MEM_C_FLASH_DP_DLY_128_S 4 +/** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ +#define SPI1_MEM_C_FLASH_PER_DLY_128 (BIT(5)) +#define SPI1_MEM_C_FLASH_PER_DLY_128_M (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S) +#define SPI1_MEM_C_FLASH_PER_DLY_128_V 0x00000001U +#define SPI1_MEM_C_FLASH_PER_DLY_128_S 5 +/** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ +#define SPI1_MEM_C_FLASH_PES_DLY_128 (BIT(6)) +#define SPI1_MEM_C_FLASH_PES_DLY_128_M (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S) +#define SPI1_MEM_C_FLASH_PES_DLY_128_V 0x00000001U +#define SPI1_MEM_C_FLASH_PES_DLY_128_S 6 +/** SPI1_MEM_C_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ +#define SPI1_MEM_C_SPI0_LOCK_EN (BIT(7)) +#define SPI1_MEM_C_SPI0_LOCK_EN_M (SPI1_MEM_C_SPI0_LOCK_EN_V << SPI1_MEM_C_SPI0_LOCK_EN_S) +#define SPI1_MEM_C_SPI0_LOCK_EN_V 0x00000001U +#define SPI1_MEM_C_SPI0_LOCK_EN_S 7 +/** SPI1_MEM_C_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ +#define SPI1_MEM_C_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI1_MEM_C_FLASH_PESR_CMD_2B_M (SPI1_MEM_C_FLASH_PESR_CMD_2B_V << SPI1_MEM_C_FLASH_PESR_CMD_2B_S) +#define SPI1_MEM_C_FLASH_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_C_FLASH_PESR_CMD_2B_S 15 +/** SPI1_MEM_C_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ +#define SPI1_MEM_C_FLASH_PER_COMMAND 0x0000FFFFU +#define SPI1_MEM_C_FLASH_PER_COMMAND_M (SPI1_MEM_C_FLASH_PER_COMMAND_V << SPI1_MEM_C_FLASH_PER_COMMAND_S) +#define SPI1_MEM_C_FLASH_PER_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_C_FLASH_PER_COMMAND_S 16 + +/** SPI1_MEM_C_INT_ENA_REG register + * SPI1 interrupt enable register + */ +#define SPI1_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI1_BASE + 0xc0) +/** SPI1_MEM_C_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_C_PER_END_INT interrupt. + */ +#define SPI1_MEM_C_PER_END_INT_ENA (BIT(0)) +#define SPI1_MEM_C_PER_END_INT_ENA_M (SPI1_MEM_C_PER_END_INT_ENA_V << SPI1_MEM_C_PER_END_INT_ENA_S) +#define SPI1_MEM_C_PER_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_PER_END_INT_ENA_S 0 +/** SPI1_MEM_C_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_C_PES_END_INT interrupt. + */ +#define SPI1_MEM_C_PES_END_INT_ENA (BIT(1)) +#define SPI1_MEM_C_PES_END_INT_ENA_M (SPI1_MEM_C_PES_END_INT_ENA_V << SPI1_MEM_C_PES_END_INT_ENA_S) +#define SPI1_MEM_C_PES_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_PES_END_INT_ENA_S 1 +/** SPI1_MEM_C_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ +#define SPI1_MEM_C_WPE_END_INT_ENA (BIT(2)) +#define SPI1_MEM_C_WPE_END_INT_ENA_M (SPI1_MEM_C_WPE_END_INT_ENA_V << SPI1_MEM_C_WPE_END_INT_ENA_S) +#define SPI1_MEM_C_WPE_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_WPE_END_INT_ENA_S 2 +/** SPI1_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI1_MEM_C_SLV_ST_END_INT_ENA_M (SPI1_MEM_C_SLV_ST_END_INT_ENA_V << SPI1_MEM_C_SLV_ST_END_INT_ENA_S) +#define SPI1_MEM_C_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_SLV_ST_END_INT_ENA_S 3 +/** SPI1_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_MST_ST_END_INT_ENA (BIT(4)) +#define SPI1_MEM_C_MST_ST_END_INT_ENA_M (SPI1_MEM_C_MST_ST_END_INT_ENA_V << SPI1_MEM_C_MST_ST_END_INT_ENA_S) +#define SPI1_MEM_C_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_MST_ST_END_INT_ENA_S 4 +/** SPI1_MEM_C_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_C_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI1_MEM_C_BROWN_OUT_INT_ENA_M (SPI1_MEM_C_BROWN_OUT_INT_ENA_V << SPI1_MEM_C_BROWN_OUT_INT_ENA_S) +#define SPI1_MEM_C_BROWN_OUT_INT_ENA_V 0x00000001U +#define SPI1_MEM_C_BROWN_OUT_INT_ENA_S 10 + +/** SPI1_MEM_C_INT_CLR_REG register + * SPI1 interrupt clear register + */ +#define SPI1_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI1_BASE + 0xc4) +/** SPI1_MEM_C_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_C_PER_END_INT interrupt. + */ +#define SPI1_MEM_C_PER_END_INT_CLR (BIT(0)) +#define SPI1_MEM_C_PER_END_INT_CLR_M (SPI1_MEM_C_PER_END_INT_CLR_V << SPI1_MEM_C_PER_END_INT_CLR_S) +#define SPI1_MEM_C_PER_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_PER_END_INT_CLR_S 0 +/** SPI1_MEM_C_PES_END_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_C_PES_END_INT interrupt. + */ +#define SPI1_MEM_C_PES_END_INT_CLR (BIT(1)) +#define SPI1_MEM_C_PES_END_INT_CLR_M (SPI1_MEM_C_PES_END_INT_CLR_V << SPI1_MEM_C_PES_END_INT_CLR_S) +#define SPI1_MEM_C_PES_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_PES_END_INT_CLR_S 1 +/** SPI1_MEM_C_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ +#define SPI1_MEM_C_WPE_END_INT_CLR (BIT(2)) +#define SPI1_MEM_C_WPE_END_INT_CLR_M (SPI1_MEM_C_WPE_END_INT_CLR_V << SPI1_MEM_C_WPE_END_INT_CLR_S) +#define SPI1_MEM_C_WPE_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_WPE_END_INT_CLR_S 2 +/** SPI1_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI1_MEM_C_SLV_ST_END_INT_CLR_M (SPI1_MEM_C_SLV_ST_END_INT_CLR_V << SPI1_MEM_C_SLV_ST_END_INT_CLR_S) +#define SPI1_MEM_C_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_SLV_ST_END_INT_CLR_S 3 +/** SPI1_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_MST_ST_END_INT_CLR (BIT(4)) +#define SPI1_MEM_C_MST_ST_END_INT_CLR_M (SPI1_MEM_C_MST_ST_END_INT_CLR_V << SPI1_MEM_C_MST_ST_END_INT_CLR_S) +#define SPI1_MEM_C_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_MST_ST_END_INT_CLR_S 4 +/** SPI1_MEM_C_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_C_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI1_MEM_C_BROWN_OUT_INT_CLR_M (SPI1_MEM_C_BROWN_OUT_INT_CLR_V << SPI1_MEM_C_BROWN_OUT_INT_CLR_S) +#define SPI1_MEM_C_BROWN_OUT_INT_CLR_V 0x00000001U +#define SPI1_MEM_C_BROWN_OUT_INT_CLR_S 10 + +/** SPI1_MEM_C_INT_RAW_REG register + * SPI1 interrupt raw register + */ +#define SPI1_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI1_BASE + 0xc8) +/** SPI1_MEM_C_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ +#define SPI1_MEM_C_PER_END_INT_RAW (BIT(0)) +#define SPI1_MEM_C_PER_END_INT_RAW_M (SPI1_MEM_C_PER_END_INT_RAW_V << SPI1_MEM_C_PER_END_INT_RAW_S) +#define SPI1_MEM_C_PER_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_PER_END_INT_RAW_S 0 +/** SPI1_MEM_C_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ +#define SPI1_MEM_C_PES_END_INT_RAW (BIT(1)) +#define SPI1_MEM_C_PES_END_INT_RAW_M (SPI1_MEM_C_PES_END_INT_RAW_V << SPI1_MEM_C_PES_END_INT_RAW_S) +#define SPI1_MEM_C_PES_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_PES_END_INT_RAW_S 1 +/** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ +#define SPI1_MEM_C_WPE_END_INT_RAW (BIT(2)) +#define SPI1_MEM_C_WPE_END_INT_RAW_M (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S) +#define SPI1_MEM_C_WPE_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_WPE_END_INT_RAW_S 2 +/** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI1_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI1_MEM_C_SLV_ST_END_INT_RAW_M (SPI1_MEM_C_SLV_ST_END_INT_RAW_V << SPI1_MEM_C_SLV_ST_END_INT_RAW_S) +#define SPI1_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_SLV_ST_END_INT_RAW_S 3 +/** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI1_MEM_C_MST_ST_END_INT_RAW (BIT(4)) +#define SPI1_MEM_C_MST_ST_END_INT_RAW_M (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S) +#define SPI1_MEM_C_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_MST_ST_END_INT_RAW_S 4 +/** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is losing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ +#define SPI1_MEM_C_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI1_MEM_C_BROWN_OUT_INT_RAW_M (SPI1_MEM_C_BROWN_OUT_INT_RAW_V << SPI1_MEM_C_BROWN_OUT_INT_RAW_S) +#define SPI1_MEM_C_BROWN_OUT_INT_RAW_V 0x00000001U +#define SPI1_MEM_C_BROWN_OUT_INT_RAW_S 10 + +/** SPI1_MEM_C_INT_ST_REG register + * SPI1 interrupt status register + */ +#define SPI1_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI1_BASE + 0xcc) +/** SPI1_MEM_C_PER_END_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_C_PER_END_INT interrupt. + */ +#define SPI1_MEM_C_PER_END_INT_ST (BIT(0)) +#define SPI1_MEM_C_PER_END_INT_ST_M (SPI1_MEM_C_PER_END_INT_ST_V << SPI1_MEM_C_PER_END_INT_ST_S) +#define SPI1_MEM_C_PER_END_INT_ST_V 0x00000001U +#define SPI1_MEM_C_PER_END_INT_ST_S 0 +/** SPI1_MEM_C_PES_END_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_C_PES_END_INT interrupt. + */ +#define SPI1_MEM_C_PES_END_INT_ST (BIT(1)) +#define SPI1_MEM_C_PES_END_INT_ST_M (SPI1_MEM_C_PES_END_INT_ST_V << SPI1_MEM_C_PES_END_INT_ST_S) +#define SPI1_MEM_C_PES_END_INT_ST_V 0x00000001U +#define SPI1_MEM_C_PES_END_INT_ST_S 1 +/** SPI1_MEM_C_WPE_END_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ +#define SPI1_MEM_C_WPE_END_INT_ST (BIT(2)) +#define SPI1_MEM_C_WPE_END_INT_ST_M (SPI1_MEM_C_WPE_END_INT_ST_V << SPI1_MEM_C_WPE_END_INT_ST_S) +#define SPI1_MEM_C_WPE_END_INT_ST_V 0x00000001U +#define SPI1_MEM_C_WPE_END_INT_ST_S 2 +/** SPI1_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_SLV_ST_END_INT_ST (BIT(3)) +#define SPI1_MEM_C_SLV_ST_END_INT_ST_M (SPI1_MEM_C_SLV_ST_END_INT_ST_V << SPI1_MEM_C_SLV_ST_END_INT_ST_S) +#define SPI1_MEM_C_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_C_SLV_ST_END_INT_ST_S 3 +/** SPI1_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_C_MST_ST_END_INT_ST (BIT(4)) +#define SPI1_MEM_C_MST_ST_END_INT_ST_M (SPI1_MEM_C_MST_ST_END_INT_ST_V << SPI1_MEM_C_MST_ST_END_INT_ST_S) +#define SPI1_MEM_C_MST_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_C_MST_ST_END_INT_ST_S 4 +/** SPI1_MEM_C_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_C_BROWN_OUT_INT_ST (BIT(10)) +#define SPI1_MEM_C_BROWN_OUT_INT_ST_M (SPI1_MEM_C_BROWN_OUT_INT_ST_V << SPI1_MEM_C_BROWN_OUT_INT_ST_S) +#define SPI1_MEM_C_BROWN_OUT_INT_ST_V 0x00000001U +#define SPI1_MEM_C_BROWN_OUT_INT_ST_S 10 + +/** SPI1_MEM_C_DDR_REG register + * SPI1 DDR control register + */ +#define SPI1_MEM_C_DDR_REG (DR_REG_FLASH_SPI1_BASE + 0xd4) +/** SPI1_MEM_C_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ +#define SPI1_MEM_C_FMEM_DDR_EN (BIT(0)) +#define SPI1_MEM_C_FMEM_DDR_EN_M (SPI1_MEM_C_FMEM_DDR_EN_V << SPI1_MEM_C_FMEM_DDR_EN_S) +#define SPI1_MEM_C_FMEM_DDR_EN_V 0x00000001U +#define SPI1_MEM_C_FMEM_DDR_EN_S 0 +/** SPI1_MEM_C_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ +#define SPI1_MEM_C_FMEM_VAR_DUMMY (BIT(1)) +#define SPI1_MEM_C_FMEM_VAR_DUMMY_M (SPI1_MEM_C_FMEM_VAR_DUMMY_V << SPI1_MEM_C_FMEM_VAR_DUMMY_S) +#define SPI1_MEM_C_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI1_MEM_C_FMEM_VAR_DUMMY_S 1 +/** SPI1_MEM_C_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ +#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_M (SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S) +#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S 2 +/** SPI1_MEM_C_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ +#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_M (SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S) +#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S 3 +/** SPI1_MEM_C_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ +#define SPI1_MEM_C_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_M (SPI1_MEM_C_FMEM_DDR_CMD_DIS_V << SPI1_MEM_C_FMEM_DDR_CMD_DIS_S) +#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_S 4 +/** SPI1_MEM_C_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI1_MEM_C_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_M (SPI1_MEM_C_FMEM_OUTMINBYTELEN_V << SPI1_MEM_C_FMEM_OUTMINBYTELEN_S) +#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_S 5 +/** SPI1_MEM_C_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_M (SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S) +#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_M (SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S) +#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S 21 +/** SPI1_MEM_C_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI1_MEM_C_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_M (SPI1_MEM_C_FMEM_CLK_DIFF_EN_V << SPI1_MEM_C_FMEM_CLK_DIFF_EN_S) +#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_S 24 +/** SPI1_MEM_C_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI1_MEM_C_FMEM_DQS_CA_IN (BIT(26)) +#define SPI1_MEM_C_FMEM_DQS_CA_IN_M (SPI1_MEM_C_FMEM_DQS_CA_IN_V << SPI1_MEM_C_FMEM_DQS_CA_IN_S) +#define SPI1_MEM_C_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI1_MEM_C_FMEM_DQS_CA_IN_S 26 +/** SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_M (SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI1_MEM_C_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI1_MEM_C_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_M (SPI1_MEM_C_FMEM_CLK_DIFF_INV_V << SPI1_MEM_C_FMEM_CLK_DIFF_INV_S) +#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_S 28 +/** SPI1_MEM_C_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_M (SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S) +#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI1_MEM_C_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI1_MEM_C_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI1_MEM_C_FMEM_HYPERBUS_CA_M (SPI1_MEM_C_FMEM_HYPERBUS_CA_V << SPI1_MEM_C_FMEM_HYPERBUS_CA_S) +#define SPI1_MEM_C_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI1_MEM_C_FMEM_HYPERBUS_CA_S 30 + +/** SPI1_MEM_C_TIMING_CALI_REG register + * SPI1 timing control register + */ +#define SPI1_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI1_BASE + 0x180) +/** SPI1_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI1_MEM_C_TIMING_CALI (BIT(1)) +#define SPI1_MEM_C_TIMING_CALI_M (SPI1_MEM_C_TIMING_CALI_V << SPI1_MEM_C_TIMING_CALI_S) +#define SPI1_MEM_C_TIMING_CALI_V 0x00000001U +#define SPI1_MEM_C_TIMING_CALI_S 1 +/** SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_M (SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S) +#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S 2 + +/** SPI1_MEM_C_CLOCK_GATE_REG register + * SPI1 clk_gate register + */ +#define SPI1_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI1_BASE + 0x200) +/** SPI1_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI1_MEM_C_CLK_EN (BIT(0)) +#define SPI1_MEM_C_CLK_EN_M (SPI1_MEM_C_CLK_EN_V << SPI1_MEM_C_CLK_EN_S) +#define SPI1_MEM_C_CLK_EN_V 0x00000001U +#define SPI1_MEM_C_CLK_EN_S 0 + +/** SPI1_MEM_C_DATE_REG register + * Version control register + */ +#define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc) +/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ +#define SPI1_MEM_C_DATE 0x0FFFFFFFU +#define SPI1_MEM_C_DATE_M (SPI1_MEM_C_DATE_V << SPI1_MEM_C_DATE_S) +#define SPI1_MEM_C_DATE_V 0x0FFFFFFFU +#define SPI1_MEM_C_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_struct.h new file mode 100644 index 0000000000..52941e2d36 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_c_struct.h @@ -0,0 +1,1042 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * SPI1 memory command register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:9; + /** flash_pe : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ + uint32_t flash_pe:1; + /** usr : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t usr:1; + /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t flash_hpm:1; + /** flash_res : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ + uint32_t flash_res:1; + /** flash_dp : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_dp:1; + /** flash_ce : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_ce:1; + /** flash_be : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_be:1; + /** flash_se : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_se:1; + /** flash_pp : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ + uint32_t flash_pp:1; + /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_wrsr:1; + /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_rdsr:1; + /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_rdid:1; + /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wrdi:1; + /** flash_wren : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wren:1; + /** flash_read : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_read:1; + }; + uint32_t val; +} spi1_mem_c_cmd_reg_t; + +/** Type of addr register + * SPI1 address register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi1_mem_c_addr_reg_t; + +/** Type of user register + * SPI1 user register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + uint32_t fwrite_quad:1; + /** fwrite_dio : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ + uint32_t fwrite_dio:1; + /** fwrite_qio : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ + uint32_t fwrite_qio:1; + uint32_t reserved_16:8; + /** usr_miso_highpart : HRO; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * enable 0: disable. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * enable 0: disable. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi1_mem_c_user_reg_t; + +/** Type of user1 register + * SPI1 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + uint32_t reserved_6:20; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi1_mem_c_user1_reg_t; + +/** Type of user2 register + * SPI1 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi1_mem_c_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI1 control register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + /** fcs_crc_en : HRO; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ + uint32_t fcs_crc_en:1; + /** tx_crc_en : HRO; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ + uint32_t tx_crc_en:1; + uint32_t reserved_12:1; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout + * and spi1_mem_c_fread_dout. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + /** resandres : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with + * spi1_mem_c_flash_res bit. 1: enable 0: disable. + */ + uint32_t resandres:1; + uint32_t reserved_16:2; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + /** wrsr_2b : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ + uint32_t wrsr_2b:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi1_mem_c_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI1 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t clk_mode:2; + /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_res:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi1_mem_c_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI1 control2 register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi1_mem_c_ctrl2_reg_t; + +/** Type of clock register + * SPI1 clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is + * system/(spi1_mem_c_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi1_mem_c_clock_reg_t; + +/** Type of mosi_dlen register + * SPI1 send data bit length control register. + */ +typedef union { + struct { + /** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + uint32_t usr_mosi_bit_len:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_c_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * SPI1 receive data bit length control register. + */ +typedef union { + struct { + /** usr_miso_bit_len : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + uint32_t usr_miso_bit_len:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_c_miso_dlen_reg_t; + +/** Type of rd_status register + * SPI1 status register. + */ +typedef union { + struct { + /** status : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + */ + uint32_t status:16; + /** wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + */ + uint32_t wb_mode:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi1_mem_c_rd_status_reg_t; + +/** Type of misc register + * SPI1 misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs1_dis:1; + uint32_t reserved_2:7; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_c_misc_reg_t; + +/** Type of cache_fctrl register + * SPI1 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ + uint32_t cache_usr_addr_4byte:1; + uint32_t reserved_2:1; + /** fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi1_mem_c_fread_dio. + */ + uint32_t fdin_dual:1; + /** fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_dio. + */ + uint32_t fdout_dual:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_dio. + */ + uint32_t faddr_dual:1; + /** fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ + uint32_t fdin_quad:1; + /** fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ + uint32_t fdout_quad:1; + /** faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_c_fread_qio. + */ + uint32_t faddr_quad:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi1_mem_c_cache_fctrl_reg_t; + +/** Type of flash_waiti_ctrl register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_en : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ + uint32_t waiti_en:1; + /** waiti_dummy : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ + uint32_t waiti_dummy:1; + /** waiti_addr_en : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ + uint32_t waiti_addr_en:1; + /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + */ + uint32_t waiti_addr_cyclelen:2; + uint32_t reserved_5:4; + /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ + uint32_t waiti_cmd_2b:1; + /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ + uint32_t waiti_dummy_cyclelen:6; + /** waiti_cmd : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ + uint32_t waiti_cmd:16; + }; + uint32_t val; +} spi1_mem_c_flash_waiti_ctrl_reg_t; + +/** Type of flash_sus_ctrl register + * SPI1 flash suspend control register + */ +typedef union { + struct { + /** flash_per : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_per:1; + /** flash_pes : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_pes:1; + /** flash_per_wait_en : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ + uint32_t flash_per_wait_en:1; + /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ + uint32_t flash_pes_wait_en:1; + /** pes_per_en : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ + uint32_t pes_per_en:1; + /** flash_pes_en : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ + uint32_t flash_pes_en:1; + /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0]. + */ + uint32_t pesr_end_msk:16; + /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ + uint32_t fmem_rd_sus_2b:1; + /** per_end_en : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ + uint32_t per_end_en:1; + /** pes_end_en : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ + uint32_t pes_end_en:1; + /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ + uint32_t sus_timeout_cnt:7; + }; + uint32_t val; +} spi1_mem_c_flash_sus_ctrl_reg_t; + +/** Type of flash_sus_cmd register + * SPI1 flash suspend command register + */ +typedef union { + struct { + /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ + uint32_t flash_pes_command:16; + /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ + uint32_t wait_pesr_command:16; + }; + uint32_t val; +} spi1_mem_c_flash_sus_cmd_reg_t; + +/** Type of sus_status register + * SPI1 flash suspend status register + */ +typedef union { + struct { + /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ + uint32_t flash_sus:1; + /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ + uint32_t wait_pesr_cmd_2b:1; + /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ + uint32_t flash_hpm_dly_128:1; + /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ + uint32_t flash_res_dly_128:1; + /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ + uint32_t flash_dp_dly_128:1; + /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ + uint32_t flash_per_dly_128:1; + /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ + uint32_t flash_pes_dly_128:1; + /** spi0_lock_en : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ + uint32_t spi0_lock_en:1; + uint32_t reserved_8:7; + /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ + uint32_t flash_pesr_cmd_2b:1; + /** flash_per_command : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ + uint32_t flash_per_command:16; + }; + uint32_t val; +} spi1_mem_c_sus_status_reg_t; + +/** Type of ddr register + * SPI1 DDR control register + */ +typedef union { + struct { + /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + uint32_t reserved_12:2; + /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi1_mem_c_ddr_reg_t; + +/** Type of clock_gate register + * SPI1 clk_gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi1_mem_c_clock_gate_reg_t; + + +/** Group: Status register */ +/** Type of tx_crc register + * SPI1 TX CRC data register. + */ +typedef union { + struct { + /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ + uint32_t tx_crc_data:32; + }; + uint32_t val; +} spi1_mem_c_tx_crc_reg_t; + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI1 interrupt enable register + */ +typedef union { + struct { + /** per_end_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_C_PER_END_INT interrupt. + */ + uint32_t per_end_int_ena:1; + /** pes_end_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_C_PES_END_INT interrupt. + */ + uint32_t pes_end_int_ena:1; + /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_ena:1; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + uint32_t reserved_5:5; + /** brown_out_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_ena:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_c_int_ena_reg_t; + +/** Type of int_clr register + * SPI1 interrupt clear register + */ +typedef union { + struct { + /** per_end_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_C_PER_END_INT interrupt. + */ + uint32_t per_end_int_clr:1; + /** pes_end_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_C_PES_END_INT interrupt. + */ + uint32_t pes_end_int_clr:1; + /** wpe_end_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_clr:1; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + uint32_t reserved_5:5; + /** brown_out_int_clr : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_clr:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_c_int_clr_reg_t; + +/** Type of int_raw register + * SPI1 interrupt raw register + */ +typedef union { + struct { + /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ + uint32_t per_end_int_raw:1; + /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ + uint32_t pes_end_int_raw:1; + /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ + uint32_t wpe_end_int_raw:1; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + uint32_t reserved_5:5; + /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is losing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ + uint32_t brown_out_int_raw:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_c_int_raw_reg_t; + +/** Type of int_st register + * SPI1 interrupt status register + */ +typedef union { + struct { + /** per_end_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_C_PER_END_INT interrupt. + */ + uint32_t per_end_int_st:1; + /** pes_end_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_C_PES_END_INT interrupt. + */ + uint32_t pes_end_int_st:1; + /** wpe_end_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_C_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_st:1; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + uint32_t reserved_5:5; + /** brown_out_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_st:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_c_int_st_reg_t; + + +/** Group: Timing registers */ +/** Type of timing_cali register + * SPI1 timing control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi1_mem_c_timing_cali_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi1_mem_c_date_reg_t; + + +typedef struct spi1_mem_c_dev_s { + volatile spi1_mem_c_cmd_reg_t cmd; + volatile uint32_t addr; + volatile spi1_mem_c_ctrl_reg_t ctrl; + volatile spi1_mem_c_ctrl1_reg_t ctrl1; + volatile spi1_mem_c_ctrl2_reg_t ctrl2; + volatile spi1_mem_c_clock_reg_t clock; + volatile spi1_mem_c_user_reg_t user; + volatile spi1_mem_c_user1_reg_t user1; + volatile spi1_mem_c_user2_reg_t user2; + volatile spi1_mem_c_mosi_dlen_reg_t mosi_dlen; + volatile spi1_mem_c_miso_dlen_reg_t miso_dlen; + volatile spi1_mem_c_rd_status_reg_t rd_status; + uint32_t reserved_030; + volatile spi1_mem_c_misc_reg_t misc; + volatile spi1_mem_c_tx_crc_reg_t tx_crc; + volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl; + uint32_t reserved_040[6]; + volatile uint32_t data_buf[16]; + volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl; + volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl; + volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd; + volatile spi1_mem_c_sus_status_reg_t sus_status; + uint32_t reserved_0a8[6]; + volatile spi1_mem_c_int_ena_reg_t int_ena; + volatile spi1_mem_c_int_clr_reg_t int_clr; + volatile spi1_mem_c_int_raw_reg_t int_raw; + volatile spi1_mem_c_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi1_mem_c_ddr_reg_t ddr; + uint32_t reserved_0d8[42]; + volatile spi1_mem_c_timing_cali_reg_t timing_cali; + uint32_t reserved_184[31]; + volatile spi1_mem_c_clock_gate_reg_t clock_gate; + uint32_t reserved_204[126]; + volatile spi1_mem_c_date_reg_t date; +} spi1_mem_c_dev_t; + +#ifndef __cplusplus +_Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_reg.h new file mode 100644 index 0000000000..22df90ee72 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_reg.h @@ -0,0 +1,1481 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI1_MEM_S_CMD_REG register + * SPI1 memory command register + */ +#define SPI1_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0) +/** SPI1_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ +#define SPI1_MEM_S_MST_ST 0x0000000FU +#define SPI1_MEM_S_MST_ST_M (SPI1_MEM_S_MST_ST_V << SPI1_MEM_S_MST_ST_S) +#define SPI1_MEM_S_MST_ST_V 0x0000000FU +#define SPI1_MEM_S_MST_ST_S 0 +/** SPI1_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI1_MEM_S_SLV_ST 0x0000000FU +#define SPI1_MEM_S_SLV_ST_M (SPI1_MEM_S_SLV_ST_V << SPI1_MEM_S_SLV_ST_S) +#define SPI1_MEM_S_SLV_ST_V 0x0000000FU +#define SPI1_MEM_S_SLV_ST_S 4 +/** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_PE (BIT(17)) +#define SPI1_MEM_S_FLASH_PE_M (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S) +#define SPI1_MEM_S_FLASH_PE_V 0x00000001U +#define SPI1_MEM_S_FLASH_PE_S 17 +/** SPI1_MEM_S_USR : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_USR (BIT(18)) +#define SPI1_MEM_S_USR_M (SPI1_MEM_S_USR_V << SPI1_MEM_S_USR_S) +#define SPI1_MEM_S_USR_V 0x00000001U +#define SPI1_MEM_S_USR_S 18 +/** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_HPM (BIT(19)) +#define SPI1_MEM_S_FLASH_HPM_M (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S) +#define SPI1_MEM_S_FLASH_HPM_V 0x00000001U +#define SPI1_MEM_S_FLASH_HPM_S 19 +/** SPI1_MEM_S_FLASH_RES : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_RES (BIT(20)) +#define SPI1_MEM_S_FLASH_RES_M (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S) +#define SPI1_MEM_S_FLASH_RES_V 0x00000001U +#define SPI1_MEM_S_FLASH_RES_S 20 +/** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_DP (BIT(21)) +#define SPI1_MEM_S_FLASH_DP_M (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S) +#define SPI1_MEM_S_FLASH_DP_V 0x00000001U +#define SPI1_MEM_S_FLASH_DP_S 21 +/** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_CE (BIT(22)) +#define SPI1_MEM_S_FLASH_CE_M (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S) +#define SPI1_MEM_S_FLASH_CE_V 0x00000001U +#define SPI1_MEM_S_FLASH_CE_S 22 +/** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_BE (BIT(23)) +#define SPI1_MEM_S_FLASH_BE_M (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S) +#define SPI1_MEM_S_FLASH_BE_V 0x00000001U +#define SPI1_MEM_S_FLASH_BE_S 23 +/** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_SE (BIT(24)) +#define SPI1_MEM_S_FLASH_SE_M (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S) +#define SPI1_MEM_S_FLASH_SE_V 0x00000001U +#define SPI1_MEM_S_FLASH_SE_S 24 +/** SPI1_MEM_S_FLASH_PP : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_PP (BIT(25)) +#define SPI1_MEM_S_FLASH_PP_M (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S) +#define SPI1_MEM_S_FLASH_PP_V 0x00000001U +#define SPI1_MEM_S_FLASH_PP_S 25 +/** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_WRSR (BIT(26)) +#define SPI1_MEM_S_FLASH_WRSR_M (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S) +#define SPI1_MEM_S_FLASH_WRSR_V 0x00000001U +#define SPI1_MEM_S_FLASH_WRSR_S 26 +/** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_RDSR (BIT(27)) +#define SPI1_MEM_S_FLASH_RDSR_M (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S) +#define SPI1_MEM_S_FLASH_RDSR_V 0x00000001U +#define SPI1_MEM_S_FLASH_RDSR_S 27 +/** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_RDID (BIT(28)) +#define SPI1_MEM_S_FLASH_RDID_M (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S) +#define SPI1_MEM_S_FLASH_RDID_V 0x00000001U +#define SPI1_MEM_S_FLASH_RDID_S 28 +/** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_WRDI (BIT(29)) +#define SPI1_MEM_S_FLASH_WRDI_M (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S) +#define SPI1_MEM_S_FLASH_WRDI_V 0x00000001U +#define SPI1_MEM_S_FLASH_WRDI_S 29 +/** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_WREN (BIT(30)) +#define SPI1_MEM_S_FLASH_WREN_M (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S) +#define SPI1_MEM_S_FLASH_WREN_V 0x00000001U +#define SPI1_MEM_S_FLASH_WREN_S 30 +/** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FLASH_READ (BIT(31)) +#define SPI1_MEM_S_FLASH_READ_M (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S) +#define SPI1_MEM_S_FLASH_READ_V 0x00000001U +#define SPI1_MEM_S_FLASH_READ_S 31 + +/** SPI1_MEM_S_ADDR_REG register + * SPI1 address register + */ +#define SPI1_MEM_S_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4) +/** SPI1_MEM_S_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ +#define SPI1_MEM_S_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI1_MEM_S_USR_ADDR_VALUE_M (SPI1_MEM_S_USR_ADDR_VALUE_V << SPI1_MEM_S_USR_ADDR_VALUE_S) +#define SPI1_MEM_S_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI1_MEM_S_USR_ADDR_VALUE_S 0 + +/** SPI1_MEM_S_CTRL_REG register + * SPI1 control register. + */ +#define SPI1_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8) +/** SPI1_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_S_FDUMMY_RIN (BIT(2)) +#define SPI1_MEM_S_FDUMMY_RIN_M (SPI1_MEM_S_FDUMMY_RIN_V << SPI1_MEM_S_FDUMMY_RIN_S) +#define SPI1_MEM_S_FDUMMY_RIN_V 0x00000001U +#define SPI1_MEM_S_FDUMMY_RIN_S 2 +/** SPI1_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_S_FDUMMY_WOUT (BIT(3)) +#define SPI1_MEM_S_FDUMMY_WOUT_M (SPI1_MEM_S_FDUMMY_WOUT_V << SPI1_MEM_S_FDUMMY_WOUT_S) +#define SPI1_MEM_S_FDUMMY_WOUT_V 0x00000001U +#define SPI1_MEM_S_FDUMMY_WOUT_S 3 +/** SPI1_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI1_MEM_S_FDOUT_OCT (BIT(4)) +#define SPI1_MEM_S_FDOUT_OCT_M (SPI1_MEM_S_FDOUT_OCT_V << SPI1_MEM_S_FDOUT_OCT_S) +#define SPI1_MEM_S_FDOUT_OCT_V 0x00000001U +#define SPI1_MEM_S_FDOUT_OCT_S 4 +/** SPI1_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI1_MEM_S_FDIN_OCT (BIT(5)) +#define SPI1_MEM_S_FDIN_OCT_M (SPI1_MEM_S_FDIN_OCT_V << SPI1_MEM_S_FDIN_OCT_S) +#define SPI1_MEM_S_FDIN_OCT_V 0x00000001U +#define SPI1_MEM_S_FDIN_OCT_S 5 +/** SPI1_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI1_MEM_S_FADDR_OCT (BIT(6)) +#define SPI1_MEM_S_FADDR_OCT_M (SPI1_MEM_S_FADDR_OCT_V << SPI1_MEM_S_FADDR_OCT_S) +#define SPI1_MEM_S_FADDR_OCT_V 0x00000001U +#define SPI1_MEM_S_FADDR_OCT_S 6 +/** SPI1_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_S_FCMD_QUAD (BIT(8)) +#define SPI1_MEM_S_FCMD_QUAD_M (SPI1_MEM_S_FCMD_QUAD_V << SPI1_MEM_S_FCMD_QUAD_S) +#define SPI1_MEM_S_FCMD_QUAD_V 0x00000001U +#define SPI1_MEM_S_FCMD_QUAD_S 8 +/** SPI1_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_S_FCMD_OCT (BIT(9)) +#define SPI1_MEM_S_FCMD_OCT_M (SPI1_MEM_S_FCMD_OCT_V << SPI1_MEM_S_FCMD_OCT_S) +#define SPI1_MEM_S_FCMD_OCT_V 0x00000001U +#define SPI1_MEM_S_FCMD_OCT_S 9 +/** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ +#define SPI1_MEM_S_FCS_CRC_EN (BIT(10)) +#define SPI1_MEM_S_FCS_CRC_EN_M (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S) +#define SPI1_MEM_S_FCS_CRC_EN_V 0x00000001U +#define SPI1_MEM_S_FCS_CRC_EN_S 10 +/** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ +#define SPI1_MEM_S_TX_CRC_EN (BIT(11)) +#define SPI1_MEM_S_TX_CRC_EN_M (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S) +#define SPI1_MEM_S_TX_CRC_EN_V 0x00000001U +#define SPI1_MEM_S_TX_CRC_EN_S 11 +/** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout + * and spi1_mem_s_fread_dout. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FASTRD_MODE (BIT(13)) +#define SPI1_MEM_S_FASTRD_MODE_M (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S) +#define SPI1_MEM_S_FASTRD_MODE_V 0x00000001U +#define SPI1_MEM_S_FASTRD_MODE_S 13 +/** SPI1_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FREAD_DUAL (BIT(14)) +#define SPI1_MEM_S_FREAD_DUAL_M (SPI1_MEM_S_FREAD_DUAL_V << SPI1_MEM_S_FREAD_DUAL_S) +#define SPI1_MEM_S_FREAD_DUAL_V 0x00000001U +#define SPI1_MEM_S_FREAD_DUAL_S 14 +/** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with + * spi1_mem_s_flash_res bit. 1: enable 0: disable. + */ +#define SPI1_MEM_S_RESANDRES (BIT(15)) +#define SPI1_MEM_S_RESANDRES_M (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S) +#define SPI1_MEM_S_RESANDRES_V 0x00000001U +#define SPI1_MEM_S_RESANDRES_S 15 +/** SPI1_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI1_MEM_S_Q_POL (BIT(18)) +#define SPI1_MEM_S_Q_POL_M (SPI1_MEM_S_Q_POL_V << SPI1_MEM_S_Q_POL_S) +#define SPI1_MEM_S_Q_POL_V 0x00000001U +#define SPI1_MEM_S_Q_POL_S 18 +/** SPI1_MEM_S_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI1_MEM_S_D_POL (BIT(19)) +#define SPI1_MEM_S_D_POL_M (SPI1_MEM_S_D_POL_V << SPI1_MEM_S_D_POL_S) +#define SPI1_MEM_S_D_POL_V 0x00000001U +#define SPI1_MEM_S_D_POL_S 19 +/** SPI1_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_S_FREAD_QUAD (BIT(20)) +#define SPI1_MEM_S_FREAD_QUAD_M (SPI1_MEM_S_FREAD_QUAD_V << SPI1_MEM_S_FREAD_QUAD_S) +#define SPI1_MEM_S_FREAD_QUAD_V 0x00000001U +#define SPI1_MEM_S_FREAD_QUAD_S 20 +/** SPI1_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI1_MEM_S_WP_REG (BIT(21)) +#define SPI1_MEM_S_WP_REG_M (SPI1_MEM_S_WP_REG_V << SPI1_MEM_S_WP_REG_S) +#define SPI1_MEM_S_WP_REG_V 0x00000001U +#define SPI1_MEM_S_WP_REG_S 21 +/** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ +#define SPI1_MEM_S_WRSR_2B (BIT(22)) +#define SPI1_MEM_S_WRSR_2B_M (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S) +#define SPI1_MEM_S_WRSR_2B_V 0x00000001U +#define SPI1_MEM_S_WRSR_2B_S 22 +/** SPI1_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_S_FREAD_DIO (BIT(23)) +#define SPI1_MEM_S_FREAD_DIO_M (SPI1_MEM_S_FREAD_DIO_V << SPI1_MEM_S_FREAD_DIO_S) +#define SPI1_MEM_S_FREAD_DIO_V 0x00000001U +#define SPI1_MEM_S_FREAD_DIO_S 23 +/** SPI1_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_S_FREAD_QIO (BIT(24)) +#define SPI1_MEM_S_FREAD_QIO_M (SPI1_MEM_S_FREAD_QIO_V << SPI1_MEM_S_FREAD_QIO_S) +#define SPI1_MEM_S_FREAD_QIO_V 0x00000001U +#define SPI1_MEM_S_FREAD_QIO_S 24 + +/** SPI1_MEM_S_CTRL1_REG register + * SPI1 control1 register. + */ +#define SPI1_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc) +/** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI1_MEM_S_CLK_MODE 0x00000003U +#define SPI1_MEM_S_CLK_MODE_M (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S) +#define SPI1_MEM_S_CLK_MODE_V 0x00000003U +#define SPI1_MEM_S_CLK_MODE_S 0 +/** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ +#define SPI1_MEM_S_CS_HOLD_DLY_RES 0x000003FFU +#define SPI1_MEM_S_CS_HOLD_DLY_RES_M (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S) +#define SPI1_MEM_S_CS_HOLD_DLY_RES_V 0x000003FFU +#define SPI1_MEM_S_CS_HOLD_DLY_RES_S 2 + +/** SPI1_MEM_S_CTRL2_REG register + * SPI1 control2 register. + */ +#define SPI1_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10) +/** SPI1_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ +#define SPI1_MEM_S_SYNC_RESET (BIT(31)) +#define SPI1_MEM_S_SYNC_RESET_M (SPI1_MEM_S_SYNC_RESET_V << SPI1_MEM_S_SYNC_RESET_S) +#define SPI1_MEM_S_SYNC_RESET_V 0x00000001U +#define SPI1_MEM_S_SYNC_RESET_S 31 + +/** SPI1_MEM_S_CLOCK_REG register + * SPI1 clock division control register. + */ +#define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14) +/** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + */ +#define SPI1_MEM_S_CLKCNT_L 0x000000FFU +#define SPI1_MEM_S_CLKCNT_L_M (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S) +#define SPI1_MEM_S_CLKCNT_L_V 0x000000FFU +#define SPI1_MEM_S_CLKCNT_L_S 0 +/** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + */ +#define SPI1_MEM_S_CLKCNT_H 0x000000FFU +#define SPI1_MEM_S_CLKCNT_H_M (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S) +#define SPI1_MEM_S_CLKCNT_H_V 0x000000FFU +#define SPI1_MEM_S_CLKCNT_H_S 8 +/** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is + * system/(spi1_mem_s_clkcnt_N+1) + */ +#define SPI1_MEM_S_CLKCNT_N 0x000000FFU +#define SPI1_MEM_S_CLKCNT_N_M (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S) +#define SPI1_MEM_S_CLKCNT_N_V 0x000000FFU +#define SPI1_MEM_S_CLKCNT_N_S 16 +/** SPI1_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SPI1_MEM_S_CLK_EQU_SYSCLK (BIT(31)) +#define SPI1_MEM_S_CLK_EQU_SYSCLK_M (SPI1_MEM_S_CLK_EQU_SYSCLK_V << SPI1_MEM_S_CLK_EQU_SYSCLK_S) +#define SPI1_MEM_S_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI1_MEM_S_CLK_EQU_SYSCLK_S 31 + +/** SPI1_MEM_S_USER_REG register + * SPI1 user register. + */ +#define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18) +/** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + */ +#define SPI1_MEM_S_CK_OUT_EDGE (BIT(9)) +#define SPI1_MEM_S_CK_OUT_EDGE_M (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S) +#define SPI1_MEM_S_CK_OUT_EDGE_V 0x00000001U +#define SPI1_MEM_S_CK_OUT_EDGE_S 9 +/** SPI1_MEM_S_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ +#define SPI1_MEM_S_FWRITE_DUAL (BIT(12)) +#define SPI1_MEM_S_FWRITE_DUAL_M (SPI1_MEM_S_FWRITE_DUAL_V << SPI1_MEM_S_FWRITE_DUAL_S) +#define SPI1_MEM_S_FWRITE_DUAL_V 0x00000001U +#define SPI1_MEM_S_FWRITE_DUAL_S 12 +/** SPI1_MEM_S_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ +#define SPI1_MEM_S_FWRITE_QUAD (BIT(13)) +#define SPI1_MEM_S_FWRITE_QUAD_M (SPI1_MEM_S_FWRITE_QUAD_V << SPI1_MEM_S_FWRITE_QUAD_S) +#define SPI1_MEM_S_FWRITE_QUAD_V 0x00000001U +#define SPI1_MEM_S_FWRITE_QUAD_S 13 +/** SPI1_MEM_S_FWRITE_DIO : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ +#define SPI1_MEM_S_FWRITE_DIO (BIT(14)) +#define SPI1_MEM_S_FWRITE_DIO_M (SPI1_MEM_S_FWRITE_DIO_V << SPI1_MEM_S_FWRITE_DIO_S) +#define SPI1_MEM_S_FWRITE_DIO_V 0x00000001U +#define SPI1_MEM_S_FWRITE_DIO_S 14 +/** SPI1_MEM_S_FWRITE_QIO : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ +#define SPI1_MEM_S_FWRITE_QIO (BIT(15)) +#define SPI1_MEM_S_FWRITE_QIO_M (SPI1_MEM_S_FWRITE_QIO_V << SPI1_MEM_S_FWRITE_QIO_S) +#define SPI1_MEM_S_FWRITE_QIO_V 0x00000001U +#define SPI1_MEM_S_FWRITE_QIO_S 15 +/** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * enable 0: disable. + */ +#define SPI1_MEM_S_USR_MISO_HIGHPART (BIT(24)) +#define SPI1_MEM_S_USR_MISO_HIGHPART_M (SPI1_MEM_S_USR_MISO_HIGHPART_V << SPI1_MEM_S_USR_MISO_HIGHPART_S) +#define SPI1_MEM_S_USR_MISO_HIGHPART_V 0x00000001U +#define SPI1_MEM_S_USR_MISO_HIGHPART_S 24 +/** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * enable 0: disable. + */ +#define SPI1_MEM_S_USR_MOSI_HIGHPART (BIT(25)) +#define SPI1_MEM_S_USR_MOSI_HIGHPART_M (SPI1_MEM_S_USR_MOSI_HIGHPART_V << SPI1_MEM_S_USR_MOSI_HIGHPART_S) +#define SPI1_MEM_S_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI1_MEM_S_USR_MOSI_HIGHPART_S 25 +/** SPI1_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ +#define SPI1_MEM_S_USR_DUMMY_IDLE (BIT(26)) +#define SPI1_MEM_S_USR_DUMMY_IDLE_M (SPI1_MEM_S_USR_DUMMY_IDLE_V << SPI1_MEM_S_USR_DUMMY_IDLE_S) +#define SPI1_MEM_S_USR_DUMMY_IDLE_V 0x00000001U +#define SPI1_MEM_S_USR_DUMMY_IDLE_S 26 +/** SPI1_MEM_S_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ +#define SPI1_MEM_S_USR_MOSI (BIT(27)) +#define SPI1_MEM_S_USR_MOSI_M (SPI1_MEM_S_USR_MOSI_V << SPI1_MEM_S_USR_MOSI_S) +#define SPI1_MEM_S_USR_MOSI_V 0x00000001U +#define SPI1_MEM_S_USR_MOSI_S 27 +/** SPI1_MEM_S_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ +#define SPI1_MEM_S_USR_MISO (BIT(28)) +#define SPI1_MEM_S_USR_MISO_M (SPI1_MEM_S_USR_MISO_V << SPI1_MEM_S_USR_MISO_S) +#define SPI1_MEM_S_USR_MISO_V 0x00000001U +#define SPI1_MEM_S_USR_MISO_S 28 +/** SPI1_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI1_MEM_S_USR_DUMMY (BIT(29)) +#define SPI1_MEM_S_USR_DUMMY_M (SPI1_MEM_S_USR_DUMMY_V << SPI1_MEM_S_USR_DUMMY_S) +#define SPI1_MEM_S_USR_DUMMY_V 0x00000001U +#define SPI1_MEM_S_USR_DUMMY_S 29 +/** SPI1_MEM_S_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ +#define SPI1_MEM_S_USR_ADDR (BIT(30)) +#define SPI1_MEM_S_USR_ADDR_M (SPI1_MEM_S_USR_ADDR_V << SPI1_MEM_S_USR_ADDR_S) +#define SPI1_MEM_S_USR_ADDR_V 0x00000001U +#define SPI1_MEM_S_USR_ADDR_S 30 +/** SPI1_MEM_S_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ +#define SPI1_MEM_S_USR_COMMAND (BIT(31)) +#define SPI1_MEM_S_USR_COMMAND_M (SPI1_MEM_S_USR_COMMAND_V << SPI1_MEM_S_USR_COMMAND_S) +#define SPI1_MEM_S_USR_COMMAND_V 0x00000001U +#define SPI1_MEM_S_USR_COMMAND_S 31 + +/** SPI1_MEM_S_USER1_REG register + * SPI1 user1 register. + */ +#define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c) +/** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI1_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_M (SPI1_MEM_S_USR_DUMMY_CYCLELEN_V << SPI1_MEM_S_USR_DUMMY_CYCLELEN_S) +#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_S 0 +/** SPI1_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_S_USR_ADDR_BITLEN 0x0000003FU +#define SPI1_MEM_S_USR_ADDR_BITLEN_M (SPI1_MEM_S_USR_ADDR_BITLEN_V << SPI1_MEM_S_USR_ADDR_BITLEN_S) +#define SPI1_MEM_S_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI1_MEM_S_USR_ADDR_BITLEN_S 26 + +/** SPI1_MEM_S_USER2_REG register + * SPI1 user2 register. + */ +#define SPI1_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20) +/** SPI1_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI1_MEM_S_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI1_MEM_S_USR_COMMAND_VALUE_M (SPI1_MEM_S_USR_COMMAND_VALUE_V << SPI1_MEM_S_USR_COMMAND_VALUE_S) +#define SPI1_MEM_S_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI1_MEM_S_USR_COMMAND_VALUE_S 0 +/** SPI1_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI1_MEM_S_USR_COMMAND_BITLEN 0x0000000FU +#define SPI1_MEM_S_USR_COMMAND_BITLEN_M (SPI1_MEM_S_USR_COMMAND_BITLEN_V << SPI1_MEM_S_USR_COMMAND_BITLEN_S) +#define SPI1_MEM_S_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI1_MEM_S_USR_COMMAND_BITLEN_S 28 + +/** SPI1_MEM_S_MOSI_DLEN_REG register + * SPI1 send data bit length control register. + */ +#define SPI1_MEM_S_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24) +/** SPI1_MEM_S_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_S_USR_MOSI_DBITLEN 0x000003FFU +#define SPI1_MEM_S_USR_MOSI_DBITLEN_M (SPI1_MEM_S_USR_MOSI_DBITLEN_V << SPI1_MEM_S_USR_MOSI_DBITLEN_S) +#define SPI1_MEM_S_USR_MOSI_DBITLEN_V 0x000003FFU +#define SPI1_MEM_S_USR_MOSI_DBITLEN_S 0 + +/** SPI1_MEM_S_MISO_DLEN_REG register + * SPI1 receive data bit length control register. + */ +#define SPI1_MEM_S_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28) +/** SPI1_MEM_S_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_S_USR_MISO_DBITLEN 0x000003FFU +#define SPI1_MEM_S_USR_MISO_DBITLEN_M (SPI1_MEM_S_USR_MISO_DBITLEN_V << SPI1_MEM_S_USR_MISO_DBITLEN_S) +#define SPI1_MEM_S_USR_MISO_DBITLEN_V 0x000003FFU +#define SPI1_MEM_S_USR_MISO_DBITLEN_S 0 + +/** SPI1_MEM_S_RD_STATUS_REG register + * SPI1 status register. + */ +#define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c) +/** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + */ +#define SPI1_MEM_S_STATUS 0x0000FFFFU +#define SPI1_MEM_S_STATUS_M (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S) +#define SPI1_MEM_S_STATUS_V 0x0000FFFFU +#define SPI1_MEM_S_STATUS_S 0 +/** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + */ +#define SPI1_MEM_S_WB_MODE 0x000000FFU +#define SPI1_MEM_S_WB_MODE_M (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S) +#define SPI1_MEM_S_WB_MODE_V 0x000000FFU +#define SPI1_MEM_S_WB_MODE_S 16 + +/** SPI1_MEM_S_MISC_REG register + * SPI1 misc register + */ +#define SPI1_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34) +/** SPI1_MEM_S_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_S_CS0_DIS (BIT(0)) +#define SPI1_MEM_S_CS0_DIS_M (SPI1_MEM_S_CS0_DIS_V << SPI1_MEM_S_CS0_DIS_S) +#define SPI1_MEM_S_CS0_DIS_V 0x00000001U +#define SPI1_MEM_S_CS0_DIS_S 0 +/** SPI1_MEM_S_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_S_CS1_DIS (BIT(1)) +#define SPI1_MEM_S_CS1_DIS_M (SPI1_MEM_S_CS1_DIS_V << SPI1_MEM_S_CS1_DIS_S) +#define SPI1_MEM_S_CS1_DIS_V 0x00000001U +#define SPI1_MEM_S_CS1_DIS_S 1 +/** SPI1_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ +#define SPI1_MEM_S_CK_IDLE_EDGE (BIT(9)) +#define SPI1_MEM_S_CK_IDLE_EDGE_M (SPI1_MEM_S_CK_IDLE_EDGE_V << SPI1_MEM_S_CK_IDLE_EDGE_S) +#define SPI1_MEM_S_CK_IDLE_EDGE_V 0x00000001U +#define SPI1_MEM_S_CK_IDLE_EDGE_S 9 +/** SPI1_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ +#define SPI1_MEM_S_CS_KEEP_ACTIVE (BIT(10)) +#define SPI1_MEM_S_CS_KEEP_ACTIVE_M (SPI1_MEM_S_CS_KEEP_ACTIVE_V << SPI1_MEM_S_CS_KEEP_ACTIVE_S) +#define SPI1_MEM_S_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI1_MEM_S_CS_KEEP_ACTIVE_S 10 + +/** SPI1_MEM_S_TX_CRC_REG register + * SPI1 TX CRC data register. + */ +#define SPI1_MEM_S_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38) +/** SPI1_MEM_S_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ +#define SPI1_MEM_S_TX_CRC_DATA 0xFFFFFFFFU +#define SPI1_MEM_S_TX_CRC_DATA_M (SPI1_MEM_S_TX_CRC_DATA_V << SPI1_MEM_S_TX_CRC_DATA_S) +#define SPI1_MEM_S_TX_CRC_DATA_V 0xFFFFFFFFU +#define SPI1_MEM_S_TX_CRC_DATA_S 0 + +/** SPI1_MEM_S_CACHE_FCTRL_REG register + * SPI1 bit mode control register. + */ +#define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c) +/** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ +#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S) +#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi1_mem_s_fread_dio. + */ +#define SPI1_MEM_S_FDIN_DUAL (BIT(3)) +#define SPI1_MEM_S_FDIN_DUAL_M (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S) +#define SPI1_MEM_S_FDIN_DUAL_V 0x00000001U +#define SPI1_MEM_S_FDIN_DUAL_S 3 +/** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_dio. + */ +#define SPI1_MEM_S_FDOUT_DUAL (BIT(4)) +#define SPI1_MEM_S_FDOUT_DUAL_M (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S) +#define SPI1_MEM_S_FDOUT_DUAL_V 0x00000001U +#define SPI1_MEM_S_FDOUT_DUAL_S 4 +/** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_dio. + */ +#define SPI1_MEM_S_FADDR_DUAL (BIT(5)) +#define SPI1_MEM_S_FADDR_DUAL_M (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S) +#define SPI1_MEM_S_FADDR_DUAL_V 0x00000001U +#define SPI1_MEM_S_FADDR_DUAL_S 5 +/** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ +#define SPI1_MEM_S_FDIN_QUAD (BIT(6)) +#define SPI1_MEM_S_FDIN_QUAD_M (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S) +#define SPI1_MEM_S_FDIN_QUAD_V 0x00000001U +#define SPI1_MEM_S_FDIN_QUAD_S 6 +/** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ +#define SPI1_MEM_S_FDOUT_QUAD (BIT(7)) +#define SPI1_MEM_S_FDOUT_QUAD_M (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S) +#define SPI1_MEM_S_FDOUT_QUAD_V 0x00000001U +#define SPI1_MEM_S_FDOUT_QUAD_S 7 +/** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ +#define SPI1_MEM_S_FADDR_QUAD (BIT(8)) +#define SPI1_MEM_S_FADDR_QUAD_M (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S) +#define SPI1_MEM_S_FADDR_QUAD_V 0x00000001U +#define SPI1_MEM_S_FADDR_QUAD_S 8 + +/** SPI1_MEM_S_W0_REG register + * SPI1 memory data buffer0 + */ +#define SPI1_MEM_S_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58) +/** SPI1_MEM_S_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF0 0xFFFFFFFFU +#define SPI1_MEM_S_BUF0_M (SPI1_MEM_S_BUF0_V << SPI1_MEM_S_BUF0_S) +#define SPI1_MEM_S_BUF0_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF0_S 0 + +/** SPI1_MEM_S_W1_REG register + * SPI1 memory data buffer1 + */ +#define SPI1_MEM_S_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c) +/** SPI1_MEM_S_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF1 0xFFFFFFFFU +#define SPI1_MEM_S_BUF1_M (SPI1_MEM_S_BUF1_V << SPI1_MEM_S_BUF1_S) +#define SPI1_MEM_S_BUF1_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF1_S 0 + +/** SPI1_MEM_S_W2_REG register + * SPI1 memory data buffer2 + */ +#define SPI1_MEM_S_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60) +/** SPI1_MEM_S_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF2 0xFFFFFFFFU +#define SPI1_MEM_S_BUF2_M (SPI1_MEM_S_BUF2_V << SPI1_MEM_S_BUF2_S) +#define SPI1_MEM_S_BUF2_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF2_S 0 + +/** SPI1_MEM_S_W3_REG register + * SPI1 memory data buffer3 + */ +#define SPI1_MEM_S_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64) +/** SPI1_MEM_S_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF3 0xFFFFFFFFU +#define SPI1_MEM_S_BUF3_M (SPI1_MEM_S_BUF3_V << SPI1_MEM_S_BUF3_S) +#define SPI1_MEM_S_BUF3_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF3_S 0 + +/** SPI1_MEM_S_W4_REG register + * SPI1 memory data buffer4 + */ +#define SPI1_MEM_S_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68) +/** SPI1_MEM_S_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF4 0xFFFFFFFFU +#define SPI1_MEM_S_BUF4_M (SPI1_MEM_S_BUF4_V << SPI1_MEM_S_BUF4_S) +#define SPI1_MEM_S_BUF4_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF4_S 0 + +/** SPI1_MEM_S_W5_REG register + * SPI1 memory data buffer5 + */ +#define SPI1_MEM_S_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c) +/** SPI1_MEM_S_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF5 0xFFFFFFFFU +#define SPI1_MEM_S_BUF5_M (SPI1_MEM_S_BUF5_V << SPI1_MEM_S_BUF5_S) +#define SPI1_MEM_S_BUF5_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF5_S 0 + +/** SPI1_MEM_S_W6_REG register + * SPI1 memory data buffer6 + */ +#define SPI1_MEM_S_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70) +/** SPI1_MEM_S_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF6 0xFFFFFFFFU +#define SPI1_MEM_S_BUF6_M (SPI1_MEM_S_BUF6_V << SPI1_MEM_S_BUF6_S) +#define SPI1_MEM_S_BUF6_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF6_S 0 + +/** SPI1_MEM_S_W7_REG register + * SPI1 memory data buffer7 + */ +#define SPI1_MEM_S_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74) +/** SPI1_MEM_S_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF7 0xFFFFFFFFU +#define SPI1_MEM_S_BUF7_M (SPI1_MEM_S_BUF7_V << SPI1_MEM_S_BUF7_S) +#define SPI1_MEM_S_BUF7_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF7_S 0 + +/** SPI1_MEM_S_W8_REG register + * SPI1 memory data buffer8 + */ +#define SPI1_MEM_S_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78) +/** SPI1_MEM_S_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF8 0xFFFFFFFFU +#define SPI1_MEM_S_BUF8_M (SPI1_MEM_S_BUF8_V << SPI1_MEM_S_BUF8_S) +#define SPI1_MEM_S_BUF8_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF8_S 0 + +/** SPI1_MEM_S_W9_REG register + * SPI1 memory data buffer9 + */ +#define SPI1_MEM_S_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c) +/** SPI1_MEM_S_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF9 0xFFFFFFFFU +#define SPI1_MEM_S_BUF9_M (SPI1_MEM_S_BUF9_V << SPI1_MEM_S_BUF9_S) +#define SPI1_MEM_S_BUF9_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF9_S 0 + +/** SPI1_MEM_S_W10_REG register + * SPI1 memory data buffer10 + */ +#define SPI1_MEM_S_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80) +/** SPI1_MEM_S_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF10 0xFFFFFFFFU +#define SPI1_MEM_S_BUF10_M (SPI1_MEM_S_BUF10_V << SPI1_MEM_S_BUF10_S) +#define SPI1_MEM_S_BUF10_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF10_S 0 + +/** SPI1_MEM_S_W11_REG register + * SPI1 memory data buffer11 + */ +#define SPI1_MEM_S_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84) +/** SPI1_MEM_S_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF11 0xFFFFFFFFU +#define SPI1_MEM_S_BUF11_M (SPI1_MEM_S_BUF11_V << SPI1_MEM_S_BUF11_S) +#define SPI1_MEM_S_BUF11_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF11_S 0 + +/** SPI1_MEM_S_W12_REG register + * SPI1 memory data buffer12 + */ +#define SPI1_MEM_S_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88) +/** SPI1_MEM_S_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF12 0xFFFFFFFFU +#define SPI1_MEM_S_BUF12_M (SPI1_MEM_S_BUF12_V << SPI1_MEM_S_BUF12_S) +#define SPI1_MEM_S_BUF12_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF12_S 0 + +/** SPI1_MEM_S_W13_REG register + * SPI1 memory data buffer13 + */ +#define SPI1_MEM_S_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c) +/** SPI1_MEM_S_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF13 0xFFFFFFFFU +#define SPI1_MEM_S_BUF13_M (SPI1_MEM_S_BUF13_V << SPI1_MEM_S_BUF13_S) +#define SPI1_MEM_S_BUF13_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF13_S 0 + +/** SPI1_MEM_S_W14_REG register + * SPI1 memory data buffer14 + */ +#define SPI1_MEM_S_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90) +/** SPI1_MEM_S_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF14 0xFFFFFFFFU +#define SPI1_MEM_S_BUF14_M (SPI1_MEM_S_BUF14_V << SPI1_MEM_S_BUF14_S) +#define SPI1_MEM_S_BUF14_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF14_S 0 + +/** SPI1_MEM_S_W15_REG register + * SPI1 memory data buffer15 + */ +#define SPI1_MEM_S_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94) +/** SPI1_MEM_S_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_S_BUF15 0xFFFFFFFFU +#define SPI1_MEM_S_BUF15_M (SPI1_MEM_S_BUF15_V << SPI1_MEM_S_BUF15_S) +#define SPI1_MEM_S_BUF15_V 0xFFFFFFFFU +#define SPI1_MEM_S_BUF15_S 0 + +/** SPI1_MEM_S_FLASH_WAITI_CTRL_REG register + * SPI1 wait idle control register + */ +#define SPI1_MEM_S_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98) +/** SPI1_MEM_S_WAITI_EN : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ +#define SPI1_MEM_S_WAITI_EN (BIT(0)) +#define SPI1_MEM_S_WAITI_EN_M (SPI1_MEM_S_WAITI_EN_V << SPI1_MEM_S_WAITI_EN_S) +#define SPI1_MEM_S_WAITI_EN_V 0x00000001U +#define SPI1_MEM_S_WAITI_EN_S 0 +/** SPI1_MEM_S_WAITI_DUMMY : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ +#define SPI1_MEM_S_WAITI_DUMMY (BIT(1)) +#define SPI1_MEM_S_WAITI_DUMMY_M (SPI1_MEM_S_WAITI_DUMMY_V << SPI1_MEM_S_WAITI_DUMMY_S) +#define SPI1_MEM_S_WAITI_DUMMY_V 0x00000001U +#define SPI1_MEM_S_WAITI_DUMMY_S 1 +/** SPI1_MEM_S_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ +#define SPI1_MEM_S_WAITI_ADDR_EN (BIT(2)) +#define SPI1_MEM_S_WAITI_ADDR_EN_M (SPI1_MEM_S_WAITI_ADDR_EN_V << SPI1_MEM_S_WAITI_ADDR_EN_S) +#define SPI1_MEM_S_WAITI_ADDR_EN_V 0x00000001U +#define SPI1_MEM_S_WAITI_ADDR_EN_S 2 +/** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + */ +#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN 0x00000003U +#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S) +#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V 0x00000003U +#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S 3 +/** SPI1_MEM_S_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ +#define SPI1_MEM_S_WAITI_CMD_2B (BIT(9)) +#define SPI1_MEM_S_WAITI_CMD_2B_M (SPI1_MEM_S_WAITI_CMD_2B_V << SPI1_MEM_S_WAITI_CMD_2B_S) +#define SPI1_MEM_S_WAITI_CMD_2B_V 0x00000001U +#define SPI1_MEM_S_WAITI_CMD_2B_S 9 +/** SPI1_MEM_S_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ +#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_M (SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S) +#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S 10 +/** SPI1_MEM_S_WAITI_CMD : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ +#define SPI1_MEM_S_WAITI_CMD 0x0000FFFFU +#define SPI1_MEM_S_WAITI_CMD_M (SPI1_MEM_S_WAITI_CMD_V << SPI1_MEM_S_WAITI_CMD_S) +#define SPI1_MEM_S_WAITI_CMD_V 0x0000FFFFU +#define SPI1_MEM_S_WAITI_CMD_S 16 + +/** SPI1_MEM_S_FLASH_SUS_CTRL_REG register + * SPI1 flash suspend control register + */ +#define SPI1_MEM_S_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c) +/** SPI1_MEM_S_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_S_FLASH_PER (BIT(0)) +#define SPI1_MEM_S_FLASH_PER_M (SPI1_MEM_S_FLASH_PER_V << SPI1_MEM_S_FLASH_PER_S) +#define SPI1_MEM_S_FLASH_PER_V 0x00000001U +#define SPI1_MEM_S_FLASH_PER_S 0 +/** SPI1_MEM_S_FLASH_PES : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_S_FLASH_PES (BIT(1)) +#define SPI1_MEM_S_FLASH_PES_M (SPI1_MEM_S_FLASH_PES_V << SPI1_MEM_S_FLASH_PES_S) +#define SPI1_MEM_S_FLASH_PES_V 0x00000001U +#define SPI1_MEM_S_FLASH_PES_S 1 +/** SPI1_MEM_S_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ +#define SPI1_MEM_S_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI1_MEM_S_FLASH_PER_WAIT_EN_M (SPI1_MEM_S_FLASH_PER_WAIT_EN_V << SPI1_MEM_S_FLASH_PER_WAIT_EN_S) +#define SPI1_MEM_S_FLASH_PER_WAIT_EN_V 0x00000001U +#define SPI1_MEM_S_FLASH_PER_WAIT_EN_S 2 +/** SPI1_MEM_S_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ +#define SPI1_MEM_S_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI1_MEM_S_FLASH_PES_WAIT_EN_M (SPI1_MEM_S_FLASH_PES_WAIT_EN_V << SPI1_MEM_S_FLASH_PES_WAIT_EN_S) +#define SPI1_MEM_S_FLASH_PES_WAIT_EN_V 0x00000001U +#define SPI1_MEM_S_FLASH_PES_WAIT_EN_S 3 +/** SPI1_MEM_S_PES_PER_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ +#define SPI1_MEM_S_PES_PER_EN (BIT(4)) +#define SPI1_MEM_S_PES_PER_EN_M (SPI1_MEM_S_PES_PER_EN_V << SPI1_MEM_S_PES_PER_EN_S) +#define SPI1_MEM_S_PES_PER_EN_V 0x00000001U +#define SPI1_MEM_S_PES_PER_EN_S 4 +/** SPI1_MEM_S_FLASH_PES_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ +#define SPI1_MEM_S_FLASH_PES_EN (BIT(5)) +#define SPI1_MEM_S_FLASH_PES_EN_M (SPI1_MEM_S_FLASH_PES_EN_V << SPI1_MEM_S_FLASH_PES_EN_S) +#define SPI1_MEM_S_FLASH_PES_EN_V 0x00000001U +#define SPI1_MEM_S_FLASH_PES_EN_S 5 +/** SPI1_MEM_S_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0]. + */ +#define SPI1_MEM_S_PESR_END_MSK 0x0000FFFFU +#define SPI1_MEM_S_PESR_END_MSK_M (SPI1_MEM_S_PESR_END_MSK_V << SPI1_MEM_S_PESR_END_MSK_S) +#define SPI1_MEM_S_PESR_END_MSK_V 0x0000FFFFU +#define SPI1_MEM_S_PESR_END_MSK_S 6 +/** SPI1_MEM_S_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ +#define SPI1_MEM_S_FMEM_RD_SUS_2B (BIT(22)) +#define SPI1_MEM_S_FMEM_RD_SUS_2B_M (SPI1_MEM_S_FMEM_RD_SUS_2B_V << SPI1_MEM_S_FMEM_RD_SUS_2B_S) +#define SPI1_MEM_S_FMEM_RD_SUS_2B_V 0x00000001U +#define SPI1_MEM_S_FMEM_RD_SUS_2B_S 22 +/** SPI1_MEM_S_PER_END_EN : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_S_PER_END_EN (BIT(23)) +#define SPI1_MEM_S_PER_END_EN_M (SPI1_MEM_S_PER_END_EN_V << SPI1_MEM_S_PER_END_EN_S) +#define SPI1_MEM_S_PER_END_EN_V 0x00000001U +#define SPI1_MEM_S_PER_END_EN_S 23 +/** SPI1_MEM_S_PES_END_EN : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_S_PES_END_EN (BIT(24)) +#define SPI1_MEM_S_PES_END_EN_M (SPI1_MEM_S_PES_END_EN_V << SPI1_MEM_S_PES_END_EN_S) +#define SPI1_MEM_S_PES_END_EN_V 0x00000001U +#define SPI1_MEM_S_PES_END_EN_S 24 +/** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ +#define SPI1_MEM_S_SUS_TIMEOUT_CNT 0x0000007FU +#define SPI1_MEM_S_SUS_TIMEOUT_CNT_M (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S) +#define SPI1_MEM_S_SUS_TIMEOUT_CNT_V 0x0000007FU +#define SPI1_MEM_S_SUS_TIMEOUT_CNT_S 25 + +/** SPI1_MEM_S_FLASH_SUS_CMD_REG register + * SPI1 flash suspend command register + */ +#define SPI1_MEM_S_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0) +/** SPI1_MEM_S_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ +#define SPI1_MEM_S_FLASH_PES_COMMAND 0x0000FFFFU +#define SPI1_MEM_S_FLASH_PES_COMMAND_M (SPI1_MEM_S_FLASH_PES_COMMAND_V << SPI1_MEM_S_FLASH_PES_COMMAND_S) +#define SPI1_MEM_S_FLASH_PES_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_S_FLASH_PES_COMMAND_S 0 +/** SPI1_MEM_S_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ +#define SPI1_MEM_S_WAIT_PESR_COMMAND 0x0000FFFFU +#define SPI1_MEM_S_WAIT_PESR_COMMAND_M (SPI1_MEM_S_WAIT_PESR_COMMAND_V << SPI1_MEM_S_WAIT_PESR_COMMAND_S) +#define SPI1_MEM_S_WAIT_PESR_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_S_WAIT_PESR_COMMAND_S 16 + +/** SPI1_MEM_S_SUS_STATUS_REG register + * SPI1 flash suspend status register + */ +#define SPI1_MEM_S_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4) +/** SPI1_MEM_S_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ +#define SPI1_MEM_S_FLASH_SUS (BIT(0)) +#define SPI1_MEM_S_FLASH_SUS_M (SPI1_MEM_S_FLASH_SUS_V << SPI1_MEM_S_FLASH_SUS_S) +#define SPI1_MEM_S_FLASH_SUS_V 0x00000001U +#define SPI1_MEM_S_FLASH_SUS_S 0 +/** SPI1_MEM_S_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ +#define SPI1_MEM_S_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI1_MEM_S_WAIT_PESR_CMD_2B_M (SPI1_MEM_S_WAIT_PESR_CMD_2B_V << SPI1_MEM_S_WAIT_PESR_CMD_2B_S) +#define SPI1_MEM_S_WAIT_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_S_WAIT_PESR_CMD_2B_S 1 +/** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ +#define SPI1_MEM_S_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI1_MEM_S_FLASH_HPM_DLY_128_M (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S) +#define SPI1_MEM_S_FLASH_HPM_DLY_128_V 0x00000001U +#define SPI1_MEM_S_FLASH_HPM_DLY_128_S 2 +/** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ +#define SPI1_MEM_S_FLASH_RES_DLY_128 (BIT(3)) +#define SPI1_MEM_S_FLASH_RES_DLY_128_M (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S) +#define SPI1_MEM_S_FLASH_RES_DLY_128_V 0x00000001U +#define SPI1_MEM_S_FLASH_RES_DLY_128_S 3 +/** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ +#define SPI1_MEM_S_FLASH_DP_DLY_128 (BIT(4)) +#define SPI1_MEM_S_FLASH_DP_DLY_128_M (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S) +#define SPI1_MEM_S_FLASH_DP_DLY_128_V 0x00000001U +#define SPI1_MEM_S_FLASH_DP_DLY_128_S 4 +/** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ +#define SPI1_MEM_S_FLASH_PER_DLY_128 (BIT(5)) +#define SPI1_MEM_S_FLASH_PER_DLY_128_M (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S) +#define SPI1_MEM_S_FLASH_PER_DLY_128_V 0x00000001U +#define SPI1_MEM_S_FLASH_PER_DLY_128_S 5 +/** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ +#define SPI1_MEM_S_FLASH_PES_DLY_128 (BIT(6)) +#define SPI1_MEM_S_FLASH_PES_DLY_128_M (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S) +#define SPI1_MEM_S_FLASH_PES_DLY_128_V 0x00000001U +#define SPI1_MEM_S_FLASH_PES_DLY_128_S 6 +/** SPI1_MEM_S_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ +#define SPI1_MEM_S_SPI0_LOCK_EN (BIT(7)) +#define SPI1_MEM_S_SPI0_LOCK_EN_M (SPI1_MEM_S_SPI0_LOCK_EN_V << SPI1_MEM_S_SPI0_LOCK_EN_S) +#define SPI1_MEM_S_SPI0_LOCK_EN_V 0x00000001U +#define SPI1_MEM_S_SPI0_LOCK_EN_S 7 +/** SPI1_MEM_S_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ +#define SPI1_MEM_S_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI1_MEM_S_FLASH_PESR_CMD_2B_M (SPI1_MEM_S_FLASH_PESR_CMD_2B_V << SPI1_MEM_S_FLASH_PESR_CMD_2B_S) +#define SPI1_MEM_S_FLASH_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_S_FLASH_PESR_CMD_2B_S 15 +/** SPI1_MEM_S_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ +#define SPI1_MEM_S_FLASH_PER_COMMAND 0x0000FFFFU +#define SPI1_MEM_S_FLASH_PER_COMMAND_M (SPI1_MEM_S_FLASH_PER_COMMAND_V << SPI1_MEM_S_FLASH_PER_COMMAND_S) +#define SPI1_MEM_S_FLASH_PER_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_S_FLASH_PER_COMMAND_S 16 + +/** SPI1_MEM_S_INT_ENA_REG register + * SPI1 interrupt enable register + */ +#define SPI1_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0) +/** SPI1_MEM_S_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_S_PER_END_INT interrupt. + */ +#define SPI1_MEM_S_PER_END_INT_ENA (BIT(0)) +#define SPI1_MEM_S_PER_END_INT_ENA_M (SPI1_MEM_S_PER_END_INT_ENA_V << SPI1_MEM_S_PER_END_INT_ENA_S) +#define SPI1_MEM_S_PER_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_PER_END_INT_ENA_S 0 +/** SPI1_MEM_S_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_S_PES_END_INT interrupt. + */ +#define SPI1_MEM_S_PES_END_INT_ENA (BIT(1)) +#define SPI1_MEM_S_PES_END_INT_ENA_M (SPI1_MEM_S_PES_END_INT_ENA_V << SPI1_MEM_S_PES_END_INT_ENA_S) +#define SPI1_MEM_S_PES_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_PES_END_INT_ENA_S 1 +/** SPI1_MEM_S_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ +#define SPI1_MEM_S_WPE_END_INT_ENA (BIT(2)) +#define SPI1_MEM_S_WPE_END_INT_ENA_M (SPI1_MEM_S_WPE_END_INT_ENA_V << SPI1_MEM_S_WPE_END_INT_ENA_S) +#define SPI1_MEM_S_WPE_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_WPE_END_INT_ENA_S 2 +/** SPI1_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI1_MEM_S_SLV_ST_END_INT_ENA_M (SPI1_MEM_S_SLV_ST_END_INT_ENA_V << SPI1_MEM_S_SLV_ST_END_INT_ENA_S) +#define SPI1_MEM_S_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_SLV_ST_END_INT_ENA_S 3 +/** SPI1_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_MST_ST_END_INT_ENA (BIT(4)) +#define SPI1_MEM_S_MST_ST_END_INT_ENA_M (SPI1_MEM_S_MST_ST_END_INT_ENA_V << SPI1_MEM_S_MST_ST_END_INT_ENA_S) +#define SPI1_MEM_S_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_MST_ST_END_INT_ENA_S 4 +/** SPI1_MEM_S_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_S_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI1_MEM_S_BROWN_OUT_INT_ENA_M (SPI1_MEM_S_BROWN_OUT_INT_ENA_V << SPI1_MEM_S_BROWN_OUT_INT_ENA_S) +#define SPI1_MEM_S_BROWN_OUT_INT_ENA_V 0x00000001U +#define SPI1_MEM_S_BROWN_OUT_INT_ENA_S 10 + +/** SPI1_MEM_S_INT_CLR_REG register + * SPI1 interrupt clear register + */ +#define SPI1_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4) +/** SPI1_MEM_S_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_S_PER_END_INT interrupt. + */ +#define SPI1_MEM_S_PER_END_INT_CLR (BIT(0)) +#define SPI1_MEM_S_PER_END_INT_CLR_M (SPI1_MEM_S_PER_END_INT_CLR_V << SPI1_MEM_S_PER_END_INT_CLR_S) +#define SPI1_MEM_S_PER_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_PER_END_INT_CLR_S 0 +/** SPI1_MEM_S_PES_END_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_S_PES_END_INT interrupt. + */ +#define SPI1_MEM_S_PES_END_INT_CLR (BIT(1)) +#define SPI1_MEM_S_PES_END_INT_CLR_M (SPI1_MEM_S_PES_END_INT_CLR_V << SPI1_MEM_S_PES_END_INT_CLR_S) +#define SPI1_MEM_S_PES_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_PES_END_INT_CLR_S 1 +/** SPI1_MEM_S_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ +#define SPI1_MEM_S_WPE_END_INT_CLR (BIT(2)) +#define SPI1_MEM_S_WPE_END_INT_CLR_M (SPI1_MEM_S_WPE_END_INT_CLR_V << SPI1_MEM_S_WPE_END_INT_CLR_S) +#define SPI1_MEM_S_WPE_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_WPE_END_INT_CLR_S 2 +/** SPI1_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI1_MEM_S_SLV_ST_END_INT_CLR_M (SPI1_MEM_S_SLV_ST_END_INT_CLR_V << SPI1_MEM_S_SLV_ST_END_INT_CLR_S) +#define SPI1_MEM_S_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_SLV_ST_END_INT_CLR_S 3 +/** SPI1_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_MST_ST_END_INT_CLR (BIT(4)) +#define SPI1_MEM_S_MST_ST_END_INT_CLR_M (SPI1_MEM_S_MST_ST_END_INT_CLR_V << SPI1_MEM_S_MST_ST_END_INT_CLR_S) +#define SPI1_MEM_S_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_MST_ST_END_INT_CLR_S 4 +/** SPI1_MEM_S_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_S_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI1_MEM_S_BROWN_OUT_INT_CLR_M (SPI1_MEM_S_BROWN_OUT_INT_CLR_V << SPI1_MEM_S_BROWN_OUT_INT_CLR_S) +#define SPI1_MEM_S_BROWN_OUT_INT_CLR_V 0x00000001U +#define SPI1_MEM_S_BROWN_OUT_INT_CLR_S 10 + +/** SPI1_MEM_S_INT_RAW_REG register + * SPI1 interrupt raw register + */ +#define SPI1_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8) +/** SPI1_MEM_S_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ +#define SPI1_MEM_S_PER_END_INT_RAW (BIT(0)) +#define SPI1_MEM_S_PER_END_INT_RAW_M (SPI1_MEM_S_PER_END_INT_RAW_V << SPI1_MEM_S_PER_END_INT_RAW_S) +#define SPI1_MEM_S_PER_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_PER_END_INT_RAW_S 0 +/** SPI1_MEM_S_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ +#define SPI1_MEM_S_PES_END_INT_RAW (BIT(1)) +#define SPI1_MEM_S_PES_END_INT_RAW_M (SPI1_MEM_S_PES_END_INT_RAW_V << SPI1_MEM_S_PES_END_INT_RAW_S) +#define SPI1_MEM_S_PES_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_PES_END_INT_RAW_S 1 +/** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ +#define SPI1_MEM_S_WPE_END_INT_RAW (BIT(2)) +#define SPI1_MEM_S_WPE_END_INT_RAW_M (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S) +#define SPI1_MEM_S_WPE_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_WPE_END_INT_RAW_S 2 +/** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI1_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI1_MEM_S_SLV_ST_END_INT_RAW_M (SPI1_MEM_S_SLV_ST_END_INT_RAW_V << SPI1_MEM_S_SLV_ST_END_INT_RAW_S) +#define SPI1_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_SLV_ST_END_INT_RAW_S 3 +/** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI1_MEM_S_MST_ST_END_INT_RAW (BIT(4)) +#define SPI1_MEM_S_MST_ST_END_INT_RAW_M (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S) +#define SPI1_MEM_S_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_MST_ST_END_INT_RAW_S 4 +/** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is losing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ +#define SPI1_MEM_S_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI1_MEM_S_BROWN_OUT_INT_RAW_M (SPI1_MEM_S_BROWN_OUT_INT_RAW_V << SPI1_MEM_S_BROWN_OUT_INT_RAW_S) +#define SPI1_MEM_S_BROWN_OUT_INT_RAW_V 0x00000001U +#define SPI1_MEM_S_BROWN_OUT_INT_RAW_S 10 + +/** SPI1_MEM_S_INT_ST_REG register + * SPI1 interrupt status register + */ +#define SPI1_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc) +/** SPI1_MEM_S_PER_END_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_S_PER_END_INT interrupt. + */ +#define SPI1_MEM_S_PER_END_INT_ST (BIT(0)) +#define SPI1_MEM_S_PER_END_INT_ST_M (SPI1_MEM_S_PER_END_INT_ST_V << SPI1_MEM_S_PER_END_INT_ST_S) +#define SPI1_MEM_S_PER_END_INT_ST_V 0x00000001U +#define SPI1_MEM_S_PER_END_INT_ST_S 0 +/** SPI1_MEM_S_PES_END_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_S_PES_END_INT interrupt. + */ +#define SPI1_MEM_S_PES_END_INT_ST (BIT(1)) +#define SPI1_MEM_S_PES_END_INT_ST_M (SPI1_MEM_S_PES_END_INT_ST_V << SPI1_MEM_S_PES_END_INT_ST_S) +#define SPI1_MEM_S_PES_END_INT_ST_V 0x00000001U +#define SPI1_MEM_S_PES_END_INT_ST_S 1 +/** SPI1_MEM_S_WPE_END_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ +#define SPI1_MEM_S_WPE_END_INT_ST (BIT(2)) +#define SPI1_MEM_S_WPE_END_INT_ST_M (SPI1_MEM_S_WPE_END_INT_ST_V << SPI1_MEM_S_WPE_END_INT_ST_S) +#define SPI1_MEM_S_WPE_END_INT_ST_V 0x00000001U +#define SPI1_MEM_S_WPE_END_INT_ST_S 2 +/** SPI1_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_SLV_ST_END_INT_ST (BIT(3)) +#define SPI1_MEM_S_SLV_ST_END_INT_ST_M (SPI1_MEM_S_SLV_ST_END_INT_ST_V << SPI1_MEM_S_SLV_ST_END_INT_ST_S) +#define SPI1_MEM_S_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_S_SLV_ST_END_INT_ST_S 3 +/** SPI1_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_S_MST_ST_END_INT_ST (BIT(4)) +#define SPI1_MEM_S_MST_ST_END_INT_ST_M (SPI1_MEM_S_MST_ST_END_INT_ST_V << SPI1_MEM_S_MST_ST_END_INT_ST_S) +#define SPI1_MEM_S_MST_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_S_MST_ST_END_INT_ST_S 4 +/** SPI1_MEM_S_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_S_BROWN_OUT_INT_ST (BIT(10)) +#define SPI1_MEM_S_BROWN_OUT_INT_ST_M (SPI1_MEM_S_BROWN_OUT_INT_ST_V << SPI1_MEM_S_BROWN_OUT_INT_ST_S) +#define SPI1_MEM_S_BROWN_OUT_INT_ST_V 0x00000001U +#define SPI1_MEM_S_BROWN_OUT_INT_ST_S 10 + +/** SPI1_MEM_S_DDR_REG register + * SPI1 DDR control register + */ +#define SPI1_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4) +/** SPI1_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ +#define SPI1_MEM_S_FMEM_DDR_EN (BIT(0)) +#define SPI1_MEM_S_FMEM_DDR_EN_M (SPI1_MEM_S_FMEM_DDR_EN_V << SPI1_MEM_S_FMEM_DDR_EN_S) +#define SPI1_MEM_S_FMEM_DDR_EN_V 0x00000001U +#define SPI1_MEM_S_FMEM_DDR_EN_S 0 +/** SPI1_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ +#define SPI1_MEM_S_FMEM_VAR_DUMMY (BIT(1)) +#define SPI1_MEM_S_FMEM_VAR_DUMMY_M (SPI1_MEM_S_FMEM_VAR_DUMMY_V << SPI1_MEM_S_FMEM_VAR_DUMMY_S) +#define SPI1_MEM_S_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI1_MEM_S_FMEM_VAR_DUMMY_S 1 +/** SPI1_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ +#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_M (SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S) +#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S 2 +/** SPI1_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ +#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_M (SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S) +#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S 3 +/** SPI1_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ +#define SPI1_MEM_S_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_M (SPI1_MEM_S_FMEM_DDR_CMD_DIS_V << SPI1_MEM_S_FMEM_DDR_CMD_DIS_S) +#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_S 4 +/** SPI1_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI1_MEM_S_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_M (SPI1_MEM_S_FMEM_OUTMINBYTELEN_V << SPI1_MEM_S_FMEM_OUTMINBYTELEN_S) +#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_S 5 +/** SPI1_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_M (SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S) +#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_M (SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S) +#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S 21 +/** SPI1_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI1_MEM_S_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_M (SPI1_MEM_S_FMEM_CLK_DIFF_EN_V << SPI1_MEM_S_FMEM_CLK_DIFF_EN_S) +#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_S 24 +/** SPI1_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI1_MEM_S_FMEM_DQS_CA_IN (BIT(26)) +#define SPI1_MEM_S_FMEM_DQS_CA_IN_M (SPI1_MEM_S_FMEM_DQS_CA_IN_V << SPI1_MEM_S_FMEM_DQS_CA_IN_S) +#define SPI1_MEM_S_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI1_MEM_S_FMEM_DQS_CA_IN_S 26 +/** SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M (SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI1_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI1_MEM_S_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_M (SPI1_MEM_S_FMEM_CLK_DIFF_INV_V << SPI1_MEM_S_FMEM_CLK_DIFF_INV_S) +#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_S 28 +/** SPI1_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_M (SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S) +#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI1_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI1_MEM_S_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI1_MEM_S_FMEM_HYPERBUS_CA_M (SPI1_MEM_S_FMEM_HYPERBUS_CA_V << SPI1_MEM_S_FMEM_HYPERBUS_CA_S) +#define SPI1_MEM_S_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI1_MEM_S_FMEM_HYPERBUS_CA_S 30 + +/** SPI1_MEM_S_TIMING_CALI_REG register + * SPI1 timing control register + */ +#define SPI1_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180) +/** SPI1_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI1_MEM_S_TIMING_CALI (BIT(1)) +#define SPI1_MEM_S_TIMING_CALI_M (SPI1_MEM_S_TIMING_CALI_V << SPI1_MEM_S_TIMING_CALI_S) +#define SPI1_MEM_S_TIMING_CALI_V 0x00000001U +#define SPI1_MEM_S_TIMING_CALI_S 1 +/** SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_M (SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S) +#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S 2 + +/** SPI1_MEM_S_CLOCK_GATE_REG register + * SPI1 clk_gate register + */ +#define SPI1_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200) +/** SPI1_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI1_MEM_S_CLK_EN (BIT(0)) +#define SPI1_MEM_S_CLK_EN_M (SPI1_MEM_S_CLK_EN_V << SPI1_MEM_S_CLK_EN_S) +#define SPI1_MEM_S_CLK_EN_V 0x00000001U +#define SPI1_MEM_S_CLK_EN_S 0 + +/** SPI1_MEM_S_DATE_REG register + * Version control register + */ +#define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc) +/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216; + * Version control register + */ +#define SPI1_MEM_S_DATE 0x0FFFFFFFU +#define SPI1_MEM_S_DATE_M (SPI1_MEM_S_DATE_V << SPI1_MEM_S_DATE_S) +#define SPI1_MEM_S_DATE_V 0x0FFFFFFFU +#define SPI1_MEM_S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_struct.h new file mode 100644 index 0000000000..756985a047 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi1_mem_s_struct.h @@ -0,0 +1,1270 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * SPI1 memory command register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:9; + /** flash_pe : R/W/SC; bitpos: [17]; default: 0; + * In user mode, it is set to indicate that program/erase operation will be triggered. + * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * operation done.1: enable 0: disable. + */ + uint32_t flash_pe:1; + /** usr : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t usr:1; + /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; + * Drive Flash into high performance mode. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t flash_hpm:1; + /** flash_res : R/W/SC; bitpos: [20]; default: 0; + * This bit combined with reg_resandres bit releases Flash from the power-down state + * or high performance mode and obtains the devices ID. The bit will be cleared once + * the operation done.1: enable 0: disable. + */ + uint32_t flash_res:1; + /** flash_dp : R/W/SC; bitpos: [21]; default: 0; + * Drive Flash into power down. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_dp:1; + /** flash_ce : R/W/SC; bitpos: [22]; default: 0; + * Chip erase enable. Chip erase operation will be triggered when the bit is set. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_ce:1; + /** flash_be : R/W/SC; bitpos: [23]; default: 0; + * Block erase enable(32KB) . Block erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_be:1; + /** flash_se : R/W/SC; bitpos: [24]; default: 0; + * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_se:1; + /** flash_pp : R/W/SC; bitpos: [25]; default: 0; + * Page program enable(1 byte ~256 bytes data to be programmed). Page program + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done .1: enable 0: disable. + */ + uint32_t flash_pp:1; + /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; + * Write status register enable. Write status operation will be triggered when the + * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_wrsr:1; + /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; + * Read status register-1. Read status operation will be triggered when the bit is + * set. The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t flash_rdsr:1; + /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; + * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be + * cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_rdid:1; + /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; + * Write flash disable. Write disable command will be sent when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wrdi:1; + /** flash_wren : R/W/SC; bitpos: [30]; default: 0; + * Write flash enable. Write enable command will be sent when the bit is set. The bit + * will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_wren:1; + /** flash_read : R/W/SC; bitpos: [31]; default: 0; + * Read flash enable. Read flash operation will be triggered when the bit is set. The + * bit will be cleared once the operation done. 1: enable 0: disable. + */ + uint32_t flash_read:1; + }; + uint32_t val; +} spi1_mem_s_cmd_reg_t; + +/** Type of addr register + * SPI1 address register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi1_mem_s_addr_reg_t; + +/** Type of user register + * SPI1 user register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + uint32_t fwrite_quad:1; + /** fwrite_dio : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ + uint32_t fwrite_dio:1; + /** fwrite_qio : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ + uint32_t fwrite_qio:1; + uint32_t reserved_16:8; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * enable 0: disable. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * enable 0: disable. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi1_mem_s_user_reg_t; + +/** Type of user1 register + * SPI1 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + uint32_t reserved_6:20; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi1_mem_s_user1_reg_t; + +/** Type of user2 register + * SPI1 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi1_mem_s_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI1 control register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + /** fcs_crc_en : R/W; bitpos: [10]; default: 0; + * For SPI1, initialize crc32 module before writing encrypted data to flash. Active + * low. + */ + uint32_t fcs_crc_en:1; + /** tx_crc_en : R/W; bitpos: [11]; default: 0; + * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + */ + uint32_t tx_crc_en:1; + uint32_t reserved_12:1; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout + * and spi1_mem_s_fread_dout. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + /** resandres : R/W; bitpos: [15]; default: 1; + * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with + * spi1_mem_s_flash_res bit. 1: enable 0: disable. + */ + uint32_t resandres:1; + uint32_t reserved_16:2; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + /** wrsr_2b : R/W; bitpos: [22]; default: 0; + * two bytes data will be written to status register when it is set. 1: enable 0: + * disable. + */ + uint32_t wrsr_2b:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi1_mem_s_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI1 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t clk_mode:2; + /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_res:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi1_mem_s_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI1 control2 register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi1_mem_s_ctrl2_reg_t; + +/** Type of clock register + * SPI1 clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is + * system/(spi1_mem_s_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi1_mem_s_clock_reg_t; + +/** Type of mosi_dlen register + * SPI1 send data bit length control register. + */ +typedef union { + struct { + /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + uint32_t usr_mosi_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_s_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * SPI1 receive data bit length control register. + */ +typedef union { + struct { + /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + uint32_t usr_miso_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_s_miso_dlen_reg_t; + +/** Type of rd_status register + * SPI1 status register. + */ +typedef union { + struct { + /** status : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + */ + uint32_t status:16; + /** wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + */ + uint32_t wb_mode:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi1_mem_s_rd_status_reg_t; + +/** Type of misc register + * SPI1 misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs1_dis:1; + uint32_t reserved_2:7; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_s_misc_reg_t; + +/** Type of cache_fctrl register + * SPI1 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ + uint32_t cache_usr_addr_4byte:1; + uint32_t reserved_2:1; + /** fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with + * spi1_mem_s_fread_dio. + */ + uint32_t fdin_dual:1; + /** fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_dio. + */ + uint32_t fdout_dual:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_dio. + */ + uint32_t faddr_dual:1; + /** fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ + uint32_t fdin_quad:1; + /** fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ + uint32_t fdout_quad:1; + /** faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same + * with spi1_mem_s_fread_qio. + */ + uint32_t faddr_quad:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi1_mem_s_cache_fctrl_reg_t; + +/** Type of flash_waiti_ctrl register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_en : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ + uint32_t waiti_en:1; + /** waiti_dummy : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ + uint32_t waiti_dummy:1; + /** waiti_addr_en : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ + uint32_t waiti_addr_en:1; + /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when + * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + */ + uint32_t waiti_addr_cyclelen:2; + uint32_t reserved_5:4; + /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ + uint32_t waiti_cmd_2b:1; + /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ + uint32_t waiti_dummy_cyclelen:6; + /** waiti_cmd : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ + uint32_t waiti_cmd:16; + }; + uint32_t val; +} spi1_mem_s_flash_waiti_ctrl_reg_t; + +/** Type of flash_sus_ctrl register + * SPI1 flash suspend control register + */ +typedef union { + struct { + /** flash_per : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_per:1; + /** flash_pes : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_pes:1; + /** flash_per_wait_en : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ + uint32_t flash_per_wait_en:1; + /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ + uint32_t flash_pes_wait_en:1; + /** pes_per_en : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ + uint32_t pes_per_en:1; + /** flash_pes_en : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ + uint32_t flash_pes_en:1; + /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0]. + */ + uint32_t pesr_end_msk:16; + /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ + uint32_t fmem_rd_sus_2b:1; + /** per_end_en : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ + uint32_t per_end_en:1; + /** pes_end_en : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ + uint32_t pes_end_en:1; + /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it + * will be treated as check pass. + */ + uint32_t sus_timeout_cnt:7; + }; + uint32_t val; +} spi1_mem_s_flash_sus_ctrl_reg_t; + +/** Type of flash_sus_cmd register + * SPI1 flash suspend command register + */ +typedef union { + struct { + /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ + uint32_t flash_pes_command:16; + /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ + uint32_t wait_pesr_command:16; + }; + uint32_t val; +} spi1_mem_s_flash_sus_cmd_reg_t; + +/** Type of sus_status register + * SPI1 flash suspend status register + */ +typedef union { + struct { + /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ + uint32_t flash_sus:1; + /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ + uint32_t wait_pesr_cmd_2b:1; + /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ + uint32_t flash_hpm_dly_128:1; + /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ + uint32_t flash_res_dly_128:1; + /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ + uint32_t flash_dp_dly_128:1; + /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: + * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is + * sent. + */ + uint32_t flash_per_dly_128:1; + /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: + * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is + * sent. + */ + uint32_t flash_pes_dly_128:1; + /** spi0_lock_en : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ + uint32_t spi0_lock_en:1; + uint32_t reserved_8:7; + /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ + uint32_t flash_pesr_cmd_2b:1; + /** flash_per_command : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ + uint32_t flash_per_command:16; + }; + uint32_t val; +} spi1_mem_s_sus_status_reg_t; + +/** Type of ddr register + * SPI1 DDR control register + */ +typedef union { + struct { + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + uint32_t reserved_12:2; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi1_mem_s_ddr_reg_t; + +/** Type of clock_gate register + * SPI1 clk_gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi1_mem_s_clock_gate_reg_t; + + +/** Group: Status register */ +/** Type of tx_crc register + * SPI1 TX CRC data register. + */ +typedef union { + struct { + /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; + * For SPI1, the value of crc32. + */ + uint32_t tx_crc_data:32; + }; + uint32_t val; +} spi1_mem_s_tx_crc_reg_t; + + +/** Group: Memory data buffer register */ +/** Type of w0 register + * SPI1 memory data buffer0 + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi1_mem_s_w0_reg_t; + +/** Type of w1 register + * SPI1 memory data buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi1_mem_s_w1_reg_t; + +/** Type of w2 register + * SPI1 memory data buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi1_mem_s_w2_reg_t; + +/** Type of w3 register + * SPI1 memory data buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi1_mem_s_w3_reg_t; + +/** Type of w4 register + * SPI1 memory data buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi1_mem_s_w4_reg_t; + +/** Type of w5 register + * SPI1 memory data buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi1_mem_s_w5_reg_t; + +/** Type of w6 register + * SPI1 memory data buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi1_mem_s_w6_reg_t; + +/** Type of w7 register + * SPI1 memory data buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi1_mem_s_w7_reg_t; + +/** Type of w8 register + * SPI1 memory data buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi1_mem_s_w8_reg_t; + +/** Type of w9 register + * SPI1 memory data buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi1_mem_s_w9_reg_t; + +/** Type of w10 register + * SPI1 memory data buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi1_mem_s_w10_reg_t; + +/** Type of w11 register + * SPI1 memory data buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi1_mem_s_w11_reg_t; + +/** Type of w12 register + * SPI1 memory data buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi1_mem_s_w12_reg_t; + +/** Type of w13 register + * SPI1 memory data buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi1_mem_s_w13_reg_t; + +/** Type of w14 register + * SPI1 memory data buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi1_mem_s_w14_reg_t; + +/** Type of w15 register + * SPI1 memory data buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi1_mem_s_w15_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI1 interrupt enable register + */ +typedef union { + struct { + /** per_end_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_S_PER_END_INT interrupt. + */ + uint32_t per_end_int_ena:1; + /** pes_end_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_S_PES_END_INT interrupt. + */ + uint32_t pes_end_int_ena:1; + /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_ena:1; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + uint32_t reserved_5:5; + /** brown_out_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_ena:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_s_int_ena_reg_t; + +/** Type of int_clr register + * SPI1 interrupt clear register + */ +typedef union { + struct { + /** per_end_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_S_PER_END_INT interrupt. + */ + uint32_t per_end_int_clr:1; + /** pes_end_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_S_PES_END_INT interrupt. + */ + uint32_t pes_end_int_clr:1; + /** wpe_end_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_clr:1; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + uint32_t reserved_5:5; + /** brown_out_int_clr : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_clr:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_s_int_clr_reg_t; + +/** Type of int_raw register + * SPI1 interrupt raw register + */ +typedef union { + struct { + /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ + uint32_t per_end_int_raw:1; + /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ + uint32_t pes_end_int_raw:1; + /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ + uint32_t wpe_end_int_raw:1; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + uint32_t reserved_5:5; + /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is losing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ + uint32_t brown_out_int_raw:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_s_int_raw_reg_t; + +/** Type of int_st register + * SPI1 interrupt status register + */ +typedef union { + struct { + /** per_end_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_S_PER_END_INT interrupt. + */ + uint32_t per_end_int_st:1; + /** pes_end_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_S_PES_END_INT interrupt. + */ + uint32_t pes_end_int_st:1; + /** wpe_end_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_S_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_st:1; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + uint32_t reserved_5:5; + /** brown_out_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_st:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_s_int_st_reg_t; + + +/** Group: Timing registers */ +/** Type of timing_cali register + * SPI1 timing control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi1_mem_s_timing_cali_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34673216; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi1_mem_s_date_reg_t; + + +typedef struct spi1_mem_s_dev_s { + volatile spi1_mem_s_cmd_reg_t cmd; + volatile spi1_mem_s_addr_reg_t addr; + volatile spi1_mem_s_ctrl_reg_t ctrl; + volatile spi1_mem_s_ctrl1_reg_t ctrl1; + volatile spi1_mem_s_ctrl2_reg_t ctrl2; + volatile spi1_mem_s_clock_reg_t clock; + volatile spi1_mem_s_user_reg_t user; + volatile spi1_mem_s_user1_reg_t user1; + volatile spi1_mem_s_user2_reg_t user2; + volatile spi1_mem_s_mosi_dlen_reg_t mosi_dlen; + volatile spi1_mem_s_miso_dlen_reg_t miso_dlen; + volatile spi1_mem_s_rd_status_reg_t rd_status; + uint32_t reserved_030; + volatile spi1_mem_s_misc_reg_t misc; + volatile spi1_mem_s_tx_crc_reg_t tx_crc; + volatile spi1_mem_s_cache_fctrl_reg_t cache_fctrl; + uint32_t reserved_040[6]; + volatile spi1_mem_s_w0_reg_t w0; + volatile spi1_mem_s_w1_reg_t w1; + volatile spi1_mem_s_w2_reg_t w2; + volatile spi1_mem_s_w3_reg_t w3; + volatile spi1_mem_s_w4_reg_t w4; + volatile spi1_mem_s_w5_reg_t w5; + volatile spi1_mem_s_w6_reg_t w6; + volatile spi1_mem_s_w7_reg_t w7; + volatile spi1_mem_s_w8_reg_t w8; + volatile spi1_mem_s_w9_reg_t w9; + volatile spi1_mem_s_w10_reg_t w10; + volatile spi1_mem_s_w11_reg_t w11; + volatile spi1_mem_s_w12_reg_t w12; + volatile spi1_mem_s_w13_reg_t w13; + volatile spi1_mem_s_w14_reg_t w14; + volatile spi1_mem_s_w15_reg_t w15; + volatile spi1_mem_s_flash_waiti_ctrl_reg_t flash_waiti_ctrl; + volatile spi1_mem_s_flash_sus_ctrl_reg_t flash_sus_ctrl; + volatile spi1_mem_s_flash_sus_cmd_reg_t flash_sus_cmd; + volatile spi1_mem_s_sus_status_reg_t sus_status; + uint32_t reserved_0a8[6]; + volatile spi1_mem_s_int_ena_reg_t int_ena; + volatile spi1_mem_s_int_clr_reg_t int_clr; + volatile spi1_mem_s_int_raw_reg_t int_raw; + volatile spi1_mem_s_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi1_mem_s_ddr_reg_t ddr; + uint32_t reserved_0d8[42]; + volatile spi1_mem_s_timing_cali_reg_t timing_cali; + uint32_t reserved_184[31]; + volatile spi1_mem_s_clock_gate_reg_t clock_gate; + uint32_t reserved_204[126]; + volatile spi1_mem_s_date_reg_t date; +} spi1_mem_s_dev_t; + +extern spi1_mem_s_dev_t SPIMEM3; + +#ifndef __cplusplus +_Static_assert(sizeof(spi1_mem_s_dev_t) == 0x400, "Invalid size of spi1_mem_s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_eco5_struct.h new file mode 100644 index 0000000000..1263f22ba5 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_eco5_struct.h @@ -0,0 +1,1623 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : R/W; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : R/W; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : R/W; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : R/W; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ + uint32_t slv_last_byte_strb:8; + uint32_t reserved_20:2; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:8; + /** clk_edge_sel : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ + uint32_t clk_edge_sel:1; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : R/W; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : R/W; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : R/W; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : R/W; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : R/W; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of w0 register + * SPI CPU-controlled buffer0 + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi_w0_reg_t; + +/** Type of w1 register + * SPI CPU-controlled buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi_w1_reg_t; + +/** Type of w2 register + * SPI CPU-controlled buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi_w2_reg_t; + +/** Type of w3 register + * SPI CPU-controlled buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi_w3_reg_t; + +/** Type of w4 register + * SPI CPU-controlled buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi_w4_reg_t; + +/** Type of w5 register + * SPI CPU-controlled buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi_w5_reg_t; + +/** Type of w6 register + * SPI CPU-controlled buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi_w6_reg_t; + +/** Type of w7 register + * SPI CPU-controlled buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi_w7_reg_t; + +/** Type of w8 register + * SPI CPU-controlled buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi_w8_reg_t; + +/** Type of w9 register + * SPI CPU-controlled buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi_w9_reg_t; + +/** Type of w10 register + * SPI CPU-controlled buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi_w10_reg_t; + +/** Type of w11 register + * SPI CPU-controlled buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi_w11_reg_t; + +/** Type of w12 register + * SPI CPU-controlled buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi_w12_reg_t; + +/** Type of w13 register + * SPI CPU-controlled buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi_w13_reg_t; + +/** Type of w14 register + * SPI CPU-controlled buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi_w14_reg_t; + +/** Type of w15 register + * SPI CPU-controlled buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi_w15_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37761424; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_w0_reg_t w0; + volatile spi_w1_reg_t w1; + volatile spi_w2_reg_t w2; + volatile spi_w3_reg_t w3; + volatile spi_w4_reg_t w4; + volatile spi_w5_reg_t w5; + volatile spi_w6_reg_t w6; + volatile spi_w7_reg_t w7; + volatile spi_w8_reg_t w8; + volatile spi_w9_reg_t w9; + volatile spi_w10_reg_t w10; + volatile spi_w11_reg_t w11; + volatile spi_w12_reg_t w12; + volatile spi_w13_reg_t w13; + volatile spi_w14_reg_t w14; + volatile spi_w15_reg_t w15; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_reg.h new file mode 100644 index 0000000000..d105863da3 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_reg.h @@ -0,0 +1,2737 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_C_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_C_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x0) +/** SPI_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_C_MST_ST 0x0000000FU +#define SPI_MEM_C_MST_ST_M (SPI_MEM_C_MST_ST_V << SPI_MEM_C_MST_ST_S) +#define SPI_MEM_C_MST_ST_V 0x0000000FU +#define SPI_MEM_C_MST_ST_S 0 +/** SPI_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_C_SLV_ST 0x0000000FU +#define SPI_MEM_C_SLV_ST_M (SPI_MEM_C_SLV_ST_V << SPI_MEM_C_SLV_ST_S) +#define SPI_MEM_C_SLV_ST_V 0x0000000FU +#define SPI_MEM_C_SLV_ST_S 4 +/** SPI_MEM_C_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_C_USR (BIT(18)) +#define SPI_MEM_C_USR_M (SPI_MEM_C_USR_V << SPI_MEM_C_USR_S) +#define SPI_MEM_C_USR_V 0x00000001U +#define SPI_MEM_C_USR_S 18 + +/** SPI_MEM_C_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_C_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x8) +/** SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_C_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_C_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_C_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_M (SPI_MEM_C_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_C_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_C_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_C_FDUMMY_RIN_M (SPI_MEM_C_FDUMMY_RIN_V << SPI_MEM_C_FDUMMY_RIN_S) +#define SPI_MEM_C_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_C_FDUMMY_RIN_S 2 +/** SPI_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_C_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_C_FDUMMY_WOUT_M (SPI_MEM_C_FDUMMY_WOUT_V << SPI_MEM_C_FDUMMY_WOUT_S) +#define SPI_MEM_C_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_C_FDUMMY_WOUT_S 3 +/** SPI_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_C_FDOUT_OCT (BIT(4)) +#define SPI_MEM_C_FDOUT_OCT_M (SPI_MEM_C_FDOUT_OCT_V << SPI_MEM_C_FDOUT_OCT_S) +#define SPI_MEM_C_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_C_FDOUT_OCT_S 4 +/** SPI_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_C_FDIN_OCT (BIT(5)) +#define SPI_MEM_C_FDIN_OCT_M (SPI_MEM_C_FDIN_OCT_V << SPI_MEM_C_FDIN_OCT_S) +#define SPI_MEM_C_FDIN_OCT_V 0x00000001U +#define SPI_MEM_C_FDIN_OCT_S 5 +/** SPI_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_C_FADDR_OCT (BIT(6)) +#define SPI_MEM_C_FADDR_OCT_M (SPI_MEM_C_FADDR_OCT_V << SPI_MEM_C_FADDR_OCT_S) +#define SPI_MEM_C_FADDR_OCT_V 0x00000001U +#define SPI_MEM_C_FADDR_OCT_S 6 +/** SPI_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_C_FCMD_QUAD (BIT(8)) +#define SPI_MEM_C_FCMD_QUAD_M (SPI_MEM_C_FCMD_QUAD_V << SPI_MEM_C_FCMD_QUAD_S) +#define SPI_MEM_C_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_C_FCMD_QUAD_S 8 +/** SPI_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_C_FCMD_OCT (BIT(9)) +#define SPI_MEM_C_FCMD_OCT_M (SPI_MEM_C_FCMD_OCT_V << SPI_MEM_C_FCMD_OCT_S) +#define SPI_MEM_C_FCMD_OCT_V 0x00000001U +#define SPI_MEM_C_FCMD_OCT_S 9 +/** SPI_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, SPI_MEM_C_FREAD_QOUT + * and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_C_FASTRD_MODE (BIT(13)) +#define SPI_MEM_C_FASTRD_MODE_M (SPI_MEM_C_FASTRD_MODE_V << SPI_MEM_C_FASTRD_MODE_S) +#define SPI_MEM_C_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_C_FASTRD_MODE_S 13 +/** SPI_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_C_FREAD_DUAL (BIT(14)) +#define SPI_MEM_C_FREAD_DUAL_M (SPI_MEM_C_FREAD_DUAL_V << SPI_MEM_C_FREAD_DUAL_S) +#define SPI_MEM_C_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_C_FREAD_DUAL_S 14 +/** SPI_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_C_Q_POL (BIT(18)) +#define SPI_MEM_C_Q_POL_M (SPI_MEM_C_Q_POL_V << SPI_MEM_C_Q_POL_S) +#define SPI_MEM_C_Q_POL_V 0x00000001U +#define SPI_MEM_C_Q_POL_S 18 +/** SPI_MEM_C_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_C_D_POL (BIT(19)) +#define SPI_MEM_C_D_POL_M (SPI_MEM_C_D_POL_V << SPI_MEM_C_D_POL_S) +#define SPI_MEM_C_D_POL_V 0x00000001U +#define SPI_MEM_C_D_POL_S 19 +/** SPI_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_C_FREAD_QUAD (BIT(20)) +#define SPI_MEM_C_FREAD_QUAD_M (SPI_MEM_C_FREAD_QUAD_V << SPI_MEM_C_FREAD_QUAD_S) +#define SPI_MEM_C_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_C_FREAD_QUAD_S 20 +/** SPI_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_C_WP_REG (BIT(21)) +#define SPI_MEM_C_WP_REG_M (SPI_MEM_C_WP_REG_V << SPI_MEM_C_WP_REG_S) +#define SPI_MEM_C_WP_REG_V 0x00000001U +#define SPI_MEM_C_WP_REG_S 21 +/** SPI_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_C_FREAD_DIO (BIT(23)) +#define SPI_MEM_C_FREAD_DIO_M (SPI_MEM_C_FREAD_DIO_V << SPI_MEM_C_FREAD_DIO_S) +#define SPI_MEM_C_FREAD_DIO_V 0x00000001U +#define SPI_MEM_C_FREAD_DIO_S 23 +/** SPI_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_C_FREAD_QIO (BIT(24)) +#define SPI_MEM_C_FREAD_QIO_M (SPI_MEM_C_FREAD_QIO_V << SPI_MEM_C_FREAD_QIO_S) +#define SPI_MEM_C_FREAD_QIO_V 0x00000001U +#define SPI_MEM_C_FREAD_QIO_S 24 +/** SPI_MEM_C_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_C_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_C_DQS_IE_ALWAYS_ON_M (SPI_MEM_C_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_C_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_C_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_C_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_C_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_C_DATA_IE_ALWAYS_ON_M (SPI_MEM_C_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_C_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_C_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_C_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI0_BASE + 0xc) +/** SPI_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI_MEM_C_CLK_MODE 0x00000003U +#define SPI_MEM_C_CLK_MODE_M (SPI_MEM_C_CLK_MODE_V << SPI_MEM_C_CLK_MODE_S) +#define SPI_MEM_C_CLK_MODE_V 0x00000003U +#define SPI_MEM_C_CLK_MODE_S 0 +/** SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_M (SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_C_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_MEM_C_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ +#define SPI_MEM_C_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_C_AXI_RDATA_BACK_FAST_M (SPI_MEM_C_AXI_RDATA_BACK_FAST_V << SPI_MEM_C_AXI_RDATA_BACK_FAST_S) +#define SPI_MEM_C_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_MEM_C_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_C_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_C_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_C_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_C_RRESP_ECC_ERR_EN_M (SPI_MEM_C_RRESP_ECC_ERR_EN_V << SPI_MEM_C_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_C_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_C_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_C_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_C_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_C_AR_SPLICE_EN_M (SPI_MEM_C_AR_SPLICE_EN_V << SPI_MEM_C_AR_SPLICE_EN_S) +#define SPI_MEM_C_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_C_AR_SPLICE_EN_S 25 +/** SPI_MEM_C_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_C_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_C_AW_SPLICE_EN_M (SPI_MEM_C_AW_SPLICE_EN_V << SPI_MEM_C_AW_SPLICE_EN_S) +#define SPI_MEM_C_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_C_AW_SPLICE_EN_S 26 +/** SPI_MEM_C_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_C_RAM0_EN (BIT(27)) +#define SPI_MEM_C_RAM0_EN_M (SPI_MEM_C_RAM0_EN_V << SPI_MEM_C_RAM0_EN_S) +#define SPI_MEM_C_RAM0_EN_V 0x00000001U +#define SPI_MEM_C_RAM0_EN_S 27 +/** SPI_MEM_C_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_C_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_C_DUAL_RAM_EN_M (SPI_MEM_C_DUAL_RAM_EN_V << SPI_MEM_C_DUAL_RAM_EN_S) +#define SPI_MEM_C_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_C_DUAL_RAM_EN_S 28 +/** SPI_MEM_C_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_C_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_C_FAST_WRITE_EN_M (SPI_MEM_C_FAST_WRITE_EN_V << SPI_MEM_C_FAST_WRITE_EN_S) +#define SPI_MEM_C_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_C_FAST_WRITE_EN_S 29 +/** SPI_MEM_C_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_C_RXFIFO_RST (BIT(30)) +#define SPI_MEM_C_RXFIFO_RST_M (SPI_MEM_C_RXFIFO_RST_V << SPI_MEM_C_RXFIFO_RST_S) +#define SPI_MEM_C_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_C_RXFIFO_RST_S 30 +/** SPI_MEM_C_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_C_TXFIFO_RST (BIT(31)) +#define SPI_MEM_C_TXFIFO_RST_M (SPI_MEM_C_TXFIFO_RST_V << SPI_MEM_C_TXFIFO_RST_S) +#define SPI_MEM_C_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_C_TXFIFO_RST_S 31 + +/** SPI_MEM_C_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI0_BASE + 0x10) +/** SPI_MEM_C_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_C_CS_SETUP bit. + */ +#define SPI_MEM_C_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_C_CS_SETUP_TIME_M (SPI_MEM_C_CS_SETUP_TIME_V << SPI_MEM_C_CS_SETUP_TIME_S) +#define SPI_MEM_C_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_C_CS_SETUP_TIME_S 0 +/** SPI_MEM_C_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_C_CS_HOLD bit. + */ +#define SPI_MEM_C_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_C_CS_HOLD_TIME_M (SPI_MEM_C_CS_HOLD_TIME_V << SPI_MEM_C_CS_HOLD_TIME_S) +#define SPI_MEM_C_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_C_CS_HOLD_TIME_S 5 +/** SPI_MEM_C_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; + * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_C_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_C_ECC_CS_HOLD_TIME_M (SPI_MEM_C_ECC_CS_HOLD_TIME_V << SPI_MEM_C_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_C_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_C_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_C_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_C_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_C_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_C_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_C_ECC_16TO18_BYTE_EN_M (SPI_MEM_C_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_C_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_C_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_C_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_C_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_C_SPLIT_TRANS_EN_M (SPI_MEM_C_SPLIT_TRANS_EN_V << SPI_MEM_C_SPLIT_TRANS_EN_S) +#define SPI_MEM_C_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_C_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_C_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_C_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_C_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_C_CS_HOLD_DELAY_M (SPI_MEM_C_CS_HOLD_DELAY_V << SPI_MEM_C_CS_HOLD_DELAY_S) +#define SPI_MEM_C_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_C_CS_HOLD_DELAY_S 25 +/** SPI_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_C_SYNC_RESET (BIT(31)) +#define SPI_MEM_C_SYNC_RESET_M (SPI_MEM_C_SYNC_RESET_V << SPI_MEM_C_SYNC_RESET_S) +#define SPI_MEM_C_SYNC_RESET_V 0x00000001U +#define SPI_MEM_C_SYNC_RESET_S 31 + +/** SPI_MEM_C_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI0_BASE + 0x14) +/** SPI_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_C_CLKCNT_L 0x000000FFU +#define SPI_MEM_C_CLKCNT_L_M (SPI_MEM_C_CLKCNT_L_V << SPI_MEM_C_CLKCNT_L_S) +#define SPI_MEM_C_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_C_CLKCNT_L_S 0 +/** SPI_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_C_CLKCNT_H 0x000000FFU +#define SPI_MEM_C_CLKCNT_H_M (SPI_MEM_C_CLKCNT_H_V << SPI_MEM_C_CLKCNT_H_S) +#define SPI_MEM_C_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_C_CLKCNT_H_S 8 +/** SPI_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_C_CLKCNT_N 0x000000FFU +#define SPI_MEM_C_CLKCNT_N_M (SPI_MEM_C_CLKCNT_N_V << SPI_MEM_C_CLKCNT_N_S) +#define SPI_MEM_C_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_C_CLKCNT_N_S 16 +/** SPI_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_C_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_C_CLK_EQU_SYSCLK_M (SPI_MEM_C_CLK_EQU_SYSCLK_V << SPI_MEM_C_CLK_EQU_SYSCLK_S) +#define SPI_MEM_C_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_C_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_C_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_C_USER_REG (DR_REG_FLASH_SPI0_BASE + 0x18) +/** SPI_MEM_C_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_C_CS_HOLD (BIT(6)) +#define SPI_MEM_C_CS_HOLD_M (SPI_MEM_C_CS_HOLD_V << SPI_MEM_C_CS_HOLD_S) +#define SPI_MEM_C_CS_HOLD_V 0x00000001U +#define SPI_MEM_C_CS_HOLD_S 6 +/** SPI_MEM_C_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_C_CS_SETUP (BIT(7)) +#define SPI_MEM_C_CS_SETUP_M (SPI_MEM_C_CS_SETUP_V << SPI_MEM_C_CS_SETUP_S) +#define SPI_MEM_C_CS_SETUP_V 0x00000001U +#define SPI_MEM_C_CS_SETUP_S 7 +/** SPI_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_C_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_C_CK_OUT_EDGE_M (SPI_MEM_C_CK_OUT_EDGE_V << SPI_MEM_C_CK_OUT_EDGE_S) +#define SPI_MEM_C_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_C_CK_OUT_EDGE_S 9 +/** SPI_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_C_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_C_USR_DUMMY_IDLE_M (SPI_MEM_C_USR_DUMMY_IDLE_V << SPI_MEM_C_USR_DUMMY_IDLE_S) +#define SPI_MEM_C_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_C_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_C_USR_DUMMY (BIT(29)) +#define SPI_MEM_C_USR_DUMMY_M (SPI_MEM_C_USR_DUMMY_V << SPI_MEM_C_USR_DUMMY_S) +#define SPI_MEM_C_USR_DUMMY_V 0x00000001U +#define SPI_MEM_C_USR_DUMMY_S 29 + +/** SPI_MEM_C_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_C_USER1_REG (DR_REG_FLASH_SPI0_BASE + 0x1c) +/** SPI_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_C_USR_DUMMY_CYCLELEN_M (SPI_MEM_C_USR_DUMMY_CYCLELEN_V << SPI_MEM_C_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_C_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_C_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_C_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_C_USR_DBYTELEN 0x00000007U +#define SPI_MEM_C_USR_DBYTELEN_M (SPI_MEM_C_USR_DBYTELEN_V << SPI_MEM_C_USR_DBYTELEN_S) +#define SPI_MEM_C_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_C_USR_DBYTELEN_S 6 +/** SPI_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_C_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_C_USR_ADDR_BITLEN_M (SPI_MEM_C_USR_ADDR_BITLEN_V << SPI_MEM_C_USR_ADDR_BITLEN_S) +#define SPI_MEM_C_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_C_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_C_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_C_USER2_REG (DR_REG_FLASH_SPI0_BASE + 0x20) +/** SPI_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_C_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_C_USR_COMMAND_VALUE_M (SPI_MEM_C_USR_COMMAND_VALUE_V << SPI_MEM_C_USR_COMMAND_VALUE_S) +#define SPI_MEM_C_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_C_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_C_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_C_USR_COMMAND_BITLEN_M (SPI_MEM_C_USR_COMMAND_BITLEN_V << SPI_MEM_C_USR_COMMAND_BITLEN_S) +#define SPI_MEM_C_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_C_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_C_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_C_MISC_REG (DR_REG_FLASH_SPI0_BASE + 0x34) +/** SPI_MEM_C_FSUB_PIN : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_C_FSUB_PIN (BIT(7)) +#define SPI_MEM_C_FSUB_PIN_M (SPI_MEM_C_FSUB_PIN_V << SPI_MEM_C_FSUB_PIN_S) +#define SPI_MEM_C_FSUB_PIN_V 0x00000001U +#define SPI_MEM_C_FSUB_PIN_S 7 +/** SPI_MEM_C_SSUB_PIN : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_C_SSUB_PIN (BIT(8)) +#define SPI_MEM_C_SSUB_PIN_M (SPI_MEM_C_SSUB_PIN_V << SPI_MEM_C_SSUB_PIN_S) +#define SPI_MEM_C_SSUB_PIN_V 0x00000001U +#define SPI_MEM_C_SSUB_PIN_S 8 +/** SPI_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_C_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_C_CK_IDLE_EDGE_M (SPI_MEM_C_CK_IDLE_EDGE_V << SPI_MEM_C_CK_IDLE_EDGE_S) +#define SPI_MEM_C_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_C_CK_IDLE_EDGE_S 9 +/** SPI_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_C_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_C_CS_KEEP_ACTIVE_M (SPI_MEM_C_CS_KEEP_ACTIVE_V << SPI_MEM_C_CS_KEEP_ACTIVE_S) +#define SPI_MEM_C_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_C_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_C_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c) +/** SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_MEM_C_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_MEM_C_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_C_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_MEM_C_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_MEM_C_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_C_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_C_SRAM_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x44) +/** SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_C_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ +#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_C_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_C_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_C_FSM_REG (DR_REG_FLASH_SPI0_BASE + 0x54) +/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_C_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME_M (SPI_MEM_C_LOCK_DELAY_TIME_V << SPI_MEM_C_LOCK_DELAY_TIME_S) +#define SPI_MEM_C_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME_S 7 + +/** SPI_MEM_C_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI0_BASE + 0xc0) +/** SPI_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_C_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_C_SLV_ST_END_INT_ENA_M (SPI_MEM_C_SLV_ST_END_INT_ENA_V << SPI_MEM_C_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_C_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_C_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_C_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_C_MST_ST_END_INT_ENA_M (SPI_MEM_C_MST_ST_END_INT_ENA_V << SPI_MEM_C_MST_ST_END_INT_ENA_S) +#define SPI_MEM_C_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_C_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_C_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_C_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_C_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_C_ECC_ERR_INT_ENA_M (SPI_MEM_C_ECC_ERR_INT_ENA_V << SPI_MEM_C_ECC_ERR_INT_ENA_S) +#define SPI_MEM_C_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_C_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_C_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_C_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_C_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_C_PMS_REJECT_INT_ENA_M (SPI_MEM_C_PMS_REJECT_INT_ENA_V << SPI_MEM_C_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_C_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_C_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_C_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_C_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S 9 + +/** SPI_MEM_C_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI0_BASE + 0xc4) +/** SPI_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_C_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_C_SLV_ST_END_INT_CLR_M (SPI_MEM_C_SLV_ST_END_INT_CLR_V << SPI_MEM_C_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_C_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_C_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_C_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_C_MST_ST_END_INT_CLR_M (SPI_MEM_C_MST_ST_END_INT_CLR_V << SPI_MEM_C_MST_ST_END_INT_CLR_S) +#define SPI_MEM_C_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_C_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_C_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_C_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_C_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_C_ECC_ERR_INT_CLR_M (SPI_MEM_C_ECC_ERR_INT_CLR_V << SPI_MEM_C_ECC_ERR_INT_CLR_S) +#define SPI_MEM_C_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_C_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_C_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_C_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_C_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_C_PMS_REJECT_INT_CLR_M (SPI_MEM_C_PMS_REJECT_INT_CLR_V << SPI_MEM_C_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_C_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_C_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_C_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_C_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_C_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S 9 + +/** SPI_MEM_C_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI0_BASE + 0xc8) +/** SPI_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_C_SLV_ST_END_INT_RAW_M (SPI_MEM_C_SLV_ST_END_INT_RAW_V << SPI_MEM_C_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_C_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_C_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_C_MST_ST_END_INT_RAW_M (SPI_MEM_C_MST_ST_END_INT_RAW_V << SPI_MEM_C_MST_ST_END_INT_RAW_S) +#define SPI_MEM_C_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_C_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_C_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set + * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When + * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_C_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_C_ECC_ERR_INT_RAW_M (SPI_MEM_C_ECC_ERR_INT_RAW_V << SPI_MEM_C_ECC_ERR_INT_RAW_S) +#define SPI_MEM_C_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_C_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_C_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_C_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_C_PMS_REJECT_INT_RAW_M (SPI_MEM_C_PMS_REJECT_INT_RAW_V << SPI_MEM_C_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_C_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_C_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_C_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_C_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S 9 + +/** SPI_MEM_C_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI0_BASE + 0xcc) +/** SPI_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_C_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_C_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_C_SLV_ST_END_INT_ST_M (SPI_MEM_C_SLV_ST_END_INT_ST_V << SPI_MEM_C_SLV_ST_END_INT_ST_S) +#define SPI_MEM_C_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_C_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_C_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_C_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_C_MST_ST_END_INT_ST_M (SPI_MEM_C_MST_ST_END_INT_ST_V << SPI_MEM_C_MST_ST_END_INT_ST_S) +#define SPI_MEM_C_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_C_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_C_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_C_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_C_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_C_ECC_ERR_INT_ST_M (SPI_MEM_C_ECC_ERR_INT_ST_V << SPI_MEM_C_ECC_ERR_INT_ST_S) +#define SPI_MEM_C_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_C_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_C_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_C_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_C_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_C_PMS_REJECT_INT_ST_M (SPI_MEM_C_PMS_REJECT_INT_ST_V << SPI_MEM_C_PMS_REJECT_INT_ST_S) +#define SPI_MEM_C_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_C_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_C_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_C_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_C_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S 9 + +/** SPI_MEM_C_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_C_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd4) +/** SPI_MEM_C_FMEM__DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_MEM_C_FMEM__DDR_EN (BIT(0)) +#define SPI_MEM_C_FMEM__DDR_EN_M (SPI_MEM_C_FMEM__DDR_EN_V << SPI_MEM_C_FMEM__DDR_EN_S) +#define SPI_MEM_C_FMEM__DDR_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__DDR_EN_S 0 +/** SPI_MEM_C_FMEM__VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_MEM_C_FMEM__VAR_DUMMY (BIT(1)) +#define SPI_MEM_C_FMEM__VAR_DUMMY_M (SPI_MEM_C_FMEM__VAR_DUMMY_V << SPI_MEM_C_FMEM__VAR_DUMMY_S) +#define SPI_MEM_C_FMEM__VAR_DUMMY_V 0x00000001U +#define SPI_MEM_C_FMEM__VAR_DUMMY_S 1 +/** SPI_MEM_C_FMEM__DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_MEM_C_FMEM__DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_M (SPI_MEM_C_FMEM__DDR_RDAT_SWP_V << SPI_MEM_C_FMEM__DDR_RDAT_SWP_S) +#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_C_FMEM__DDR_RDAT_SWP_S 2 +/** SPI_MEM_C_FMEM__DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_MEM_C_FMEM__DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_M (SPI_MEM_C_FMEM__DDR_WDAT_SWP_V << SPI_MEM_C_FMEM__DDR_WDAT_SWP_S) +#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_C_FMEM__DDR_WDAT_SWP_S 3 +/** SPI_MEM_C_FMEM__DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_MEM_C_FMEM__DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_C_FMEM__DDR_CMD_DIS_M (SPI_MEM_C_FMEM__DDR_CMD_DIS_V << SPI_MEM_C_FMEM__DDR_CMD_DIS_S) +#define SPI_MEM_C_FMEM__DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_C_FMEM__DDR_CMD_DIS_S 4 +/** SPI_MEM_C_FMEM__OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_MEM_C_FMEM__OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_C_FMEM__OUTMINBYTELEN_M (SPI_MEM_C_FMEM__OUTMINBYTELEN_V << SPI_MEM_C_FMEM__OUTMINBYTELEN_S) +#define SPI_MEM_C_FMEM__OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_C_FMEM__OUTMINBYTELEN_S 5 +/** SPI_MEM_C_FMEM__TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_M (SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S) +#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__TX_DDR_MSK_EN_S 12 +/** SPI_MEM_C_FMEM__RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_M (SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V << SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S) +#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__RX_DDR_MSK_EN_S 13 +/** SPI_MEM_C_FMEM__USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_M (SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V << SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S) +#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S 14 +/** SPI_MEM_C_FMEM__DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_MEM_C_FMEM__DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_M (SPI_MEM_C_FMEM__DDR_DQS_LOOP_V << SPI_MEM_C_FMEM__DDR_DQS_LOOP_S) +#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_C_FMEM__DDR_DQS_LOOP_S 21 +/** SPI_MEM_C_FMEM__CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_MEM_C_FMEM__CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_C_FMEM__CLK_DIFF_EN_M (SPI_MEM_C_FMEM__CLK_DIFF_EN_V << SPI_MEM_C_FMEM__CLK_DIFF_EN_S) +#define SPI_MEM_C_FMEM__CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__CLK_DIFF_EN_S 24 +/** SPI_MEM_C_FMEM__DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_MEM_C_FMEM__DQS_CA_IN (BIT(26)) +#define SPI_MEM_C_FMEM__DQS_CA_IN_M (SPI_MEM_C_FMEM__DQS_CA_IN_V << SPI_MEM_C_FMEM__DQS_CA_IN_S) +#define SPI_MEM_C_FMEM__DQS_CA_IN_V 0x00000001U +#define SPI_MEM_C_FMEM__DQS_CA_IN_S 26 +/** SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_M (SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V << SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_C_FMEM__HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_C_FMEM__CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_MEM_C_FMEM__CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_C_FMEM__CLK_DIFF_INV_M (SPI_MEM_C_FMEM__CLK_DIFF_INV_V << SPI_MEM_C_FMEM__CLK_DIFF_INV_S) +#define SPI_MEM_C_FMEM__CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_C_FMEM__CLK_DIFF_INV_S 28 +/** SPI_MEM_C_FMEM__OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_M (SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V << SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S) +#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_C_FMEM__OCTA_RAM_ADDR_S 29 +/** SPI_MEM_C_FMEM__HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_MEM_C_FMEM__HYPERBUS_CA (BIT(30)) +#define SPI_MEM_C_FMEM__HYPERBUS_CA_M (SPI_MEM_C_FMEM__HYPERBUS_CA_V << SPI_MEM_C_FMEM__HYPERBUS_CA_S) +#define SPI_MEM_C_FMEM__HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_C_FMEM__HYPERBUS_CA_S 30 + +/** SPI_MEM_C_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_MEM_C_SMEM_DDR_REG (DR_REG_FLASH_SPI0_BASE + 0xd8) +/** SPI_MEM_C_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_MEM_C_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_C_SMEM_DDR_EN_M (SPI_MEM_C_SMEM_DDR_EN_V << SPI_MEM_C_SMEM_DDR_EN_S) +#define SPI_MEM_C_SMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_DDR_EN_S 0 +/** SPI_MEM_C_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_MEM_C_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_C_SMEM_VAR_DUMMY_M (SPI_MEM_C_SMEM_VAR_DUMMY_V << SPI_MEM_C_SMEM_VAR_DUMMY_S) +#define SPI_MEM_C_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_C_SMEM_VAR_DUMMY_S 1 +/** SPI_MEM_C_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_MEM_C_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_M (SPI_MEM_C_SMEM_DDR_RDAT_SWP_V << SPI_MEM_C_SMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_C_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_C_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_MEM_C_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_M (SPI_MEM_C_SMEM_DDR_WDAT_SWP_V << SPI_MEM_C_SMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_C_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_C_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_MEM_C_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_C_SMEM_DDR_CMD_DIS_M (SPI_MEM_C_SMEM_DDR_CMD_DIS_V << SPI_MEM_C_SMEM_DDR_CMD_DIS_S) +#define SPI_MEM_C_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_C_SMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_C_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_MEM_C_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_C_SMEM_OUTMINBYTELEN_M (SPI_MEM_C_SMEM_OUTMINBYTELEN_V << SPI_MEM_C_SMEM_OUTMINBYTELEN_S) +#define SPI_MEM_C_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_C_SMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_C_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_M (SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S) +#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_MEM_C_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_M (SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S) +#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_MEM_C_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_M (SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_C_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_MEM_C_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_M (SPI_MEM_C_SMEM_DDR_DQS_LOOP_V << SPI_MEM_C_SMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_C_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_C_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_MEM_C_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_C_SMEM_CLK_DIFF_EN_M (SPI_MEM_C_SMEM_CLK_DIFF_EN_V << SPI_MEM_C_SMEM_CLK_DIFF_EN_S) +#define SPI_MEM_C_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_C_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_MEM_C_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_C_SMEM_DQS_CA_IN_M (SPI_MEM_C_SMEM_DQS_CA_IN_V << SPI_MEM_C_SMEM_DQS_CA_IN_S) +#define SPI_MEM_C_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_C_SMEM_DQS_CA_IN_S 26 +/** SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_C_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_C_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_MEM_C_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_C_SMEM_CLK_DIFF_INV_M (SPI_MEM_C_SMEM_CLK_DIFF_INV_V << SPI_MEM_C_SMEM_CLK_DIFF_INV_S) +#define SPI_MEM_C_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_C_SMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_C_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_M (SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_C_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_C_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_MEM_C_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_C_SMEM_HYPERBUS_CA_M (SPI_MEM_C_SMEM_HYPERBUS_CA_V << SPI_MEM_C_SMEM_HYPERBUS_CA_S) +#define SPI_MEM_C_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_C_SMEM_HYPERBUS_CA_S 30 + +/** SPI_MEM_C_FMEM__PMS0_ATTR_REG register + * MSPI flash PMS section 0 attribute register + */ +#define SPI_MEM_C_FMEM__PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x100) +/** SPI_MEM_C_FMEM__PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_M (SPI_MEM_C_FMEM__PMS0_RD_ATTR_V << SPI_MEM_C_FMEM__PMS0_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_RD_ATTR_S 0 +/** SPI_MEM_C_FMEM__PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_M (SPI_MEM_C_FMEM__PMS0_WR_ATTR_V << SPI_MEM_C_FMEM__PMS0_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_WR_ATTR_S 1 +/** SPI_MEM_C_FMEM__PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_MEM_C_FMEM__PMS0_ADDR_REG and + * SPI_MEM_C_FMEM__PMS0_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS0_ECC (BIT(2)) +#define SPI_MEM_C_FMEM__PMS0_ECC_M (SPI_MEM_C_FMEM__PMS0_ECC_V << SPI_MEM_C_FMEM__PMS0_ECC_S) +#define SPI_MEM_C_FMEM__PMS0_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_ECC_S 2 + +/** SPI_MEM_C_FMEM__PMS1_ATTR_REG register + * MSPI flash PMS section 1 attribute register + */ +#define SPI_MEM_C_FMEM__PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x104) +/** SPI_MEM_C_FMEM__PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_M (SPI_MEM_C_FMEM__PMS1_RD_ATTR_V << SPI_MEM_C_FMEM__PMS1_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_RD_ATTR_S 0 +/** SPI_MEM_C_FMEM__PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_M (SPI_MEM_C_FMEM__PMS1_WR_ATTR_V << SPI_MEM_C_FMEM__PMS1_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_WR_ATTR_S 1 +/** SPI_MEM_C_FMEM__PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_MEM_C_FMEM__PMS1_ADDR_REG and + * SPI_MEM_C_FMEM__PMS1_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS1_ECC (BIT(2)) +#define SPI_MEM_C_FMEM__PMS1_ECC_M (SPI_MEM_C_FMEM__PMS1_ECC_V << SPI_MEM_C_FMEM__PMS1_ECC_S) +#define SPI_MEM_C_FMEM__PMS1_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_ECC_S 2 + +/** SPI_MEM_C_FMEM__PMS2_ATTR_REG register + * MSPI flash PMS section 2 attribute register + */ +#define SPI_MEM_C_FMEM__PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x108) +/** SPI_MEM_C_FMEM__PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_M (SPI_MEM_C_FMEM__PMS2_RD_ATTR_V << SPI_MEM_C_FMEM__PMS2_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_RD_ATTR_S 0 +/** SPI_MEM_C_FMEM__PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_M (SPI_MEM_C_FMEM__PMS2_WR_ATTR_V << SPI_MEM_C_FMEM__PMS2_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_WR_ATTR_S 1 +/** SPI_MEM_C_FMEM__PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_MEM_C_FMEM__PMS2_ADDR_REG and + * SPI_MEM_C_FMEM__PMS2_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS2_ECC (BIT(2)) +#define SPI_MEM_C_FMEM__PMS2_ECC_M (SPI_MEM_C_FMEM__PMS2_ECC_V << SPI_MEM_C_FMEM__PMS2_ECC_S) +#define SPI_MEM_C_FMEM__PMS2_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_ECC_S 2 + +/** SPI_MEM_C_FMEM__PMS3_ATTR_REG register + * MSPI flash PMS section 3 attribute register + */ +#define SPI_MEM_C_FMEM__PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x10c) +/** SPI_MEM_C_FMEM__PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_M (SPI_MEM_C_FMEM__PMS3_RD_ATTR_V << SPI_MEM_C_FMEM__PMS3_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_RD_ATTR_S 0 +/** SPI_MEM_C_FMEM__PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_M (SPI_MEM_C_FMEM__PMS3_WR_ATTR_V << SPI_MEM_C_FMEM__PMS3_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_WR_ATTR_S 1 +/** SPI_MEM_C_FMEM__PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_MEM_C_FMEM__PMS3_ADDR_REG and + * SPI_MEM_C_FMEM__PMS3_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS3_ECC (BIT(2)) +#define SPI_MEM_C_FMEM__PMS3_ECC_M (SPI_MEM_C_FMEM__PMS3_ECC_V << SPI_MEM_C_FMEM__PMS3_ECC_S) +#define SPI_MEM_C_FMEM__PMS3_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_ECC_S 2 + +/** SPI_MEM_C_FMEM__PMS0_ADDR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_MEM_C_FMEM__PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x110) +/** SPI_MEM_C_FMEM__PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 0 start address value + */ +#define SPI_MEM_C_FMEM__PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS0_ADDR_S_M (SPI_MEM_C_FMEM__PMS0_ADDR_S_V << SPI_MEM_C_FMEM__PMS0_ADDR_S_S) +#define SPI_MEM_C_FMEM__PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS0_ADDR_S_S 0 + +/** SPI_MEM_C_FMEM__PMS1_ADDR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_MEM_C_FMEM__PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x114) +/** SPI_MEM_C_FMEM__PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 1 start address value + */ +#define SPI_MEM_C_FMEM__PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS1_ADDR_S_M (SPI_MEM_C_FMEM__PMS1_ADDR_S_V << SPI_MEM_C_FMEM__PMS1_ADDR_S_S) +#define SPI_MEM_C_FMEM__PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS1_ADDR_S_S 0 + +/** SPI_MEM_C_FMEM__PMS2_ADDR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_MEM_C_FMEM__PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x118) +/** SPI_MEM_C_FMEM__PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 2 start address value + */ +#define SPI_MEM_C_FMEM__PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS2_ADDR_S_M (SPI_MEM_C_FMEM__PMS2_ADDR_S_V << SPI_MEM_C_FMEM__PMS2_ADDR_S_S) +#define SPI_MEM_C_FMEM__PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS2_ADDR_S_S 0 + +/** SPI_MEM_C_FMEM__PMS3_ADDR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_MEM_C_FMEM__PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x11c) +/** SPI_MEM_C_FMEM__PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 3 start address value + */ +#define SPI_MEM_C_FMEM__PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS3_ADDR_S_M (SPI_MEM_C_FMEM__PMS3_ADDR_S_V << SPI_MEM_C_FMEM__PMS3_ADDR_S_S) +#define SPI_MEM_C_FMEM__PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_FMEM__PMS3_ADDR_S_S 0 + +/** SPI_MEM_C_FMEM__PMS0_SIZE_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_MEM_C_FMEM__PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x120) +/** SPI_MEM_C_FMEM__PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_MEM_C_FMEM__PMS0_ADDR_S, + * SPI_MEM_C_FMEM__PMS0_ADDR_S + SPI_MEM_C_FMEM__PMS0_SIZE) + */ +#define SPI_MEM_C_FMEM__PMS0_SIZE 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS0_SIZE_M (SPI_MEM_C_FMEM__PMS0_SIZE_V << SPI_MEM_C_FMEM__PMS0_SIZE_S) +#define SPI_MEM_C_FMEM__PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS0_SIZE_S 0 + +/** SPI_MEM_C_FMEM__PMS1_SIZE_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_MEM_C_FMEM__PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x124) +/** SPI_MEM_C_FMEM__PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_MEM_C_FMEM__PMS1_ADDR_S, + * SPI_MEM_C_FMEM__PMS1_ADDR_S + SPI_MEM_C_FMEM__PMS1_SIZE) + */ +#define SPI_MEM_C_FMEM__PMS1_SIZE 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS1_SIZE_M (SPI_MEM_C_FMEM__PMS1_SIZE_V << SPI_MEM_C_FMEM__PMS1_SIZE_S) +#define SPI_MEM_C_FMEM__PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS1_SIZE_S 0 + +/** SPI_MEM_C_FMEM__PMS2_SIZE_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_MEM_C_FMEM__PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x128) +/** SPI_MEM_C_FMEM__PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_MEM_C_FMEM__PMS2_ADDR_S, + * SPI_MEM_C_FMEM__PMS2_ADDR_S + SPI_MEM_C_FMEM__PMS2_SIZE) + */ +#define SPI_MEM_C_FMEM__PMS2_SIZE 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS2_SIZE_M (SPI_MEM_C_FMEM__PMS2_SIZE_V << SPI_MEM_C_FMEM__PMS2_SIZE_S) +#define SPI_MEM_C_FMEM__PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS2_SIZE_S 0 + +/** SPI_MEM_C_FMEM__PMS3_SIZE_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_MEM_C_FMEM__PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x12c) +/** SPI_MEM_C_FMEM__PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_MEM_C_FMEM__PMS3_ADDR_S, + * SPI_MEM_C_FMEM__PMS3_ADDR_S + SPI_MEM_C_FMEM__PMS3_SIZE) + */ +#define SPI_MEM_C_FMEM__PMS3_SIZE 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS3_SIZE_M (SPI_MEM_C_FMEM__PMS3_SIZE_V << SPI_MEM_C_FMEM__PMS3_SIZE_S) +#define SPI_MEM_C_FMEM__PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_C_FMEM__PMS3_SIZE_S 0 + +/** SPI_MEM_C_SMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_MEM_C_SMEM_PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x130) +/** SPI_MEM_C_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_M (SPI_MEM_C_SMEM_PMS0_RD_ATTR_V << SPI_MEM_C_SMEM_PMS0_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_MEM_C_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_M (SPI_MEM_C_SMEM_PMS0_WR_ATTR_V << SPI_MEM_C_SMEM_PMS0_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_MEM_C_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG and + * SPI_MEM_C_SMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_C_SMEM_PMS0_ECC_M (SPI_MEM_C_SMEM_PMS0_ECC_V << SPI_MEM_C_SMEM_PMS0_ECC_S) +#define SPI_MEM_C_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_ECC_S 2 + +/** SPI_MEM_C_SMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_MEM_C_SMEM_PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x134) +/** SPI_MEM_C_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_M (SPI_MEM_C_SMEM_PMS1_RD_ATTR_V << SPI_MEM_C_SMEM_PMS1_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_MEM_C_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_M (SPI_MEM_C_SMEM_PMS1_WR_ATTR_V << SPI_MEM_C_SMEM_PMS1_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_MEM_C_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG and + * SPI_MEM_C_SMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_C_SMEM_PMS1_ECC_M (SPI_MEM_C_SMEM_PMS1_ECC_V << SPI_MEM_C_SMEM_PMS1_ECC_S) +#define SPI_MEM_C_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_ECC_S 2 + +/** SPI_MEM_C_SMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_MEM_C_SMEM_PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x138) +/** SPI_MEM_C_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_M (SPI_MEM_C_SMEM_PMS2_RD_ATTR_V << SPI_MEM_C_SMEM_PMS2_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_MEM_C_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_M (SPI_MEM_C_SMEM_PMS2_WR_ATTR_V << SPI_MEM_C_SMEM_PMS2_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_MEM_C_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG and + * SPI_MEM_C_SMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_C_SMEM_PMS2_ECC_M (SPI_MEM_C_SMEM_PMS2_ECC_V << SPI_MEM_C_SMEM_PMS2_ECC_S) +#define SPI_MEM_C_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_ECC_S 2 + +/** SPI_MEM_C_SMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_MEM_C_SMEM_PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x13c) +/** SPI_MEM_C_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_M (SPI_MEM_C_SMEM_PMS3_RD_ATTR_V << SPI_MEM_C_SMEM_PMS3_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_MEM_C_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_M (SPI_MEM_C_SMEM_PMS3_WR_ATTR_V << SPI_MEM_C_SMEM_PMS3_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_MEM_C_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG and + * SPI_MEM_C_SMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_C_SMEM_PMS3_ECC_M (SPI_MEM_C_SMEM_PMS3_ECC_V << SPI_MEM_C_SMEM_PMS3_ECC_S) +#define SPI_MEM_C_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_ECC_S 2 + +/** SPI_MEM_C_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_MEM_C_SMEM_PMS0_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x140) +/** SPI_MEM_C_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 0 start address value + */ +#define SPI_MEM_C_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS0_ADDR_S_M (SPI_MEM_C_SMEM_PMS0_ADDR_S_V << SPI_MEM_C_SMEM_PMS0_ADDR_S_S) +#define SPI_MEM_C_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_MEM_C_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_MEM_C_SMEM_PMS1_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x144) +/** SPI_MEM_C_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value + */ +#define SPI_MEM_C_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS1_ADDR_S_M (SPI_MEM_C_SMEM_PMS1_ADDR_S_V << SPI_MEM_C_SMEM_PMS1_ADDR_S_S) +#define SPI_MEM_C_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_MEM_C_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_MEM_C_SMEM_PMS2_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x148) +/** SPI_MEM_C_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value + */ +#define SPI_MEM_C_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS2_ADDR_S_M (SPI_MEM_C_SMEM_PMS2_ADDR_S_V << SPI_MEM_C_SMEM_PMS2_ADDR_S_S) +#define SPI_MEM_C_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_MEM_C_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_MEM_C_SMEM_PMS3_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x14c) +/** SPI_MEM_C_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value + */ +#define SPI_MEM_C_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS3_ADDR_S_M (SPI_MEM_C_SMEM_PMS3_ADDR_S_V << SPI_MEM_C_SMEM_PMS3_ADDR_S_S) +#define SPI_MEM_C_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_C_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_MEM_C_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_MEM_C_SMEM_PMS0_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x150) +/** SPI_MEM_C_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_MEM_C_SMEM_PMS0_ADDR_S, + * SPI_MEM_C_SMEM_PMS0_ADDR_S + SPI_MEM_C_SMEM_PMS0_SIZE) + */ +#define SPI_MEM_C_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS0_SIZE_M (SPI_MEM_C_SMEM_PMS0_SIZE_V << SPI_MEM_C_SMEM_PMS0_SIZE_S) +#define SPI_MEM_C_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS0_SIZE_S 0 + +/** SPI_MEM_C_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_MEM_C_SMEM_PMS1_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x154) +/** SPI_MEM_C_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_MEM_C_SMEM_PMS1_ADDR_S, + * SPI_MEM_C_SMEM_PMS1_ADDR_S + SPI_MEM_C_SMEM_PMS1_SIZE) + */ +#define SPI_MEM_C_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS1_SIZE_M (SPI_MEM_C_SMEM_PMS1_SIZE_V << SPI_MEM_C_SMEM_PMS1_SIZE_S) +#define SPI_MEM_C_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS1_SIZE_S 0 + +/** SPI_MEM_C_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_MEM_C_SMEM_PMS2_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x158) +/** SPI_MEM_C_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_MEM_C_SMEM_PMS2_ADDR_S, + * SPI_MEM_C_SMEM_PMS2_ADDR_S + SPI_MEM_C_SMEM_PMS2_SIZE) + */ +#define SPI_MEM_C_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS2_SIZE_M (SPI_MEM_C_SMEM_PMS2_SIZE_V << SPI_MEM_C_SMEM_PMS2_SIZE_S) +#define SPI_MEM_C_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS2_SIZE_S 0 + +/** SPI_MEM_C_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_MEM_C_SMEM_PMS3_SIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x15c) +/** SPI_MEM_C_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_MEM_C_SMEM_PMS3_ADDR_S, + * SPI_MEM_C_SMEM_PMS3_ADDR_S + SPI_MEM_C_SMEM_PMS3_SIZE) + */ +#define SPI_MEM_C_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS3_SIZE_M (SPI_MEM_C_SMEM_PMS3_SIZE_V << SPI_MEM_C_SMEM_PMS3_SIZE_S) +#define SPI_MEM_C_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_C_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_C_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_C_PMS_REJECT_REG (DR_REG_FLASH_SPI0_BASE + 0x164) +/** SPI_MEM_C_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_C_REJECT_ADDR 0x07FFFFFFU +#define SPI_MEM_C_REJECT_ADDR_M (SPI_MEM_C_REJECT_ADDR_V << SPI_MEM_C_REJECT_ADDR_S) +#define SPI_MEM_C_REJECT_ADDR_V 0x07FFFFFFU +#define SPI_MEM_C_REJECT_ADDR_S 0 +/** SPI_MEM_C_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_C_PM_EN (BIT(27)) +#define SPI_MEM_C_PM_EN_M (SPI_MEM_C_PM_EN_V << SPI_MEM_C_PM_EN_S) +#define SPI_MEM_C_PM_EN_V 0x00000001U +#define SPI_MEM_C_PM_EN_S 27 +/** SPI_MEM_C_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_C_PMS_LD (BIT(28)) +#define SPI_MEM_C_PMS_LD_M (SPI_MEM_C_PMS_LD_V << SPI_MEM_C_PMS_LD_S) +#define SPI_MEM_C_PMS_LD_V 0x00000001U +#define SPI_MEM_C_PMS_LD_S 28 +/** SPI_MEM_C_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_C_PMS_ST (BIT(29)) +#define SPI_MEM_C_PMS_ST_M (SPI_MEM_C_PMS_ST_V << SPI_MEM_C_PMS_ST_S) +#define SPI_MEM_C_PMS_ST_V 0x00000001U +#define SPI_MEM_C_PMS_ST_S 29 +/** SPI_MEM_C_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_C_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_C_PMS_MULTI_HIT_M (SPI_MEM_C_PMS_MULTI_HIT_V << SPI_MEM_C_PMS_MULTI_HIT_S) +#define SPI_MEM_C_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_C_PMS_MULTI_HIT_S 30 +/** SPI_MEM_C_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_C_PMS_IVD (BIT(31)) +#define SPI_MEM_C_PMS_IVD_M (SPI_MEM_C_PMS_IVD_V << SPI_MEM_C_PMS_IVD_S) +#define SPI_MEM_C_PMS_IVD_V 0x00000001U +#define SPI_MEM_C_PMS_IVD_S 31 + +/** SPI_MEM_C_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_C_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x168) +/** SPI_MEM_C_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_C_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_C_ECC_ERR_CNT_M (SPI_MEM_C_ECC_ERR_CNT_V << SPI_MEM_C_ECC_ERR_CNT_S) +#define SPI_MEM_C_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_C_ECC_ERR_CNT_S 5 +/** SPI_MEM_C_FMEM__ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM 0x0000003FU +#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_M (SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V << SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S) +#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S 11 +/** SPI_MEM_C_FMEM__ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_M (SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V << SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S) +#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__ECC_ERR_INT_EN_S 17 +/** SPI_MEM_C_FMEM__PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_MEM_C_FMEM__PAGE_SIZE 0x00000003U +#define SPI_MEM_C_FMEM__PAGE_SIZE_M (SPI_MEM_C_FMEM__PAGE_SIZE_V << SPI_MEM_C_FMEM__PAGE_SIZE_S) +#define SPI_MEM_C_FMEM__PAGE_SIZE_V 0x00000003U +#define SPI_MEM_C_FMEM__PAGE_SIZE_S 18 +/** SPI_MEM_C_FMEM__ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_MEM_C_FMEM__ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_C_FMEM__ECC_ADDR_EN_M (SPI_MEM_C_FMEM__ECC_ADDR_EN_V << SPI_MEM_C_FMEM__ECC_ADDR_EN_S) +#define SPI_MEM_C_FMEM__ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_C_FMEM__ECC_ADDR_EN_S 20 +/** SPI_MEM_C_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_C_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_C_USR_ECC_ADDR_EN_M (SPI_MEM_C_USR_ECC_ADDR_EN_V << SPI_MEM_C_USR_ECC_ADDR_EN_S) +#define SPI_MEM_C_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_C_USR_ECC_ADDR_EN_S 21 +/** SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_C_ECC_ERR_BITS and SPI_MEM_C_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_C_ECC_ERR_BITS and + * SPI_MEM_C_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_C_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_C_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_C_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_C_ECC_ERR_BITS_M (SPI_MEM_C_ECC_ERR_BITS_V << SPI_MEM_C_ECC_ERR_BITS_S) +#define SPI_MEM_C_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_C_ECC_ERR_BITS_S 25 + +/** SPI_MEM_C_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_C_ECC_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x16c) +/** SPI_MEM_C_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_C_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_C_ECC_ERR_ADDR_M (SPI_MEM_C_ECC_ERR_ADDR_V << SPI_MEM_C_ECC_ERR_ADDR_S) +#define SPI_MEM_C_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_C_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_C_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_C_AXI_ERR_ADDR_REG (DR_REG_FLASH_SPI0_BASE + 0x170) +/** SPI_MEM_C_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_C_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_C_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_C_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_C_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_C_AXI_ERR_ADDR_M (SPI_MEM_C_AXI_ERR_ADDR_V << SPI_MEM_C_AXI_ERR_ADDR_S) +#define SPI_MEM_C_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_C_AXI_ERR_ADDR_S 0 + +/** SPI_MEM_C_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_C_SMEM_ECC_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x174) +/** SPI_MEM_C_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_M (SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S) +#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_MEM_C_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_MEM_C_SMEM_PAGE_SIZE 0x00000003U +#define SPI_MEM_C_SMEM_PAGE_SIZE_M (SPI_MEM_C_SMEM_PAGE_SIZE_V << SPI_MEM_C_SMEM_PAGE_SIZE_S) +#define SPI_MEM_C_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_C_SMEM_PAGE_SIZE_S 18 +/** SPI_MEM_C_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_MEM_C_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_C_SMEM_ECC_ADDR_EN_M (SPI_MEM_C_SMEM_ECC_ADDR_EN_V << SPI_MEM_C_SMEM_ECC_ADDR_EN_S) +#define SPI_MEM_C_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_MEM_C_SMEM_AXI_ADDR_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x178) +/** SPI_MEM_C_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_C_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_C_ALL_FIFO_EMPTY_M (SPI_MEM_C_ALL_FIFO_EMPTY_V << SPI_MEM_C_ALL_FIFO_EMPTY_S) +#define SPI_MEM_C_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_C_ALL_FIFO_EMPTY_S 26 +/** SPI_MEM_C_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_MEM_C_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_C_RDATA_AFIFO_REMPTY_M (SPI_MEM_C_RDATA_AFIFO_REMPTY_V << SPI_MEM_C_RDATA_AFIFO_REMPTY_S) +#define SPI_MEM_C_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_C_RDATA_AFIFO_REMPTY_S 27 +/** SPI_MEM_C_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_MEM_C_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_C_RADDR_AFIFO_REMPTY_M (SPI_MEM_C_RADDR_AFIFO_REMPTY_V << SPI_MEM_C_RADDR_AFIFO_REMPTY_S) +#define SPI_MEM_C_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_C_RADDR_AFIFO_REMPTY_S 28 +/** SPI_MEM_C_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_MEM_C_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_C_WDATA_AFIFO_REMPTY_M (SPI_MEM_C_WDATA_AFIFO_REMPTY_V << SPI_MEM_C_WDATA_AFIFO_REMPTY_S) +#define SPI_MEM_C_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_C_WDATA_AFIFO_REMPTY_S 29 +/** SPI_MEM_C_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_MEM_C_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_M (SPI_MEM_C_WBLEN_AFIFO_REMPTY_V << SPI_MEM_C_WBLEN_AFIFO_REMPTY_S) +#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_C_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_MEM_C_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_C_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_C_AXI_ERR_RESP_EN_REG (DR_REG_FLASH_SPI0_BASE + 0x17c) +/** SPI_MEM_C_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_M (SPI_MEM_C_AW_RESP_EN_MMU_VLD_V << SPI_MEM_C_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_C_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_C_AW_RESP_EN_MMU_GID_M (SPI_MEM_C_AW_RESP_EN_MMU_GID_V << SPI_MEM_C_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_C_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_C_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_C_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_C_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_M (SPI_MEM_C_AW_RESP_EN_MMU_ECC_V << SPI_MEM_C_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_C_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_M (SPI_MEM_C_AW_RESP_EN_MMU_SENS_V << SPI_MEM_C_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_C_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_C_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_C_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_C_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_M (SPI_MEM_C_AR_RESP_EN_MMU_VLD_V << SPI_MEM_C_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_C_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_C_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_C_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_C_AR_RESP_EN_MMU_GID_M (SPI_MEM_C_AR_RESP_EN_MMU_GID_V << SPI_MEM_C_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_C_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_C_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_C_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_C_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_M (SPI_MEM_C_AR_RESP_EN_MMU_ECC_V << SPI_MEM_C_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_C_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_C_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_C_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_M (SPI_MEM_C_AR_RESP_EN_MMU_SENS_V << SPI_MEM_C_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_C_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_C_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_C_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_C_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x180) +/** SPI_MEM_C_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_C_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_C_TIMING_CLK_ENA_M (SPI_MEM_C_TIMING_CLK_ENA_V << SPI_MEM_C_TIMING_CLK_ENA_S) +#define SPI_MEM_C_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_C_TIMING_CLK_ENA_S 0 +/** SPI_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_C_TIMING_CALI (BIT(1)) +#define SPI_MEM_C_TIMING_CALI_M (SPI_MEM_C_TIMING_CALI_V << SPI_MEM_C_TIMING_CALI_S) +#define SPI_MEM_C_TIMING_CALI_V 0x00000001U +#define SPI_MEM_C_TIMING_CALI_S 1 +/** SPI_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_C_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_C_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_C_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_C_DLL_TIMING_CALI_M (SPI_MEM_C_DLL_TIMING_CALI_V << SPI_MEM_C_DLL_TIMING_CALI_S) +#define SPI_MEM_C_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_C_DLL_TIMING_CALI_S 5 +/** SPI_MEM_C_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_C_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_C_TIMING_CALI_UPDATE_M (SPI_MEM_C_TIMING_CALI_UPDATE_V << SPI_MEM_C_TIMING_CALI_UPDATE_S) +#define SPI_MEM_C_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_C_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_C_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_C_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x184) +/** SPI_MEM_C_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_DIN0_MODE 0x00000007U +#define SPI_MEM_C_DIN0_MODE_M (SPI_MEM_C_DIN0_MODE_V << SPI_MEM_C_DIN0_MODE_S) +#define SPI_MEM_C_DIN0_MODE_V 0x00000007U +#define SPI_MEM_C_DIN0_MODE_S 0 +/** SPI_MEM_C_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_DIN1_MODE 0x00000007U +#define SPI_MEM_C_DIN1_MODE_M (SPI_MEM_C_DIN1_MODE_V << SPI_MEM_C_DIN1_MODE_S) +#define SPI_MEM_C_DIN1_MODE_V 0x00000007U +#define SPI_MEM_C_DIN1_MODE_S 3 +/** SPI_MEM_C_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_DIN2_MODE 0x00000007U +#define SPI_MEM_C_DIN2_MODE_M (SPI_MEM_C_DIN2_MODE_V << SPI_MEM_C_DIN2_MODE_S) +#define SPI_MEM_C_DIN2_MODE_V 0x00000007U +#define SPI_MEM_C_DIN2_MODE_S 6 +/** SPI_MEM_C_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_DIN3_MODE 0x00000007U +#define SPI_MEM_C_DIN3_MODE_M (SPI_MEM_C_DIN3_MODE_V << SPI_MEM_C_DIN3_MODE_S) +#define SPI_MEM_C_DIN3_MODE_V 0x00000007U +#define SPI_MEM_C_DIN3_MODE_S 9 +/** SPI_MEM_C_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_C_DIN4_MODE 0x00000007U +#define SPI_MEM_C_DIN4_MODE_M (SPI_MEM_C_DIN4_MODE_V << SPI_MEM_C_DIN4_MODE_S) +#define SPI_MEM_C_DIN4_MODE_V 0x00000007U +#define SPI_MEM_C_DIN4_MODE_S 12 +/** SPI_MEM_C_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_C_DIN5_MODE 0x00000007U +#define SPI_MEM_C_DIN5_MODE_M (SPI_MEM_C_DIN5_MODE_V << SPI_MEM_C_DIN5_MODE_S) +#define SPI_MEM_C_DIN5_MODE_V 0x00000007U +#define SPI_MEM_C_DIN5_MODE_S 15 +/** SPI_MEM_C_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_C_DIN6_MODE 0x00000007U +#define SPI_MEM_C_DIN6_MODE_M (SPI_MEM_C_DIN6_MODE_V << SPI_MEM_C_DIN6_MODE_S) +#define SPI_MEM_C_DIN6_MODE_V 0x00000007U +#define SPI_MEM_C_DIN6_MODE_S 18 +/** SPI_MEM_C_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_C_DIN7_MODE 0x00000007U +#define SPI_MEM_C_DIN7_MODE_M (SPI_MEM_C_DIN7_MODE_V << SPI_MEM_C_DIN7_MODE_S) +#define SPI_MEM_C_DIN7_MODE_V 0x00000007U +#define SPI_MEM_C_DIN7_MODE_S 21 +/** SPI_MEM_C_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_C_DINS_MODE 0x00000007U +#define SPI_MEM_C_DINS_MODE_M (SPI_MEM_C_DINS_MODE_V << SPI_MEM_C_DINS_MODE_S) +#define SPI_MEM_C_DINS_MODE_V 0x00000007U +#define SPI_MEM_C_DINS_MODE_S 24 + +/** SPI_MEM_C_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_C_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x188) +/** SPI_MEM_C_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN0_NUM 0x00000003U +#define SPI_MEM_C_DIN0_NUM_M (SPI_MEM_C_DIN0_NUM_V << SPI_MEM_C_DIN0_NUM_S) +#define SPI_MEM_C_DIN0_NUM_V 0x00000003U +#define SPI_MEM_C_DIN0_NUM_S 0 +/** SPI_MEM_C_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN1_NUM 0x00000003U +#define SPI_MEM_C_DIN1_NUM_M (SPI_MEM_C_DIN1_NUM_V << SPI_MEM_C_DIN1_NUM_S) +#define SPI_MEM_C_DIN1_NUM_V 0x00000003U +#define SPI_MEM_C_DIN1_NUM_S 2 +/** SPI_MEM_C_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN2_NUM 0x00000003U +#define SPI_MEM_C_DIN2_NUM_M (SPI_MEM_C_DIN2_NUM_V << SPI_MEM_C_DIN2_NUM_S) +#define SPI_MEM_C_DIN2_NUM_V 0x00000003U +#define SPI_MEM_C_DIN2_NUM_S 4 +/** SPI_MEM_C_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN3_NUM 0x00000003U +#define SPI_MEM_C_DIN3_NUM_M (SPI_MEM_C_DIN3_NUM_V << SPI_MEM_C_DIN3_NUM_S) +#define SPI_MEM_C_DIN3_NUM_V 0x00000003U +#define SPI_MEM_C_DIN3_NUM_S 6 +/** SPI_MEM_C_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN4_NUM 0x00000003U +#define SPI_MEM_C_DIN4_NUM_M (SPI_MEM_C_DIN4_NUM_V << SPI_MEM_C_DIN4_NUM_S) +#define SPI_MEM_C_DIN4_NUM_V 0x00000003U +#define SPI_MEM_C_DIN4_NUM_S 8 +/** SPI_MEM_C_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN5_NUM 0x00000003U +#define SPI_MEM_C_DIN5_NUM_M (SPI_MEM_C_DIN5_NUM_V << SPI_MEM_C_DIN5_NUM_S) +#define SPI_MEM_C_DIN5_NUM_V 0x00000003U +#define SPI_MEM_C_DIN5_NUM_S 10 +/** SPI_MEM_C_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN6_NUM 0x00000003U +#define SPI_MEM_C_DIN6_NUM_M (SPI_MEM_C_DIN6_NUM_V << SPI_MEM_C_DIN6_NUM_S) +#define SPI_MEM_C_DIN6_NUM_V 0x00000003U +#define SPI_MEM_C_DIN6_NUM_S 12 +/** SPI_MEM_C_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DIN7_NUM 0x00000003U +#define SPI_MEM_C_DIN7_NUM_M (SPI_MEM_C_DIN7_NUM_V << SPI_MEM_C_DIN7_NUM_S) +#define SPI_MEM_C_DIN7_NUM_V 0x00000003U +#define SPI_MEM_C_DIN7_NUM_S 14 +/** SPI_MEM_C_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_DINS_NUM 0x00000003U +#define SPI_MEM_C_DINS_NUM_M (SPI_MEM_C_DINS_NUM_V << SPI_MEM_C_DINS_NUM_S) +#define SPI_MEM_C_DINS_NUM_V 0x00000003U +#define SPI_MEM_C_DINS_NUM_S 16 + +/** SPI_MEM_C_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_C_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x18c) +/** SPI_MEM_C_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_DOUT0_MODE (BIT(0)) +#define SPI_MEM_C_DOUT0_MODE_M (SPI_MEM_C_DOUT0_MODE_V << SPI_MEM_C_DOUT0_MODE_S) +#define SPI_MEM_C_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT0_MODE_S 0 +/** SPI_MEM_C_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_DOUT1_MODE (BIT(1)) +#define SPI_MEM_C_DOUT1_MODE_M (SPI_MEM_C_DOUT1_MODE_V << SPI_MEM_C_DOUT1_MODE_S) +#define SPI_MEM_C_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT1_MODE_S 1 +/** SPI_MEM_C_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_DOUT2_MODE (BIT(2)) +#define SPI_MEM_C_DOUT2_MODE_M (SPI_MEM_C_DOUT2_MODE_V << SPI_MEM_C_DOUT2_MODE_S) +#define SPI_MEM_C_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT2_MODE_S 2 +/** SPI_MEM_C_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_DOUT3_MODE (BIT(3)) +#define SPI_MEM_C_DOUT3_MODE_M (SPI_MEM_C_DOUT3_MODE_V << SPI_MEM_C_DOUT3_MODE_S) +#define SPI_MEM_C_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT3_MODE_S 3 +/** SPI_MEM_C_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_C_DOUT4_MODE (BIT(4)) +#define SPI_MEM_C_DOUT4_MODE_M (SPI_MEM_C_DOUT4_MODE_V << SPI_MEM_C_DOUT4_MODE_S) +#define SPI_MEM_C_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT4_MODE_S 4 +/** SPI_MEM_C_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_C_DOUT5_MODE (BIT(5)) +#define SPI_MEM_C_DOUT5_MODE_M (SPI_MEM_C_DOUT5_MODE_V << SPI_MEM_C_DOUT5_MODE_S) +#define SPI_MEM_C_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT5_MODE_S 5 +/** SPI_MEM_C_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_C_DOUT6_MODE (BIT(6)) +#define SPI_MEM_C_DOUT6_MODE_M (SPI_MEM_C_DOUT6_MODE_V << SPI_MEM_C_DOUT6_MODE_S) +#define SPI_MEM_C_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT6_MODE_S 6 +/** SPI_MEM_C_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_C_DOUT7_MODE (BIT(7)) +#define SPI_MEM_C_DOUT7_MODE_M (SPI_MEM_C_DOUT7_MODE_V << SPI_MEM_C_DOUT7_MODE_S) +#define SPI_MEM_C_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_C_DOUT7_MODE_S 7 +/** SPI_MEM_C_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_C_DOUTS_MODE (BIT(8)) +#define SPI_MEM_C_DOUTS_MODE_M (SPI_MEM_C_DOUTS_MODE_V << SPI_MEM_C_DOUTS_MODE_S) +#define SPI_MEM_C_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_C_DOUTS_MODE_S 8 + +/** SPI_MEM_C_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_MEM_C_SMEM_TIMING_CALI_REG (DR_REG_FLASH_SPI0_BASE + 0x190) +/** SPI_MEM_C_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_C_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_M (SPI_MEM_C_SMEM_TIMING_CLK_ENA_V << SPI_MEM_C_SMEM_TIMING_CLK_ENA_S) +#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_C_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_C_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_MEM_C_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_C_SMEM_TIMING_CALI_M (SPI_MEM_C_SMEM_TIMING_CALI_V << SPI_MEM_C_SMEM_TIMING_CALI_S) +#define SPI_MEM_C_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_C_SMEM_TIMING_CALI_S 1 +/** SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_C_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_C_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_MEM_C_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_M (SPI_MEM_C_SMEM_DLL_TIMING_CALI_V << SPI_MEM_C_SMEM_DLL_TIMING_CALI_S) +#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_C_SMEM_DLL_TIMING_CALI_S 5 + +/** SPI_MEM_C_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_MEM_C_SMEM_DIN_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x194) +/** SPI_MEM_C_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN0_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN0_MODE_M (SPI_MEM_C_SMEM_DIN0_MODE_V << SPI_MEM_C_SMEM_DIN0_MODE_S) +#define SPI_MEM_C_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN0_MODE_S 0 +/** SPI_MEM_C_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN1_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN1_MODE_M (SPI_MEM_C_SMEM_DIN1_MODE_V << SPI_MEM_C_SMEM_DIN1_MODE_S) +#define SPI_MEM_C_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN1_MODE_S 3 +/** SPI_MEM_C_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN2_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN2_MODE_M (SPI_MEM_C_SMEM_DIN2_MODE_V << SPI_MEM_C_SMEM_DIN2_MODE_S) +#define SPI_MEM_C_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN2_MODE_S 6 +/** SPI_MEM_C_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN3_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN3_MODE_M (SPI_MEM_C_SMEM_DIN3_MODE_V << SPI_MEM_C_SMEM_DIN3_MODE_S) +#define SPI_MEM_C_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN3_MODE_S 9 +/** SPI_MEM_C_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN4_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN4_MODE_M (SPI_MEM_C_SMEM_DIN4_MODE_V << SPI_MEM_C_SMEM_DIN4_MODE_S) +#define SPI_MEM_C_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN4_MODE_S 12 +/** SPI_MEM_C_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN5_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN5_MODE_M (SPI_MEM_C_SMEM_DIN5_MODE_V << SPI_MEM_C_SMEM_DIN5_MODE_S) +#define SPI_MEM_C_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN5_MODE_S 15 +/** SPI_MEM_C_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN6_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN6_MODE_M (SPI_MEM_C_SMEM_DIN6_MODE_V << SPI_MEM_C_SMEM_DIN6_MODE_S) +#define SPI_MEM_C_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN6_MODE_S 18 +/** SPI_MEM_C_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DIN7_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DIN7_MODE_M (SPI_MEM_C_SMEM_DIN7_MODE_V << SPI_MEM_C_SMEM_DIN7_MODE_S) +#define SPI_MEM_C_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DIN7_MODE_S 21 +/** SPI_MEM_C_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DINS_MODE 0x00000007U +#define SPI_MEM_C_SMEM_DINS_MODE_M (SPI_MEM_C_SMEM_DINS_MODE_V << SPI_MEM_C_SMEM_DINS_MODE_S) +#define SPI_MEM_C_SMEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_C_SMEM_DINS_MODE_S 24 + +/** SPI_MEM_C_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_MEM_C_SMEM_DIN_NUM_REG (DR_REG_FLASH_SPI0_BASE + 0x198) +/** SPI_MEM_C_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN0_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN0_NUM_M (SPI_MEM_C_SMEM_DIN0_NUM_V << SPI_MEM_C_SMEM_DIN0_NUM_S) +#define SPI_MEM_C_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN0_NUM_S 0 +/** SPI_MEM_C_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN1_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN1_NUM_M (SPI_MEM_C_SMEM_DIN1_NUM_V << SPI_MEM_C_SMEM_DIN1_NUM_S) +#define SPI_MEM_C_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN1_NUM_S 2 +/** SPI_MEM_C_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN2_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN2_NUM_M (SPI_MEM_C_SMEM_DIN2_NUM_V << SPI_MEM_C_SMEM_DIN2_NUM_S) +#define SPI_MEM_C_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN2_NUM_S 4 +/** SPI_MEM_C_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN3_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN3_NUM_M (SPI_MEM_C_SMEM_DIN3_NUM_V << SPI_MEM_C_SMEM_DIN3_NUM_S) +#define SPI_MEM_C_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN3_NUM_S 6 +/** SPI_MEM_C_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN4_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN4_NUM_M (SPI_MEM_C_SMEM_DIN4_NUM_V << SPI_MEM_C_SMEM_DIN4_NUM_S) +#define SPI_MEM_C_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN4_NUM_S 8 +/** SPI_MEM_C_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN5_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN5_NUM_M (SPI_MEM_C_SMEM_DIN5_NUM_V << SPI_MEM_C_SMEM_DIN5_NUM_S) +#define SPI_MEM_C_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN5_NUM_S 10 +/** SPI_MEM_C_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN6_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN6_NUM_M (SPI_MEM_C_SMEM_DIN6_NUM_V << SPI_MEM_C_SMEM_DIN6_NUM_S) +#define SPI_MEM_C_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN6_NUM_S 12 +/** SPI_MEM_C_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DIN7_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DIN7_NUM_M (SPI_MEM_C_SMEM_DIN7_NUM_V << SPI_MEM_C_SMEM_DIN7_NUM_S) +#define SPI_MEM_C_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DIN7_NUM_S 14 +/** SPI_MEM_C_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_C_SMEM_DINS_NUM 0x00000003U +#define SPI_MEM_C_SMEM_DINS_NUM_M (SPI_MEM_C_SMEM_DINS_NUM_V << SPI_MEM_C_SMEM_DINS_NUM_S) +#define SPI_MEM_C_SMEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_C_SMEM_DINS_NUM_S 16 + +/** SPI_MEM_C_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_MEM_C_SMEM_DOUT_MODE_REG (DR_REG_FLASH_SPI0_BASE + 0x19c) +/** SPI_MEM_C_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_C_SMEM_DOUT0_MODE_M (SPI_MEM_C_SMEM_DOUT0_MODE_V << SPI_MEM_C_SMEM_DOUT0_MODE_S) +#define SPI_MEM_C_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT0_MODE_S 0 +/** SPI_MEM_C_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_C_SMEM_DOUT1_MODE_M (SPI_MEM_C_SMEM_DOUT1_MODE_V << SPI_MEM_C_SMEM_DOUT1_MODE_S) +#define SPI_MEM_C_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT1_MODE_S 1 +/** SPI_MEM_C_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_C_SMEM_DOUT2_MODE_M (SPI_MEM_C_SMEM_DOUT2_MODE_V << SPI_MEM_C_SMEM_DOUT2_MODE_S) +#define SPI_MEM_C_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT2_MODE_S 2 +/** SPI_MEM_C_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_C_SMEM_DOUT3_MODE_M (SPI_MEM_C_SMEM_DOUT3_MODE_V << SPI_MEM_C_SMEM_DOUT3_MODE_S) +#define SPI_MEM_C_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT3_MODE_S 3 +/** SPI_MEM_C_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_C_SMEM_DOUT4_MODE_M (SPI_MEM_C_SMEM_DOUT4_MODE_V << SPI_MEM_C_SMEM_DOUT4_MODE_S) +#define SPI_MEM_C_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT4_MODE_S 4 +/** SPI_MEM_C_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_C_SMEM_DOUT5_MODE_M (SPI_MEM_C_SMEM_DOUT5_MODE_V << SPI_MEM_C_SMEM_DOUT5_MODE_S) +#define SPI_MEM_C_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT5_MODE_S 5 +/** SPI_MEM_C_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_C_SMEM_DOUT6_MODE_M (SPI_MEM_C_SMEM_DOUT6_MODE_V << SPI_MEM_C_SMEM_DOUT6_MODE_S) +#define SPI_MEM_C_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT6_MODE_S 6 +/** SPI_MEM_C_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_C_SMEM_DOUT7_MODE_M (SPI_MEM_C_SMEM_DOUT7_MODE_V << SPI_MEM_C_SMEM_DOUT7_MODE_S) +#define SPI_MEM_C_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUT7_MODE_S 7 +/** SPI_MEM_C_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_C_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_C_SMEM_DOUTS_MODE_M (SPI_MEM_C_SMEM_DOUTS_MODE_V << SPI_MEM_C_SMEM_DOUTS_MODE_S) +#define SPI_MEM_C_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_C_SMEM_DOUTS_MODE_S 8 + +/** SPI_MEM_C_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_MEM_C_SMEM_AC_REG (DR_REG_FLASH_SPI0_BASE + 0x1a0) +/** SPI_MEM_C_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_MEM_C_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_C_SMEM_CS_SETUP_M (SPI_MEM_C_SMEM_CS_SETUP_V << SPI_MEM_C_SMEM_CS_SETUP_S) +#define SPI_MEM_C_SMEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_C_SMEM_CS_SETUP_S 0 +/** SPI_MEM_C_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_C_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_C_SMEM_CS_HOLD_M (SPI_MEM_C_SMEM_CS_HOLD_V << SPI_MEM_C_SMEM_CS_HOLD_S) +#define SPI_MEM_C_SMEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_C_SMEM_CS_HOLD_S 1 +/** SPI_MEM_C_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_MEM_C_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_C_SMEM_CS_SETUP_TIME_M (SPI_MEM_C_SMEM_CS_SETUP_TIME_V << SPI_MEM_C_SMEM_CS_SETUP_TIME_S) +#define SPI_MEM_C_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_C_SMEM_CS_SETUP_TIME_S 2 +/** SPI_MEM_C_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_MEM_C_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_C_SMEM_CS_HOLD_TIME_M (SPI_MEM_C_SMEM_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_CS_HOLD_TIME_S) +#define SPI_MEM_C_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_C_SMEM_CS_HOLD_TIME_S 7 +/** SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_C_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_MEM_C_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_MEM_C_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_M (SPI_MEM_C_SMEM_CS_HOLD_DELAY_V << SPI_MEM_C_SMEM_CS_HOLD_DELAY_S) +#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_C_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_C_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_M (SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_C_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_MEM_C_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI0_BASE + 0x200) +/** SPI_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_MEM_C_CLK_EN (BIT(0)) +#define SPI_MEM_C_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_MEM_C_CLK_EN_V 0x00000001U +#define SPI_MEM_C_CLK_EN_S 0 + +/** SPI_MEM_C_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_C_XTS_PLAIN_BASE_REG (DR_REG_FLASH_SPI0_BASE + 0x300) +/** SPI_MEM_C_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_MEM_C_XTS_PLAIN 0xFFFFFFFFU +#define SPI_MEM_C_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_MEM_C_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_MEM_C_XTS_PLAIN_S 0 + +/** SPI_MEM_C_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_C_XTS_LINESIZE_REG (DR_REG_FLASH_SPI0_BASE + 0x340) +/** SPI_MEM_C_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_MEM_C_XTS_LINESIZE 0x00000003U +#define SPI_MEM_C_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_MEM_C_XTS_LINESIZE_V 0x00000003U +#define SPI_MEM_C_XTS_LINESIZE_S 0 + +/** SPI_MEM_C_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_C_XTS_DESTINATION_REG (DR_REG_FLASH_SPI0_BASE + 0x344) +/** SPI_MEM_C_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_MEM_C_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_C_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_MEM_C_XTS_DESTINATION_V 0x00000001U +#define SPI_MEM_C_XTS_DESTINATION_S 0 + +/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG (DR_REG_FLASH_SPI0_BASE + 0x348) +/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_C_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_C_XTS_TRIGGER_REG (DR_REG_FLASH_SPI0_BASE + 0x34c) +/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_XTS_TRIGGER (BIT(0)) +#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_XTS_TRIGGER_V 0x00000001U +#define SPI_XTS_TRIGGER_S 0 + +/** SPI_MEM_C_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_C_XTS_RELEASE_REG (DR_REG_FLASH_SPI0_BASE + 0x350) +/** SPI_MEM_C_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_MEM_C_XTS_RELEASE (BIT(0)) +#define SPI_MEM_C_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_MEM_C_XTS_RELEASE_V 0x00000001U +#define SPI_MEM_C_XTS_RELEASE_S 0 + +/** SPI_MEM_C_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_C_XTS_DESTROY_REG (DR_REG_FLASH_SPI0_BASE + 0x354) +/** SPI_MEM_C_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_MEM_C_XTS_DESTROY (BIT(0)) +#define SPI_MEM_C_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_MEM_C_XTS_DESTROY_V 0x00000001U +#define SPI_MEM_C_XTS_DESTROY_S 0 + +/** SPI_MEM_C_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_C_XTS_STATE_REG (DR_REG_FLASH_SPI0_BASE + 0x358) +/** SPI_MEM_C_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_MEM_C_XTS_STATE 0x00000003U +#define SPI_MEM_C_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_MEM_C_XTS_STATE_V 0x00000003U +#define SPI_MEM_C_XTS_STATE_S 0 + +/** SPI_MEM_C_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_C_XTS_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x35c) +/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_MEM_C_XTS_DATE 0x3FFFFFFFU +#define SPI_MEM_C_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_MEM_C_XTS_DATE_V 0x3FFFFFFFU +#define SPI_MEM_C_XTS_DATE_S 0 + +/** SPI_MEM_C_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_C_MMU_ITEM_CONTENT_REG (DR_REG_FLASH_SPI0_BASE + 0x37c) +/** SPI_MEM_C_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MEM_C_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MEM_C_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MEM_C_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MEM_C_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_C_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_C_MMU_ITEM_INDEX_REG (DR_REG_FLASH_SPI0_BASE + 0x380) +/** SPI_MEM_C_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MEM_C_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MEM_C_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MEM_C_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MEM_C_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_C_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_C_MMU_POWER_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x384) +/** SPI_MEM_C_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MEM_C_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_C_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MEM_C_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MEM_C_MMU_MEM_FORCE_ON_S 0 +/** SPI_MEM_C_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MEM_C_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_C_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MEM_C_MMU_MEM_FORCE_PD_S 1 +/** SPI_MEM_C_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MEM_C_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_C_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MEM_C_MMU_MEM_FORCE_PU_S 2 +/** SPI_MEM_C_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MEM_C_MMU_PAGE_SIZE 0x00000003U +#define SPI_MEM_C_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MEM_C_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_C_MMU_PAGE_SIZE_S 3 +/** SPI_MEM_C_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_C_AUX_CTRL 0x00003FFFU +#define SPI_MEM_C_AUX_CTRL_M (SPI_MEM_C_AUX_CTRL_V << SPI_MEM_C_AUX_CTRL_S) +#define SPI_MEM_C_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_C_AUX_CTRL_S 16 + +/** SPI_MEM_C_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_C_DPA_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x388) +/** SPI_MEM_C_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_MEM_C_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_C_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_C_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x3fc) +/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ +#define SPI_MEM_C_DATE 0x0FFFFFFFU +#define SPI_MEM_C_DATE_M (SPI_MEM_C_DATE_V << SPI_MEM_C_DATE_S) +#define SPI_MEM_C_DATE_V 0x0FFFFFFFU +#define SPI_MEM_C_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_struct.h new file mode 100644 index 0000000000..9ddcb3f6ce --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_c_struct.h @@ -0,0 +1,2028 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:10; + /** usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_c_cmd_reg_t; + +/** Type of axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR, + * spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t axi_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t wdummy_dqs_always_out:1; + /** wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t wdummy_always_out:1; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + uint32_t reserved_10:3; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT + * and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + uint32_t reserved_15:3; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + uint32_t reserved_22:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:5; + /** dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t dqs_ie_always_on:1; + /** data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_c_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t clk_mode:2; + uint32_t reserved_2:19; + /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ + uint32_t axi_rdata_back_fast:1; + /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in spi_mem_c_C_ECC_ERR_ADDR_REG. + */ + uint32_t rresp_ecc_err_en:1; + /** ar_splice_en : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t ar_splice_en:1; + /** aw_splice_en : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t aw_splice_en:1; + /** ram0_en : HRO; bitpos: [27]; default: 1; + * When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t ram0_en:1; + /** dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t dual_ram_en:1; + /** fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t fast_write_en:1; + /** rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t txfifo_rst:1; + }; + uint32_t val; +} spi_mem_c_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * spi_mem_c_C_CS_SETUP bit. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * spi_mem_c_C_CS_HOLD bit. + */ + uint32_t cs_hold_time:5; + /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; + * spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t ecc_cs_hold_time:3; + /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t ecc_skip_page_corner:1; + /** ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** split_trans_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t split_trans_en:1; + /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t cs_hold_delay:6; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi_mem_c_ctrl2_reg_t; + +/** Type of misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** fsub_pin : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t fsub_pin:1; + /** ssub_pin : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t ssub_pin:1; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_c_misc_reg_t; + +/** Type of cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_c_cache_fctrl_reg_t; + +/** Type of ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_c_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_c_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is + * system/(spi_mem_c_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_c_clock_reg_t; + +/** Type of clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_c_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t cs_setup:1; + uint32_t reserved_8:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:16; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + uint32_t reserved_27:2; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_c_user_reg_t; + +/** Type of user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + /** usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t usr_dbytelen:3; + uint32_t reserved_9:17; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_c_user1_reg_t; + +/** Type of user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_c_user2_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + uint32_t reserved_26:4; + /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_c_sram_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_c_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_c_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_c_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_mem_c_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** lock_delay_time : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t lock_delay_time:5; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_c_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0; + * The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt. + */ + uint32_t ecc_err_int_ena:1; + /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + */ + uint32_t pms_reject_int_ena:1; + /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t axi_raddr_err_int_ena:1; + /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; + * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t axi_wr_flash_err_int_ena:1; + /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; + * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t axi_waddr_err_int__ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_c_int_ena_reg_t; + +/** Type of int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0; + * The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt. + */ + uint32_t ecc_err_int_clr:1; + /** pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + */ + uint32_t pms_reject_int_clr:1; + /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t axi_raddr_err_int_clr:1; + /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; + * The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t axi_wr_flash_err_int_clr:1; + /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; + * The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t axi_waddr_err_int_clr:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_c_int_clr_reg_t; + +/** Type of int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0; + * The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set + * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When + * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t ecc_err_int_raw:1; + /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t pms_reject_int_raw:1; + /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t axi_raddr_err_int_raw:1; + /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; + * The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t axi_wr_flash_err_int_raw:1; + /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; + * The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t axi_waddr_err_int_raw:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_c_int_raw_reg_t; + +/** Type of int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for spi_mem_c_C_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + /** ecc_err_int_st : HRO; bitpos: [5]; default: 0; + * The status bit for spi_mem_c_C_ECC_ERR_INT interrupt. + */ + uint32_t ecc_err_int_st:1; + /** pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + */ + uint32_t pms_reject_int_st:1; + /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t axi_raddr_err_int_st:1; + /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; + * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t axi_wr_flash_err_int_st:1; + /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; + * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t axi_waddr_err_int_st:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_c_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * MSPI flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and + * SPI_MEM_C_FMEM__PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_mem_c_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section n start address value + */ + uint32_t fmem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S, + * SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE) + */ + uint32_t fmem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_c_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_rd_attr:1; + /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_wr_attr:1; + /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and + * SPI_MEM_C_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_mem_c_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section n start address value + */ + uint32_t smem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_MEM_C_SMEM_PMSn_ADDR_S, + * SPI_MEM_C_SMEM_PMSn_ADDR_S + SPI_MEM_C_SMEM_PMSn_SIZE) + */ + uint32_t smem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_c_smem_pmsn_size_reg_t; + +/** Type of pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t reject_addr:27; + /** pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t pm_en:1; + /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t pms_ld:1; + /** pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t pms_st:1; + /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t pms_multi_hit:1; + /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t pms_ivd:1; + }; + uint32_t val; +} spi_mem_c_pms_reject_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + */ + uint32_t ecc_err_cnt:6; + /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t usr_ecc_addr_en:1; + uint32_t reserved_22:2; + /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; + * 1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and + * spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t ecc_continue_record_err_en:1; + /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_c_ecc_ctrl_reg_t; + +/** Type of ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + */ + uint32_t ecc_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_mem_c_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_mem_c_smem_axi_addr_ctrl_reg_t; + +/** Type of axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t aw_resp_en_mmu_vld:1; + /** aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t aw_resp_en_mmu_gid:1; + /** aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t aw_resp_en_axi_size:1; + /** aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t aw_resp_en_axi_flash:1; + /** aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t aw_resp_en_mmu_ecc:1; + /** aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t aw_resp_en_mmu_sens:1; + /** aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t aw_resp_en_axi_wstrb:1; + /** ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t ar_resp_en_mmu_vld:1; + /** ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t ar_resp_en_mmu_gid:1; + /** ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t ar_resp_en_mmu_ecc:1; + /** ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t ar_resp_en_mmu_sens:1; + /** ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_c_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t timing_clk_ena:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + /** dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t dll_timing_cali:1; + /** timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_c_timing_cali_reg_t; + +/** Type of din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t din0_mode:3; + /** din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t din1_mode:3; + /** din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t din2_mode:3; + /** din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t din3_mode:3; + /** din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t din4_mode:3; + /** din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t din5_mode:3; + /** din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t din6_mode:3; + /** din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t din7_mode:3; + /** dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_din_mode_reg_t; + +/** Type of din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din4_num:2; + /** din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din5_num:2; + /** din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din6_num:2; + /** din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t din7_num:2; + /** dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_c_din_num_reg_t; + +/** Type of dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t dout3_mode:1; + /** dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t dout4_mode:1; + /** dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t dout5_mode:1; + /** dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t dout6_mode:1; + /** dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t dout7_mode:1; + /** douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_c_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_mem_c_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_c_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_c_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_c_smem_dout_mode_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_c_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_c_xts_linesize_reg_t; + +/** Type of xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_c_xts_destination_reg_t; + +/** Type of xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:26; + uint32_t reserved_26:6; + }; + uint32_t val; +} spi_mem_c_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_c_xts_trigger_reg_t; + +/** Type of xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_c_xts_release_reg_t; + +/** Type of xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_c_xts_destroy_reg_t; + +/** Type of xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_c_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_c_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_c_mmu_item_content_reg_t; + +/** Type of mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_c_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; + /** aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_c_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_c_dpa_ctrl_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * SPI0 version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_c_date_reg_t; + + +typedef struct spi_mem_c_dev_s { + volatile spi_mem_c_cmd_reg_t cmd; + uint32_t reserved_004; + volatile spi_mem_c_ctrl_reg_t ctrl; + volatile spi_mem_c_ctrl1_reg_t ctrl1; + volatile spi_mem_c_ctrl2_reg_t ctrl2; + volatile spi_mem_c_clock_reg_t clock; + volatile spi_mem_c_user_reg_t user; + volatile spi_mem_c_user1_reg_t user1; + volatile spi_mem_c_user2_reg_t user2; + uint32_t reserved_024[4]; + volatile spi_mem_c_misc_reg_t misc; + uint32_t reserved_038; + volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl; + uint32_t reserved_040; + volatile spi_mem_c_sram_cmd_reg_t sram_cmd; + uint32_t reserved_048[3]; + volatile spi_mem_c_fsm_reg_t fsm; + uint32_t reserved_058[26]; + volatile spi_mem_c_int_ena_reg_t int_ena; + volatile spi_mem_c_int_clr_reg_t int_clr; + volatile spi_mem_c_int_raw_reg_t int_raw; + volatile spi_mem_c_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi_mem_c_ddr_reg_t ddr; + volatile spi_mem_c_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_mem_c_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4]; + uint32_t reserved_160; + volatile spi_mem_c_pms_reject_reg_t pms_reject; + volatile spi_mem_c_ecc_ctrl_reg_t ecc_ctrl; + volatile spi_mem_c_ecc_err_addr_reg_t ecc_err_addr; + volatile spi_mem_c_axi_err_addr_reg_t axi_err_addr; + volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_c_axi_err_resp_en_reg_t axi_err_resp_en; + volatile spi_mem_c_timing_cali_reg_t timing_cali; + volatile spi_mem_c_din_mode_reg_t din_mode; + volatile spi_mem_c_din_num_reg_t din_num; + volatile spi_mem_c_dout_mode_reg_t dout_mode; + volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode; + volatile spi_mem_c_smem_din_num_reg_t smem_din_num; + volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_mem_c_smem_ac_reg_t smem_ac; + uint32_t reserved_1a4[23]; + volatile spi_mem_c_clock_gate_reg_t clock_gate; + uint32_t reserved_204[63]; + volatile spi_mem_c_xts_plain_base_reg_t xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_c_xts_linesize_reg_t xts_linesize; + volatile spi_mem_c_xts_destination_reg_t xts_destination; + volatile spi_mem_c_xts_physical_address_reg_t xts_physical_address; + volatile spi_mem_c_xts_trigger_reg_t xts_trigger; + volatile spi_mem_c_xts_release_reg_t xts_release; + volatile spi_mem_c_xts_destroy_reg_t xts_destroy; + volatile spi_mem_c_xts_state_reg_t xts_state; + volatile spi_mem_c_xts_date_reg_t xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_c_mmu_item_content_reg_t mmu_item_content; + volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index; + volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl; + volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl; + uint32_t reserved_38c[28]; + volatile spi_mem_c_date_reg_t date; +} spi_mem_c_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_c_dev_t) == 0x400, "Invalid size of spi_mem_c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_reg.h new file mode 100644 index 0000000000..cb15d5b07d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_reg.h @@ -0,0 +1,3528 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_S_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x0) +/** SPI_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_S_MST_ST 0x0000000FU +#define SPI_MEM_S_MST_ST_M (SPI_MEM_S_MST_ST_V << SPI_MEM_S_MST_ST_S) +#define SPI_MEM_S_MST_ST_V 0x0000000FU +#define SPI_MEM_S_MST_ST_S 0 +/** SPI_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_S_SLV_ST 0x0000000FU +#define SPI_MEM_S_SLV_ST_M (SPI_MEM_S_SLV_ST_V << SPI_MEM_S_SLV_ST_S) +#define SPI_MEM_S_SLV_ST_V 0x0000000FU +#define SPI_MEM_S_SLV_ST_S 4 +/** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_S_USR (BIT(18)) +#define SPI_MEM_S_USR_M (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S) +#define SPI_MEM_S_USR_V 0x00000001U +#define SPI_MEM_S_USR_S 18 + +/** SPI_MEM_S_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x8) +/** SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_S_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_S_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_S_FDUMMY_RIN_M (SPI_MEM_S_FDUMMY_RIN_V << SPI_MEM_S_FDUMMY_RIN_S) +#define SPI_MEM_S_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_S_FDUMMY_RIN_S 2 +/** SPI_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_S_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_S_FDUMMY_WOUT_M (SPI_MEM_S_FDUMMY_WOUT_V << SPI_MEM_S_FDUMMY_WOUT_S) +#define SPI_MEM_S_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_S_FDUMMY_WOUT_S 3 +/** SPI_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_S_FDOUT_OCT (BIT(4)) +#define SPI_MEM_S_FDOUT_OCT_M (SPI_MEM_S_FDOUT_OCT_V << SPI_MEM_S_FDOUT_OCT_S) +#define SPI_MEM_S_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_S_FDOUT_OCT_S 4 +/** SPI_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_S_FDIN_OCT (BIT(5)) +#define SPI_MEM_S_FDIN_OCT_M (SPI_MEM_S_FDIN_OCT_V << SPI_MEM_S_FDIN_OCT_S) +#define SPI_MEM_S_FDIN_OCT_V 0x00000001U +#define SPI_MEM_S_FDIN_OCT_S 5 +/** SPI_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_S_FADDR_OCT (BIT(6)) +#define SPI_MEM_S_FADDR_OCT_M (SPI_MEM_S_FADDR_OCT_V << SPI_MEM_S_FADDR_OCT_S) +#define SPI_MEM_S_FADDR_OCT_V 0x00000001U +#define SPI_MEM_S_FADDR_OCT_S 6 +/** SPI_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_S_FCMD_QUAD (BIT(8)) +#define SPI_MEM_S_FCMD_QUAD_M (SPI_MEM_S_FCMD_QUAD_V << SPI_MEM_S_FCMD_QUAD_S) +#define SPI_MEM_S_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_S_FCMD_QUAD_S 8 +/** SPI_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_S_FCMD_OCT (BIT(9)) +#define SPI_MEM_S_FCMD_OCT_M (SPI_MEM_S_FCMD_OCT_V << SPI_MEM_S_FCMD_OCT_S) +#define SPI_MEM_S_FCMD_OCT_V 0x00000001U +#define SPI_MEM_S_FCMD_OCT_S 9 +/** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT + * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_S_FASTRD_MODE (BIT(13)) +#define SPI_MEM_S_FASTRD_MODE_M (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S) +#define SPI_MEM_S_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_S_FASTRD_MODE_S 13 +/** SPI_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_FREAD_DUAL (BIT(14)) +#define SPI_MEM_S_FREAD_DUAL_M (SPI_MEM_S_FREAD_DUAL_V << SPI_MEM_S_FREAD_DUAL_S) +#define SPI_MEM_S_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_S_FREAD_DUAL_S 14 +/** SPI_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_S_Q_POL (BIT(18)) +#define SPI_MEM_S_Q_POL_M (SPI_MEM_S_Q_POL_V << SPI_MEM_S_Q_POL_S) +#define SPI_MEM_S_Q_POL_V 0x00000001U +#define SPI_MEM_S_Q_POL_S 18 +/** SPI_MEM_S_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_S_D_POL (BIT(19)) +#define SPI_MEM_S_D_POL_M (SPI_MEM_S_D_POL_V << SPI_MEM_S_D_POL_S) +#define SPI_MEM_S_D_POL_V 0x00000001U +#define SPI_MEM_S_D_POL_S 19 +/** SPI_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_FREAD_QUAD (BIT(20)) +#define SPI_MEM_S_FREAD_QUAD_M (SPI_MEM_S_FREAD_QUAD_V << SPI_MEM_S_FREAD_QUAD_S) +#define SPI_MEM_S_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_S_FREAD_QUAD_S 20 +/** SPI_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_S_WP_REG (BIT(21)) +#define SPI_MEM_S_WP_REG_M (SPI_MEM_S_WP_REG_V << SPI_MEM_S_WP_REG_S) +#define SPI_MEM_S_WP_REG_V 0x00000001U +#define SPI_MEM_S_WP_REG_S 21 +/** SPI_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_S_FREAD_DIO (BIT(23)) +#define SPI_MEM_S_FREAD_DIO_M (SPI_MEM_S_FREAD_DIO_V << SPI_MEM_S_FREAD_DIO_S) +#define SPI_MEM_S_FREAD_DIO_V 0x00000001U +#define SPI_MEM_S_FREAD_DIO_S 23 +/** SPI_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_S_FREAD_QIO (BIT(24)) +#define SPI_MEM_S_FREAD_QIO_M (SPI_MEM_S_FREAD_QIO_V << SPI_MEM_S_FREAD_QIO_S) +#define SPI_MEM_S_FREAD_QIO_V 0x00000001U +#define SPI_MEM_S_FREAD_QIO_S 24 +/** SPI_MEM_S_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_S_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_M (SPI_MEM_S_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_S_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_S_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_M (SPI_MEM_S_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_S_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc) +/** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI_MEM_S_CLK_MODE 0x00000003U +#define SPI_MEM_S_CLK_MODE_M (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S) +#define SPI_MEM_S_CLK_MODE_V 0x00000003U +#define SPI_MEM_S_CLK_MODE_S 0 +/** SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_S_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ +#define SPI_MEM_S_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S) +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_S_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_S_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_S_RRESP_ECC_ERR_EN_M (SPI_MEM_S_RRESP_ECC_ERR_EN_V << SPI_MEM_S_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_S_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_S_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_S_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_S_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_S_AR_SPLICE_EN_M (SPI_MEM_S_AR_SPLICE_EN_V << SPI_MEM_S_AR_SPLICE_EN_S) +#define SPI_MEM_S_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_S_AR_SPLICE_EN_S 25 +/** SPI_MEM_S_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_S_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_S_AW_SPLICE_EN_M (SPI_MEM_S_AW_SPLICE_EN_V << SPI_MEM_S_AW_SPLICE_EN_S) +#define SPI_MEM_S_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_S_AW_SPLICE_EN_S 26 +/** SPI_MEM_S_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_S_RAM0_EN (BIT(27)) +#define SPI_MEM_S_RAM0_EN_M (SPI_MEM_S_RAM0_EN_V << SPI_MEM_S_RAM0_EN_S) +#define SPI_MEM_S_RAM0_EN_V 0x00000001U +#define SPI_MEM_S_RAM0_EN_S 27 +/** SPI_MEM_S_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_S_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_S_DUAL_RAM_EN_M (SPI_MEM_S_DUAL_RAM_EN_V << SPI_MEM_S_DUAL_RAM_EN_S) +#define SPI_MEM_S_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_S_DUAL_RAM_EN_S 28 +/** SPI_MEM_S_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_S_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_S_FAST_WRITE_EN_M (SPI_MEM_S_FAST_WRITE_EN_V << SPI_MEM_S_FAST_WRITE_EN_S) +#define SPI_MEM_S_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_S_FAST_WRITE_EN_S 29 +/** SPI_MEM_S_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_S_RXFIFO_RST (BIT(30)) +#define SPI_MEM_S_RXFIFO_RST_M (SPI_MEM_S_RXFIFO_RST_V << SPI_MEM_S_RXFIFO_RST_S) +#define SPI_MEM_S_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_S_RXFIFO_RST_S 30 +/** SPI_MEM_S_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_S_TXFIFO_RST (BIT(31)) +#define SPI_MEM_S_TXFIFO_RST_M (SPI_MEM_S_TXFIFO_RST_V << SPI_MEM_S_TXFIFO_RST_S) +#define SPI_MEM_S_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_S_TXFIFO_RST_S 31 + +/** SPI_MEM_S_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10) +/** SPI_MEM_S_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_S_CS_SETUP bit. + */ +#define SPI_MEM_S_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_S_CS_SETUP_TIME_M (SPI_MEM_S_CS_SETUP_TIME_V << SPI_MEM_S_CS_SETUP_TIME_S) +#define SPI_MEM_S_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_S_CS_SETUP_TIME_S 0 +/** SPI_MEM_S_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_S_CS_HOLD bit. + */ +#define SPI_MEM_S_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_S_CS_HOLD_TIME_M (SPI_MEM_S_CS_HOLD_TIME_V << SPI_MEM_S_CS_HOLD_TIME_S) +#define SPI_MEM_S_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_S_CS_HOLD_TIME_S 5 +/** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_S_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_S_ECC_CS_HOLD_TIME_M (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_S_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_S_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_S_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_S_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_S_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_S_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_M (SPI_MEM_S_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_S_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_S_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_S_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_S_SPLIT_TRANS_EN_M (SPI_MEM_S_SPLIT_TRANS_EN_V << SPI_MEM_S_SPLIT_TRANS_EN_S) +#define SPI_MEM_S_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_S_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_S_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_S_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_S_CS_HOLD_DELAY_M (SPI_MEM_S_CS_HOLD_DELAY_V << SPI_MEM_S_CS_HOLD_DELAY_S) +#define SPI_MEM_S_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_S_CS_HOLD_DELAY_S 25 +/** SPI_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_S_SYNC_RESET (BIT(31)) +#define SPI_MEM_S_SYNC_RESET_M (SPI_MEM_S_SYNC_RESET_V << SPI_MEM_S_SYNC_RESET_S) +#define SPI_MEM_S_SYNC_RESET_V 0x00000001U +#define SPI_MEM_S_SYNC_RESET_S 31 + +/** SPI_MEM_S_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14) +/** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_S_CLKCNT_L 0x000000FFU +#define SPI_MEM_S_CLKCNT_L_M (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S) +#define SPI_MEM_S_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_L_S 0 +/** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_S_CLKCNT_H 0x000000FFU +#define SPI_MEM_S_CLKCNT_H_M (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S) +#define SPI_MEM_S_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_H_S 8 +/** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_S_CLKCNT_N 0x000000FFU +#define SPI_MEM_S_CLKCNT_N_M (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S) +#define SPI_MEM_S_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_S_CLKCNT_N_S 16 +/** SPI_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_S_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_S_CLK_EQU_SYSCLK_M (SPI_MEM_S_CLK_EQU_SYSCLK_V << SPI_MEM_S_CLK_EQU_SYSCLK_S) +#define SPI_MEM_S_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_S_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_S_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_S_USER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18) +/** SPI_MEM_S_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_S_CS_HOLD (BIT(6)) +#define SPI_MEM_S_CS_HOLD_M (SPI_MEM_S_CS_HOLD_V << SPI_MEM_S_CS_HOLD_S) +#define SPI_MEM_S_CS_HOLD_V 0x00000001U +#define SPI_MEM_S_CS_HOLD_S 6 +/** SPI_MEM_S_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_S_CS_SETUP (BIT(7)) +#define SPI_MEM_S_CS_SETUP_M (SPI_MEM_S_CS_SETUP_V << SPI_MEM_S_CS_SETUP_S) +#define SPI_MEM_S_CS_SETUP_V 0x00000001U +#define SPI_MEM_S_CS_SETUP_S 7 +/** SPI_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_S_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_S_CK_OUT_EDGE_M (SPI_MEM_S_CK_OUT_EDGE_V << SPI_MEM_S_CK_OUT_EDGE_S) +#define SPI_MEM_S_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_S_CK_OUT_EDGE_S 9 +/** SPI_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_S_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_S_USR_DUMMY_IDLE_M (SPI_MEM_S_USR_DUMMY_IDLE_V << SPI_MEM_S_USR_DUMMY_IDLE_S) +#define SPI_MEM_S_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_S_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_S_USR_DUMMY (BIT(29)) +#define SPI_MEM_S_USR_DUMMY_M (SPI_MEM_S_USR_DUMMY_V << SPI_MEM_S_USR_DUMMY_S) +#define SPI_MEM_S_USR_DUMMY_V 0x00000001U +#define SPI_MEM_S_USR_DUMMY_S 29 + +/** SPI_MEM_S_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1c) +/** SPI_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_M (SPI_MEM_S_USR_DUMMY_CYCLELEN_V << SPI_MEM_S_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_S_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_S_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_S_USR_DBYTELEN 0x00000007U +#define SPI_MEM_S_USR_DBYTELEN_M (SPI_MEM_S_USR_DBYTELEN_V << SPI_MEM_S_USR_DBYTELEN_S) +#define SPI_MEM_S_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_S_USR_DBYTELEN_S 6 +/** SPI_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_S_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_S_USR_ADDR_BITLEN_M (SPI_MEM_S_USR_ADDR_BITLEN_V << SPI_MEM_S_USR_ADDR_BITLEN_S) +#define SPI_MEM_S_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_S_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_S_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI0_BASE + 0x20) +/** SPI_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_S_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_S_USR_COMMAND_VALUE_M (SPI_MEM_S_USR_COMMAND_VALUE_V << SPI_MEM_S_USR_COMMAND_VALUE_S) +#define SPI_MEM_S_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_S_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_S_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_S_USR_COMMAND_BITLEN_M (SPI_MEM_S_USR_COMMAND_BITLEN_V << SPI_MEM_S_USR_COMMAND_BITLEN_S) +#define SPI_MEM_S_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_S_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_S_RD_STATUS_REG register + * SPI0 read control register. + */ +#define SPI_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x2c) +/** SPI_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + */ +#define SPI_MEM_S_WB_MODE 0x000000FFU +#define SPI_MEM_S_WB_MODE_M (SPI_MEM_S_WB_MODE_V << SPI_MEM_S_WB_MODE_S) +#define SPI_MEM_S_WB_MODE_V 0x000000FFU +#define SPI_MEM_S_WB_MODE_S 16 + +/** SPI_MEM_S_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34) +/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_S_FSUB_PIN (BIT(7)) +#define SPI_MEM_S_FSUB_PIN_M (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S) +#define SPI_MEM_S_FSUB_PIN_V 0x00000001U +#define SPI_MEM_S_FSUB_PIN_S 7 +/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_S_SSUB_PIN (BIT(8)) +#define SPI_MEM_S_SSUB_PIN_M (SPI_MEM_S_SSUB_PIN_V << SPI_MEM_S_SSUB_PIN_S) +#define SPI_MEM_S_SSUB_PIN_V 0x00000001U +#define SPI_MEM_S_SSUB_PIN_S 8 +/** SPI_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_S_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_S_CK_IDLE_EDGE_M (SPI_MEM_S_CK_IDLE_EDGE_V << SPI_MEM_S_CK_IDLE_EDGE_S) +#define SPI_MEM_S_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_S_CK_IDLE_EDGE_S 9 +/** SPI_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_S_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_S_CS_KEEP_ACTIVE_M (SPI_MEM_S_CS_KEEP_ACTIVE_V << SPI_MEM_S_CS_KEEP_ACTIVE_S) +#define SPI_MEM_S_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_S_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_S_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c) +/** SPI_MEM_S_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + */ +#define SPI_MEM_S_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_S_AXI_REQ_EN_M (SPI_MEM_S_AXI_REQ_EN_V << SPI_MEM_S_AXI_REQ_EN_S) +#define SPI_MEM_S_AXI_REQ_EN_V 0x00000001U +#define SPI_MEM_S_AXI_REQ_EN_S 0 +/** SPI_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ +#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_S_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + */ +#define SPI_MEM_S_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_S_CACHE_FLASH_USR_CMD_M (SPI_MEM_S_CACHE_FLASH_USR_CMD_V << SPI_MEM_S_CACHE_FLASH_USR_CMD_S) +#define SPI_MEM_S_CACHE_FLASH_USR_CMD_V 0x00000001U +#define SPI_MEM_S_CACHE_FLASH_USR_CMD_S 2 +/** SPI_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ +#define SPI_MEM_S_FDIN_DUAL (BIT(3)) +#define SPI_MEM_S_FDIN_DUAL_M (SPI_MEM_S_FDIN_DUAL_V << SPI_MEM_S_FDIN_DUAL_S) +#define SPI_MEM_S_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_S_FDIN_DUAL_S 3 +/** SPI_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + */ +#define SPI_MEM_S_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_S_FDOUT_DUAL_M (SPI_MEM_S_FDOUT_DUAL_V << SPI_MEM_S_FDOUT_DUAL_S) +#define SPI_MEM_S_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_S_FDOUT_DUAL_S 4 +/** SPI_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + */ +#define SPI_MEM_S_FADDR_DUAL (BIT(5)) +#define SPI_MEM_S_FADDR_DUAL_M (SPI_MEM_S_FADDR_DUAL_V << SPI_MEM_S_FADDR_DUAL_S) +#define SPI_MEM_S_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_S_FADDR_DUAL_S 5 +/** SPI_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ +#define SPI_MEM_S_FDIN_QUAD (BIT(6)) +#define SPI_MEM_S_FDIN_QUAD_M (SPI_MEM_S_FDIN_QUAD_V << SPI_MEM_S_FDIN_QUAD_S) +#define SPI_MEM_S_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_S_FDIN_QUAD_S 6 +/** SPI_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + */ +#define SPI_MEM_S_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_S_FDOUT_QUAD_M (SPI_MEM_S_FDOUT_QUAD_V << SPI_MEM_S_FDOUT_QUAD_S) +#define SPI_MEM_S_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_S_FDOUT_QUAD_S 7 +/** SPI_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + */ +#define SPI_MEM_S_FADDR_QUAD (BIT(8)) +#define SPI_MEM_S_FADDR_QUAD_M (SPI_MEM_S_FADDR_QUAD_V << SPI_MEM_S_FADDR_QUAD_S) +#define SPI_MEM_S_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_S_FADDR_QUAD_S 8 +/** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_M (SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V << SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_MEM_S_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_MEM_S_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_S_CLOSE_AXI_INF_EN_M (SPI_MEM_S_CLOSE_AXI_INF_EN_V << SPI_MEM_S_CLOSE_AXI_INF_EN_S) +#define SPI_MEM_S_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_MEM_S_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_S_CACHE_SCTRL_REG register + * SPI0 external RAM control register + */ +#define SPI_MEM_S_CACHE_SCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x40) +/** SPI_MEM_S_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + */ +#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S) +#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V 0x00000001U +#define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S 0 +/** SPI_MEM_S_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + */ +#define SPI_MEM_S_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_S_USR_SRAM_DIO_M (SPI_MEM_S_USR_SRAM_DIO_V << SPI_MEM_S_USR_SRAM_DIO_S) +#define SPI_MEM_S_USR_SRAM_DIO_V 0x00000001U +#define SPI_MEM_S_USR_SRAM_DIO_S 1 +/** SPI_MEM_S_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + */ +#define SPI_MEM_S_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_S_USR_SRAM_QIO_M (SPI_MEM_S_USR_SRAM_QIO_V << SPI_MEM_S_USR_SRAM_QIO_S) +#define SPI_MEM_S_USR_SRAM_QIO_V 0x00000001U +#define SPI_MEM_S_USR_SRAM_QIO_S 2 +/** SPI_MEM_S_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + */ +#define SPI_MEM_S_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_S_USR_WR_SRAM_DUMMY_M (SPI_MEM_S_USR_WR_SRAM_DUMMY_V << SPI_MEM_S_USR_WR_SRAM_DUMMY_S) +#define SPI_MEM_S_USR_WR_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_S_USR_WR_SRAM_DUMMY_S 3 +/** SPI_MEM_S_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + */ +#define SPI_MEM_S_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_S_USR_RD_SRAM_DUMMY_M (SPI_MEM_S_USR_RD_SRAM_DUMMY_V << SPI_MEM_S_USR_RD_SRAM_DUMMY_S) +#define SPI_MEM_S_USR_RD_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_S_USR_RD_SRAM_DUMMY_S 4 +/** SPI_MEM_S_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + */ +#define SPI_MEM_S_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_M (SPI_MEM_S_CACHE_SRAM_USR_RCMD_V << SPI_MEM_S_CACHE_SRAM_USR_RCMD_S) +#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_V 0x00000001U +#define SPI_MEM_S_CACHE_SRAM_USR_RCMD_S 5 +/** SPI_MEM_S_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S) +#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S 6 +/** SPI_MEM_S_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + */ +#define SPI_MEM_S_SRAM_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_S_SRAM_ADDR_BITLEN_M (SPI_MEM_S_SRAM_ADDR_BITLEN_V << SPI_MEM_S_SRAM_ADDR_BITLEN_S) +#define SPI_MEM_S_SRAM_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_S_SRAM_ADDR_BITLEN_S 14 +/** SPI_MEM_S_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + */ +#define SPI_MEM_S_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_M (SPI_MEM_S_CACHE_SRAM_USR_WCMD_V << SPI_MEM_S_CACHE_SRAM_USR_WCMD_S) +#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_V 0x00000001U +#define SPI_MEM_S_CACHE_SRAM_USR_WCMD_S 20 +/** SPI_MEM_S_SRAM_OCT : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SPI_MEM_S_SRAM_OCT (BIT(21)) +#define SPI_MEM_S_SRAM_OCT_M (SPI_MEM_S_SRAM_OCT_V << SPI_MEM_S_SRAM_OCT_S) +#define SPI_MEM_S_SRAM_OCT_V 0x00000001U +#define SPI_MEM_S_SRAM_OCT_S 21 +/** SPI_MEM_S_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S) +#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S 22 + +/** SPI_MEM_S_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_S_SRAM_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x44) +/** SPI_MEM_S_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ +#define SPI_MEM_S_SCLK_MODE 0x00000003U +#define SPI_MEM_S_SCLK_MODE_M (SPI_MEM_S_SCLK_MODE_V << SPI_MEM_S_SCLK_MODE_S) +#define SPI_MEM_S_SCLK_MODE_V 0x00000003U +#define SPI_MEM_S_SCLK_MODE_S 0 +/** SPI_MEM_S_SWB_MODE : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + */ +#define SPI_MEM_S_SWB_MODE 0x000000FFU +#define SPI_MEM_S_SWB_MODE_M (SPI_MEM_S_SWB_MODE_V << SPI_MEM_S_SWB_MODE_S) +#define SPI_MEM_S_SWB_MODE_V 0x000000FFU +#define SPI_MEM_S_SWB_MODE_S 2 +/** SPI_MEM_S_SDIN_DUAL : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_S_SDIN_DUAL (BIT(10)) +#define SPI_MEM_S_SDIN_DUAL_M (SPI_MEM_S_SDIN_DUAL_V << SPI_MEM_S_SDIN_DUAL_S) +#define SPI_MEM_S_SDIN_DUAL_V 0x00000001U +#define SPI_MEM_S_SDIN_DUAL_S 10 +/** SPI_MEM_S_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_S_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_S_SDOUT_DUAL_M (SPI_MEM_S_SDOUT_DUAL_V << SPI_MEM_S_SDOUT_DUAL_S) +#define SPI_MEM_S_SDOUT_DUAL_V 0x00000001U +#define SPI_MEM_S_SDOUT_DUAL_S 11 +/** SPI_MEM_S_SADDR_DUAL : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + */ +#define SPI_MEM_S_SADDR_DUAL (BIT(12)) +#define SPI_MEM_S_SADDR_DUAL_M (SPI_MEM_S_SADDR_DUAL_V << SPI_MEM_S_SADDR_DUAL_S) +#define SPI_MEM_S_SADDR_DUAL_V 0x00000001U +#define SPI_MEM_S_SADDR_DUAL_S 12 +/** SPI_MEM_S_SDIN_QUAD : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_S_SDIN_QUAD (BIT(14)) +#define SPI_MEM_S_SDIN_QUAD_M (SPI_MEM_S_SDIN_QUAD_V << SPI_MEM_S_SDIN_QUAD_S) +#define SPI_MEM_S_SDIN_QUAD_V 0x00000001U +#define SPI_MEM_S_SDIN_QUAD_S 14 +/** SPI_MEM_S_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_S_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_S_SDOUT_QUAD_M (SPI_MEM_S_SDOUT_QUAD_V << SPI_MEM_S_SDOUT_QUAD_S) +#define SPI_MEM_S_SDOUT_QUAD_V 0x00000001U +#define SPI_MEM_S_SDOUT_QUAD_S 15 +/** SPI_MEM_S_SADDR_QUAD : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_S_SADDR_QUAD (BIT(16)) +#define SPI_MEM_S_SADDR_QUAD_M (SPI_MEM_S_SADDR_QUAD_V << SPI_MEM_S_SADDR_QUAD_S) +#define SPI_MEM_S_SADDR_QUAD_V 0x00000001U +#define SPI_MEM_S_SADDR_QUAD_S 16 +/** SPI_MEM_S_SCMD_QUAD : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + */ +#define SPI_MEM_S_SCMD_QUAD (BIT(17)) +#define SPI_MEM_S_SCMD_QUAD_M (SPI_MEM_S_SCMD_QUAD_V << SPI_MEM_S_SCMD_QUAD_S) +#define SPI_MEM_S_SCMD_QUAD_V 0x00000001U +#define SPI_MEM_S_SCMD_QUAD_S 17 +/** SPI_MEM_S_SDIN_OCT : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SDIN_OCT (BIT(18)) +#define SPI_MEM_S_SDIN_OCT_M (SPI_MEM_S_SDIN_OCT_V << SPI_MEM_S_SDIN_OCT_S) +#define SPI_MEM_S_SDIN_OCT_V 0x00000001U +#define SPI_MEM_S_SDIN_OCT_S 18 +/** SPI_MEM_S_SDOUT_OCT : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SDOUT_OCT (BIT(19)) +#define SPI_MEM_S_SDOUT_OCT_M (SPI_MEM_S_SDOUT_OCT_V << SPI_MEM_S_SDOUT_OCT_S) +#define SPI_MEM_S_SDOUT_OCT_V 0x00000001U +#define SPI_MEM_S_SDOUT_OCT_S 19 +/** SPI_MEM_S_SADDR_OCT : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SADDR_OCT (BIT(20)) +#define SPI_MEM_S_SADDR_OCT_M (SPI_MEM_S_SADDR_OCT_V << SPI_MEM_S_SADDR_OCT_S) +#define SPI_MEM_S_SADDR_OCT_V 0x00000001U +#define SPI_MEM_S_SADDR_OCT_S 20 +/** SPI_MEM_S_SCMD_OCT : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SCMD_OCT (BIT(21)) +#define SPI_MEM_S_SCMD_OCT_M (SPI_MEM_S_SCMD_OCT_V << SPI_MEM_S_SCMD_OCT_S) +#define SPI_MEM_S_SCMD_OCT_V 0x00000001U +#define SPI_MEM_S_SCMD_OCT_S 21 +/** SPI_MEM_S_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_S_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_S_SDUMMY_RIN_M (SPI_MEM_S_SDUMMY_RIN_V << SPI_MEM_S_SDUMMY_RIN_S) +#define SPI_MEM_S_SDUMMY_RIN_V 0x00000001U +#define SPI_MEM_S_SDUMMY_RIN_S 22 +/** SPI_MEM_S_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ +#define SPI_MEM_S_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_S_SDUMMY_WOUT_M (SPI_MEM_S_SDUMMY_WOUT_V << SPI_MEM_S_SDUMMY_WOUT_S) +#define SPI_MEM_S_SDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_S_SDUMMY_WOUT_S 23 +/** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_MEM_S_DQS is output by the MSPI controller. + */ +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_MEM_S_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_MEM_S_SDIN_HEX : R/W; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SDIN_HEX (BIT(26)) +#define SPI_MEM_S_SDIN_HEX_M (SPI_MEM_S_SDIN_HEX_V << SPI_MEM_S_SDIN_HEX_S) +#define SPI_MEM_S_SDIN_HEX_V 0x00000001U +#define SPI_MEM_S_SDIN_HEX_S 26 +/** SPI_MEM_S_SDOUT_HEX : R/W; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + */ +#define SPI_MEM_S_SDOUT_HEX (BIT(27)) +#define SPI_MEM_S_SDOUT_HEX_M (SPI_MEM_S_SDOUT_HEX_V << SPI_MEM_S_SDOUT_HEX_S) +#define SPI_MEM_S_SDOUT_HEX_V 0x00000001U +#define SPI_MEM_S_SDOUT_HEX_S 27 +/** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_DQS are + * always 1. 0: Others. + */ +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_S_SRAM_DRD_CMD_REG register + * SPI0 external RAM DDR read command control register + */ +#define SPI_MEM_S_SRAM_DRD_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x48) +/** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + */ +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S) +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + */ +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S) +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/** SPI_MEM_S_SRAM_DWR_CMD_REG register + * SPI0 external RAM DDR write command control register + */ +#define SPI_MEM_S_SRAM_DWR_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x4c) +/** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + */ +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S) +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + */ +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S) +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/** SPI_MEM_S_SRAM_CLK_REG register + * SPI0 external RAM clock control register + */ +#define SPI_MEM_S_SRAM_CLK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x50) +/** SPI_MEM_S_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_S_SCLKCNT_L 0x000000FFU +#define SPI_MEM_S_SCLKCNT_L_M (SPI_MEM_S_SCLKCNT_L_V << SPI_MEM_S_SCLKCNT_L_S) +#define SPI_MEM_S_SCLKCNT_L_V 0x000000FFU +#define SPI_MEM_S_SCLKCNT_L_S 0 +/** SPI_MEM_S_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_S_SCLKCNT_H 0x000000FFU +#define SPI_MEM_S_SCLKCNT_H_M (SPI_MEM_S_SCLKCNT_H_V << SPI_MEM_S_SCLKCNT_H_S) +#define SPI_MEM_S_SCLKCNT_H_V 0x000000FFU +#define SPI_MEM_S_SCLKCNT_H_S 8 +/** SPI_MEM_S_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_S_SCLKCNT_N 0x000000FFU +#define SPI_MEM_S_SCLKCNT_N_M (SPI_MEM_S_SCLKCNT_N_V << SPI_MEM_S_SCLKCNT_N_S) +#define SPI_MEM_S_SCLKCNT_N_V 0x000000FFU +#define SPI_MEM_S_SCLKCNT_N_S 16 +/** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + */ +#define SPI_MEM_S_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_S_SCLK_EQU_SYSCLK_M (SPI_MEM_S_SCLK_EQU_SYSCLK_V << SPI_MEM_S_SCLK_EQU_SYSCLK_S) +#define SPI_MEM_S_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_S_SCLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_S_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54) +/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_S_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_M (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S) +#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_S 7 + +/** SPI_MEM_S_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc0) +/** SPI_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_S_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_ENA_M (SPI_MEM_S_SLV_ST_END_INT_ENA_V << SPI_MEM_S_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_S_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_S_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_ENA_M (SPI_MEM_S_MST_ST_END_INT_ENA_V << SPI_MEM_S_MST_ST_END_INT_ENA_S) +#define SPI_MEM_S_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_S_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_S_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_ENA_M (SPI_MEM_S_ECC_ERR_INT_ENA_V << SPI_MEM_S_ECC_ERR_INT_ENA_S) +#define SPI_MEM_S_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_S_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_ENA_M (SPI_MEM_S_PMS_REJECT_INT_ENA_V << SPI_MEM_S_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_S_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ENA_S 31 + +/** SPI_MEM_S_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc4) +/** SPI_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_S_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_CLR_M (SPI_MEM_S_SLV_ST_END_INT_CLR_V << SPI_MEM_S_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_S_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_S_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_CLR_M (SPI_MEM_S_MST_ST_END_INT_CLR_V << SPI_MEM_S_MST_ST_END_INT_CLR_S) +#define SPI_MEM_S_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_S_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_S_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_CLR_M (SPI_MEM_S_ECC_ERR_INT_CLR_V << SPI_MEM_S_ECC_ERR_INT_CLR_S) +#define SPI_MEM_S_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_S_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_CLR_M (SPI_MEM_S_PMS_REJECT_INT_CLR_V << SPI_MEM_S_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_S_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_CLR_S 31 + +/** SPI_MEM_S_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8) +/** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_RAW_M (SPI_MEM_S_SLV_ST_END_INT_RAW_V << SPI_MEM_S_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_S_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_RAW_M (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S) +#define SPI_MEM_S_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set + * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_S_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_RAW_M (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S) +#define SPI_MEM_S_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_S_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_RAW_M (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_S_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S 31 + +/** SPI_MEM_S_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI0_BASE + 0xcc) +/** SPI_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_S_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_S_SLV_ST_END_INT_ST_M (SPI_MEM_S_SLV_ST_END_INT_ST_V << SPI_MEM_S_SLV_ST_END_INT_ST_S) +#define SPI_MEM_S_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_S_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_S_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_S_MST_ST_END_INT_ST_M (SPI_MEM_S_MST_ST_END_INT_ST_V << SPI_MEM_S_MST_ST_END_INT_ST_S) +#define SPI_MEM_S_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_S_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_S_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_S_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_S_ECC_ERR_INT_ST_M (SPI_MEM_S_ECC_ERR_INT_ST_V << SPI_MEM_S_ECC_ERR_INT_ST_S) +#define SPI_MEM_S_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_S_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_S_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_S_PMS_REJECT_INT_ST_M (SPI_MEM_S_PMS_REJECT_INT_ST_V << SPI_MEM_S_PMS_REJECT_INT_ST_S) +#define SPI_MEM_S_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_S_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_S_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_S_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_S_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_S_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_BUS_FIFO0_UDF_INT_ST_S 31 + +/** SPI_MEM_S_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd4) +/** SPI_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_MEM_S_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_S_FMEM_DDR_EN_M (SPI_MEM_S_FMEM_DDR_EN_V << SPI_MEM_S_FMEM_DDR_EN_S) +#define SPI_MEM_S_FMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_EN_S 0 +/** SPI_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_MEM_S_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_S_FMEM_VAR_DUMMY_M (SPI_MEM_S_FMEM_VAR_DUMMY_V << SPI_MEM_S_FMEM_VAR_DUMMY_S) +#define SPI_MEM_S_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_S_FMEM_VAR_DUMMY_S 1 +/** SPI_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_M (SPI_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI_MEM_S_FMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_M (SPI_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI_MEM_S_FMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_MEM_S_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_M (SPI_MEM_S_FMEM_DDR_CMD_DIS_V << SPI_MEM_S_FMEM_DDR_CMD_DIS_S) +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_MEM_S_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_M (SPI_MEM_S_FMEM_OUTMINBYTELEN_V << SPI_MEM_S_FMEM_OUTMINBYTELEN_S) +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_S_FMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_S_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_M (SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S) +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_MEM_S_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_M (SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S) +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_M (SPI_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI_MEM_S_FMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_S_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_MEM_S_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_M (SPI_MEM_S_FMEM_CLK_DIFF_EN_V << SPI_MEM_S_FMEM_CLK_DIFF_EN_S) +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_MEM_S_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_S_FMEM_DQS_CA_IN_M (SPI_MEM_S_FMEM_DQS_CA_IN_V << SPI_MEM_S_FMEM_DQS_CA_IN_S) +#define SPI_MEM_S_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_S_FMEM_DQS_CA_IN_S 26 +/** SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_MEM_S_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_M (SPI_MEM_S_FMEM_CLK_DIFF_INV_V << SPI_MEM_S_FMEM_CLK_DIFF_INV_S) +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_S_FMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_S_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_MEM_S_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_S_FMEM_HYPERBUS_CA_M (SPI_MEM_S_FMEM_HYPERBUS_CA_V << SPI_MEM_S_FMEM_HYPERBUS_CA_S) +#define SPI_MEM_S_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_S_FMEM_HYPERBUS_CA_S 30 + +/** SPI_MEM_S_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_MEM_S_SMEM_DDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0xd8) +/** SPI_MEM_S_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_MEM_S_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_S_SMEM_DDR_EN_M (SPI_MEM_S_SMEM_DDR_EN_V << SPI_MEM_S_SMEM_DDR_EN_S) +#define SPI_MEM_S_SMEM_DDR_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_EN_S 0 +/** SPI_MEM_S_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_MEM_S_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_S_SMEM_VAR_DUMMY_M (SPI_MEM_S_SMEM_VAR_DUMMY_V << SPI_MEM_S_SMEM_VAR_DUMMY_S) +#define SPI_MEM_S_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_MEM_S_SMEM_VAR_DUMMY_S 1 +/** SPI_MEM_S_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_M (SPI_MEM_S_SMEM_DDR_RDAT_SWP_V << SPI_MEM_S_SMEM_DDR_RDAT_SWP_S) +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_MEM_S_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_M (SPI_MEM_S_SMEM_DDR_WDAT_SWP_V << SPI_MEM_S_SMEM_DDR_WDAT_SWP_S) +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_MEM_S_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_MEM_S_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_M (SPI_MEM_S_SMEM_DDR_CMD_DIS_V << SPI_MEM_S_SMEM_DDR_CMD_DIS_S) +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_CMD_DIS_S 4 +/** SPI_MEM_S_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_MEM_S_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_M (SPI_MEM_S_SMEM_OUTMINBYTELEN_V << SPI_MEM_S_SMEM_OUTMINBYTELEN_S) +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_MEM_S_SMEM_OUTMINBYTELEN_S 5 +/** SPI_MEM_S_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_M (SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S) +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_MEM_S_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_M (SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V << SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S) +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_MEM_S_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_M (SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V << SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S) +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_M (SPI_MEM_S_SMEM_DDR_DQS_LOOP_V << SPI_MEM_S_SMEM_DDR_DQS_LOOP_S) +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_MEM_S_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_MEM_S_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_MEM_S_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_M (SPI_MEM_S_SMEM_CLK_DIFF_EN_V << SPI_MEM_S_SMEM_CLK_DIFF_EN_S) +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_CLK_DIFF_EN_S 24 +/** SPI_MEM_S_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_MEM_S_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_S_SMEM_DQS_CA_IN_M (SPI_MEM_S_SMEM_DQS_CA_IN_V << SPI_MEM_S_SMEM_DQS_CA_IN_S) +#define SPI_MEM_S_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_MEM_S_SMEM_DQS_CA_IN_S 26 +/** SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_MEM_S_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_MEM_S_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_MEM_S_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_M (SPI_MEM_S_SMEM_CLK_DIFF_INV_V << SPI_MEM_S_SMEM_CLK_DIFF_INV_S) +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_MEM_S_SMEM_CLK_DIFF_INV_S 28 +/** SPI_MEM_S_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_M (SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V << SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S) +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_MEM_S_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_MEM_S_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_MEM_S_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_S_SMEM_HYPERBUS_CA_M (SPI_MEM_S_SMEM_HYPERBUS_CA_V << SPI_MEM_S_SMEM_HYPERBUS_CA_S) +#define SPI_MEM_S_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_MEM_S_SMEM_HYPERBUS_CA_S 30 + +/** SPI_MEM_S_FMEM_PMS0_ATTR_REG register + * MSPI flash PMS section $n attribute register + */ +#define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100) +/** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS0_ECC_M (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S) +#define SPI_MEM_S_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_ECC_S 2 + +/** SPI_MEM_S_FMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section $n attribute register + */ +#define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104) +/** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS1_ECC_M (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S) +#define SPI_MEM_S_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_ECC_S 2 + +/** SPI_MEM_S_FMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section $n attribute register + */ +#define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108) +/** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS2_ECC_M (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S) +#define SPI_MEM_S_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_ECC_S 2 + +/** SPI_MEM_S_FMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section $n attribute register + */ +#define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c) +/** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_S_FMEM_PMS3_ECC_M (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S) +#define SPI_MEM_S_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_ECC_S 2 + +/** SPI_MEM_S_FMEM_PMS0_ADDR_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110) +/** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section $n start address value + */ +#define SPI_MEM_S_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_M (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS0_ADDR_S_S 0 + +/** SPI_MEM_S_FMEM_PMS1_ADDR_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114) +/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; + * SPI1 flash PMS section $n start address value + */ +#define SPI_MEM_S_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_M (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS1_ADDR_S_S 0 + +/** SPI_MEM_S_FMEM_PMS2_ADDR_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118) +/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; + * SPI1 flash PMS section $n start address value + */ +#define SPI_MEM_S_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_M (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS2_ADDR_S_S 0 + +/** SPI_MEM_S_FMEM_PMS3_ADDR_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c) +/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; + * SPI1 flash PMS section $n start address value + */ +#define SPI_MEM_S_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_M (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S) +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_FMEM_PMS3_ADDR_S_S 0 + +/** SPI_MEM_S_FMEM_PMS0_SIZE_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120) +/** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, + * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS0_SIZE_M (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S) +#define SPI_MEM_S_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS0_SIZE_S 0 + +/** SPI_MEM_S_FMEM_PMS1_SIZE_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124) +/** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, + * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS1_SIZE_M (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S) +#define SPI_MEM_S_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS1_SIZE_S 0 + +/** SPI_MEM_S_FMEM_PMS2_SIZE_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128) +/** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, + * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS2_SIZE_M (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S) +#define SPI_MEM_S_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS2_SIZE_S 0 + +/** SPI_MEM_S_FMEM_PMS3_SIZE_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c) +/** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, + * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS3_SIZE_M (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S) +#define SPI_MEM_S_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_S_FMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_S_SMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130) +/** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS0_ECC_M (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S) +#define SPI_MEM_S_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_ECC_S 2 + +/** SPI_MEM_S_SMEM_PMS1_ATTR_REG register + * SPI1 external RAM PMS section $n attribute register + */ +#define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134) +/** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS1_ECC_M (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S) +#define SPI_MEM_S_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_ECC_S 2 + +/** SPI_MEM_S_SMEM_PMS2_ATTR_REG register + * SPI1 external RAM PMS section $n attribute register + */ +#define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138) +/** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS2_ECC_M (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S) +#define SPI_MEM_S_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_ECC_S 2 + +/** SPI_MEM_S_SMEM_PMS3_ATTR_REG register + * SPI1 external RAM PMS section $n attribute register + */ +#define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c) +/** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_S_SMEM_PMS3_ECC_M (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S) +#define SPI_MEM_S_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_ECC_S 2 + +/** SPI_MEM_S_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140) +/** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section $n start address value + */ +#define SPI_MEM_S_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_M (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_MEM_S_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144) +/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; + * SPI1 external RAM PMS section $n start address value + */ +#define SPI_MEM_S_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_M (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_MEM_S_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148) +/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; + * SPI1 external RAM PMS section $n start address value + */ +#define SPI_MEM_S_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_M (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_MEM_S_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c) +/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; + * SPI1 external RAM PMS section $n start address value + */ +#define SPI_MEM_S_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_M (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S) +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_MEM_S_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_MEM_S_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150) +/** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, + * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS0_SIZE_M (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S) +#define SPI_MEM_S_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS0_SIZE_S 0 + +/** SPI_MEM_S_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154) +/** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, + * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS1_SIZE_M (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S) +#define SPI_MEM_S_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS1_SIZE_S 0 + +/** SPI_MEM_S_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158) +/** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, + * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS2_SIZE_M (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S) +#define SPI_MEM_S_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS2_SIZE_S 0 + +/** SPI_MEM_S_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section $n start address register + */ +#define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c) +/** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, + * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + */ +#define SPI_MEM_S_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS3_SIZE_M (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S) +#define SPI_MEM_S_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_MEM_S_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_S_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_S_PMS_REJECT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x164) +/** SPI_MEM_S_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_S_REJECT_ADDR 0x07FFFFFFU +#define SPI_MEM_S_REJECT_ADDR_M (SPI_MEM_S_REJECT_ADDR_V << SPI_MEM_S_REJECT_ADDR_S) +#define SPI_MEM_S_REJECT_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_REJECT_ADDR_S 0 +/** SPI_MEM_S_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_S_PM_EN (BIT(27)) +#define SPI_MEM_S_PM_EN_M (SPI_MEM_S_PM_EN_V << SPI_MEM_S_PM_EN_S) +#define SPI_MEM_S_PM_EN_V 0x00000001U +#define SPI_MEM_S_PM_EN_S 27 +/** SPI_MEM_S_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_S_PMS_LD (BIT(28)) +#define SPI_MEM_S_PMS_LD_M (SPI_MEM_S_PMS_LD_V << SPI_MEM_S_PMS_LD_S) +#define SPI_MEM_S_PMS_LD_V 0x00000001U +#define SPI_MEM_S_PMS_LD_S 28 +/** SPI_MEM_S_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_S_PMS_ST (BIT(29)) +#define SPI_MEM_S_PMS_ST_M (SPI_MEM_S_PMS_ST_V << SPI_MEM_S_PMS_ST_S) +#define SPI_MEM_S_PMS_ST_V 0x00000001U +#define SPI_MEM_S_PMS_ST_S 29 +/** SPI_MEM_S_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_S_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_S_PMS_MULTI_HIT_M (SPI_MEM_S_PMS_MULTI_HIT_V << SPI_MEM_S_PMS_MULTI_HIT_S) +#define SPI_MEM_S_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_S_PMS_MULTI_HIT_S 30 +/** SPI_MEM_S_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_S_PMS_IVD (BIT(31)) +#define SPI_MEM_S_PMS_IVD_M (SPI_MEM_S_PMS_IVD_V << SPI_MEM_S_PMS_IVD_S) +#define SPI_MEM_S_PMS_IVD_V 0x00000001U +#define SPI_MEM_S_PMS_IVD_S 31 + +/** SPI_MEM_S_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_S_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x168) +/** SPI_MEM_S_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_S_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_S_ECC_ERR_CNT_M (SPI_MEM_S_ECC_ERR_CNT_V << SPI_MEM_S_ECC_ERR_CNT_S) +#define SPI_MEM_S_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_S_ECC_ERR_CNT_S 5 +/** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_MEM_S_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_M (SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S) +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_MEM_S_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_MEM_S_FMEM_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_FMEM_PAGE_SIZE_M (SPI_MEM_S_FMEM_PAGE_SIZE_V << SPI_MEM_S_FMEM_PAGE_SIZE_S) +#define SPI_MEM_S_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_FMEM_PAGE_SIZE_S 18 +/** SPI_MEM_S_FMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_MEM_S_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_M (SPI_MEM_S_FMEM_ECC_ADDR_EN_V << SPI_MEM_S_FMEM_ECC_ADDR_EN_S) +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_FMEM_ECC_ADDR_EN_S 20 +/** SPI_MEM_S_USR_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_S_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_S_USR_ECC_ADDR_EN_M (SPI_MEM_S_USR_ECC_ADDR_EN_V << SPI_MEM_S_USR_ECC_ADDR_EN_S) +#define SPI_MEM_S_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_USR_ECC_ADDR_EN_S 21 +/** SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and + * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_S_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_S_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_S_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_S_ECC_ERR_BITS_M (SPI_MEM_S_ECC_ERR_BITS_V << SPI_MEM_S_ECC_ERR_BITS_S) +#define SPI_MEM_S_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_S_ECC_ERR_BITS_S 25 + +/** SPI_MEM_S_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_S_ECC_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x16c) +/** SPI_MEM_S_ECC_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_S_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_S_ECC_ERR_ADDR_M (SPI_MEM_S_ECC_ERR_ADDR_V << SPI_MEM_S_ECC_ERR_ADDR_S) +#define SPI_MEM_S_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_S_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_S_AXI_ERR_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x170) +/** SPI_MEM_S_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_S_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_S_AXI_ERR_ADDR_M (SPI_MEM_S_AXI_ERR_ADDR_V << SPI_MEM_S_AXI_ERR_ADDR_S) +#define SPI_MEM_S_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_S_AXI_ERR_ADDR_S 0 + +/** SPI_MEM_S_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_S_SMEM_ECC_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x174) +/** SPI_MEM_S_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_M (SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V << SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S) +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_MEM_S_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_MEM_S_SMEM_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_SMEM_PAGE_SIZE_M (SPI_MEM_S_SMEM_PAGE_SIZE_V << SPI_MEM_S_SMEM_PAGE_SIZE_S) +#define SPI_MEM_S_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_SMEM_PAGE_SIZE_S 18 +/** SPI_MEM_S_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_MEM_S_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_M (SPI_MEM_S_SMEM_ECC_ADDR_EN_V << SPI_MEM_S_SMEM_ECC_ADDR_EN_S) +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_MEM_S_SMEM_AXI_ADDR_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x178) +/** SPI_MEM_S_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_S_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_S_ALL_FIFO_EMPTY_M (SPI_MEM_S_ALL_FIFO_EMPTY_V << SPI_MEM_S_ALL_FIFO_EMPTY_S) +#define SPI_MEM_S_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_S_ALL_FIFO_EMPTY_S 26 +/** SPI_MEM_S_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_MEM_S_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_M (SPI_MEM_S_RDATA_AFIFO_REMPTY_V << SPI_MEM_S_RDATA_AFIFO_REMPTY_S) +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_RDATA_AFIFO_REMPTY_S 27 +/** SPI_MEM_S_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_MEM_S_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_M (SPI_MEM_S_RADDR_AFIFO_REMPTY_V << SPI_MEM_S_RADDR_AFIFO_REMPTY_S) +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_RADDR_AFIFO_REMPTY_S 28 +/** SPI_MEM_S_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_MEM_S_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_M (SPI_MEM_S_WDATA_AFIFO_REMPTY_V << SPI_MEM_S_WDATA_AFIFO_REMPTY_S) +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_WDATA_AFIFO_REMPTY_S 29 +/** SPI_MEM_S_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_M (SPI_MEM_S_WBLEN_AFIFO_REMPTY_V << SPI_MEM_S_WBLEN_AFIFO_REMPTY_S) +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_MEM_S_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_MEM_S_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_S_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_S_AXI_ERR_RESP_EN_REG (DR_REG_PSRAM_MSPI0_BASE + 0x17c) +/** SPI_MEM_S_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_M (SPI_MEM_S_AW_RESP_EN_MMU_VLD_V << SPI_MEM_S_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_S_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_M (SPI_MEM_S_AW_RESP_EN_MMU_GID_V << SPI_MEM_S_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_S_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_S_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_S_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_M (SPI_MEM_S_AW_RESP_EN_MMU_ECC_V << SPI_MEM_S_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_S_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_M (SPI_MEM_S_AW_RESP_EN_MMU_SENS_V << SPI_MEM_S_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_S_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_S_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_S_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_M (SPI_MEM_S_AR_RESP_EN_MMU_VLD_V << SPI_MEM_S_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_S_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_S_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_M (SPI_MEM_S_AR_RESP_EN_MMU_GID_V << SPI_MEM_S_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_S_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_M (SPI_MEM_S_AR_RESP_EN_MMU_ECC_V << SPI_MEM_S_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_S_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_M (SPI_MEM_S_AR_RESP_EN_MMU_SENS_V << SPI_MEM_S_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_S_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_S_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_S_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x180) +/** SPI_MEM_S_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_S_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_S_TIMING_CLK_ENA_M (SPI_MEM_S_TIMING_CLK_ENA_V << SPI_MEM_S_TIMING_CLK_ENA_S) +#define SPI_MEM_S_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_S_TIMING_CLK_ENA_S 0 +/** SPI_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_S_TIMING_CALI (BIT(1)) +#define SPI_MEM_S_TIMING_CALI_M (SPI_MEM_S_TIMING_CALI_V << SPI_MEM_S_TIMING_CALI_S) +#define SPI_MEM_S_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_TIMING_CALI_S 1 +/** SPI_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_S_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_S_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_S_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_S_DLL_TIMING_CALI_M (SPI_MEM_S_DLL_TIMING_CALI_V << SPI_MEM_S_DLL_TIMING_CALI_S) +#define SPI_MEM_S_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_DLL_TIMING_CALI_S 5 +/** SPI_MEM_S_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_S_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_S_TIMING_CALI_UPDATE_M (SPI_MEM_S_TIMING_CALI_UPDATE_V << SPI_MEM_S_TIMING_CALI_UPDATE_S) +#define SPI_MEM_S_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_S_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_S_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_S_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x184) +/** SPI_MEM_S_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_DIN0_MODE 0x00000007U +#define SPI_MEM_S_DIN0_MODE_M (SPI_MEM_S_DIN0_MODE_V << SPI_MEM_S_DIN0_MODE_S) +#define SPI_MEM_S_DIN0_MODE_V 0x00000007U +#define SPI_MEM_S_DIN0_MODE_S 0 +/** SPI_MEM_S_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_DIN1_MODE 0x00000007U +#define SPI_MEM_S_DIN1_MODE_M (SPI_MEM_S_DIN1_MODE_V << SPI_MEM_S_DIN1_MODE_S) +#define SPI_MEM_S_DIN1_MODE_V 0x00000007U +#define SPI_MEM_S_DIN1_MODE_S 3 +/** SPI_MEM_S_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_DIN2_MODE 0x00000007U +#define SPI_MEM_S_DIN2_MODE_M (SPI_MEM_S_DIN2_MODE_V << SPI_MEM_S_DIN2_MODE_S) +#define SPI_MEM_S_DIN2_MODE_V 0x00000007U +#define SPI_MEM_S_DIN2_MODE_S 6 +/** SPI_MEM_S_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_DIN3_MODE 0x00000007U +#define SPI_MEM_S_DIN3_MODE_M (SPI_MEM_S_DIN3_MODE_V << SPI_MEM_S_DIN3_MODE_S) +#define SPI_MEM_S_DIN3_MODE_V 0x00000007U +#define SPI_MEM_S_DIN3_MODE_S 9 +/** SPI_MEM_S_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_S_DIN4_MODE 0x00000007U +#define SPI_MEM_S_DIN4_MODE_M (SPI_MEM_S_DIN4_MODE_V << SPI_MEM_S_DIN4_MODE_S) +#define SPI_MEM_S_DIN4_MODE_V 0x00000007U +#define SPI_MEM_S_DIN4_MODE_S 12 +/** SPI_MEM_S_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_S_DIN5_MODE 0x00000007U +#define SPI_MEM_S_DIN5_MODE_M (SPI_MEM_S_DIN5_MODE_V << SPI_MEM_S_DIN5_MODE_S) +#define SPI_MEM_S_DIN5_MODE_V 0x00000007U +#define SPI_MEM_S_DIN5_MODE_S 15 +/** SPI_MEM_S_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_S_DIN6_MODE 0x00000007U +#define SPI_MEM_S_DIN6_MODE_M (SPI_MEM_S_DIN6_MODE_V << SPI_MEM_S_DIN6_MODE_S) +#define SPI_MEM_S_DIN6_MODE_V 0x00000007U +#define SPI_MEM_S_DIN6_MODE_S 18 +/** SPI_MEM_S_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_S_DIN7_MODE 0x00000007U +#define SPI_MEM_S_DIN7_MODE_M (SPI_MEM_S_DIN7_MODE_V << SPI_MEM_S_DIN7_MODE_S) +#define SPI_MEM_S_DIN7_MODE_V 0x00000007U +#define SPI_MEM_S_DIN7_MODE_S 21 +/** SPI_MEM_S_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_S_DINS_MODE 0x00000007U +#define SPI_MEM_S_DINS_MODE_M (SPI_MEM_S_DINS_MODE_V << SPI_MEM_S_DINS_MODE_S) +#define SPI_MEM_S_DINS_MODE_V 0x00000007U +#define SPI_MEM_S_DINS_MODE_S 24 + +/** SPI_MEM_S_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_S_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x188) +/** SPI_MEM_S_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN0_NUM 0x00000003U +#define SPI_MEM_S_DIN0_NUM_M (SPI_MEM_S_DIN0_NUM_V << SPI_MEM_S_DIN0_NUM_S) +#define SPI_MEM_S_DIN0_NUM_V 0x00000003U +#define SPI_MEM_S_DIN0_NUM_S 0 +/** SPI_MEM_S_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN1_NUM 0x00000003U +#define SPI_MEM_S_DIN1_NUM_M (SPI_MEM_S_DIN1_NUM_V << SPI_MEM_S_DIN1_NUM_S) +#define SPI_MEM_S_DIN1_NUM_V 0x00000003U +#define SPI_MEM_S_DIN1_NUM_S 2 +/** SPI_MEM_S_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN2_NUM 0x00000003U +#define SPI_MEM_S_DIN2_NUM_M (SPI_MEM_S_DIN2_NUM_V << SPI_MEM_S_DIN2_NUM_S) +#define SPI_MEM_S_DIN2_NUM_V 0x00000003U +#define SPI_MEM_S_DIN2_NUM_S 4 +/** SPI_MEM_S_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN3_NUM 0x00000003U +#define SPI_MEM_S_DIN3_NUM_M (SPI_MEM_S_DIN3_NUM_V << SPI_MEM_S_DIN3_NUM_S) +#define SPI_MEM_S_DIN3_NUM_V 0x00000003U +#define SPI_MEM_S_DIN3_NUM_S 6 +/** SPI_MEM_S_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN4_NUM 0x00000003U +#define SPI_MEM_S_DIN4_NUM_M (SPI_MEM_S_DIN4_NUM_V << SPI_MEM_S_DIN4_NUM_S) +#define SPI_MEM_S_DIN4_NUM_V 0x00000003U +#define SPI_MEM_S_DIN4_NUM_S 8 +/** SPI_MEM_S_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN5_NUM 0x00000003U +#define SPI_MEM_S_DIN5_NUM_M (SPI_MEM_S_DIN5_NUM_V << SPI_MEM_S_DIN5_NUM_S) +#define SPI_MEM_S_DIN5_NUM_V 0x00000003U +#define SPI_MEM_S_DIN5_NUM_S 10 +/** SPI_MEM_S_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN6_NUM 0x00000003U +#define SPI_MEM_S_DIN6_NUM_M (SPI_MEM_S_DIN6_NUM_V << SPI_MEM_S_DIN6_NUM_S) +#define SPI_MEM_S_DIN6_NUM_V 0x00000003U +#define SPI_MEM_S_DIN6_NUM_S 12 +/** SPI_MEM_S_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DIN7_NUM 0x00000003U +#define SPI_MEM_S_DIN7_NUM_M (SPI_MEM_S_DIN7_NUM_V << SPI_MEM_S_DIN7_NUM_S) +#define SPI_MEM_S_DIN7_NUM_V 0x00000003U +#define SPI_MEM_S_DIN7_NUM_S 14 +/** SPI_MEM_S_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_DINS_NUM 0x00000003U +#define SPI_MEM_S_DINS_NUM_M (SPI_MEM_S_DINS_NUM_V << SPI_MEM_S_DINS_NUM_S) +#define SPI_MEM_S_DINS_NUM_V 0x00000003U +#define SPI_MEM_S_DINS_NUM_S 16 + +/** SPI_MEM_S_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_S_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x18c) +/** SPI_MEM_S_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_DOUT0_MODE (BIT(0)) +#define SPI_MEM_S_DOUT0_MODE_M (SPI_MEM_S_DOUT0_MODE_V << SPI_MEM_S_DOUT0_MODE_S) +#define SPI_MEM_S_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT0_MODE_S 0 +/** SPI_MEM_S_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_DOUT1_MODE (BIT(1)) +#define SPI_MEM_S_DOUT1_MODE_M (SPI_MEM_S_DOUT1_MODE_V << SPI_MEM_S_DOUT1_MODE_S) +#define SPI_MEM_S_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT1_MODE_S 1 +/** SPI_MEM_S_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_DOUT2_MODE (BIT(2)) +#define SPI_MEM_S_DOUT2_MODE_M (SPI_MEM_S_DOUT2_MODE_V << SPI_MEM_S_DOUT2_MODE_S) +#define SPI_MEM_S_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT2_MODE_S 2 +/** SPI_MEM_S_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_DOUT3_MODE (BIT(3)) +#define SPI_MEM_S_DOUT3_MODE_M (SPI_MEM_S_DOUT3_MODE_V << SPI_MEM_S_DOUT3_MODE_S) +#define SPI_MEM_S_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT3_MODE_S 3 +/** SPI_MEM_S_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_S_DOUT4_MODE (BIT(4)) +#define SPI_MEM_S_DOUT4_MODE_M (SPI_MEM_S_DOUT4_MODE_V << SPI_MEM_S_DOUT4_MODE_S) +#define SPI_MEM_S_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT4_MODE_S 4 +/** SPI_MEM_S_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_S_DOUT5_MODE (BIT(5)) +#define SPI_MEM_S_DOUT5_MODE_M (SPI_MEM_S_DOUT5_MODE_V << SPI_MEM_S_DOUT5_MODE_S) +#define SPI_MEM_S_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT5_MODE_S 5 +/** SPI_MEM_S_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_S_DOUT6_MODE (BIT(6)) +#define SPI_MEM_S_DOUT6_MODE_M (SPI_MEM_S_DOUT6_MODE_V << SPI_MEM_S_DOUT6_MODE_S) +#define SPI_MEM_S_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT6_MODE_S 6 +/** SPI_MEM_S_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_S_DOUT7_MODE (BIT(7)) +#define SPI_MEM_S_DOUT7_MODE_M (SPI_MEM_S_DOUT7_MODE_V << SPI_MEM_S_DOUT7_MODE_S) +#define SPI_MEM_S_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_S_DOUT7_MODE_S 7 +/** SPI_MEM_S_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_S_DOUTS_MODE (BIT(8)) +#define SPI_MEM_S_DOUTS_MODE_M (SPI_MEM_S_DOUTS_MODE_V << SPI_MEM_S_DOUTS_MODE_S) +#define SPI_MEM_S_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_S_DOUTS_MODE_S 8 + +/** SPI_MEM_S_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_MEM_S_SMEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI0_BASE + 0x190) +/** SPI_MEM_S_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_M (SPI_MEM_S_SMEM_TIMING_CLK_ENA_V << SPI_MEM_S_SMEM_TIMING_CLK_ENA_S) +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_S_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_S_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_MEM_S_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_S_SMEM_TIMING_CALI_M (SPI_MEM_S_SMEM_TIMING_CALI_V << SPI_MEM_S_SMEM_TIMING_CALI_S) +#define SPI_MEM_S_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_SMEM_TIMING_CALI_S 1 +/** SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_S_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_S_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_M (SPI_MEM_S_SMEM_DLL_TIMING_CALI_V << SPI_MEM_S_SMEM_DLL_TIMING_CALI_S) +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_S_SMEM_DLL_TIMING_CALI_S 5 + +/** SPI_MEM_S_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_MEM_S_SMEM_DIN_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x194) +/** SPI_MEM_S_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN0_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN0_MODE_M (SPI_MEM_S_SMEM_DIN0_MODE_V << SPI_MEM_S_SMEM_DIN0_MODE_S) +#define SPI_MEM_S_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN0_MODE_S 0 +/** SPI_MEM_S_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN1_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN1_MODE_M (SPI_MEM_S_SMEM_DIN1_MODE_V << SPI_MEM_S_SMEM_DIN1_MODE_S) +#define SPI_MEM_S_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN1_MODE_S 3 +/** SPI_MEM_S_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN2_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN2_MODE_M (SPI_MEM_S_SMEM_DIN2_MODE_V << SPI_MEM_S_SMEM_DIN2_MODE_S) +#define SPI_MEM_S_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN2_MODE_S 6 +/** SPI_MEM_S_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN3_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN3_MODE_M (SPI_MEM_S_SMEM_DIN3_MODE_V << SPI_MEM_S_SMEM_DIN3_MODE_S) +#define SPI_MEM_S_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN3_MODE_S 9 +/** SPI_MEM_S_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN4_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN4_MODE_M (SPI_MEM_S_SMEM_DIN4_MODE_V << SPI_MEM_S_SMEM_DIN4_MODE_S) +#define SPI_MEM_S_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN4_MODE_S 12 +/** SPI_MEM_S_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN5_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN5_MODE_M (SPI_MEM_S_SMEM_DIN5_MODE_V << SPI_MEM_S_SMEM_DIN5_MODE_S) +#define SPI_MEM_S_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN5_MODE_S 15 +/** SPI_MEM_S_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN6_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN6_MODE_M (SPI_MEM_S_SMEM_DIN6_MODE_V << SPI_MEM_S_SMEM_DIN6_MODE_S) +#define SPI_MEM_S_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN6_MODE_S 18 +/** SPI_MEM_S_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN7_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN7_MODE_M (SPI_MEM_S_SMEM_DIN7_MODE_V << SPI_MEM_S_SMEM_DIN7_MODE_S) +#define SPI_MEM_S_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN7_MODE_S 21 +/** SPI_MEM_S_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DINS_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DINS_MODE_M (SPI_MEM_S_SMEM_DINS_MODE_V << SPI_MEM_S_SMEM_DINS_MODE_S) +#define SPI_MEM_S_SMEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DINS_MODE_S 24 + +/** SPI_MEM_S_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_MEM_S_SMEM_DIN_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x198) +/** SPI_MEM_S_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN0_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN0_NUM_M (SPI_MEM_S_SMEM_DIN0_NUM_V << SPI_MEM_S_SMEM_DIN0_NUM_S) +#define SPI_MEM_S_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN0_NUM_S 0 +/** SPI_MEM_S_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN1_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN1_NUM_M (SPI_MEM_S_SMEM_DIN1_NUM_V << SPI_MEM_S_SMEM_DIN1_NUM_S) +#define SPI_MEM_S_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN1_NUM_S 2 +/** SPI_MEM_S_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN2_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN2_NUM_M (SPI_MEM_S_SMEM_DIN2_NUM_V << SPI_MEM_S_SMEM_DIN2_NUM_S) +#define SPI_MEM_S_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN2_NUM_S 4 +/** SPI_MEM_S_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN3_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN3_NUM_M (SPI_MEM_S_SMEM_DIN3_NUM_V << SPI_MEM_S_SMEM_DIN3_NUM_S) +#define SPI_MEM_S_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN3_NUM_S 6 +/** SPI_MEM_S_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN4_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN4_NUM_M (SPI_MEM_S_SMEM_DIN4_NUM_V << SPI_MEM_S_SMEM_DIN4_NUM_S) +#define SPI_MEM_S_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN4_NUM_S 8 +/** SPI_MEM_S_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN5_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN5_NUM_M (SPI_MEM_S_SMEM_DIN5_NUM_V << SPI_MEM_S_SMEM_DIN5_NUM_S) +#define SPI_MEM_S_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN5_NUM_S 10 +/** SPI_MEM_S_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN6_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN6_NUM_M (SPI_MEM_S_SMEM_DIN6_NUM_V << SPI_MEM_S_SMEM_DIN6_NUM_S) +#define SPI_MEM_S_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN6_NUM_S 12 +/** SPI_MEM_S_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN7_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN7_NUM_M (SPI_MEM_S_SMEM_DIN7_NUM_V << SPI_MEM_S_SMEM_DIN7_NUM_S) +#define SPI_MEM_S_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN7_NUM_S 14 +/** SPI_MEM_S_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DINS_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DINS_NUM_M (SPI_MEM_S_SMEM_DINS_NUM_V << SPI_MEM_S_SMEM_DINS_NUM_S) +#define SPI_MEM_S_SMEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DINS_NUM_S 16 + +/** SPI_MEM_S_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_MEM_S_SMEM_DOUT_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x19c) +/** SPI_MEM_S_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_S_SMEM_DOUT0_MODE_M (SPI_MEM_S_SMEM_DOUT0_MODE_V << SPI_MEM_S_SMEM_DOUT0_MODE_S) +#define SPI_MEM_S_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT0_MODE_S 0 +/** SPI_MEM_S_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_S_SMEM_DOUT1_MODE_M (SPI_MEM_S_SMEM_DOUT1_MODE_V << SPI_MEM_S_SMEM_DOUT1_MODE_S) +#define SPI_MEM_S_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT1_MODE_S 1 +/** SPI_MEM_S_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_S_SMEM_DOUT2_MODE_M (SPI_MEM_S_SMEM_DOUT2_MODE_V << SPI_MEM_S_SMEM_DOUT2_MODE_S) +#define SPI_MEM_S_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT2_MODE_S 2 +/** SPI_MEM_S_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_S_SMEM_DOUT3_MODE_M (SPI_MEM_S_SMEM_DOUT3_MODE_V << SPI_MEM_S_SMEM_DOUT3_MODE_S) +#define SPI_MEM_S_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT3_MODE_S 3 +/** SPI_MEM_S_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_S_SMEM_DOUT4_MODE_M (SPI_MEM_S_SMEM_DOUT4_MODE_V << SPI_MEM_S_SMEM_DOUT4_MODE_S) +#define SPI_MEM_S_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT4_MODE_S 4 +/** SPI_MEM_S_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_S_SMEM_DOUT5_MODE_M (SPI_MEM_S_SMEM_DOUT5_MODE_V << SPI_MEM_S_SMEM_DOUT5_MODE_S) +#define SPI_MEM_S_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT5_MODE_S 5 +/** SPI_MEM_S_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_S_SMEM_DOUT6_MODE_M (SPI_MEM_S_SMEM_DOUT6_MODE_V << SPI_MEM_S_SMEM_DOUT6_MODE_S) +#define SPI_MEM_S_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT6_MODE_S 6 +/** SPI_MEM_S_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_S_SMEM_DOUT7_MODE_M (SPI_MEM_S_SMEM_DOUT7_MODE_V << SPI_MEM_S_SMEM_DOUT7_MODE_S) +#define SPI_MEM_S_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT7_MODE_S 7 +/** SPI_MEM_S_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_S_SMEM_DOUTS_MODE_M (SPI_MEM_S_SMEM_DOUTS_MODE_V << SPI_MEM_S_SMEM_DOUTS_MODE_S) +#define SPI_MEM_S_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUTS_MODE_S 8 + +/** SPI_MEM_S_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_MEM_S_SMEM_AC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a0) +/** SPI_MEM_S_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_MEM_S_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_S_SMEM_CS_SETUP_M (SPI_MEM_S_SMEM_CS_SETUP_V << SPI_MEM_S_SMEM_CS_SETUP_S) +#define SPI_MEM_S_SMEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_S_SMEM_CS_SETUP_S 0 +/** SPI_MEM_S_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_S_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_S_SMEM_CS_HOLD_M (SPI_MEM_S_SMEM_CS_HOLD_V << SPI_MEM_S_SMEM_CS_HOLD_S) +#define SPI_MEM_S_SMEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_S_SMEM_CS_HOLD_S 1 +/** SPI_MEM_S_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_MEM_S_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_M (SPI_MEM_S_SMEM_CS_SETUP_TIME_V << SPI_MEM_S_SMEM_CS_SETUP_TIME_S) +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_S_SMEM_CS_SETUP_TIME_S 2 +/** SPI_MEM_S_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_MEM_S_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_CS_HOLD_TIME_S) +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_S_SMEM_CS_HOLD_TIME_S 7 +/** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S) +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_S_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_S_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_M (SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V << SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_S_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_MEM_S_SMEM_DIN_HEX_MODE_REG register + * MSPI 16x external RAM input timing delay mode control register + */ +#define SPI_MEM_S_SMEM_DIN_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a4) +/** SPI_MEM_S_SMEM_DIN08_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN08_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN08_MODE_M (SPI_MEM_S_SMEM_DIN08_MODE_V << SPI_MEM_S_SMEM_DIN08_MODE_S) +#define SPI_MEM_S_SMEM_DIN08_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN08_MODE_S 0 +/** SPI_MEM_S_SMEM_DIN09_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN09_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN09_MODE_M (SPI_MEM_S_SMEM_DIN09_MODE_V << SPI_MEM_S_SMEM_DIN09_MODE_S) +#define SPI_MEM_S_SMEM_DIN09_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN09_MODE_S 3 +/** SPI_MEM_S_SMEM_DIN10_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN10_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN10_MODE_M (SPI_MEM_S_SMEM_DIN10_MODE_V << SPI_MEM_S_SMEM_DIN10_MODE_S) +#define SPI_MEM_S_SMEM_DIN10_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN10_MODE_S 6 +/** SPI_MEM_S_SMEM_DIN11_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN11_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN11_MODE_M (SPI_MEM_S_SMEM_DIN11_MODE_V << SPI_MEM_S_SMEM_DIN11_MODE_S) +#define SPI_MEM_S_SMEM_DIN11_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN11_MODE_S 9 +/** SPI_MEM_S_SMEM_DIN12_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN12_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN12_MODE_M (SPI_MEM_S_SMEM_DIN12_MODE_V << SPI_MEM_S_SMEM_DIN12_MODE_S) +#define SPI_MEM_S_SMEM_DIN12_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN12_MODE_S 12 +/** SPI_MEM_S_SMEM_DIN13_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN13_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN13_MODE_M (SPI_MEM_S_SMEM_DIN13_MODE_V << SPI_MEM_S_SMEM_DIN13_MODE_S) +#define SPI_MEM_S_SMEM_DIN13_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN13_MODE_S 15 +/** SPI_MEM_S_SMEM_DIN14_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN14_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN14_MODE_M (SPI_MEM_S_SMEM_DIN14_MODE_V << SPI_MEM_S_SMEM_DIN14_MODE_S) +#define SPI_MEM_S_SMEM_DIN14_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN14_MODE_S 18 +/** SPI_MEM_S_SMEM_DIN15_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DIN15_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DIN15_MODE_M (SPI_MEM_S_SMEM_DIN15_MODE_V << SPI_MEM_S_SMEM_DIN15_MODE_S) +#define SPI_MEM_S_SMEM_DIN15_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DIN15_MODE_S 21 +/** SPI_MEM_S_SMEM_DINS_HEX_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DINS_HEX_MODE 0x00000007U +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_M (SPI_MEM_S_SMEM_DINS_HEX_MODE_V << SPI_MEM_S_SMEM_DINS_HEX_MODE_S) +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_V 0x00000007U +#define SPI_MEM_S_SMEM_DINS_HEX_MODE_S 24 + +/** SPI_MEM_S_SMEM_DIN_HEX_NUM_REG register + * MSPI 16x external RAM input timing delay number control register + */ +#define SPI_MEM_S_SMEM_DIN_HEX_NUM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1a8) +/** SPI_MEM_S_SMEM_DIN08_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN08_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN08_NUM_M (SPI_MEM_S_SMEM_DIN08_NUM_V << SPI_MEM_S_SMEM_DIN08_NUM_S) +#define SPI_MEM_S_SMEM_DIN08_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN08_NUM_S 0 +/** SPI_MEM_S_SMEM_DIN09_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN09_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN09_NUM_M (SPI_MEM_S_SMEM_DIN09_NUM_V << SPI_MEM_S_SMEM_DIN09_NUM_S) +#define SPI_MEM_S_SMEM_DIN09_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN09_NUM_S 2 +/** SPI_MEM_S_SMEM_DIN10_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN10_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN10_NUM_M (SPI_MEM_S_SMEM_DIN10_NUM_V << SPI_MEM_S_SMEM_DIN10_NUM_S) +#define SPI_MEM_S_SMEM_DIN10_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN10_NUM_S 4 +/** SPI_MEM_S_SMEM_DIN11_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN11_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN11_NUM_M (SPI_MEM_S_SMEM_DIN11_NUM_V << SPI_MEM_S_SMEM_DIN11_NUM_S) +#define SPI_MEM_S_SMEM_DIN11_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN11_NUM_S 6 +/** SPI_MEM_S_SMEM_DIN12_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN12_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN12_NUM_M (SPI_MEM_S_SMEM_DIN12_NUM_V << SPI_MEM_S_SMEM_DIN12_NUM_S) +#define SPI_MEM_S_SMEM_DIN12_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN12_NUM_S 8 +/** SPI_MEM_S_SMEM_DIN13_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN13_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN13_NUM_M (SPI_MEM_S_SMEM_DIN13_NUM_V << SPI_MEM_S_SMEM_DIN13_NUM_S) +#define SPI_MEM_S_SMEM_DIN13_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN13_NUM_S 10 +/** SPI_MEM_S_SMEM_DIN14_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN14_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN14_NUM_M (SPI_MEM_S_SMEM_DIN14_NUM_V << SPI_MEM_S_SMEM_DIN14_NUM_S) +#define SPI_MEM_S_SMEM_DIN14_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN14_NUM_S 12 +/** SPI_MEM_S_SMEM_DIN15_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DIN15_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DIN15_NUM_M (SPI_MEM_S_SMEM_DIN15_NUM_V << SPI_MEM_S_SMEM_DIN15_NUM_S) +#define SPI_MEM_S_SMEM_DIN15_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DIN15_NUM_S 14 +/** SPI_MEM_S_SMEM_DINS_HEX_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_S_SMEM_DINS_HEX_NUM 0x00000003U +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_M (SPI_MEM_S_SMEM_DINS_HEX_NUM_V << SPI_MEM_S_SMEM_DINS_HEX_NUM_S) +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_V 0x00000003U +#define SPI_MEM_S_SMEM_DINS_HEX_NUM_S 16 + +/** SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG register + * MSPI 16x external RAM output timing adjustment control register + */ +#define SPI_MEM_S_SMEM_DOUT_HEX_MODE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x1ac) +/** SPI_MEM_S_SMEM_DOUT08_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT08_MODE (BIT(0)) +#define SPI_MEM_S_SMEM_DOUT08_MODE_M (SPI_MEM_S_SMEM_DOUT08_MODE_V << SPI_MEM_S_SMEM_DOUT08_MODE_S) +#define SPI_MEM_S_SMEM_DOUT08_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT08_MODE_S 0 +/** SPI_MEM_S_SMEM_DOUT09_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT09_MODE (BIT(1)) +#define SPI_MEM_S_SMEM_DOUT09_MODE_M (SPI_MEM_S_SMEM_DOUT09_MODE_V << SPI_MEM_S_SMEM_DOUT09_MODE_S) +#define SPI_MEM_S_SMEM_DOUT09_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT09_MODE_S 1 +/** SPI_MEM_S_SMEM_DOUT10_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT10_MODE (BIT(2)) +#define SPI_MEM_S_SMEM_DOUT10_MODE_M (SPI_MEM_S_SMEM_DOUT10_MODE_V << SPI_MEM_S_SMEM_DOUT10_MODE_S) +#define SPI_MEM_S_SMEM_DOUT10_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT10_MODE_S 2 +/** SPI_MEM_S_SMEM_DOUT11_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT11_MODE (BIT(3)) +#define SPI_MEM_S_SMEM_DOUT11_MODE_M (SPI_MEM_S_SMEM_DOUT11_MODE_V << SPI_MEM_S_SMEM_DOUT11_MODE_S) +#define SPI_MEM_S_SMEM_DOUT11_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT11_MODE_S 3 +/** SPI_MEM_S_SMEM_DOUT12_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT12_MODE (BIT(4)) +#define SPI_MEM_S_SMEM_DOUT12_MODE_M (SPI_MEM_S_SMEM_DOUT12_MODE_V << SPI_MEM_S_SMEM_DOUT12_MODE_S) +#define SPI_MEM_S_SMEM_DOUT12_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT12_MODE_S 4 +/** SPI_MEM_S_SMEM_DOUT13_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT13_MODE (BIT(5)) +#define SPI_MEM_S_SMEM_DOUT13_MODE_M (SPI_MEM_S_SMEM_DOUT13_MODE_V << SPI_MEM_S_SMEM_DOUT13_MODE_S) +#define SPI_MEM_S_SMEM_DOUT13_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT13_MODE_S 5 +/** SPI_MEM_S_SMEM_DOUT14_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT14_MODE (BIT(6)) +#define SPI_MEM_S_SMEM_DOUT14_MODE_M (SPI_MEM_S_SMEM_DOUT14_MODE_V << SPI_MEM_S_SMEM_DOUT14_MODE_S) +#define SPI_MEM_S_SMEM_DOUT14_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT14_MODE_S 6 +/** SPI_MEM_S_SMEM_DOUT15_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUT15_MODE (BIT(7)) +#define SPI_MEM_S_SMEM_DOUT15_MODE_M (SPI_MEM_S_SMEM_DOUT15_MODE_V << SPI_MEM_S_SMEM_DOUT15_MODE_S) +#define SPI_MEM_S_SMEM_DOUT15_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUT15_MODE_S 7 +/** SPI_MEM_S_SMEM_DOUTS_HEX_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE (BIT(8)) +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_M (SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V << SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S) +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_V 0x00000001U +#define SPI_MEM_S_SMEM_DOUTS_HEX_MODE_S 8 + +/** SPI_MEM_S_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x200) +/** SPI_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_MEM_S_CLK_EN (BIT(0)) +#define SPI_MEM_S_CLK_EN_M (SPI_MEM_S_CLK_EN_V << SPI_MEM_S_CLK_EN_S) +#define SPI_MEM_S_CLK_EN_V 0x00000001U +#define SPI_MEM_S_CLK_EN_S 0 + +/** SPI_MEM_S_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_S_XTS_PLAIN_BASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x300) +/** SPI_MEM_S_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_MEM_S_XTS_PLAIN 0xFFFFFFFFU +#define SPI_MEM_S_XTS_PLAIN_M (SPI_MEM_S_XTS_PLAIN_V << SPI_MEM_S_XTS_PLAIN_S) +#define SPI_MEM_S_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_MEM_S_XTS_PLAIN_S 0 + +/** SPI_MEM_S_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_S_XTS_LINESIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x340) +/** SPI_MEM_S_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_MEM_S_XTS_LINESIZE 0x00000003U +#define SPI_MEM_S_XTS_LINESIZE_M (SPI_MEM_S_XTS_LINESIZE_V << SPI_MEM_S_XTS_LINESIZE_S) +#define SPI_MEM_S_XTS_LINESIZE_V 0x00000003U +#define SPI_MEM_S_XTS_LINESIZE_S 0 + +/** SPI_MEM_S_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_S_XTS_DESTINATION_REG (DR_REG_PSRAM_MSPI0_BASE + 0x344) +/** SPI_MEM_S_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_MEM_S_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_S_XTS_DESTINATION_M (SPI_MEM_S_XTS_DESTINATION_V << SPI_MEM_S_XTS_DESTINATION_S) +#define SPI_MEM_S_XTS_DESTINATION_V 0x00000001U +#define SPI_MEM_S_XTS_DESTINATION_S 0 + +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348) +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M (SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S) +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_S_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_S_XTS_TRIGGER_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34c) +/** SPI_MEM_S_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_MEM_S_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_S_XTS_TRIGGER_M (SPI_MEM_S_XTS_TRIGGER_V << SPI_MEM_S_XTS_TRIGGER_S) +#define SPI_MEM_S_XTS_TRIGGER_V 0x00000001U +#define SPI_MEM_S_XTS_TRIGGER_S 0 + +/** SPI_MEM_S_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_S_XTS_RELEASE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x350) +/** SPI_MEM_S_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_MEM_S_XTS_RELEASE (BIT(0)) +#define SPI_MEM_S_XTS_RELEASE_M (SPI_MEM_S_XTS_RELEASE_V << SPI_MEM_S_XTS_RELEASE_S) +#define SPI_MEM_S_XTS_RELEASE_V 0x00000001U +#define SPI_MEM_S_XTS_RELEASE_S 0 + +/** SPI_MEM_S_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_S_XTS_DESTROY_REG (DR_REG_PSRAM_MSPI0_BASE + 0x354) +/** SPI_MEM_S_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_MEM_S_XTS_DESTROY (BIT(0)) +#define SPI_MEM_S_XTS_DESTROY_M (SPI_MEM_S_XTS_DESTROY_V << SPI_MEM_S_XTS_DESTROY_S) +#define SPI_MEM_S_XTS_DESTROY_V 0x00000001U +#define SPI_MEM_S_XTS_DESTROY_S 0 + +/** SPI_MEM_S_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_S_XTS_STATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x358) +/** SPI_MEM_S_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_MEM_S_XTS_STATE 0x00000003U +#define SPI_MEM_S_XTS_STATE_M (SPI_MEM_S_XTS_STATE_V << SPI_MEM_S_XTS_STATE_S) +#define SPI_MEM_S_XTS_STATE_V 0x00000003U +#define SPI_MEM_S_XTS_STATE_S 0 + +/** SPI_MEM_S_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c) +/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_MEM_S_XTS_DATE 0x3FFFFFFFU +#define SPI_MEM_S_XTS_DATE_M (SPI_MEM_S_XTS_DATE_V << SPI_MEM_S_XTS_DATE_S) +#define SPI_MEM_S_XTS_DATE_V 0x3FFFFFFFU +#define SPI_MEM_S_XTS_DATE_S 0 + +/** SPI_MEM_S_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_S_MMU_ITEM_CONTENT_REG (DR_REG_PSRAM_MSPI0_BASE + 0x37c) +/** SPI_MEM_S_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MEM_S_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_CONTENT_M (SPI_MEM_S_MMU_ITEM_CONTENT_V << SPI_MEM_S_MMU_ITEM_CONTENT_S) +#define SPI_MEM_S_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_S_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_S_MMU_ITEM_INDEX_REG (DR_REG_PSRAM_MSPI0_BASE + 0x380) +/** SPI_MEM_S_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MEM_S_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_INDEX_M (SPI_MEM_S_MMU_ITEM_INDEX_V << SPI_MEM_S_MMU_ITEM_INDEX_S) +#define SPI_MEM_S_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MEM_S_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_S_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_S_MMU_POWER_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x384) +/** SPI_MEM_S_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MEM_S_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_S_MMU_MEM_FORCE_ON_M (SPI_MEM_S_MMU_MEM_FORCE_ON_V << SPI_MEM_S_MMU_MEM_FORCE_ON_S) +#define SPI_MEM_S_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_ON_S 0 +/** SPI_MEM_S_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MEM_S_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_S_MMU_MEM_FORCE_PD_M (SPI_MEM_S_MMU_MEM_FORCE_PD_V << SPI_MEM_S_MMU_MEM_FORCE_PD_S) +#define SPI_MEM_S_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_PD_S 1 +/** SPI_MEM_S_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MEM_S_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_S_MMU_MEM_FORCE_PU_M (SPI_MEM_S_MMU_MEM_FORCE_PU_V << SPI_MEM_S_MMU_MEM_FORCE_PU_S) +#define SPI_MEM_S_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MEM_S_MMU_MEM_FORCE_PU_S 2 +/** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_S_AUX_CTRL 0x00003FFFU +#define SPI_MEM_S_AUX_CTRL_M (SPI_MEM_S_AUX_CTRL_V << SPI_MEM_S_AUX_CTRL_S) +#define SPI_MEM_S_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_S_AUX_CTRL_S 16 +/** SPI_MEM_S_RDN_ENA : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + */ +#define SPI_MEM_S_RDN_ENA (BIT(30)) +#define SPI_MEM_S_RDN_ENA_M (SPI_MEM_S_RDN_ENA_V << SPI_MEM_S_RDN_ENA_S) +#define SPI_MEM_S_RDN_ENA_V 0x00000001U +#define SPI_MEM_S_RDN_ENA_S 30 +/** SPI_MEM_S_RDN_RESULT : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + */ +#define SPI_MEM_S_RDN_RESULT (BIT(31)) +#define SPI_MEM_S_RDN_RESULT_M (SPI_MEM_S_RDN_RESULT_V << SPI_MEM_S_RDN_RESULT_S) +#define SPI_MEM_S_RDN_RESULT_V 0x00000001U +#define SPI_MEM_S_RDN_RESULT_S 31 + +/** SPI_MEM_S_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388) +/** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_M (SPI_MEM_S_CRYPT_SECURITY_LEVEL_V << SPI_MEM_S_CRYPT_SECURITY_LEVEL_S) +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_MEM_S_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_MEM_S_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_MEM_S_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_M (SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V << SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S) +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_MEM_S_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_MEM_S_CRYPT_CALC_D_DPA_EN and + * SPI_MEM_S_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_M (SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V << SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_S_REGISTERRND_ECO_HIGH_REG register + * MSPI ECO high register + */ +#define SPI_MEM_S_REGISTERRND_ECO_HIGH_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f0) +/** SPI_MEM_S_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; + * ECO high register + */ +#define SPI_MEM_S_REGISTERRND_ECO_HIGH 0xFFFFFFFFU +#define SPI_MEM_S_REGISTERRND_ECO_HIGH_M (SPI_MEM_S_REGISTERRND_ECO_HIGH_V << SPI_MEM_S_REGISTERRND_ECO_HIGH_S) +#define SPI_MEM_S_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_S_REGISTERRND_ECO_HIGH_S 0 + +/** SPI_MEM_S_REGISTERRND_ECO_LOW_REG register + * MSPI ECO low register + */ +#define SPI_MEM_S_REGISTERRND_ECO_LOW_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f4) +/** SPI_MEM_S_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; + * ECO low register + */ +#define SPI_MEM_S_REGISTERRND_ECO_LOW 0xFFFFFFFFU +#define SPI_MEM_S_REGISTERRND_ECO_LOW_M (SPI_MEM_S_REGISTERRND_ECO_LOW_V << SPI_MEM_S_REGISTERRND_ECO_LOW_S) +#define SPI_MEM_S_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_S_REGISTERRND_ECO_LOW_S 0 + +/** SPI_MEM_S_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc) +/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704; + * SPI0 register version. + */ +#define SPI_MEM_S_DATE 0x0FFFFFFFU +#define SPI_MEM_S_DATE_M (SPI_MEM_S_DATE_V << SPI_MEM_S_DATE_S) +#define SPI_MEM_S_DATE_V 0x0FFFFFFFU +#define SPI_MEM_S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_struct.h new file mode 100644 index 0000000000..05386290ac --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_mem_s_struct.h @@ -0,0 +1,2605 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of mem_cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mem_mst_st:4; + /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t mem_slv_st:4; + uint32_t reserved_8:10; + /** mem_usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t mem_usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_s_cmd_reg_t; + +/** Type of mem_axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_S_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_S_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_S_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t mem_axi_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of mem_ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t mem_wdummy_dqs_always_out:1; + /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t mem_wdummy_always_out:1; + /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t mem_fdummy_rin:1; + /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t mem_fdummy_wout:1; + /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t mem_fdout_oct:1; + /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t mem_fdin_oct:1; + /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t mem_faddr_oct:1; + uint32_t reserved_7:1; + /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_quad:1; + /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_oct:1; + uint32_t reserved_10:3; + /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT + * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t mem_fastrd_mode:1; + /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_dual:1; + uint32_t reserved_15:3; + /** mem_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t mem_q_pol:1; + /** mem_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t mem_d_pol:1; + /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_quad:1; + /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t mem_wp_reg:1; + uint32_t reserved_22:1; + /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_dio:1; + /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_qio:1; + uint32_t reserved_25:5; + /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t mem_dqs_ie_always_on:1; + /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t mem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_s_ctrl_reg_t; + +/** Type of mem_ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t mem_clk_mode:2; + uint32_t reserved_2:19; + /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ + uint32_t axi_rdata_back_fast:1; + /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_S_ECC_ERR_ADDR_REG. + */ + uint32_t mem_rresp_ecc_err_en:1; + /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t mem_ar_splice_en:1; + /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t mem_aw_splice_en:1; + /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t mem_ram0_en:1; + /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t mem_dual_ram_en:1; + /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t mem_fast_write_en:1; + /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_rxfifo_rst:1; + /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_txfifo_rst:1; + }; + uint32_t val; +} spi_mem_s_ctrl1_reg_t; + +/** Type of mem_ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_S_CS_SETUP bit. + */ + uint32_t mem_cs_setup_time:5; + /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_S_CS_HOLD bit. + */ + uint32_t mem_cs_hold_time:5; + /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t mem_ecc_cs_hold_time:3; + /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t mem_ecc_skip_page_corner:1; + /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t mem_ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** mem_split_trans_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t mem_split_trans_en:1; + /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_S_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t mem_cs_hold_delay:6; + /** mem_sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t mem_sync_reset:1; + }; + uint32_t val; +} spi_mem_s_ctrl2_reg_t; + +/** Type of mem_misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_fsub_pin : R/W; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t mem_fsub_pin:1; + /** mem_ssub_pin : R/W; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t mem_ssub_pin:1; + /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t mem_ck_idle_edge:1; + /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t mem_cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_s_misc_reg_t; + +/** Type of mem_cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + */ + uint32_t mem_axi_req_en:1; + /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + */ + uint32_t mem_cache_usr_addr_4byte:1; + /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + */ + uint32_t mem_cache_flash_usr_cmd:1; + /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_s_fread_dio. + */ + uint32_t mem_fdin_dual:1; + /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_s_fread_dio. + */ + uint32_t mem_fdout_dual:1; + /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_s_fread_dio. + */ + uint32_t mem_faddr_dual:1; + /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_s_fread_qio. + */ + uint32_t mem_fdin_quad:1; + /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_s_fread_qio. + */ + uint32_t mem_fdout_quad:1; + /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_s_fread_qio. + */ + uint32_t mem_faddr_quad:1; + uint32_t reserved_9:21; + /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_s_cache_fctrl_reg_t; + +/** Type of mem_ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_s_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of mem_clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_s_clkcnt_N. + */ + uint32_t mem_clkcnt_l:8; + /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + */ + uint32_t mem_clkcnt_h:8; + /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is + * system/(spi_mem_s_clkcnt_N+1) + */ + uint32_t mem_clkcnt_n:8; + uint32_t reserved_24:7; + /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t mem_clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_s_clock_reg_t; + +/** Type of mem_sram_clk register + * SPI0 external RAM clock control register + */ +typedef union { + struct { + /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to spi_mem_s_clkcnt_N. + */ + uint32_t mem_sclkcnt_l:8; + /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + */ + uint32_t mem_sclkcnt_h:8; + /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk + * frequency is system/(spi_mem_s_clkcnt_N+1) + */ + uint32_t mem_sclkcnt_n:8; + uint32_t reserved_24:7; + /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk + * is divided from system clock. + */ + uint32_t mem_sclk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_s_sram_clk_reg_t; + +/** Type of mem_clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_s_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of mem_user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t mem_cs_hold:1; + /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t mem_cs_setup:1; + uint32_t reserved_8:1; + /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t mem_ck_out_edge:1; + uint32_t reserved_10:16; + /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t mem_usr_dummy_idle:1; + uint32_t reserved_27:2; + /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t mem_usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_s_user_reg_t; + +/** Type of mem_user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_s_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t mem_usr_dummy_cyclelen:6; + /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t mem_usr_dbytelen:3; + uint32_t reserved_9:17; + /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t mem_usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_s_user1_reg_t; + +/** Type of mem_user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t mem_usr_command_value:16; + uint32_t reserved_16:12; + /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t mem_usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_s_user2_reg_t; + +/** Type of mem_rd_status register + * SPI0 read control register. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_s_fastrd_mode bit. + */ + uint32_t mem_wb_mode:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi_mem_s_rd_status_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of mem_cache_sctrl register + * SPI0 external RAM control register + */ +typedef union { + struct { + /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + */ + uint32_t mem_cache_usr_saddr_4byte:1; + /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + */ + uint32_t mem_usr_sram_dio:1; + /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + */ + uint32_t mem_usr_sram_qio:1; + /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + */ + uint32_t mem_usr_wr_sram_dummy:1; + /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + */ + uint32_t mem_usr_rd_sram_dummy:1; + /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + */ + uint32_t mem_cache_sram_usr_rcmd:1; + /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + */ + uint32_t mem_sram_rdummy_cyclelen:6; + uint32_t reserved_12:2; + /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + */ + uint32_t mem_sram_addr_bitlen:6; + /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + */ + uint32_t mem_cache_sram_usr_wcmd:1; + /** mem_sram_oct : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t mem_sram_oct:1; + /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + */ + uint32_t mem_sram_wdummy_cyclelen:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_s_cache_sctrl_reg_t; + +/** Type of mem_sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + */ + uint32_t mem_sclk_mode:2; + /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_s_fastrd_mode bit. + */ + uint32_t mem_swb_mode:8; + /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_s_usr_sram_dio. + */ + uint32_t mem_sdin_dual:1; + /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_s_usr_sram_dio. + */ + uint32_t mem_sdout_dual:1; + /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_s_usr_sram_dio. + */ + uint32_t mem_saddr_dual:1; + uint32_t reserved_13:1; + /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_s_usr_sram_qio. + */ + uint32_t mem_sdin_quad:1; + /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_s_usr_sram_qio. + */ + uint32_t mem_sdout_quad:1; + /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_s_usr_sram_qio. + */ + uint32_t mem_saddr_quad:1; + /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_s_usr_sram_qio. + */ + uint32_t mem_scmd_quad:1; + /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_sdin_oct:1; + /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_sdout_oct:1; + /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_saddr_oct:1; + /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + */ + uint32_t mem_scmd_oct:1; + /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ + uint32_t mem_sdummy_rin:1; + /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + */ + uint32_t mem_sdummy_wout:1; + /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + /** mem_sdin_hex : R/W; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + */ + uint32_t mem_sdin_hex:1; + /** mem_sdout_hex : R/W; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + */ + uint32_t mem_sdout_hex:1; + uint32_t reserved_28:2; + /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_s_sram_cmd_reg_t; + +/** Type of mem_sram_drd_cmd register + * SPI0 external RAM DDR read command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + */ + uint32_t mem_cache_sram_usr_rd_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + */ + uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_s_sram_drd_cmd_reg_t; + +/** Type of mem_sram_dwr_cmd register + * SPI0 external RAM DDR write command control register + */ +typedef union { + struct { + /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + */ + uint32_t mem_cache_sram_usr_wr_cmd_value:16; + uint32_t reserved_16:12; + /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + */ + uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_s_sram_dwr_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : R/W; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : R/W; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_s_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : R/W; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : R/W; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_s_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_s_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : R/W; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_mem_s_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of mem_fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t mem_lock_delay_time:5; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_s_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of mem_int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_ena:1; + /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_ena:1; + /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_ena:1; + /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_ena:1; + /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_ena:1; + /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_ena:1; + /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_ena:1; + /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_ena:1; + /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_ena:1; + /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_ena:1; + }; + uint32_t val; +} spi_mem_s_int_ena_reg_t; + +/** Type of mem_int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_clr:1; + /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_clr:1; + /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_clr:1; + /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_clr:1; + /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_clr:1; + /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_clr:1; + /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_clr:1; + /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_clr:1; + /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_clr:1; + /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_clr:1; + }; + uint32_t val; +} spi_mem_s_int_clr_reg_t; + +/** Type of mem_int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t mem_slv_st_end_int_raw:1; + /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mem_mst_st_end_int_raw:1; + /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set + * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t mem_ecc_err_int_raw:1; + /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t mem_pms_reject_int_raw:1; + /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_raddr_err_int_raw:1; + /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t mem_axi_wr_flash_err_int_raw:1; + /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ + uint32_t mem_dqs0_afifo_ovf_int_raw:1; + /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ + uint32_t mem_dqs1_afifo_ovf_int_raw:1; + /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo1_udf_int_raw:1; + /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo0_udf_int_raw:1; + }; + uint32_t val; +} spi_mem_s_int_raw_reg_t; + +/** Type of mem_int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_S_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_st:1; + /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_S_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_st:1; + /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_S_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_st:1; + /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_S_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_st:1; + /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_S_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_st:1; + /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_st:1; + /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_st:1; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_st:1; + /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_S_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_st:1; + /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_st:1; + /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_st:1; + }; + uint32_t val; +} spi_mem_s_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * MSPI flash PMS section $n attribute register + */ +typedef union { + struct { + /** fmem_pms_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + */ + uint32_t fmem_pms_rd_attr:1; + /** fmem_pms_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + */ + uint32_t fmem_pms_wr_attr:1; + /** fmem_pms_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + */ + uint32_t fmem_pms_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_mem_s_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section $n start address register + */ +typedef union { + struct { + /** fmem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section $n start address value + */ + uint32_t fmem_pms_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section $n start address register + */ +typedef union { + struct { + /** fmem_pms_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, + * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + */ + uint32_t fmem_pms_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_s_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 flash PMS section $n start address register + */ +typedef union { + struct { + /** smem_pms_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + */ + uint32_t smem_pms_rd_attr:1; + /** smem_pms_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + */ + uint32_t smem_pms_wr_attr:1; + /** smem_pms_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and + * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + */ + uint32_t smem_pms_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_mem_s_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section $n start address register + */ +typedef union { + struct { + /** smem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section $n start address value + */ + uint32_t smem_pms_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section $n start address register + */ +typedef union { + struct { + /** smem_pms_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, + * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + */ + uint32_t smem_pms_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_mem_s_smem_pmsn_size_reg_t; + +/** Type of mem_pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:27; + /** mem_pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t mem_pm_en:1; + /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ld:1; + /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_st:1; + /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_multi_hit:1; + /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ivd:1; + }; + uint32_t val; +} spi_mem_s_pms_reject_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of mem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_cnt:6; + /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + /** fmem_ecc_addr_en : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** mem_usr_ecc_addr_en : R/W; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t mem_usr_ecc_addr_en:1; + uint32_t reserved_22:2; + /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and + * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t mem_ecc_continue_record_err_en:1; + /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t mem_ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_s_ecc_ctrl_reg_t; + +/** Type of mem_ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : R/W; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_mem_s_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t mem_all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_mem_s_smem_axi_addr_ctrl_reg_t; + +/** Type of mem_axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_vld:1; + /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_gid:1; + /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_size:1; + /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_flash:1; + /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_ecc:1; + /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_sens:1; + /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_wstrb:1; + /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_vld:1; + /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_gid:1; + /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_ecc:1; + /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t mem_ar_resp_en_mmu_sens:1; + /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t mem_ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_s_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of mem_timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t mem_timing_clk_ena:1; + /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t mem_timing_cali:1; + /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t mem_extra_dummy_cyclelen:3; + /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t mem_dll_timing_cali:1; + /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t mem_timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_s_timing_cali_reg_t; + +/** Type of mem_din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din0_mode:3; + /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din1_mode:3; + /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din2_mode:3; + /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din3_mode:3; + /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din4_mode:3; + /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din5_mode:3; + /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din6_mode:3; + /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din7_mode:3; + /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_din_mode_reg_t; + +/** Type of mem_din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din0_num:2; + /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din1_num:2; + /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din2_num:2; + /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din3_num:2; + /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din4_num:2; + /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din5_num:2; + /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din6_num:2; + /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din7_num:2; + /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_s_din_num_reg_t; + +/** Type of mem_dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout0_mode:1; + /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout1_mode:1; + /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout2_mode:1; + /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout3_mode:1; + /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout4_mode:1; + /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout5_mode:1; + /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout6_mode:1; + /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout7_mode:1; + /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_s_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : R/W; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_mem_s_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_s_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_s_smem_dout_mode_reg_t; + +/** Type of smem_din_hex_mode register + * MSPI 16x external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din08_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din08_mode:3; + /** smem_din09_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din09_mode:3; + /** smem_din10_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din10_mode:3; + /** smem_din11_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din11_mode:3; + /** smem_din12_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din12_mode:3; + /** smem_din13_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din13_mode:3; + /** smem_din14_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din14_mode:3; + /** smem_din15_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din15_mode:3; + /** smem_dins_hex_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_hex_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_s_smem_din_hex_mode_reg_t; + +/** Type of smem_din_hex_num register + * MSPI 16x external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din08_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din08_num:2; + /** smem_din09_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din09_num:2; + /** smem_din10_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din10_num:2; + /** smem_din11_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din11_num:2; + /** smem_din12_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din12_num:2; + /** smem_din13_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din13_num:2; + /** smem_din14_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din14_num:2; + /** smem_din15_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din15_num:2; + /** smem_dins_hex_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_hex_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_s_smem_din_hex_num_reg_t; + +/** Type of smem_dout_hex_mode register + * MSPI 16x external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout08_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout08_mode:1; + /** smem_dout09_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout09_mode:1; + /** smem_dout10_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout10_mode:1; + /** smem_dout11_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout11_mode:1; + /** smem_dout12_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout12_mode:1; + /** smem_dout13_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout13_mode:1; + /** smem_dout14_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout14_mode:1; + /** smem_dout15_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout15_mode:1; + /** smem_douts_hex_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_hex_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_s_smem_dout_hex_mode_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of mem_xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_s_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of mem_xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_s_xts_linesize_reg_t; + +/** Type of mem_xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_s_xts_destination_reg_t; + +/** Type of mem_xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:26; + uint32_t reserved_26:6; + }; + uint32_t val; +} spi_mem_s_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of mem_xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_s_xts_trigger_reg_t; + +/** Type of mem_xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_s_xts_release_reg_t; + +/** Type of mem_xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_s_xts_destroy_reg_t; + +/** Type of mem_xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_s_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of mem_xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_s_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mem_mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_s_mmu_item_content_reg_t; + +/** Type of mem_mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_s_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mem_mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + uint32_t reserved_3:13; + /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t mem_aux_ctrl:14; + /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; + * ECO register enable bit + */ + uint32_t mem_rdn_ena:1; + /** mem_rdn_result : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + */ + uint32_t mem_rdn_result:1; + }; + uint32_t val; +} spi_mem_s_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of mem_dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_s_dpa_ctrl_reg_t; + + +/** Group: ECO registers */ +/** Type of mem_registerrnd_eco_high register + * MSPI ECO high register + */ +typedef union { + struct { + /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; + * ECO high register + */ + uint32_t mem_registerrnd_eco_high:32; + }; + uint32_t val; +} spi_mem_s_registerrnd_eco_high_reg_t; + +/** Type of mem_registerrnd_eco_low register + * MSPI ECO low register + */ +typedef union { + struct { + /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; + * ECO low register + */ + uint32_t mem_registerrnd_eco_low:32; + }; + uint32_t val; +} spi_mem_s_registerrnd_eco_low_reg_t; + + +/** Group: Version control register */ +/** Type of mem_date register + * SPI0 version control register + */ +typedef union { + struct { + /** mem_date : R/W; bitpos: [27:0]; default: 36712704; + * SPI0 register version. + */ + uint32_t mem_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_s_date_reg_t; + + +typedef struct spi_mem_s_dev_t { + volatile spi_mem_s_cmd_reg_t mem_cmd; + uint32_t reserved_004; + volatile spi_mem_s_ctrl_reg_t mem_ctrl; + volatile spi_mem_s_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_s_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_s_clock_reg_t mem_clock; + volatile spi_mem_s_user_reg_t mem_user; + volatile spi_mem_s_user1_reg_t mem_user1; + volatile spi_mem_s_user2_reg_t mem_user2; + uint32_t reserved_024[2]; + volatile spi_mem_s_rd_status_reg_t mem_rd_status; + uint32_t reserved_030; + volatile spi_mem_s_misc_reg_t mem_misc; + uint32_t reserved_038; + volatile spi_mem_s_cache_fctrl_reg_t mem_cache_fctrl; + volatile spi_mem_s_cache_sctrl_reg_t mem_cache_sctrl; + volatile spi_mem_s_sram_cmd_reg_t mem_sram_cmd; + volatile spi_mem_s_sram_drd_cmd_reg_t mem_sram_drd_cmd; + volatile spi_mem_s_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; + volatile spi_mem_s_sram_clk_reg_t mem_sram_clk; + volatile spi_mem_s_fsm_reg_t mem_fsm; + uint32_t reserved_058[26]; + volatile spi_mem_s_int_ena_reg_t mem_int_ena; + volatile spi_mem_s_int_clr_reg_t mem_int_clr; + volatile spi_mem_s_int_raw_reg_t mem_int_raw; + volatile spi_mem_s_int_st_reg_t mem_int_st; + uint32_t reserved_0d0; + volatile spi_mem_s_ddr_reg_t mem_ddr; + volatile spi_mem_s_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_mem_s_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_mem_s_smem_pmsn_size_reg_t smem_pmsn_size[4]; + uint32_t reserved_160; + volatile spi_mem_s_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_s_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_s_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_s_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_mem_s_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_mem_s_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_s_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_s_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_s_din_mode_reg_t mem_din_mode; + volatile spi_mem_s_din_num_reg_t mem_din_num; + volatile spi_mem_s_dout_mode_reg_t mem_dout_mode; + volatile spi_mem_s_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_mem_s_smem_din_mode_reg_t smem_din_mode; + volatile spi_mem_s_smem_din_num_reg_t smem_din_num; + volatile spi_mem_s_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_mem_s_smem_ac_reg_t smem_ac; + volatile spi_mem_s_smem_din_hex_mode_reg_t smem_din_hex_mode; + volatile spi_mem_s_smem_din_hex_num_reg_t smem_din_hex_num; + volatile spi_mem_s_smem_dout_hex_mode_reg_t smem_dout_hex_mode; + uint32_t reserved_1b0[20]; + volatile spi_mem_s_clock_gate_reg_t mem_clock_gate; + uint32_t reserved_204[63]; + volatile spi_mem_s_xts_plain_base_reg_t mem_xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_s_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_s_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_s_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_s_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_s_xts_release_reg_t mem_xts_release; + volatile spi_mem_s_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_s_xts_state_reg_t mem_xts_state; + volatile spi_mem_s_xts_date_reg_t mem_xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_s_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl; + uint32_t reserved_38c[25]; + volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; + volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; + uint32_t reserved_3f8; + volatile spi_mem_s_date_reg_t mem_date; +} spi_mem_s_dev_t; + +extern spi_mem_s_dev_t SPIMEM2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_s_dev_t) == 0x400, "Invalid size of spi_mem_s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_reg.h new file mode 100644 index 0000000000..f5aa935cca --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_reg.h @@ -0,0 +1,2152 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +//this field is only for GPSPI2 +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +//this field is only for GPSPI2 +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : R/W; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +//this field is only for GPSPI2 +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +//This field for GPSPI3 is only 3-bit-width +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : R/W; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +//this field is only for GPSPI2 +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : R/W; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : R/W; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : R/W; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : R/W; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +//this field is only for GPSPI2 +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +//this field is only for GPSPI2 +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +//this field is only for GPSPI2 +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ +//this field is only for GPSPI2 +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +//this field is only for GPSPI2 +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +//this field is only for GPSPI2 +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ +#define SPI_SLV_LAST_BYTE_STRB 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_M (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S) +#define SPI_SLV_LAST_BYTE_STRB_V 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_S 12 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ +//this field is only for GPSPI2 +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +//this field is only for GPSPI2 +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 35680770; + * SPI register version. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/spi_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/spi_struct.h new file mode 100644 index 0000000000..64da6d07f3 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/spi_struct.h @@ -0,0 +1,1026 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; //this field is only for GPSPI2 + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : R/W; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; //this field is only for GPSPI2 + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; //this field is only for GPSPI2 + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; //this field is only for GPSPI2 + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; //this field is only for GPSPI2 + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; //this field is only for GPSPI2 + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; //this field is only for GPSPI2 + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; //this field is only for GPSPI2 + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; //this field is only for GPSPI2 + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; //this field is only for GPSPI2 + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; //This field for GPSPI3 is only 3-bit-width + uint32_t reserved_13:3; + /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; //this field is only for GPSPI2 + /** data_dtr_en : R/W; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; //this field is only for GPSPI2 + /** addr_dtr_en : R/W; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; //this field is only for GPSPI2 + /** cmd_dtr_en : R/W; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; //this field is only for GPSPI2 + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; //this field is only for GPSPI2 + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ + uint32_t slv_last_byte_strb:8; + uint32_t reserved_20:2; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; //this field is only for GPSPI2 + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; //this field is only for GPSPI2 + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; //this field is only for GPSPI2 + /** din5_mode : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; //this field is only for GPSPI2 + /** din6_mode : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; //this field is only for GPSPI2 + /** din7_mode : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; //this field is only for GPSPI2 + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; //this field is only for GPSPI2 + /** din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; //this field is only for GPSPI2 + /** din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; //this field is only for GPSPI2 + /** din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; //this field is only for GPSPI2 + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : R/W; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; //this field is only for GPSPI2 + /** dout5_mode : R/W; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; //this field is only for GPSPI2 + /** dout6_mode : R/W; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; //this field is only for GPSPI2 + /** dout7_mode : R/W; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; //this field is only for GPSPI2 + /** d_dqs_mode : R/W; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; //this field is only for GPSPI2 + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + +/** Type of dma_int register + * SPI interrupt raw/ena/clr/sta/set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; //this field is only forPI2 + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_reg_t; + +/** Type of wn register + * SPI CPU-controlled buffer + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf:32; + }; + uint32_t val; +} spi_wn_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35680770; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_reg_t dma_int_ena; + volatile spi_dma_int_reg_t dma_int_clr; + volatile spi_dma_int_reg_t dma_int_raw; + volatile spi_dma_int_reg_t dma_int_sta; + volatile spi_dma_int_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_wn_reg_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; +extern spi_dev_t GPSPI3; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/systimer_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/systimer_reg.h new file mode 100644 index 0000000000..5a8fd9e16d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/systimer_reg.h @@ -0,0 +1,630 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/systimer_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/systimer_struct.h new file mode 100644 index 0000000000..8716983ec9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/systimer_struct.h @@ -0,0 +1,376 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit_op register + * system timer unit value update register + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit + */ + uint32_t timer_unit_update: 1; + uint32_t reserved31: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * system timer unit value high and low load register + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 20 bit + */ + uint32_t timer_unit_load_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of unit_value_hi register + * system timer unit value high and low register + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20 bit + */ + uint32_t timer_unit_value_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32 bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + +/** Type of unit_load register + * system timer unit conf sync register + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_unit_load_reg_t; + + +/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */ +/** Type of target register + * system timer comp value high and low register + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 20 bit + */ + uint32_t timer_target_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * system timer comp target mode register + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of comp_load register + * system timer comp conf sync register + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp sync enable signal + */ + uint32_t timer_comp_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_comp_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP STATUS REGISTER */ +/** Type of real_target_hi/lo register + * system timer comp actual target value low register + */ +typedef struct { + union { + struct { + /** target_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32 bits + */ + uint32_t target_lo_ro: 32; + }; + uint32_t val; + } lo; + union { + struct { + /** target_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20 bits + */ + uint32_t target_hi_ro: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; +} systimer_real_target_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct systimer_dev_t { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target_reg_t real_target[3]; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h new file mode 100644 index 0000000000..cb893d2353 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h @@ -0,0 +1,716 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0) +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_T1CONFIG_REG register + * Timer 1 configuration register + */ +#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24) +/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) +#define TIMG_T1_ALARM_EN_V 0x00000001U +#define TIMG_T1_ALARM_EN_S 10 +/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 1 's clock divider counter will be reset. + */ +#define TIMG_T1_DIVCNT_RST (BIT(12)) +#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S) +#define TIMG_T1_DIVCNT_RST_V 0x00000001U +#define TIMG_T1_DIVCNT_RST_S 12 +/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 1 clock (T1_clk) prescaler value. + */ +#define TIMG_T1_DIVIDER 0x0000FFFFU +#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) +#define TIMG_T1_DIVIDER_V 0x0000FFFFU +#define TIMG_T1_DIVIDER_S 13 +/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 1 auto-reload at alarm is enabled. + */ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) +#define TIMG_T1_AUTORELOAD_V 0x00000001U +#define TIMG_T1_AUTORELOAD_S 29 +/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 1 time-base counter will increment every clock tick. When + * cleared, the timer 1 time-base counter will decrement. + */ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) +#define TIMG_T1_INCREASE_V 0x00000001U +#define TIMG_T1_INCREASE_S 30 +/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 1 time-base counter is enabled. + */ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) +#define TIMG_T1_EN_V 0x00000001U +#define TIMG_T1_EN_S 31 + +/** TIMG_T1LO_REG register + * Timer 1 current value, low 32 bits + */ +#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28) +/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_LO 0xFFFFFFFFU +#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) +#define TIMG_T1_LO_V 0xFFFFFFFFU +#define TIMG_T1_LO_S 0 + +/** TIMG_T1HI_REG register + * Timer 1 current value, high 22 bits + */ +#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c) +/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_HI 0x003FFFFFU +#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) +#define TIMG_T1_HI_V 0x003FFFFFU +#define TIMG_T1_HI_S 0 + +/** TIMG_T1UPDATE_REG register + * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG + */ +#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30) +/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. + */ +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) +#define TIMG_T1_UPDATE_V 0x00000001U +#define TIMG_T1_UPDATE_S 31 + +/** TIMG_T1ALARMLO_REG register + * Timer 1 alarm value, low 32 bits + */ +#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34) +/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T1_ALARM_LO 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_S 0 + +/** TIMG_T1ALARMHI_REG register + * Timer 1 alarm value, high bits + */ +#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38) +/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T1_ALARM_HI 0x003FFFFFU +#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) +#define TIMG_T1_ALARM_HI_V 0x003FFFFFU +#define TIMG_T1_ALARM_HI_S 0 + +/** TIMG_T1LOADLO_REG register + * Timer 1 reload value, low 32 bits + */ +#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c) +/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 1 time-base + * Counter. + */ +#define TIMG_T1_LOAD_LO 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_S 0 + +/** TIMG_T1LOADHI_REG register + * Timer 1 reload value, high 22 bits + */ +#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40) +/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 1 time-base + * counter. + */ +#define TIMG_T1_LOAD_HI 0x003FFFFFU +#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) +#define TIMG_T1_LOAD_HI_V 0x003FFFFFU +#define TIMG_T1_LOAD_HI_S 0 + +/** TIMG_T1LOAD_REG register + * Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG + */ +#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44) +/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 1 time-base counter reload. + */ +#define TIMG_T1_LOAD 0xFFFFFFFFU +#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) +#define TIMG_T1_LOAD_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) +#define TIMG_T1_INT_ENA_V 0x00000001U +#define TIMG_T1_INT_ENA_S 1 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 2 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) +#define TIMG_T1_INT_RAW_V 0x00000001U +#define TIMG_T1_INT_RAW_S 1 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 2 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) +#define TIMG_T1_INT_ST_V 0x00000001U +#define TIMG_T1_INT_ST_S 1 +/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 2 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) +#define TIMG_T1_INT_CLR_V 0x00000001U +#define TIMG_T1_INT_CLR_S 1 +/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 2 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h new file mode 100644 index 0000000000..363dff92d1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h @@ -0,0 +1,571 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + uint32_t reserved_21:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + /** t1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_ena:1; + /** wdt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_raw:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + /** t1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_st:1; + /** wdt_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + /** t1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_clr:1; + /** wdt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_29:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct { + volatile timg_txconfig_reg_t t0config; + volatile timg_txlo_reg_t t0lo; + volatile timg_txhi_reg_t t0hi; + volatile timg_txupdate_reg_t t0update; + volatile timg_txalarmlo_reg_t t0alarmlo; + volatile timg_txalarmhi_reg_t t0alarmhi; + volatile timg_txloadlo_reg_t t0loadlo; + volatile timg_txloadhi_reg_t t0loadhi; + volatile timg_txload_reg_t t0load; + volatile timg_txconfig_reg_t t1config; + volatile timg_txlo_reg_t t1lo; + volatile timg_txhi_reg_t t1hi; + volatile timg_txupdate_reg_t t1update; + volatile timg_txalarmlo_reg_t t1alarmlo; + volatile timg_txalarmhi_reg_t t1alarmhi; + volatile timg_txloadlo_reg_t t1loadlo; + volatile timg_txloadhi_reg_t t1loadhi; + volatile timg_txload_reg_t t1load; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h new file mode 100644 index 0000000000..7df8a1271f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h @@ -0,0 +1,718 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13422 + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_T1CONFIG_REG register + * Timer 1 configuration register + */ +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24) +/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) +#define TIMG_T1_ALARM_EN_V 0x00000001U +#define TIMG_T1_ALARM_EN_S 10 +/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 1 's clock divider counter will be reset. + */ +#define TIMG_T1_DIVCNT_RST (BIT(12)) +#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S) +#define TIMG_T1_DIVCNT_RST_V 0x00000001U +#define TIMG_T1_DIVCNT_RST_S 12 +/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 1 clock (T1_clk) prescaler value. + */ +#define TIMG_T1_DIVIDER 0x0000FFFFU +#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) +#define TIMG_T1_DIVIDER_V 0x0000FFFFU +#define TIMG_T1_DIVIDER_S 13 +/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 1 auto-reload at alarm is enabled. + */ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) +#define TIMG_T1_AUTORELOAD_V 0x00000001U +#define TIMG_T1_AUTORELOAD_S 29 +/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 1 time-base counter will increment every clock tick. When + * cleared, the timer 1 time-base counter will decrement. + */ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) +#define TIMG_T1_INCREASE_V 0x00000001U +#define TIMG_T1_INCREASE_S 30 +/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 1 time-base counter is enabled. + */ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) +#define TIMG_T1_EN_V 0x00000001U +#define TIMG_T1_EN_S 31 + +/** TIMG_T1LO_REG register + * Timer 1 current value, low 32 bits + */ +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28) +/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_LO 0xFFFFFFFFU +#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) +#define TIMG_T1_LO_V 0xFFFFFFFFU +#define TIMG_T1_LO_S 0 + +/** TIMG_T1HI_REG register + * Timer 1 current value, high 22 bits + */ +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c) +/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter + * of timer 1 can be read here. + */ +#define TIMG_T1_HI 0x003FFFFFU +#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) +#define TIMG_T1_HI_V 0x003FFFFFU +#define TIMG_T1_HI_S 0 + +/** TIMG_T1UPDATE_REG register + * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG + */ +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30) +/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. + */ +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) +#define TIMG_T1_UPDATE_V 0x00000001U +#define TIMG_T1_UPDATE_S 31 + +/** TIMG_T1ALARMLO_REG register + * Timer 1 alarm value, low 32 bits + */ +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34) +/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T1_ALARM_LO 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T1_ALARM_LO_S 0 + +/** TIMG_T1ALARMHI_REG register + * Timer 1 alarm value, high bits + */ +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38) +/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T1_ALARM_HI 0x003FFFFFU +#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) +#define TIMG_T1_ALARM_HI_V 0x003FFFFFU +#define TIMG_T1_ALARM_HI_S 0 + +/** TIMG_T1LOADLO_REG register + * Timer 1 reload value, low 32 bits + */ +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c) +/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 1 time-base + * Counter. + */ +#define TIMG_T1_LOAD_LO 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_LO_S 0 + +/** TIMG_T1LOADHI_REG register + * Timer 1 reload value, high 22 bits + */ +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40) +/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 1 time-base + * counter. + */ +#define TIMG_T1_LOAD_HI 0x003FFFFFU +#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) +#define TIMG_T1_LOAD_HI_V 0x003FFFFFU +#define TIMG_T1_LOAD_HI_S 0 + +/** TIMG_T1LOAD_REG register + * Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG + */ +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44) +/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 1 time-base counter reload. + */ +#define TIMG_T1_LOAD 0xFFFFFFFFU +#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) +#define TIMG_T1_LOAD_V 0xFFFFFFFFU +#define TIMG_T1_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) +#define TIMG_T1_INT_ENA_V 0x00000001U +#define TIMG_T1_INT_ENA_S 1 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 2 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) +#define TIMG_T1_INT_RAW_V 0x00000001U +#define TIMG_T1_INT_RAW_S 1 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 2 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) +#define TIMG_T1_INT_ST_V 0x00000001U +#define TIMG_T1_INT_ST_S 1 +/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 2 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) +#define TIMG_T1_INT_CLR_V 0x00000001U +#define TIMG_T1_INT_CLR_S 1 +/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 2 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h new file mode 100644 index 0000000000..1189b1d491 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h @@ -0,0 +1,563 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13422 + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0: 10; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en: 1; + uint32_t reserved_11: 1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst: 1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider: 16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload: 1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase: 1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en: 1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo: 32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi: 22; + uint32_t reserved_22: 10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0: 31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update: 1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo: 32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi: 22; + uint32_t reserved_22: 10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo: 32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi: 22; + uint32_t reserved_22: 10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load: 32; + }; + uint32_t val; +} timg_txload_reg_t; + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0: 12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en: 1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en: 1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en: 1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length: 3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length: 3; + uint32_t reserved_21: 1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en: 1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3: 2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2: 2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1: 2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0: 2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en: 1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst: 1; + uint32_t reserved_1: 15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale: 16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold: 32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold: 32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold: 32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold: 32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed: 32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey: 32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0: 12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling: 1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel: 2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy: 1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max: 15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start: 1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld: 1; + uint32_t reserved_1: 6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value: 25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout: 1; + uint32_t reserved_1: 2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt: 4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres: 25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena: 1; + /** t1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_ena: 1; + /** wdt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw: 1; + /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_raw: 1; + /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st: 1; + /** t1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_st: 1; + /** wdt_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr: 1; + /** t1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t1_int_clr: 1; + /** wdt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ + uint32_t ntimgs_date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0: 28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en: 1; + uint32_t reserved_29: 2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} timg_regclk_reg_t; + +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; + +typedef struct timg_dev_t { + volatile timg_hwtimer_reg_t hw_timer[2]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/touch_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/touch_reg.h new file mode 100644 index 0000000000..d3173425c5 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/touch_reg.h @@ -0,0 +1,766 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13423 + +/** RTC_TOUCH_INT_RAW_REG register + * need_des + */ +#define RTC_TOUCH_INT_RAW_REG (DR_REG_LP_TOUCH_BASE + 0x0) +/** RTC_TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_RAW (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_RAW_M (RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_TOUCH_SCAN_DONE_INT_RAW_S) +#define RTC_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_RAW_S 0 +/** RTC_TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_RAW (BIT(1)) +#define RTC_TOUCH_DONE_INT_RAW_M (RTC_TOUCH_DONE_INT_RAW_V << RTC_TOUCH_DONE_INT_RAW_S) +#define RTC_TOUCH_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_DONE_INT_RAW_S 1 +/** RTC_TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_RAW_M (RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_TOUCH_ACTIVE_INT_RAW_S) +#define RTC_TOUCH_ACTIVE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_RAW_S 2 +/** RTC_TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_RAW (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_RAW_M (RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_TOUCH_INACTIVE_INT_RAW_S) +#define RTC_TOUCH_INACTIVE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_RAW_S 3 +/** RTC_TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_RAW (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_RAW_M (RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_TOUCH_TIMEOUT_INT_RAW_S) +#define RTC_TOUCH_TIMEOUT_INT_RAW_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_RAW_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5 + +/** RTC_TOUCH_INT_ST_REG register + * need_des + */ +#define RTC_TOUCH_INT_ST_REG (DR_REG_LP_TOUCH_BASE + 0x4) +/** RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_ST (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_ST_M (RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_TOUCH_SCAN_DONE_INT_ST_S) +#define RTC_TOUCH_SCAN_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_ST_S 0 +/** RTC_TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_ST (BIT(1)) +#define RTC_TOUCH_DONE_INT_ST_M (RTC_TOUCH_DONE_INT_ST_V << RTC_TOUCH_DONE_INT_ST_S) +#define RTC_TOUCH_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_DONE_INT_ST_S 1 +/** RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_ST_M (RTC_TOUCH_ACTIVE_INT_ST_V << RTC_TOUCH_ACTIVE_INT_ST_S) +#define RTC_TOUCH_ACTIVE_INT_ST_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_ST_S 2 +/** RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_ST (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_ST_M (RTC_TOUCH_INACTIVE_INT_ST_V << RTC_TOUCH_INACTIVE_INT_ST_S) +#define RTC_TOUCH_INACTIVE_INT_ST_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_ST_S 3 +/** RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_ST (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_ST_M (RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_TOUCH_TIMEOUT_INT_ST_S) +#define RTC_TOUCH_TIMEOUT_INT_ST_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_ST_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5 + +/** RTC_TOUCH_INT_ENA_REG register + * need_des + */ +#define RTC_TOUCH_INT_ENA_REG (DR_REG_LP_TOUCH_BASE + 0x8) +/** RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_ENA (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_ENA_M (RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_TOUCH_SCAN_DONE_INT_ENA_S) +#define RTC_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_ENA_S 0 +/** RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_ENA (BIT(1)) +#define RTC_TOUCH_DONE_INT_ENA_M (RTC_TOUCH_DONE_INT_ENA_V << RTC_TOUCH_DONE_INT_ENA_S) +#define RTC_TOUCH_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_DONE_INT_ENA_S 1 +/** RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_ENA_M (RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_TOUCH_ACTIVE_INT_ENA_S) +#define RTC_TOUCH_ACTIVE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_ENA_S 2 +/** RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_ENA (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_ENA_M (RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_TOUCH_INACTIVE_INT_ENA_S) +#define RTC_TOUCH_INACTIVE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_ENA_S 3 +/** RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_ENA (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_ENA_M (RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_TOUCH_TIMEOUT_INT_ENA_S) +#define RTC_TOUCH_TIMEOUT_INT_ENA_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_ENA_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5 + +/** RTC_TOUCH_INT_CLR_REG register + * need_des + */ +#define RTC_TOUCH_INT_CLR_REG (DR_REG_LP_TOUCH_BASE + 0xc) +/** RTC_TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_DONE_INT_CLR (BIT(0)) +#define RTC_TOUCH_SCAN_DONE_INT_CLR_M (RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_TOUCH_SCAN_DONE_INT_CLR_S) +#define RTC_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_SCAN_DONE_INT_CLR_S 0 +/** RTC_TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * need_des + */ +#define RTC_TOUCH_DONE_INT_CLR (BIT(1)) +#define RTC_TOUCH_DONE_INT_CLR_M (RTC_TOUCH_DONE_INT_CLR_V << RTC_TOUCH_DONE_INT_CLR_S) +#define RTC_TOUCH_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_DONE_INT_CLR_S 1 +/** RTC_TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0; + * need_des + */ +#define RTC_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define RTC_TOUCH_ACTIVE_INT_CLR_M (RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_TOUCH_ACTIVE_INT_CLR_S) +#define RTC_TOUCH_ACTIVE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_ACTIVE_INT_CLR_S 2 +/** RTC_TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0; + * need_des + */ +#define RTC_TOUCH_INACTIVE_INT_CLR (BIT(3)) +#define RTC_TOUCH_INACTIVE_INT_CLR_M (RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_TOUCH_INACTIVE_INT_CLR_S) +#define RTC_TOUCH_INACTIVE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_INACTIVE_INT_CLR_S 3 +/** RTC_TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0; + * need_des + */ +#define RTC_TOUCH_TIMEOUT_INT_CLR (BIT(4)) +#define RTC_TOUCH_TIMEOUT_INT_CLR_M (RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_TOUCH_TIMEOUT_INT_CLR_S) +#define RTC_TOUCH_TIMEOUT_INT_CLR_V 0x00000001U +#define RTC_TOUCH_TIMEOUT_INT_CLR_S 4 +/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(5)) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S) +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5 + +/** RTC_TOUCH_CHN_STATUS_REG register + * need_des + */ +#define RTC_TOUCH_CHN_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x10) +/** RTC_TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_ACTIVE 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_M (RTC_TOUCH_PAD_ACTIVE_V << RTC_TOUCH_PAD_ACTIVE_S) +#define RTC_TOUCH_PAD_ACTIVE_V 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_S 0 +/** RTC_TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define RTC_TOUCH_MEAS_DONE (BIT(15)) +#define RTC_TOUCH_MEAS_DONE_M (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S) +#define RTC_TOUCH_MEAS_DONE_V 0x00000001U +#define RTC_TOUCH_MEAS_DONE_S 15 +/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_SCAN_CURR 0x0000000FU +#define RTC_TOUCH_SCAN_CURR_M (RTC_TOUCH_SCAN_CURR_V << RTC_TOUCH_SCAN_CURR_S) +#define RTC_TOUCH_SCAN_CURR_V 0x0000000FU +#define RTC_TOUCH_SCAN_CURR_S 16 + +/** RTC_TOUCH_STATUS_0_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_0_REG (DR_REG_LP_TOUCH_BASE + 0x14) +/** RTC_TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD0_DATA_M (RTC_TOUCH_PAD0_DATA_V << RTC_TOUCH_PAD0_DATA_S) +#define RTC_TOUCH_PAD0_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD0_DATA_S 0 +/** RTC_TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_M (RTC_TOUCH_PAD0_DEBOUNCE_CNT_V << RTC_TOUCH_PAD0_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD0_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_M (RTC_TOUCH_PAD0_NEG_NOISE_CNT_V << RTC_TOUCH_PAD0_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_1_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_1_REG (DR_REG_LP_TOUCH_BASE + 0x18) +/** RTC_TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD1_DATA_M (RTC_TOUCH_PAD1_DATA_V << RTC_TOUCH_PAD1_DATA_S) +#define RTC_TOUCH_PAD1_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD1_DATA_S 0 +/** RTC_TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_M (RTC_TOUCH_PAD1_DEBOUNCE_CNT_V << RTC_TOUCH_PAD1_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD1_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_M (RTC_TOUCH_PAD1_NEG_NOISE_CNT_V << RTC_TOUCH_PAD1_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_2_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_2_REG (DR_REG_LP_TOUCH_BASE + 0x1c) +/** RTC_TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD2_DATA_M (RTC_TOUCH_PAD2_DATA_V << RTC_TOUCH_PAD2_DATA_S) +#define RTC_TOUCH_PAD2_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD2_DATA_S 0 +/** RTC_TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_M (RTC_TOUCH_PAD2_DEBOUNCE_CNT_V << RTC_TOUCH_PAD2_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD2_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_M (RTC_TOUCH_PAD2_NEG_NOISE_CNT_V << RTC_TOUCH_PAD2_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_3_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_3_REG (DR_REG_LP_TOUCH_BASE + 0x20) +/** RTC_TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD3_DATA_M (RTC_TOUCH_PAD3_DATA_V << RTC_TOUCH_PAD3_DATA_S) +#define RTC_TOUCH_PAD3_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD3_DATA_S 0 +/** RTC_TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_M (RTC_TOUCH_PAD3_DEBOUNCE_CNT_V << RTC_TOUCH_PAD3_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD3_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_M (RTC_TOUCH_PAD3_NEG_NOISE_CNT_V << RTC_TOUCH_PAD3_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_4_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_4_REG (DR_REG_LP_TOUCH_BASE + 0x24) +/** RTC_TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD4_DATA_M (RTC_TOUCH_PAD4_DATA_V << RTC_TOUCH_PAD4_DATA_S) +#define RTC_TOUCH_PAD4_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD4_DATA_S 0 +/** RTC_TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_M (RTC_TOUCH_PAD4_DEBOUNCE_CNT_V << RTC_TOUCH_PAD4_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD4_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_M (RTC_TOUCH_PAD4_NEG_NOISE_CNT_V << RTC_TOUCH_PAD4_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_5_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_5_REG (DR_REG_LP_TOUCH_BASE + 0x28) +/** RTC_TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD5_DATA_M (RTC_TOUCH_PAD5_DATA_V << RTC_TOUCH_PAD5_DATA_S) +#define RTC_TOUCH_PAD5_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD5_DATA_S 0 +/** RTC_TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_M (RTC_TOUCH_PAD5_DEBOUNCE_CNT_V << RTC_TOUCH_PAD5_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD5_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_M (RTC_TOUCH_PAD5_NEG_NOISE_CNT_V << RTC_TOUCH_PAD5_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_6_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_6_REG (DR_REG_LP_TOUCH_BASE + 0x2c) +/** RTC_TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD6_DATA_M (RTC_TOUCH_PAD6_DATA_V << RTC_TOUCH_PAD6_DATA_S) +#define RTC_TOUCH_PAD6_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD6_DATA_S 0 +/** RTC_TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_M (RTC_TOUCH_PAD6_DEBOUNCE_CNT_V << RTC_TOUCH_PAD6_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD6_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_M (RTC_TOUCH_PAD6_NEG_NOISE_CNT_V << RTC_TOUCH_PAD6_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_7_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_7_REG (DR_REG_LP_TOUCH_BASE + 0x30) +/** RTC_TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD7_DATA_M (RTC_TOUCH_PAD7_DATA_V << RTC_TOUCH_PAD7_DATA_S) +#define RTC_TOUCH_PAD7_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD7_DATA_S 0 +/** RTC_TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_M (RTC_TOUCH_PAD7_DEBOUNCE_CNT_V << RTC_TOUCH_PAD7_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD7_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_M (RTC_TOUCH_PAD7_NEG_NOISE_CNT_V << RTC_TOUCH_PAD7_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_8_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_8_REG (DR_REG_LP_TOUCH_BASE + 0x34) +/** RTC_TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD8_DATA_M (RTC_TOUCH_PAD8_DATA_V << RTC_TOUCH_PAD8_DATA_S) +#define RTC_TOUCH_PAD8_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD8_DATA_S 0 +/** RTC_TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_M (RTC_TOUCH_PAD8_DEBOUNCE_CNT_V << RTC_TOUCH_PAD8_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD8_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_M (RTC_TOUCH_PAD8_NEG_NOISE_CNT_V << RTC_TOUCH_PAD8_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_9_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_9_REG (DR_REG_LP_TOUCH_BASE + 0x38) +/** RTC_TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD9_DATA_M (RTC_TOUCH_PAD9_DATA_V << RTC_TOUCH_PAD9_DATA_S) +#define RTC_TOUCH_PAD9_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD9_DATA_S 0 +/** RTC_TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_M (RTC_TOUCH_PAD9_DEBOUNCE_CNT_V << RTC_TOUCH_PAD9_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD9_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_M (RTC_TOUCH_PAD9_NEG_NOISE_CNT_V << RTC_TOUCH_PAD9_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_10_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_10_REG (DR_REG_LP_TOUCH_BASE + 0x3c) +/** RTC_TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD10_DATA_M (RTC_TOUCH_PAD10_DATA_V << RTC_TOUCH_PAD10_DATA_S) +#define RTC_TOUCH_PAD10_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD10_DATA_S 0 +/** RTC_TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_M (RTC_TOUCH_PAD10_DEBOUNCE_CNT_V << RTC_TOUCH_PAD10_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD10_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_M (RTC_TOUCH_PAD10_NEG_NOISE_CNT_V << RTC_TOUCH_PAD10_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_11_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_11_REG (DR_REG_LP_TOUCH_BASE + 0x40) +/** RTC_TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD11_DATA_M (RTC_TOUCH_PAD11_DATA_V << RTC_TOUCH_PAD11_DATA_S) +#define RTC_TOUCH_PAD11_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD11_DATA_S 0 +/** RTC_TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_M (RTC_TOUCH_PAD11_DEBOUNCE_CNT_V << RTC_TOUCH_PAD11_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD11_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_M (RTC_TOUCH_PAD11_NEG_NOISE_CNT_V << RTC_TOUCH_PAD11_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_12_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_12_REG (DR_REG_LP_TOUCH_BASE + 0x44) +/** RTC_TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD12_DATA_M (RTC_TOUCH_PAD12_DATA_V << RTC_TOUCH_PAD12_DATA_S) +#define RTC_TOUCH_PAD12_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD12_DATA_S 0 +/** RTC_TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_M (RTC_TOUCH_PAD12_DEBOUNCE_CNT_V << RTC_TOUCH_PAD12_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD12_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_M (RTC_TOUCH_PAD12_NEG_NOISE_CNT_V << RTC_TOUCH_PAD12_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_13_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_13_REG (DR_REG_LP_TOUCH_BASE + 0x48) +/** RTC_TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD13_DATA_M (RTC_TOUCH_PAD13_DATA_V << RTC_TOUCH_PAD13_DATA_S) +#define RTC_TOUCH_PAD13_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD13_DATA_S 0 +/** RTC_TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_M (RTC_TOUCH_PAD13_DEBOUNCE_CNT_V << RTC_TOUCH_PAD13_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD13_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_M (RTC_TOUCH_PAD13_NEG_NOISE_CNT_V << RTC_TOUCH_PAD13_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_14_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_14_REG (DR_REG_LP_TOUCH_BASE + 0x4c) +/** RTC_TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_DATA 0x0000FFFFU +#define RTC_TOUCH_PAD14_DATA_M (RTC_TOUCH_PAD14_DATA_V << RTC_TOUCH_PAD14_DATA_S) +#define RTC_TOUCH_PAD14_DATA_V 0x0000FFFFU +#define RTC_TOUCH_PAD14_DATA_S 0 +/** RTC_TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_M (RTC_TOUCH_PAD14_DEBOUNCE_CNT_V << RTC_TOUCH_PAD14_DEBOUNCE_CNT_S) +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_PAD14_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_M (RTC_TOUCH_PAD14_NEG_NOISE_CNT_V << RTC_TOUCH_PAD14_NEG_NOISE_CNT_S) +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_15_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_15_REG (DR_REG_LP_TOUCH_BASE + 0x50) +/** RTC_TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_DATA 0x0000FFFFU +#define RTC_TOUCH_SLP_DATA_M (RTC_TOUCH_SLP_DATA_V << RTC_TOUCH_SLP_DATA_S) +#define RTC_TOUCH_SLP_DATA_V 0x0000FFFFU +#define RTC_TOUCH_SLP_DATA_S 0 +/** RTC_TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_DEBOUNCE_CNT 0x00000007U +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_M (RTC_TOUCH_SLP_DEBOUNCE_CNT_V << RTC_TOUCH_SLP_DEBOUNCE_CNT_S) +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_V 0x00000007U +#define RTC_TOUCH_SLP_DEBOUNCE_CNT_S 16 +/** RTC_TOUCH_SLP_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_NEG_NOISE_CNT 0x0000000FU +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_M (RTC_TOUCH_SLP_NEG_NOISE_CNT_V << RTC_TOUCH_SLP_NEG_NOISE_CNT_S) +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_V 0x0000000FU +#define RTC_TOUCH_SLP_NEG_NOISE_CNT_S 19 + +/** RTC_TOUCH_STATUS_16_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_16_REG (DR_REG_LP_TOUCH_BASE + 0x54) +/** RTC_TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD2_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD2_CNT_M (RTC_TOUCH_APPROACH_PAD2_CNT_V << RTC_TOUCH_APPROACH_PAD2_CNT_S) +#define RTC_TOUCH_APPROACH_PAD2_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD2_CNT_S 0 +/** RTC_TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD1_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD1_CNT_M (RTC_TOUCH_APPROACH_PAD1_CNT_V << RTC_TOUCH_APPROACH_PAD1_CNT_S) +#define RTC_TOUCH_APPROACH_PAD1_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD1_CNT_S 8 +/** RTC_TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0; + * need_des + */ +#define RTC_TOUCH_APPROACH_PAD0_CNT 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD0_CNT_M (RTC_TOUCH_APPROACH_PAD0_CNT_V << RTC_TOUCH_APPROACH_PAD0_CNT_S) +#define RTC_TOUCH_APPROACH_PAD0_CNT_V 0x000000FFU +#define RTC_TOUCH_APPROACH_PAD0_CNT_S 16 +/** RTC_TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0; + * need_des + */ +#define RTC_TOUCH_SLP_APPROACH_CNT 0x000000FFU +#define RTC_TOUCH_SLP_APPROACH_CNT_M (RTC_TOUCH_SLP_APPROACH_CNT_V << RTC_TOUCH_SLP_APPROACH_CNT_S) +#define RTC_TOUCH_SLP_APPROACH_CNT_V 0x000000FFU +#define RTC_TOUCH_SLP_APPROACH_CNT_S 24 + +/** RTC_TOUCH_STATUS_17_REG register + * need_des + */ +#define RTC_TOUCH_STATUS_17_REG (DR_REG_LP_TOUCH_BASE + 0x58) +/** RTC_TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0; + * Reserved + */ +#define RTC_TOUCH_DCAP_LPF 0x0000007FU +#define RTC_TOUCH_DCAP_LPF_M (RTC_TOUCH_DCAP_LPF_V << RTC_TOUCH_DCAP_LPF_S) +#define RTC_TOUCH_DCAP_LPF_V 0x0000007FU +#define RTC_TOUCH_DCAP_LPF_S 0 +/** RTC_TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRES_LPF 0x00000003U +#define RTC_TOUCH_DRES_LPF_M (RTC_TOUCH_DRES_LPF_V << RTC_TOUCH_DRES_LPF_S) +#define RTC_TOUCH_DRES_LPF_V 0x00000003U +#define RTC_TOUCH_DRES_LPF_S 7 +/** RTC_TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRV_LS 0x0000000FU +#define RTC_TOUCH_DRV_LS_M (RTC_TOUCH_DRV_LS_V << RTC_TOUCH_DRV_LS_S) +#define RTC_TOUCH_DRV_LS_V 0x0000000FU +#define RTC_TOUCH_DRV_LS_S 9 +/** RTC_TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0; + * need_des + */ +#define RTC_TOUCH_DRV_HS 0x0000001FU +#define RTC_TOUCH_DRV_HS_M (RTC_TOUCH_DRV_HS_V << RTC_TOUCH_DRV_HS_S) +#define RTC_TOUCH_DRV_HS_V 0x0000001FU +#define RTC_TOUCH_DRV_HS_S 13 +/** RTC_TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define RTC_TOUCH_DBIAS 0x0000001FU +#define RTC_TOUCH_DBIAS_M (RTC_TOUCH_DBIAS_V << RTC_TOUCH_DBIAS_S) +#define RTC_TOUCH_DBIAS_V 0x0000001FU +#define RTC_TOUCH_DBIAS_S 18 +/** RTC_TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0; + * need_des + */ +#define RTC_TOUCH_FREQ_SCAN_CNT 0x00000003U +#define RTC_TOUCH_FREQ_SCAN_CNT_M (RTC_TOUCH_FREQ_SCAN_CNT_V << RTC_TOUCH_FREQ_SCAN_CNT_S) +#define RTC_TOUCH_FREQ_SCAN_CNT_V 0x00000003U +#define RTC_TOUCH_FREQ_SCAN_CNT_S 23 + +/** RTC_TOUCH_CHN_TMP_STATUS_REG register + * need_des + */ +#define RTC_TOUCH_CHN_TMP_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x5c) +/** RTC_TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_INACTIVE_STATUS 0x00007FFFU +#define RTC_TOUCH_PAD_INACTIVE_STATUS_M (RTC_TOUCH_PAD_INACTIVE_STATUS_V << RTC_TOUCH_PAD_INACTIVE_STATUS_S) +#define RTC_TOUCH_PAD_INACTIVE_STATUS_V 0x00007FFFU +#define RTC_TOUCH_PAD_INACTIVE_STATUS_S 0 +/** RTC_TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0; + * need_des + */ +#define RTC_TOUCH_PAD_ACTIVE_STATUS 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_STATUS_M (RTC_TOUCH_PAD_ACTIVE_STATUS_V << RTC_TOUCH_PAD_ACTIVE_STATUS_S) +#define RTC_TOUCH_PAD_ACTIVE_STATUS_V 0x00007FFFU +#define RTC_TOUCH_PAD_ACTIVE_STATUS_S 15 + +/** RTC_TOUCH_DATE_REG register + * need_des + */ +#define RTC_TOUCH_DATE_REG (DR_REG_LP_TOUCH_BASE + 0x100) +/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548; + * need_des + */ +#define RTC_TOUCH_DATE 0x0FFFFFFFU +#define RTC_TOUCH_DATE_M (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S) +#define RTC_TOUCH_DATE_V 0x0FFFFFFFU +#define RTC_TOUCH_DATE_S 0 +/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TOUCH_CLK_EN (BIT(31)) +#define RTC_TOUCH_CLK_EN_M (RTC_TOUCH_CLK_EN_V << RTC_TOUCH_CLK_EN_S) +#define RTC_TOUCH_CLK_EN_V 0x00000001U +#define RTC_TOUCH_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/touch_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/touch_struct.h new file mode 100644 index 0000000000..876919bf98 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/touch_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13423 + +/** Group: configure_register */ +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + /** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_raw:1; + /** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_raw:1; + /** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_raw:1; + /** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_raw:1; + /** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_raw:1; + /** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + /** scan_done_int_st : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_st:1; + /** done_int_st : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_st:1; + /** active_int_st : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_st:1; + /** inactive_int_st : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_st:1; + /** timeout_int_st : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_st:1; + /** approach_loop_done_int_st : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + /** scan_done_int_ena : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_ena:1; + /** done_int_ena : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_ena:1; + /** active_int_ena : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_ena:1; + /** inactive_int_ena : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_ena:1; + /** timeout_int_ena : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_ena:1; + /** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + /** scan_done_int_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t scan_done_int_clr:1; + /** done_int_clr : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t done_int_clr:1; + /** active_int_clr : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t active_int_clr:1; + /** inactive_int_clr : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t inactive_int_clr:1; + /** timeout_int_clr : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t timeout_int_clr:1; + /** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t approach_loop_done_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtc_touch_int_clr_reg_t; + +/** Type of chn_status register + * Latched channel status + */ +typedef union { + struct { + /** pad_active : RO; bitpos: [14:0]; default: 0; + * need_des + */ + uint32_t pad_active:15; + /** meas_done : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t meas_done:1; + /** scan_curr : RO; bitpos: [19:16]; default: 0; + * need_des + */ + uint32_t scan_curr:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_touch_chn_status_reg_t; + +/** Type of chn_data register + * need_des + */ +typedef union { + struct { + /** pad_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t pad_data:16; + /** pad_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t pad_debounce_cnt:3; + /** pad_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t pad_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_chn_data_reg_t; + +/** Type of slp_ch_data register + * need_des + */ +typedef union { + struct { + /** slp_data : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t slp_data:16; + /** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t slp_debounce_cnt:3; + /** slp_neg_noise_cnt : RO; bitpos: [22:19]; default: 0; + * need_des + */ + uint32_t slp_neg_noise_cnt:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} rtc_touch_slp_ch_data_reg_t; + +/** Type of aprch_ch_data register + * need_des + */ +typedef union { + struct { + /** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t approach_pad2_cnt:8; + /** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t approach_pad1_cnt:8; + /** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t approach_pad0_cnt:8; + /** slp_approach_cnt : RO; bitpos: [31:24]; default: 0; + * need_des + */ + uint32_t slp_approach_cnt:8; + }; + uint32_t val; +} rtc_touch_aprch_ch_data_reg_t; + +/** Type of config register + * need_des + */ +typedef union { + struct { + /** dcap_lpf : RO; bitpos: [6:0]; default: 0; + * Reserved + */ + uint32_t dcap_lpf:7; + /** dres_lpf : RO; bitpos: [8:7]; default: 0; + * need_des + */ + uint32_t dres_lpf:2; + /** drv_ls : RO; bitpos: [12:9]; default: 0; + * need_des + */ + uint32_t drv_ls:4; + /** drv_hs : RO; bitpos: [17:13]; default: 0; + * need_des + */ + uint32_t drv_hs:5; + /** dbias : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t dbias:5; + /** freq_scan_cnt : RO; bitpos: [24:23]; default: 0; + * need_des + */ + uint32_t freq_scan_cnt:2; + uint32_t reserved_25:7; + }; + uint32_t val; +} rtc_touch_sample_status_reg_t; + +/** Type of chn_tmp_status register + * Realtime channel status + */ +typedef union { + struct { + /** pad_inactive_status : RO; bitpos: [14:0]; default: 0; + * need_des + */ + uint32_t pad_inactive_status:15; + /** pad_active_status : RO; bitpos: [29:15]; default: 0; + * need_des + */ + uint32_t pad_active_status:15; + uint32_t reserved_30:2; + }; + uint32_t val; +} rtc_touch_chn_tmp_status_reg_t; + + +/** Group: Version */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 2294548; + * need_des + */ + uint32_t date:28; + uint32_t reserved_28:3; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rtc_touch_date_reg_t; + + +typedef struct { + volatile rtc_touch_int_raw_reg_t int_raw; + volatile rtc_touch_int_st_reg_t int_st; + volatile rtc_touch_int_ena_reg_t int_ena; + volatile rtc_touch_int_clr_reg_t int_clr; + volatile rtc_touch_chn_status_reg_t chn_status; + volatile rtc_touch_chn_data_reg_t chn_data[15]; + volatile rtc_touch_slp_ch_data_reg_t slp_ch_data; + volatile rtc_touch_aprch_ch_data_reg_t aprch_ch_data; + volatile rtc_touch_sample_status_reg_t sample_status; + volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status; + uint32_t reserved_060[40]; + volatile rtc_touch_date_reg_t date; +} rtc_touch_dev_t; + +extern rtc_touch_dev_t LP_TOUCH; + +#ifndef __cplusplus +_Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/trace_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/trace_reg.h new file mode 100644 index 0000000000..2cf87ac019 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/trace_reg.h @@ -0,0 +1,503 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0) +/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_START_ADDR 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S) +#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. + * 1: empty + * 0: not empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: + * 0: idle state + * 1: working state + * 2: wait state due to hart halted or havereset + * 3: lost state + */ +#define TRACE_WORK_STATUS 0x00000003U +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000003U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace. + * 1: start trace + * 0: invalid + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace. + * 1: stop trace + * 0: invalid + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. + * 1: trace will loop write trace_mem. + * 0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart. + * 1: enable + * 0: disable + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_CONFIG_REG register + * trace configuration register + */ +#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24) +/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action. + * 1: enable + * 0:disable + */ +#define TRACE_DM_TRIGGER_ENA (BIT(0)) +#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) +#define TRACE_DM_TRIGGER_ENA_V 0x00000001U +#define TRACE_DM_TRIGGER_ENA_S 0 +/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabled, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again. + * 1: enabled + * 0: disabled + */ +#define TRACE_RESET_ENA (BIT(1)) +#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) +#define TRACE_RESET_ENA_V 0x00000001U +#define TRACE_RESET_ENA_S 1 +/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabled, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. + * 1: enabled + * 0: disabled + */ +#define TRACE_HALT_ENA (BIT(2)) +#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) +#define TRACE_HALT_ENA_V 0x00000001U +#define TRACE_HALT_ENA_S 2 +/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo. + * 1: enabled. + * 0: disabled + */ +#define TRACE_STALL_ENA (BIT(3)) +#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) +#define TRACE_STALL_ENA_V 0x00000001U +#define TRACE_STALL_ENA_S 3 +/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode. + * 1: full address mode. + * 0: delta address mode + */ +#define TRACE_FULL_ADDRESS (BIT(4)) +#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) +#define TRACE_FULL_ADDRESS_V 0x00000001U +#define TRACE_FULL_ADDRESS_S 4 +/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; + * Configure whether or not enable implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets. + * 1: enabled + * 0: disabled + */ +#define TRACE_IMPLICIT_EXCEPT (BIT(5)) +#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) +#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U +#define TRACE_IMPLICIT_EXCEPT_S 5 + +/** TRACE_FILTER_CONTROL_REG register + * filter control register + */ +#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28) +/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. + * 1: enable filter. + * 0: always match + */ +#define TRACE_FILTER_EN (BIT(0)) +#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) +#define TRACE_FILTER_EN_V 0x00000001U +#define TRACE_FILTER_EN_S 0 +/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ +#define TRACE_MATCH_COMP (BIT(1)) +#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) +#define TRACE_MATCH_COMP_V 0x00000001U +#define TRACE_MATCH_COMP_S 1 +/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ +#define TRACE_MATCH_PRIVILEGE (BIT(2)) +#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S) +#define TRACE_MATCH_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_PRIVILEGE_S 2 +/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ +#define TRACE_MATCH_ECAUSE (BIT(3)) +#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S) +#define TRACE_MATCH_ECAUSE_V 0x00000001U +#define TRACE_MATCH_ECAUSE_S 3 +/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ +#define TRACE_MATCH_INTERRUPT (BIT(4)) +#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S) +#define TRACE_MATCH_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_INTERRUPT_S 4 + +/** TRACE_FILTER_MATCH_CONTROL_REG register + * filter match control register + */ +#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c) +/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. + * 1: machine mode. + * 0: user mode + */ +#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) +#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) +#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 +/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. + * 1: match itype of 2. + * 0: match itype or 1. + */ +#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) +#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) +#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_VALUE_INTERRUPT_S 1 +/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ +#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S) +#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_S 2 + +/** TRACE_FILTER_COMPARATOR_CONTROL_REG register + * filter comparator match control register + */ +#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30) +/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, + * 0: iaddr, + * 1: tval. + */ +#define TRACE_P_INPUT (BIT(0)) +#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) +#define TRACE_P_INPUT_V 0x00000001U +#define TRACE_P_INPUT_S 0 +/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. + * 0: equal, + * 1: not equal, + * 2: less than, + * 3: less than or equal, + * 4: greater than, + * 5: greater than or equal, + * other: always match + */ +#define TRACE_P_FUNCTION 0x00000007U +#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) +#define TRACE_P_FUNCTION_V 0x00000007U +#define TRACE_P_FUNCTION_S 2 +/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ +#define TRACE_P_NOTIFY (BIT(5)) +#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) +#define TRACE_P_NOTIFY_V 0x00000001U +#define TRACE_P_NOTIFY_S 5 +/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, + * 0: iaddr, + * 1: tval. + */ +#define TRACE_S_INPUT (BIT(8)) +#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) +#define TRACE_S_INPUT_V 0x00000001U +#define TRACE_S_INPUT_S 8 +/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. + * 0: equal, + * 1: not equal, + * 2: less than, + * 3: less than or equal, + * 4: greater than, + * 5: greater than or equal, + * other: always match + */ +#define TRACE_S_FUNCTION 0x00000007U +#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) +#define TRACE_S_FUNCTION_V 0x00000007U +#define TRACE_S_FUNCTION_S 10 +/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ +#define TRACE_S_NOTIFY (BIT(13)) +#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S) +#define TRACE_S_NOTIFY_V 0x00000001U +#define TRACE_S_NOTIFY_S 13 +/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, + * 1: primary and secondary comparator both matches(P\&\&S), + * 2:either primary or secondary comparator matches !(P\&\&S), + * 3: set when primary matches and continue to match until after secondary comparator + * matches + */ +#define TRACE_MATCH_MODE 0x00000003U +#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) +#define TRACE_MATCH_MODE_V 0x00000003U +#define TRACE_MATCH_MODE_S 16 + +/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register + * primary comparator match value + */ +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34) +/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ +#define TRACE_P_MATCH 0xFFFFFFFFU +#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S) +#define TRACE_P_MATCH_V 0xFFFFFFFFU +#define TRACE_P_MATCH_S 0 + +/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register + * secondary comparator match value + */ +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38) +/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ +#define TRACE_S_MATCH 0xFFFFFFFFU +#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S) +#define TRACE_S_MATCH_V 0xFFFFFFFFU +#define TRACE_S_MATCH_S 0 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: + * 0: off, + * 2: cycle count + * 3: package num count + */ +#define TRACE_RESYNC_MODE 0x00000003U +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000003U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_AHB_CONFIG_REG register + * AHB config register + */ +#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40) +/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ +#define TRACE_HBURST 0x00000007U +#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) +#define TRACE_HBURST_V 0x00000007U +#define TRACE_HBURST_S 0 +/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ +#define TRACE_MAX_INCR 0x00000007U +#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S) +#define TRACE_MAX_INCR_V 0x00000007U +#define TRACE_MAX_INCR_S 3 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/trace_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/trace_struct.h new file mode 100644 index 0000000000..dcb4fcd9aa --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/trace_struct.h @@ -0,0 +1,503 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. + * 1: empty + * 0: not empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: + * 0: idle state + * 1: working state + * 2: wait state due to hart halted or havereset + * 3: lost state + */ + uint32_t work_status:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace. + * 1: start trace + * 0: invalid + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace. + * 1: stop trace + * 0: invalid + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. + * 1: trace will loop write trace_mem. + * 0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart. + * 1: enable + * 0: disable + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of config register + * trace configuration register + */ +typedef union { + struct { + /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action. + * 1: enable + * 0:disable + */ + uint32_t dm_trigger_ena:1; + /** reset_ena : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabled, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again. + * 1: enabled + * 0: disabled + */ + uint32_t reset_ena:1; + /** halt_ena : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabled, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. + * 1: enabled + * 0: disabled + */ + uint32_t halt_ena:1; + /** stall_ena : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo. + * 1: enabled. + * 0: disabled + */ + uint32_t stall_ena:1; + /** full_address : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode. + * 1: full address mode. + * 0: delta address mode + */ + uint32_t full_address:1; + /** implicit_except : R/W; bitpos: [5]; default: 0; + * Configure whether or not enable implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets. + * 1: enabled + * 0: disabled + */ + uint32_t implicit_except:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_config_reg_t; + +/** Type of filter_control register + * filter control register + */ +typedef union { + struct { + /** filter_en : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. + * 1: enable filter. + * 0: always match + */ + uint32_t filter_en:1; + /** match_comp : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ + uint32_t match_comp:1; + /** match_privilege : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ + uint32_t match_privilege:1; + /** match_ecause : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ + uint32_t match_ecause:1; + /** match_interrupt : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ + uint32_t match_interrupt:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} trace_filter_control_reg_t; + +/** Type of filter_match_control register + * filter match control register + */ +typedef union { + struct { + /** match_choice_privilege : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. + * 1: machine mode. + * 0: user mode + */ + uint32_t match_choice_privilege:1; + /** match_value_interrupt : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. + * 1: match itype of 2. + * 0: match itype or 1. + */ + uint32_t match_value_interrupt:1; + /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ + uint32_t match_choice_ecause:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} trace_filter_match_control_reg_t; + +/** Type of filter_comparator_control register + * filter comparator match control register + */ +typedef union { + struct { + /** p_input : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, + * 0: iaddr, + * 1: tval. + */ + uint32_t p_input:1; + uint32_t reserved_1:1; + /** p_function : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. + * 0: equal, + * 1: not equal, + * 2: less than, + * 3: less than or equal, + * 4: greater than, + * 5: greater than or equal, + * other: always match + */ + uint32_t p_function:3; + /** p_notify : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ + uint32_t p_notify:1; + uint32_t reserved_6:2; + /** s_input : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, + * 0: iaddr, + * 1: tval. + */ + uint32_t s_input:1; + uint32_t reserved_9:1; + /** s_function : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. + * 0: equal, + * 1: not equal, + * 2: less than, + * 3: less than or equal, + * 4: greater than, + * 5: greater than or equal, + * other: always match + */ + uint32_t s_function:3; + /** s_notify : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ + uint32_t s_notify:1; + uint32_t reserved_14:2; + /** match_mode : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, + * 1: primary and secondary comparator both matches(P\&\&S), + * 2:either primary or secondary comparator matches !(P\&\&S), + * 3: set when primary matches and continue to match until after secondary comparator + * matches + */ + uint32_t match_mode:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} trace_filter_comparator_control_reg_t; + +/** Type of filter_p_comparator_match register + * primary comparator match value + */ +typedef union { + struct { + /** p_match : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ + uint32_t p_match:32; + }; + uint32_t val; +} trace_filter_p_comparator_match_reg_t; + +/** Type of filter_s_comparator_match register + * secondary comparator match value + */ +typedef union { + struct { + /** s_match : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ + uint32_t s_match:32; + }; + uint32_t val; +} trace_filter_s_comparator_match_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: + * 0: off, + * 2: cycle count + * 3: package num count + */ + uint32_t resync_mode:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + +/** Type of ahb_config register + * AHB config register + */ +typedef union { + struct { + /** hburst : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ + uint32_t hburst:3; + /** max_incr : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ + uint32_t max_incr:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_ahb_config_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_config_reg_t config; + volatile trace_filter_control_reg_t filter_control; + volatile trace_filter_match_control_reg_t filter_match_control; + volatile trace_filter_comparator_control_reg_t filter_comparator_control; + volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match; + volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_ahb_config_reg_t ahb_config; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_048[237]; + volatile trace_date_reg_t date; +} trace_dev_t; + +extern trace_dev_t TRACE0; +extern trace_dev_t TRACE1; + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/trng_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/trng_reg.h new file mode 100644 index 0000000000..cbdd7e2bd1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/trng_reg.h @@ -0,0 +1,94 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RNG_CFG_REG register + * configure rng register + */ +#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x0) +/** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * enable rng RO + * 1: enable RO + * 0: disable RO + */ +#define RNG_SAMPLE_ENABLE (BIT(0)) +#define RNG_SAMPLE_ENABLE_M (RNG_SAMPLE_ENABLE_V << RNG_SAMPLE_ENABLE_S) +#define RNG_SAMPLE_ENABLE_V 0x00000001U +#define RNG_SAMPLE_ENABLE_S 0 +/** RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * configure rng timer clk div + */ +#define RNG_TIMER_PSCALE 0x000000FFU +#define RNG_TIMER_PSCALE_M (RNG_TIMER_PSCALE_V << RNG_TIMER_PSCALE_S) +#define RNG_TIMER_PSCALE_V 0x000000FFU +#define RNG_TIMER_PSCALE_S 1 +/** RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * enable rng xor async rng timer + */ +#define RNG_TIMER_EN (BIT(9)) +#define RNG_TIMER_EN_M (RNG_TIMER_EN_V << RNG_TIMER_EN_S) +#define RNG_TIMER_EN_V 0x00000001U +#define RNG_TIMER_EN_S 9 +/** RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * get rng RO sample cnt + */ +#define RNG_SAMPLE_CNT 0x000000FFU +#define RNG_SAMPLE_CNT_M (RNG_SAMPLE_CNT_V << RNG_SAMPLE_CNT_S) +#define RNG_SAMPLE_CNT_V 0x000000FFU +#define RNG_SAMPLE_CNT_S 24 + +/** RNG_DATA_REG register + * RNG result register + */ +#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x4) +/** RNG_DATA : RO; bitpos: [31:0]; default: 0; + * get rng data + */ +#define RNG_DATA 0xFFFFFFFFU +#define RNG_DATA_M (RNG_DATA_V << RNG_DATA_S) +#define RNG_DATA_V 0xFFFFFFFFU +#define RNG_DATA_S 0 + +/** RNG_RSTN_REG register + * rng rstn register + */ +#define RNG_RSTN_REG (DR_REG_RNG_BASE + 0x8) +/** RNG_RSTN : R/W; bitpos: [0]; default: 1; + * enable rng system reset: 1: not reset, 0: reset + */ +#define RNG_RSTN (BIT(0)) +#define RNG_RSTN_M (RNG_RSTN_V << RNG_RSTN_S) +#define RNG_RSTN_V 0x00000001U +#define RNG_RSTN_S 0 + +/** RNG_DATE_REG register + * need_des + */ +#define RNG_DATE_REG (DR_REG_RNG_BASE + 0xc) +/** RNG_DATE : R/W; bitpos: [30:0]; default: 2425091; + * need_des + */ +#define RNG_DATE 0x7FFFFFFFU +#define RNG_DATE_M (RNG_DATE_V << RNG_DATE_S) +#define RNG_DATE_V 0x7FFFFFFFU +#define RNG_DATE_S 0 +/** RNG_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RNG_CLK_EN (BIT(31)) +#define RNG_CLK_EN_M (RNG_CLK_EN_V << RNG_CLK_EN_S) +#define RNG_CLK_EN_V 0x00000001U +#define RNG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/trng_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/trng_struct.h new file mode 100644 index 0000000000..c669247cc1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/trng_struct.h @@ -0,0 +1,102 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of cfg register + * configure rng register + */ +typedef union { + struct { + /** sample_enable : R/W; bitpos: [0]; default: 0; + * enable rng RO + * 1: enable RO + * 0: disable RO + */ + uint32_t sample_enable:1; + /** timer_pscale : R/W; bitpos: [8:1]; default: 255; + * configure rng timer clk div + */ + uint32_t timer_pscale:8; + /** timer_en : R/W; bitpos: [9]; default: 1; + * enable rng xor async rng timer + */ + uint32_t timer_en:1; + uint32_t reserved_10:14; + /** sample_cnt : RO; bitpos: [31:24]; default: 0; + * get rng RO sample cnt + */ + uint32_t sample_cnt:8; + }; + uint32_t val; +} rng_cfg_reg_t; + +/** Type of data register + * RNG result register + */ +typedef union { + struct { + /** data : RO; bitpos: [31:0]; default: 0; + * get rng data + */ + uint32_t data:32; + }; + uint32_t val; +} rng_data_reg_t; + +/** Type of rstn register + * rng rstn register + */ +typedef union { + struct { + /** rstn : R/W; bitpos: [0]; default: 1; + * enable rng system reset: 1: not reset, 0: reset + */ + uint32_t rstn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rng_rstn_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 2425091; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rng_date_reg_t; + + +typedef struct { + volatile rng_cfg_reg_t cfg; + volatile rng_data_reg_t data; + volatile rng_rstn_reg_t rstn; + volatile rng_date_reg_t date; +} rng_dev_t; + +extern rng_dev_t LP_TRNG; + +#ifndef __cplusplus +_Static_assert(sizeof(rng_dev_t) == 0x10, "Invalid size of rng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/tsens_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/tsens_reg.h new file mode 100644 index 0000000000..0662085872 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/tsens_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TSENS_CTRL_REG register + * Tsens configuration. + */ +#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0) +/** TSENS_OUT : RO; bitpos: [7:0]; default: 0; + * Temperature sensor data out. + */ +#define TSENS_OUT 0x000000FFU +#define TSENS_OUT_M (TSENS_OUT_V << TSENS_OUT_S) +#define TSENS_OUT_V 0x000000FFU +#define TSENS_OUT_S 0 +/** TSENS_READY : RO; bitpos: [8]; default: 0; + * Indicate temperature sensor out ready. + */ +#define TSENS_READY (BIT(8)) +#define TSENS_READY_M (TSENS_READY_V << TSENS_READY_S) +#define TSENS_READY_V 0x00000001U +#define TSENS_READY_S 8 +/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0; + * Enable sample signal for wakeup module. + */ +#define TSENS_SAMPLE_EN (BIT(9)) +#define TSENS_SAMPLE_EN_M (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S) +#define TSENS_SAMPLE_EN_V 0x00000001U +#define TSENS_SAMPLE_EN_S 9 +/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1; + * Wake up signal mask. + */ +#define TSENS_WAKEUP_MASK (BIT(10)) +#define TSENS_WAKEUP_MASK_M (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S) +#define TSENS_WAKEUP_MASK_V 0x00000001U +#define TSENS_WAKEUP_MASK_S 10 +/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1; + * Enable temperature sensor to send out interrupt. + */ +#define TSENS_INT_EN (BIT(12)) +#define TSENS_INT_EN_M (TSENS_INT_EN_V << TSENS_INT_EN_S) +#define TSENS_INT_EN_V 0x00000001U +#define TSENS_INT_EN_S 12 +/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * Invert temperature sensor data. + */ +#define TSENS_IN_INV (BIT(13)) +#define TSENS_IN_INV_M (TSENS_IN_INV_V << TSENS_IN_INV_S) +#define TSENS_IN_INV_V 0x00000001U +#define TSENS_IN_INV_S 13 +/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * Temperature sensor clock divider. + */ +#define TSENS_CLK_DIV 0x000000FFU +#define TSENS_CLK_DIV_M (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S) +#define TSENS_CLK_DIV_V 0x000000FFU +#define TSENS_CLK_DIV_S 14 +/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0; + * Temperature sensor power up. + */ +#define TSENS_POWER_UP (BIT(22)) +#define TSENS_POWER_UP_M (TSENS_POWER_UP_V << TSENS_POWER_UP_S) +#define TSENS_POWER_UP_V 0x00000001U +#define TSENS_POWER_UP_S 22 +/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0; + * 1: dump out & power up controlled by SW, 0: by FSM. + */ +#define TSENS_POWER_UP_FORCE (BIT(23)) +#define TSENS_POWER_UP_FORCE_M (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S) +#define TSENS_POWER_UP_FORCE_V 0x00000001U +#define TSENS_POWER_UP_FORCE_S 23 + +/** TSENS_INT_RAW_REG register + * Tsens interrupt raw registers. + */ +#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8) +/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Tsens wakeup interrupt raw. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_RAW (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S) +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S 0 + +/** TSENS_INT_ST_REG register + * Tsens interrupt status registers. + */ +#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc) +/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0; + * Tsens wakeup interrupt status. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ST (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ST_M (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ST_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ST_S 0 + +/** TSENS_INT_ENA_REG register + * Tsens interrupt enable registers. + */ +#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0; + * Tsens wakeup interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S 0 + +/** TSENS_INT_CLR_REG register + * Tsens interrupt clear registers. + */ +#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14) +/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0; + * Tsens wakeup interrupt clear. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_CLR (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S) +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S 0 + +/** TSENS_CLK_CONF_REG register + * Tsens regbank configuration registers. + */ +#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18) +/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0; + * Tsens regbank clock gating enable. + */ +#define TSENS_CLK_EN (BIT(0)) +#define TSENS_CLK_EN_M (TSENS_CLK_EN_V << TSENS_CLK_EN_S) +#define TSENS_CLK_EN_V 0x00000001U +#define TSENS_CLK_EN_S 0 + +/** TSENS_INT_ENA_W1TS_REG register + * Tsens wakeup interrupt enable assert. + */ +#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0; + * Write 1 to this field to assert interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S 0 + +/** TSENS_INT_ENA_W1TC_REG register + * Tsens wakeup interrupt enable deassert. + */ +#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20) +/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0; + * Write 1 to this field to deassert interrupt enable. + */ +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC (BIT(0)) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S) +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V 0x00000001U +#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S 0 + +/** TSENS_WAKEUP_CTRL_REG register + * Tsens wakeup control registers. + */ +#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24) +/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * Lower threshold. + */ +#define TSENS_WAKEUP_TH_LOW 0x000000FFU +#define TSENS_WAKEUP_TH_LOW_M (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S) +#define TSENS_WAKEUP_TH_LOW_V 0x000000FFU +#define TSENS_WAKEUP_TH_LOW_S 0 +/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255; + * Upper threshold. + */ +#define TSENS_WAKEUP_TH_HIGH 0x000000FFU +#define TSENS_WAKEUP_TH_HIGH_M (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S) +#define TSENS_WAKEUP_TH_HIGH_V 0x000000FFU +#define TSENS_WAKEUP_TH_HIGH_S 14 +/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ +#define TSENS_WAKEUP_OVER_UPPER_TH (BIT(29)) +#define TSENS_WAKEUP_OVER_UPPER_TH_M (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S) +#define TSENS_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define TSENS_WAKEUP_OVER_UPPER_TH_S 29 +/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0; + * Tsens wakeup enable. + */ +#define TSENS_WAKEUP_EN (BIT(30)) +#define TSENS_WAKEUP_EN_M (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S) +#define TSENS_WAKEUP_EN_V 0x00000001U +#define TSENS_WAKEUP_EN_S 30 +/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ +#define TSENS_WAKEUP_MODE (BIT(31)) +#define TSENS_WAKEUP_MODE_M (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S) +#define TSENS_WAKEUP_MODE_V 0x00000001U +#define TSENS_WAKEUP_MODE_S 31 + +/** TSENS_SAMPLE_RATE_REG register + * Hardware automatic sampling control registers. + */ +#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28) +/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * Hardware automatic sampling rate. + */ +#define TSENS_SAMPLE_RATE 0x0000FFFFU +#define TSENS_SAMPLE_RATE_M (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S) +#define TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define TSENS_SAMPLE_RATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/tsens_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/tsens_struct.h new file mode 100644 index 0000000000..212214fa3f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/tsens_struct.h @@ -0,0 +1,233 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tsens control registers. */ +/** Type of ctrl register + * Tsens configuration. + */ +typedef union { + struct { + /** out : RO; bitpos: [7:0]; default: 0; + * Temperature sensor data out. + */ + uint32_t out:8; + /** ready : RO; bitpos: [8]; default: 0; + * Indicate temperature sensor out ready. + */ + uint32_t ready:1; + /** sample_en : R/W; bitpos: [9]; default: 0; + * Enable sample signal for wakeup module. + */ + uint32_t sample_en:1; + /** wakeup_mask : R/W; bitpos: [10]; default: 1; + * Wake up signal mask. + */ + uint32_t wakeup_mask:1; + uint32_t reserved_11:1; + /** int_en : R/W; bitpos: [12]; default: 1; + * Enable temperature sensor to send out interrupt. + */ + uint32_t int_en:1; + /** in_inv : R/W; bitpos: [13]; default: 0; + * Invert temperature sensor data. + */ + uint32_t in_inv:1; + /** clk_div : R/W; bitpos: [21:14]; default: 6; + * Temperature sensor clock divider. + */ + uint32_t clk_div:8; + /** power_up : R/W; bitpos: [22]; default: 0; + * Temperature sensor power up. + */ + uint32_t power_up:1; + /** power_up_force : R/W; bitpos: [23]; default: 0; + * 1: dump out & power up controlled by SW, 0: by FSM. + */ + uint32_t power_up_force:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} tsens_ctrl_reg_t; + + +/** Group: Tsens interrupt registers. */ +/** Type of int_raw register + * Tsens interrupt raw registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Tsens wakeup interrupt raw. + */ + uint32_t cocpu_tsens_wake_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_raw_reg_t; + +/** Type of int_st register + * Tsens interrupt status registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_st : RO; bitpos: [0]; default: 0; + * Tsens wakeup interrupt status. + */ + uint32_t cocpu_tsens_wake_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_st_reg_t; + +/** Type of int_ena register + * Tsens interrupt enable registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena : R/WTC; bitpos: [0]; default: 0; + * Tsens wakeup interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_reg_t; + +/** Type of int_clr register + * Tsens interrupt clear registers. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_clr : WT; bitpos: [0]; default: 0; + * Tsens wakeup interrupt clear. + */ + uint32_t cocpu_tsens_wake_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_clr_reg_t; + +/** Type of int_ena_w1ts register + * Tsens wakeup interrupt enable assert. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena_w1ts : WT; bitpos: [0]; default: 0; + * Write 1 to this field to assert interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena_w1ts:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_w1ts_reg_t; + +/** Type of int_ena_w1tc register + * Tsens wakeup interrupt enable deassert. + */ +typedef union { + struct { + /** cocpu_tsens_wake_int_ena_w1tc : WT; bitpos: [0]; default: 0; + * Write 1 to this field to deassert interrupt enable. + */ + uint32_t cocpu_tsens_wake_int_ena_w1tc:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_int_ena_w1tc_reg_t; + + +/** Group: Tsens regbank clock control registers. */ +/** Type of clk_conf register + * Tsens regbank configuration registers. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Tsens regbank clock gating enable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tsens_clk_conf_reg_t; + + +/** Group: Tsens wakeup control registers. */ +/** Type of wakeup_ctrl register + * Tsens wakeup control registers. + */ +typedef union { + struct { + /** wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * Lower threshold. + */ + uint32_t wakeup_th_low:8; + uint32_t reserved_8:6; + /** wakeup_th_high : R/W; bitpos: [21:14]; default: 255; + * Upper threshold. + */ + uint32_t wakeup_th_high:8; + uint32_t reserved_22:7; + /** wakeup_over_upper_th : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ + uint32_t wakeup_over_upper_th:1; + /** wakeup_en : R/W; bitpos: [30]; default: 0; + * Tsens wakeup enable. + */ + uint32_t wakeup_en:1; + /** wakeup_mode : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ + uint32_t wakeup_mode:1; + }; + uint32_t val; +} tsens_wakeup_ctrl_reg_t; + +/** Type of sample_rate register + * Hardware automatic sampling control registers. + */ +typedef union { + struct { + /** sample_rate : R/W; bitpos: [15:0]; default: 20; + * Hardware automatic sampling rate. + */ + uint32_t sample_rate:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} tsens_sample_rate_reg_t; + + +typedef struct { + volatile tsens_ctrl_reg_t ctrl; + uint32_t reserved_004; + volatile tsens_int_raw_reg_t int_raw; + volatile tsens_int_st_reg_t int_st; + volatile tsens_int_ena_reg_t int_ena; + volatile tsens_int_clr_reg_t int_clr; + volatile tsens_clk_conf_reg_t clk_conf; + volatile tsens_int_ena_w1ts_reg_t int_ena_w1ts; + volatile tsens_int_ena_w1tc_reg_t int_ena_w1tc; + volatile tsens_wakeup_ctrl_reg_t wakeup_ctrl; + volatile tsens_sample_rate_reg_t sample_rate; +} tsens_dev_t; + +extern tsens_dev_t LP_TSENS; + +#ifndef __cplusplus +_Static_assert(sizeof(tsens_dev_t) == 0x2c, "Invalid size of tsens_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/twai_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/twai_eco5_struct.h new file mode 100644 index 0000000000..429a1a7145 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/twai_eco5_struct.h @@ -0,0 +1,799 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ + uint32_t ts_counter_ovfl_int_st:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ + uint32_t ts_counter_ovfl_int_ena:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of data_0 register + * Data register 0. + */ +typedef union { + struct { + /** data_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t data_0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_0_reg_t; + +/** Type of data_1 register + * Data register 1. + */ +typedef union { + struct { + /** data_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ + uint32_t data_1:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_1_reg_t; + +/** Type of data_2 register + * Data register 2. + */ +typedef union { + struct { + /** data_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ + uint32_t data_2:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_2_reg_t; + +/** Type of data_3 register + * Data register 3. + */ +typedef union { + struct { + /** data_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ + uint32_t data_3:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_3_reg_t; + +/** Type of data_4 register + * Data register 4. + */ +typedef union { + struct { + /** data_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ + uint32_t data_4:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_4_reg_t; + +/** Type of data_5 register + * Data register 5. + */ +typedef union { + struct { + /** data_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ + uint32_t data_5:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_5_reg_t; + +/** Type of data_6 register + * Data register 6. + */ +typedef union { + struct { + /** data_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ + uint32_t data_6:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_6_reg_t; + +/** Type of data_7 register + * Data register 7. + */ +typedef union { + struct { + /** data_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ + uint32_t data_7:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_7_reg_t; + +/** Type of data_8 register + * Data register 8. + */ +typedef union { + struct { + /** data_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ + uint32_t data_8:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_8_reg_t; + +/** Type of data_9 register + * Data register 9. + */ +typedef union { + struct { + /** data_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ + uint32_t data_9:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_9_reg_t; + +/** Type of data_10 register + * Data register 10. + */ +typedef union { + struct { + /** data_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ + uint32_t data_10:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_10_reg_t; + +/** Type of data_11 register + * Data register 11. + */ +typedef union { + struct { + /** data_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ + uint32_t data_11:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_11_reg_t; + +/** Type of data_12 register + * Data register 12. + */ +typedef union { + struct { + /** data_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ + uint32_t data_12:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_12_reg_t; + + +/** Group: Timestamp Register */ +/** Type of timestamp_data register + * Timestamp data register + */ +typedef union { + struct { + /** timestamp_data : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ + uint32_t timestamp_data:32; + }; + uint32_t val; +} twai_timestamp_data_reg_t; + +/** Type of timestamp_prescaler register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_div_num : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ + uint32_t ts_div_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_timestamp_prescaler_reg_t; + +/** Type of timestamp_cfg register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_enable : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ + uint32_t ts_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_timestamp_cfg_reg_t; + + +typedef struct { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile twai_data_0_reg_t data_0; + volatile twai_data_1_reg_t data_1; + volatile twai_data_2_reg_t data_2; + volatile twai_data_3_reg_t data_3; + volatile twai_data_4_reg_t data_4; + volatile twai_data_5_reg_t data_5; + volatile twai_data_6_reg_t data_6; + volatile twai_data_7_reg_t data_7; + volatile twai_data_8_reg_t data_8; + volatile twai_data_9_reg_t data_9; + volatile twai_data_10_reg_t data_10; + volatile twai_data_11_reg_t data_11; + volatile twai_data_12_reg_t data_12; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; + volatile twai_timestamp_data_reg_t timestamp_data; + volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; + volatile twai_timestamp_cfg_reg_t timestamp_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; +extern twai_dev_t TWAI1; +extern twai_dev_t TWAI2; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/twai_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/twai_reg.h new file mode 100644 index 0000000000..3eb5c0bb37 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/twai_reg.h @@ -0,0 +1,791 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TWAI_MODE_REG register + * TWAI mode register. + */ +#define TWAI_MODE_REG(i) (DR_REG_TWAI_BASE(i) + 0x0) +/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001U +#define TWAI_RESET_MODE_S 0 +/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U +#define TWAI_LISTEN_ONLY_MODE_S 1 +/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001U +#define TWAI_SELF_TEST_MODE_S 2 +/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ +#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) +#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) +#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U +#define TWAI_ACCEPTANCE_FILTER_MODE_S 3 + +/** TWAI_CMD_REG register + * TWAI command register. + */ +#define TWAI_CMD_REG(i) (DR_REG_TWAI_BASE(i) + 0x4) +/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ +#define TWAI_TX_REQUEST (BIT(0)) +#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) +#define TWAI_TX_REQUEST_V 0x00000001U +#define TWAI_TX_REQUEST_S 0 +/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001U +#define TWAI_ABORT_TX_S 1 +/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ +#define TWAI_RELEASE_BUFFER (BIT(2)) +#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) +#define TWAI_RELEASE_BUFFER_V 0x00000001U +#define TWAI_RELEASE_BUFFER_S 2 +/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ +#define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) +#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) +#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U +#define TWAI_CLEAR_DATA_OVERRUN_S 3 +/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ +#define TWAI_SELF_RX_REQUEST (BIT(4)) +#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) +#define TWAI_SELF_RX_REQUEST_V 0x00000001U +#define TWAI_SELF_RX_REQUEST_S 4 + +/** TWAI_STATUS_REG register + * TWAI status register. + */ +#define TWAI_STATUS_REG(i) (DR_REG_TWAI_BASE(i) + 0x8) +/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ +#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) +#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) +#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U +#define TWAI_STATUS_RECEIVE_BUFFER_S 0 +/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ +#define TWAI_STATUS_OVERRUN (BIT(1)) +#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) +#define TWAI_STATUS_OVERRUN_V 0x00000001U +#define TWAI_STATUS_OVERRUN_S 1 +/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ +#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) +#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) +#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_BUFFER_S 2 +/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ +#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U +#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 +/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ +#define TWAI_STATUS_RECEIVE (BIT(4)) +#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) +#define TWAI_STATUS_RECEIVE_V 0x00000001U +#define TWAI_STATUS_RECEIVE_S 4 +/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ +#define TWAI_STATUS_TRANSMIT (BIT(5)) +#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) +#define TWAI_STATUS_TRANSMIT_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_S 5 +/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ +#define TWAI_STATUS_ERR (BIT(6)) +#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) +#define TWAI_STATUS_ERR_V 0x00000001U +#define TWAI_STATUS_ERR_S 6 +/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ +#define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) +#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) +#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U +#define TWAI_STATUS_NODE_BUS_OFF_S 7 +/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ +#define TWAI_STATUS_MISS (BIT(8)) +#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) +#define TWAI_STATUS_MISS_V 0x00000001U +#define TWAI_STATUS_MISS_S 8 + +/** TWAI_INTERRUPT_REG register + * Interrupt signals' register. + */ +#define TWAI_INTERRUPT_REG(i) (DR_REG_TWAI_BASE(i) + 0xc) +/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ +#define TWAI_RECEIVE_INT_ST (BIT(0)) +#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) +#define TWAI_RECEIVE_INT_ST_V 0x00000001U +#define TWAI_RECEIVE_INT_ST_S 0 +/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_TRANSMIT_INT_ST (BIT(1)) +#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) +#define TWAI_TRANSMIT_INT_ST_V 0x00000001U +#define TWAI_TRANSMIT_INT_ST_S 1 +/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ +#define TWAI_ERR_WARNING_INT_ST (BIT(2)) +#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) +#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U +#define TWAI_ERR_WARNING_INT_ST_S 2 +/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) +#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) +#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U +#define TWAI_DATA_OVERRUN_INT_ST_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ST (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ST_M (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S) +#define TWAI_TS_COUNTER_OVFL_INT_ST_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ST_S 4 +/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ST_S 5 +/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) +#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ST_S 6 +/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001U +#define TWAI_BUS_ERR_INT_ST_S 7 +/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_IDLE_INT_ST (BIT(8)) +#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) +#define TWAI_IDLE_INT_ST_V 0x00000001U +#define TWAI_IDLE_INT_ST_S 8 + +/** TWAI_INTERRUPT_ENABLE_REG register + * Interrupt enable register. + */ +#define TWAI_INTERRUPT_ENABLE_REG(i) (DR_REG_TWAI_BASE(i) + 0x10) +/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ +#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) +#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) +#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U +#define TWAI_EXT_RECEIVE_INT_ENA_S 0 +/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ +#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) +#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) +#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U +#define TWAI_EXT_TRANSMIT_INT_ENA_S 1 +/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) +#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) +#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U +#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 +/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ENA (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_M (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ENA_S 4 +/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 +/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ +#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) +#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ENA_S 6 +/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U +#define TWAI_BUS_ERR_INT_ENA_S 7 +/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_IDLE_INT_ENA (BIT(8)) +#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) +#define TWAI_IDLE_INT_ENA_V 0x00000001U +#define TWAI_IDLE_INT_ENA_S 8 + +/** TWAI_BUS_TIMING_0_REG register + * Bit timing configuration register 0. + */ +#define TWAI_BUS_TIMING_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x18) +/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ +#define TWAI_BAUD_PRESC 0x00003FFFU +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFFU +#define TWAI_BAUD_PRESC_S 0 +/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ +#define TWAI_SYNC_JUMP_WIDTH 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/** TWAI_BUS_TIMING_1_REG register + * Bit timing configuration register 1. + */ +#define TWAI_BUS_TIMING_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x1c) +/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT1 0x0000000FU +#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) +#define TWAI_TIME_SEGMENT1_V 0x0000000FU +#define TWAI_TIME_SEGMENT1_S 0 +/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT2 0x00000007U +#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) +#define TWAI_TIME_SEGMENT2_V 0x00000007U +#define TWAI_TIME_SEGMENT2_S 4 +/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TIME_SAMPLING (BIT(7)) +#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) +#define TWAI_TIME_SAMPLING_V 0x00000001U +#define TWAI_TIME_SAMPLING_S 7 + +/** TWAI_ARB_LOST_CAP_REG register + * TWAI arbiter lost capture register. + */ +#define TWAI_ARB_LOST_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x2c) +/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ +#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) +#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_S 0 + +/** TWAI_ERR_CODE_CAP_REG register + * TWAI error info capture register. + */ +#define TWAI_ERR_CODE_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x30) +/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ +#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 +/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ +#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 +/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ +#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) +#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 + +/** TWAI_ERR_WARNING_LIMIT_REG register + * TWAI error threshold configuration register. + */ +#define TWAI_ERR_WARNING_LIMIT_REG(i) (DR_REG_TWAI_BASE(i) + 0x34) +/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_ERR_WARNING_LIMIT 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/** TWAI_RX_ERR_CNT_REG register + * Rx error counter register. + */ +#define TWAI_RX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x38) +/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_RX_ERR_CNT 0x000000FFU +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FFU +#define TWAI_RX_ERR_CNT_S 0 + +/** TWAI_TX_ERR_CNT_REG register + * Tx error counter register. + */ +#define TWAI_TX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x3c) +/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TX_ERR_CNT 0x000000FFU +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FFU +#define TWAI_TX_ERR_CNT_S 0 + +/** TWAI_DATA_0_REG register + * Data register 0. + */ +#define TWAI_DATA_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x40) +/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ +#define TWAI_DATA_0 0x000000FFU +#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) +#define TWAI_DATA_0_V 0x000000FFU +#define TWAI_DATA_0_S 0 + +/** TWAI_DATA_1_REG register + * Data register 1. + */ +#define TWAI_DATA_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x44) +/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ +#define TWAI_DATA_1 0x000000FFU +#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) +#define TWAI_DATA_1_V 0x000000FFU +#define TWAI_DATA_1_S 0 + +/** TWAI_DATA_2_REG register + * Data register 2. + */ +#define TWAI_DATA_2_REG(i) (DR_REG_TWAI_BASE(i) + 0x48) +/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ +#define TWAI_DATA_2 0x000000FFU +#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) +#define TWAI_DATA_2_V 0x000000FFU +#define TWAI_DATA_2_S 0 + +/** TWAI_DATA_3_REG register + * Data register 3. + */ +#define TWAI_DATA_3_REG(i) (DR_REG_TWAI_BASE(i) + 0x4c) +/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ +#define TWAI_DATA_3 0x000000FFU +#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) +#define TWAI_DATA_3_V 0x000000FFU +#define TWAI_DATA_3_S 0 + +/** TWAI_DATA_4_REG register + * Data register 4. + */ +#define TWAI_DATA_4_REG(i) (DR_REG_TWAI_BASE(i) + 0x50) +/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ +#define TWAI_DATA_4 0x000000FFU +#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) +#define TWAI_DATA_4_V 0x000000FFU +#define TWAI_DATA_4_S 0 + +/** TWAI_DATA_5_REG register + * Data register 5. + */ +#define TWAI_DATA_5_REG(i) (DR_REG_TWAI_BASE(i) + 0x54) +/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ +#define TWAI_DATA_5 0x000000FFU +#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) +#define TWAI_DATA_5_V 0x000000FFU +#define TWAI_DATA_5_S 0 + +/** TWAI_DATA_6_REG register + * Data register 6. + */ +#define TWAI_DATA_6_REG(i) (DR_REG_TWAI_BASE(i) + 0x58) +/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ +#define TWAI_DATA_6 0x000000FFU +#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) +#define TWAI_DATA_6_V 0x000000FFU +#define TWAI_DATA_6_S 0 + +/** TWAI_DATA_7_REG register + * Data register 7. + */ +#define TWAI_DATA_7_REG(i) (DR_REG_TWAI_BASE(i) + 0x5c) +/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ +#define TWAI_DATA_7 0x000000FFU +#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) +#define TWAI_DATA_7_V 0x000000FFU +#define TWAI_DATA_7_S 0 + +/** TWAI_DATA_8_REG register + * Data register 8. + */ +#define TWAI_DATA_8_REG(i) (DR_REG_TWAI_BASE(i) + 0x60) +/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ +#define TWAI_DATA_8 0x000000FFU +#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) +#define TWAI_DATA_8_V 0x000000FFU +#define TWAI_DATA_8_S 0 + +/** TWAI_DATA_9_REG register + * Data register 9. + */ +#define TWAI_DATA_9_REG(i) (DR_REG_TWAI_BASE(i) + 0x64) +/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ +#define TWAI_DATA_9 0x000000FFU +#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) +#define TWAI_DATA_9_V 0x000000FFU +#define TWAI_DATA_9_S 0 + +/** TWAI_DATA_10_REG register + * Data register 10. + */ +#define TWAI_DATA_10_REG(i) (DR_REG_TWAI_BASE(i) + 0x68) +/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ +#define TWAI_DATA_10 0x000000FFU +#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) +#define TWAI_DATA_10_V 0x000000FFU +#define TWAI_DATA_10_S 0 + +/** TWAI_DATA_11_REG register + * Data register 11. + */ +#define TWAI_DATA_11_REG(i) (DR_REG_TWAI_BASE(i) + 0x6c) +/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ +#define TWAI_DATA_11 0x000000FFU +#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) +#define TWAI_DATA_11_V 0x000000FFU +#define TWAI_DATA_11_S 0 + +/** TWAI_DATA_12_REG register + * Data register 12. + */ +#define TWAI_DATA_12_REG(i) (DR_REG_TWAI_BASE(i) + 0x70) +/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ +#define TWAI_DATA_12 0x000000FFU +#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) +#define TWAI_DATA_12_V 0x000000FFU +#define TWAI_DATA_12_S 0 + +/** TWAI_RX_MESSAGE_COUNTER_REG register + * Received message counter register. + */ +#define TWAI_RX_MESSAGE_COUNTER_REG(i) (DR_REG_TWAI_BASE(i) + 0x74) +/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ +#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/** TWAI_CLOCK_DIVIDER_REG register + * Clock divider register. + */ +#define TWAI_CLOCK_DIVIDER_REG(i) (DR_REG_TWAI_BASE(i) + 0x7c) +/** TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ +#define TWAI_CD 0x000000FFU +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FFU +#define TWAI_CD_S 0 +/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001U +#define TWAI_CLOCK_OFF_S 8 + +/** TWAI_SW_STANDBY_CFG_REG register + * Software configure standby pin directly. + */ +#define TWAI_SW_STANDBY_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x80) +/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ +#define TWAI_SW_STANDBY_EN (BIT(0)) +#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) +#define TWAI_SW_STANDBY_EN_V 0x00000001U +#define TWAI_SW_STANDBY_EN_S 0 +/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ +#define TWAI_SW_STANDBY_CLR (BIT(1)) +#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) +#define TWAI_SW_STANDBY_CLR_V 0x00000001U +#define TWAI_SW_STANDBY_CLR_S 1 + +/** TWAI_HW_CFG_REG register + * Hardware configure standby pin. + */ +#define TWAI_HW_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x84) +/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ +#define TWAI_HW_STANDBY_EN (BIT(0)) +#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) +#define TWAI_HW_STANDBY_EN_V 0x00000001U +#define TWAI_HW_STANDBY_EN_S 0 + +/** TWAI_HW_STANDBY_CNT_REG register + * Configure standby counter. + */ +#define TWAI_HW_STANDBY_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x88) +/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ +#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) +#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_S 0 + +/** TWAI_IDLE_INTR_CNT_REG register + * Configure idle interrupt counter. + */ +#define TWAI_IDLE_INTR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x8c) +/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ +#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) +#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_S 0 + +/** TWAI_ECO_CFG_REG register + * ECO configuration register. + */ +#define TWAI_ECO_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x90) +/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ +#define TWAI_RDN_ENA (BIT(0)) +#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) +#define TWAI_RDN_ENA_V 0x00000001U +#define TWAI_RDN_ENA_S 0 +/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ +#define TWAI_RDN_RESULT (BIT(1)) +#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) +#define TWAI_RDN_RESULT_V 0x00000001U +#define TWAI_RDN_RESULT_S 1 + +/** TWAI_TIMESTAMP_DATA_REG register + * Timestamp data register + */ +#define TWAI_TIMESTAMP_DATA_REG(i) (DR_REG_TWAI_BASE(i) + 0x94) +/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ +#define TWAI_TIMESTAMP_DATA 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_M (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S) +#define TWAI_TIMESTAMP_DATA_V 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_S 0 + +/** TWAI_TIMESTAMP_PRESCALER_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_PRESCALER_REG(i) (DR_REG_TWAI_BASE(i) + 0x98) +/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ +#define TWAI_TS_DIV_NUM 0x0000FFFFU +#define TWAI_TS_DIV_NUM_M (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S) +#define TWAI_TS_DIV_NUM_V 0x0000FFFFU +#define TWAI_TS_DIV_NUM_S 0 + +/** TWAI_TIMESTAMP_CFG_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x9c) +/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ +#define TWAI_TS_ENABLE (BIT(0)) +#define TWAI_TS_ENABLE_M (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S) +#define TWAI_TS_ENABLE_V 0x00000001U +#define TWAI_TS_ENABLE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/twai_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/twai_struct.h new file mode 100644 index 0000000000..53bbc39af0 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/twai_struct.h @@ -0,0 +1,619 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ + uint32_t ts_counter_ovfl_int_st:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_status_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ + uint32_t ts_counter_ovfl_int_ena:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of buffer register + * TX RX Buffer. + */ +typedef union { + struct { + /** byte : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_rx_buffer_reg_t; + +typedef struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved8: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; +} acceptance_filter_reg_t; + +/** Group: Timestamp Register */ +/** Type of timestamp_data register + * Timestamp data register + */ +typedef union { + struct { + /** timestamp_data : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ + uint32_t timestamp_data:32; + }; + uint32_t val; +} twai_timestamp_data_reg_t; + +/** Type of timestamp_prescaler register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_div_num : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ + uint32_t ts_div_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_timestamp_prescaler_reg_t; + +/** Type of timestamp_cfg register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_enable : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ + uint32_t ts_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_timestamp_cfg_reg_t; + + +typedef struct twai_dev_t { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_status_reg_t interrupt_st; + volatile twai_interrupt_enable_reg_t interrupt_ena; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile union { + acceptance_filter_reg_t acceptance_filter; + twai_tx_rx_buffer_reg_t tx_rx_buffer[13]; + }; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; + volatile twai_timestamp_data_reg_t timestamp_data; + volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; + volatile twai_timestamp_cfg_reg_t timestamp_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; +extern twai_dev_t TWAI1; +extern twai_dev_t TWAI2; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_reg.h new file mode 100644 index 0000000000..c782014e86 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_reg.h @@ -0,0 +1,1579 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * a + */ +#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maximum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART Version register + */ +#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_struct.h new file mode 100644 index 0000000000..c49c9b58ba --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uart_eco5_struct.h @@ -0,0 +1,1274 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maximum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; +extern uart_dev_t UART3; +extern uart_dev_t UART4; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uart_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/uart_reg.h new file mode 100644 index 0000000000..66c4081a96 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uart_reg.h @@ -0,0 +1,1581 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13425 + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * a + */ +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maximum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART Version register + */ +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uart_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/uart_struct.h new file mode 100644 index 0000000000..5b98af7ceb --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uart_struct.h @@ -0,0 +1,1276 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13425 + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:32; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_character : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_character:8; + /** xoff_character : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_character:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** at_char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t at_char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maximum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct uart_dev_t{ + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; /* LP_UART instance has this register reserved */ + volatile uart_negpulse_reg_t negpulse; /* LP_UART instance has this register reserved */ + volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */ + volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */ + volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */ + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; +extern uart_dev_t UART3; +extern uart_dev_t UART4; +extern uart_dev_t LP_UART; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uhci_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/uhci_reg.h new file mode 100644 index 0000000000..74e047a248 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uhci_reg.h @@ -0,0 +1,966 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * UHCI Configuration Register0 + */ +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ +#define UHCI_UART_SEL 0x00000007U +#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S) +#define UHCI_UART_SEL_V 0x00000007U +#define UHCI_UART_SEL_S 2 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * UHCI Interrupt Raw Register + */ +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * UHCI Interrupt Status Register + */ +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * UHCI Interrupt Enable Register + */ +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * UHCI Interrupt Clear Register + */ +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * UHCI Configuration Register1 + */ +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * UHCI Receive Status Register + */ +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * UHCI Transmit Status Register + */ +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * UHCI Escapes Configuration Register0 + */ +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * UHCI Hung Configuration Register0 + */ +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * UHCI Ack Value Configuration Register0 + */ +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * UHCI Head Register + */ +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * UCHI Quick send Register + */ +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * UHCI Q0_WORD0 Quick Send Register + */ +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * UHCI Q0_WORD1 Quick Send Register + */ +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * UHCI Q1_WORD0 Quick Send Register + */ +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * UHCI Q1_WORD1 Quick Send Register + */ +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * UHCI Q2_WORD0 Quick Send Register + */ +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * UHCI Q2_WORD1 Quick Send Register + */ +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * UHCI Q3_WORD0 Quick Send Register + */ +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * UHCI Q3_WORD1 Quick Send Register + */ +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * UHCI Q4_WORD0 Quick Send Register + */ +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * UHCI Q4_WORD1 Quick Send Register + */ +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * UHCI Q5_WORD0 Quick Send Register + */ +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * UHCI Q5_WORD1 Quick Send Register + */ +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * UHCI Q6_WORD0 Quick Send Register + */ +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * UHCI Q6_WORD1 Quick Send Register + */ +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * UHCI Escapes Sequence Configuration Register0 + */ +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * UHCI Escapes Sequence Configuration Register1 + */ +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * UHCI Escapes Sequence Configuration Register2 + */ +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * UHCI Escapes Sequence Configuration Register3 + */ +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * UCHI Packet Length Configuration Register + */ +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * UHCI Version Register + */ +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/uhci_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/uhci_struct.h new file mode 100644 index 0000000000..b8328eecfa --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/uhci_struct.h @@ -0,0 +1,844 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * UHCI Configuration Register0 + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart_sel : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ + uint32_t uart_sel:3; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * UHCI Configuration Register1 + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * UHCI Escapes Configuration Register0 + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * UHCI Hung Configuration Register0 + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * UHCI Ack Value Configuration Register0 + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * UCHI Quick send Register + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_q0_word0 register + * UHCI Q0_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word0:32; + }; + uint32_t val; +} uhci_reg_q0_word0_reg_t; + +/** Type of reg_q0_word1 register + * UHCI Q0_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word1:32; + }; + uint32_t val; +} uhci_reg_q0_word1_reg_t; + +/** Type of reg_q1_word0 register + * UHCI Q1_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word0:32; + }; + uint32_t val; +} uhci_reg_q1_word0_reg_t; + +/** Type of reg_q1_word1 register + * UHCI Q1_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word1:32; + }; + uint32_t val; +} uhci_reg_q1_word1_reg_t; + +/** Type of reg_q2_word0 register + * UHCI Q2_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word0:32; + }; + uint32_t val; +} uhci_reg_q2_word0_reg_t; + +/** Type of reg_q2_word1 register + * UHCI Q2_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word1:32; + }; + uint32_t val; +} uhci_reg_q2_word1_reg_t; + +/** Type of reg_q3_word0 register + * UHCI Q3_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word0:32; + }; + uint32_t val; +} uhci_reg_q3_word0_reg_t; + +/** Type of reg_q3_word1 register + * UHCI Q3_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word1:32; + }; + uint32_t val; +} uhci_reg_q3_word1_reg_t; + +/** Type of reg_q4_word0 register + * UHCI Q4_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word0:32; + }; + uint32_t val; +} uhci_reg_q4_word0_reg_t; + +/** Type of reg_q4_word1 register + * UHCI Q4_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word1:32; + }; + uint32_t val; +} uhci_reg_q4_word1_reg_t; + +/** Type of reg_q5_word0 register + * UHCI Q5_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word0:32; + }; + uint32_t val; +} uhci_reg_q5_word0_reg_t; + +/** Type of reg_q5_word1 register + * UHCI Q5_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word1:32; + }; + uint32_t val; +} uhci_reg_q5_word1_reg_t; + +/** Type of reg_q6_word0 register + * UHCI Q6_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word0:32; + }; + uint32_t val; +} uhci_reg_q6_word0_reg_t; + +/** Type of reg_q6_word1 register + * UHCI Q6_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word1:32; + }; + uint32_t val; +} uhci_reg_q6_word1_reg_t; + +/** Type of esc_conf0 register + * UHCI Escapes Sequence Configuration Register0 + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * UHCI Escapes Sequence Configuration Register1 + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * UHCI Escapes Sequence Configuration Register2 + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * UHCI Escapes Sequence Configuration Register3 + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * UCHI Packet Length Configuration Register + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * UHCI Interrupt Raw Register + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * UHCI Interrupt Status Register + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * UHCI Interrupt Enable Register + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * UHCI Interrupt Clear Register + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * UHCI Receive Status Register + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * UHCI Transmit Status Register + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * UHCI Head Register + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UHCI Version Register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct uhci_dev_t { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile uhci_reg_q0_word0_reg_t reg_q0_word0; + volatile uhci_reg_q0_word1_reg_t reg_q0_word1; + volatile uhci_reg_q1_word0_reg_t reg_q1_word0; + volatile uhci_reg_q1_word1_reg_t reg_q1_word1; + volatile uhci_reg_q2_word0_reg_t reg_q2_word0; + volatile uhci_reg_q2_word1_reg_t reg_q2_word1; + volatile uhci_reg_q3_word0_reg_t reg_q3_word0; + volatile uhci_reg_q3_word1_reg_t reg_q3_word1; + volatile uhci_reg_q4_word0_reg_t reg_q4_word0; + volatile uhci_reg_q4_word1_reg_t reg_q4_word1; + volatile uhci_reg_q5_word0_reg_t reg_q5_word0; + volatile uhci_reg_q5_word1_reg_t reg_q5_word1; + volatile uhci_reg_q6_word0_reg_t reg_q6_word0; + volatile uhci_reg_q6_word1_reg_t reg_q6_word1; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + +extern uhci_dev_t UHCI0; + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..95ce3b2fe2 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1286 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_DEVICE_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +/** USB_DEVICE_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check + * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is + * received, then read data from UART Rx FIFO. + */ +#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_M (USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V << USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_DEVICE_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +/** USB_DEVICE_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_DEVICE_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_WR_DONE_M (USB_DEVICE_SERIAL_JTAG_WR_DONE_V << USB_DEVICE_SERIAL_JTAG_WR_DONE_S) +#define USB_DEVICE_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_WR_DONE_S 0 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * Host. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_DEVICE_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; + * default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; + * default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; + * default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; + * default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_DEVICE_INT_ST_REG register + * Interrupt status register. + */ +#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) +/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_DEVICE_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_DEVICE_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + */ +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_DEVICE_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +/** USB_DEVICE_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_DEVICE_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_M (USB_DEVICE_SERIAL_JTAG_PHY_SEL_V << USB_DEVICE_SERIAL_JTAG_PHY_SEL_S) +#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_DEVICE_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_DEVICE_SERIAL_JTAG_VREFH 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_VREFH_M (USB_DEVICE_SERIAL_JTAG_VREFH_V << USB_DEVICE_SERIAL_JTAG_VREFH_S) +#define USB_DEVICE_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_VREFH_S 3 +/** USB_DEVICE_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_DEVICE_SERIAL_JTAG_VREFL 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_VREFL_M (USB_DEVICE_SERIAL_JTAG_VREFL_V << USB_DEVICE_SERIAL_JTAG_VREFL_S) +#define USB_DEVICE_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_VREFL_S 5 +/** USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_DEVICE_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S) +#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_DEVICE_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S) +#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_M (USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V << USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_DEVICE_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) +/** USB_DEVICE_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_M (USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V << USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_DEVICE_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_M (USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V << USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_DEVICE_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_DEVICE_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +/** USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_DEVICE_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +/** USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_DEVICE_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) +/** USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_DEVICE_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +/** USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_DEVICE_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +/** USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_DEVICE_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_DEVICE_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_DEVICE_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_DEVICE_MISC_CONF_REG register + * Clock enable control + */ +#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +/** USB_DEVICE_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_DEVICE_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_CLK_EN_S) +#define USB_DEVICE_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_DEVICE_MEM_CONF_REG register + * Memory power control + */ +#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +/** USB_DEVICE_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_DEVICE_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_DEVICE_BASE + 0x4c) +/** USB_DEVICE_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_DEVICE_SERIAL_JTAG_RTS (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_RTS_M (USB_DEVICE_SERIAL_JTAG_RTS_V << USB_DEVICE_SERIAL_JTAG_RTS_S) +#define USB_DEVICE_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RTS_S 0 +/** USB_DEVICE_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_DEVICE_SERIAL_JTAG_DTR (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_DTR_M (USB_DEVICE_SERIAL_JTAG_DTR_V << USB_DEVICE_SERIAL_JTAG_DTR_S) +#define USB_DEVICE_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_DTR_S 1 +/** USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_DEVICE_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x50) +/** USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_DEVICE_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x54) +/** USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_DEVICE_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S) +#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_DEVICE_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x58) +/** USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_DEVICE_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x5c) +/** USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_DEVICE_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_DEVICE_BASE + 0x60) +/** USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_M (USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V << USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_DEVICE_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_DEVICE_BASE + 0x64) +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_DEVICE_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_DEVICE_BASE + 0x68) +/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_DEVICE_ECO_LOW_48_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_DEVICE_BASE + 0x6c) +/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S) +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S 0 + +/** USB_DEVICE_ECO_HIGH_48_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_DEVICE_BASE + 0x70) +/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S) +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 + +/** USB_DEVICE_ECO_CELL_CTRL_48_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_DEVICE_BASE + 0x74) +/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S) +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S 0 +/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S) +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S 1 + +/** USB_DEVICE_ECO_LOW_APB_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_DEVICE_BASE + 0x78) +/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S) +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 + +/** USB_DEVICE_ECO_HIGH_APB_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_DEVICE_BASE + 0x7c) +/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S) +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 + +/** USB_DEVICE_ECO_CELL_CTRL_APB_REG register + * Reserved. + */ +#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_DEVICE_BASE + 0x80) +/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S) +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S 0 +/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; + * Reserved. + */ +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S) +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U +#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S 1 + +/** USB_DEVICE_SRAM_CTRL_REG register + * PPA SRAM Control Register + */ +#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_DEVICE_BASE + 0x84) +/** USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ +#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU +#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S) +#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU +#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S 0 + +/** USB_DEVICE_DATE_REG register + * Date register + */ +#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x88) +/** USB_DEVICE_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; + * register version. + */ +#define USB_DEVICE_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_DATE_M (USB_DEVICE_SERIAL_JTAG_DATE_V << USB_DEVICE_SERIAL_JTAG_DATE_S) +#define USB_DEVICE_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_DEVICE_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..ca2ea0df15 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_serial_jtag_struct.h @@ -0,0 +1,1045 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : RO; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * usb_serial_jtag_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) + * into UART Tx FIFO. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is set, user can check + * usb_serial_jtag_OUT_EP1_WR_ADDR usb_serial_jtag_OUT_EP0_RD_ADDR to know how many data is + * received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * usb_serial_jtag_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB + * Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** serial_jtag_test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t serial_jtag_test_enable:1; + /** serial_jtag_test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t serial_jtag_test_usb_oe:1; + /** serial_jtag_test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t serial_jtag_test_tx_dp:1; + /** serial_jtag_test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t serial_jtag_test_tx_dm:1; + /** serial_jtag_test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t serial_jtag_test_rx_rcv:1; + /** serial_jtag_test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t serial_jtag_test_rx_dp:1; + /** serial_jtag_test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t serial_jtag_test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** serial_jtag_clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t serial_jtag_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** serial_jtag_usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t serial_jtag_usb_mem_pd:1; + /** serial_jtag_usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t serial_jtag_usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** serial_jtag_rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t serial_jtag_rts:1; + /** serial_jtag_dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t serial_jtag_dtr:1; + /** serial_jtag_usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t serial_jtag_usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bdata_bits:8; + /** serial_jtag_get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bparity_type:8; + /** serial_jtag_get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** serial_jtag_config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t serial_jtag_config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_jtag_serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_reset_wr:1; + /** serial_jtag_serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_reset_rd:1; + /** serial_jtag_serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_reset_wr:1; + /** serial_jtag_serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_reset_rd:1; + /** serial_jtag_serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_rempty:1; + /** serial_jtag_serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + +/** Type of eco_low_48 register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rnd_eco_low_48 : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rnd_eco_low_48:32; + }; + uint32_t val; +} usb_serial_jtag_eco_low_48_reg_t; + +/** Type of eco_high_48 register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rnd_eco_high_48 : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t serial_jtag_rnd_eco_high_48:32; + }; + uint32_t val; +} usb_serial_jtag_eco_high_48_reg_t; + +/** Type of eco_low_apb register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rnd_eco_low_apb : R/W; bitpos: [31:0]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rnd_eco_low_apb:32; + }; + uint32_t val; +} usb_serial_jtag_eco_low_apb_reg_t; + +/** Type of eco_high_apb register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rnd_eco_high_apb : R/W; bitpos: [31:0]; default: 4294967295; + * Reserved. + */ + uint32_t serial_jtag_rnd_eco_high_apb:32; + }; + uint32_t val; +} usb_serial_jtag_eco_high_apb_reg_t; + +/** Type of sram_ctrl register + * PPA SRAM Control Register + */ +typedef union { + struct { + /** serial_jtag_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * Control signals + */ + uint32_t serial_jtag_mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_serial_jtag_sram_ctrl_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t serial_jtag_jtag_in_flush_int_raw:1; + /** serial_jtag_sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t serial_jtag_sof_int_raw:1; + /** serial_jtag_serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_raw:1; + /** serial_jtag_serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_jtag_serial_in_empty_int_raw:1; + /** serial_jtag_pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t serial_jtag_pid_err_int_raw:1; + /** serial_jtag_crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t serial_jtag_crc5_err_int_raw:1; + /** serial_jtag_crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t serial_jtag_crc16_err_int_raw:1; + /** serial_jtag_stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t serial_jtag_stuff_err_int_raw:1; + /** serial_jtag_in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_raw:1; + /** serial_jtag_usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t serial_jtag_usb_bus_reset_int_raw:1; + /** serial_jtag_out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_raw:1; + /** serial_jtag_out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_raw:1; + /** serial_jtag_rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t serial_jtag_rts_chg_int_raw:1; + /** serial_jtag_dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t serial_jtag_dtr_chg_int_raw:1; + /** serial_jtag_get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t serial_jtag_get_line_code_int_raw:1; + /** serial_jtag_set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t serial_jtag_set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_st:1; + /** serial_jtag_sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_st:1; + /** serial_jtag_serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_st:1; + /** serial_jtag_serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_st:1; + /** serial_jtag_pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_st:1; + /** serial_jtag_crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_st:1; + /** serial_jtag_crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_st:1; + /** serial_jtag_stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_st:1; + /** serial_jtag_in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_st:1; + /** serial_jtag_usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_st:1; + /** serial_jtag_out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_st:1; + /** serial_jtag_out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_st:1; + /** serial_jtag_rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_st:1; + /** serial_jtag_dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_st:1; + /** serial_jtag_get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_st:1; + /** serial_jtag_set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the usb_serial_jtag_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_ena:1; + /** serial_jtag_sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_ena:1; + /** serial_jtag_serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_ena:1; + /** serial_jtag_serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_ena:1; + /** serial_jtag_pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_ena:1; + /** serial_jtag_crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_ena:1; + /** serial_jtag_crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_ena:1; + /** serial_jtag_stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_ena:1; + /** serial_jtag_in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_ena:1; + /** serial_jtag_usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_ena:1; + /** serial_jtag_out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_ena:1; + /** serial_jtag_out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_ena:1; + /** serial_jtag_rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_ena:1; + /** serial_jtag_dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_ena:1; + /** serial_jtag_get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_ena:1; + /** serial_jtag_set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the usb_serial_jtag_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the usb_serial_jtag_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_clr:1; + /** serial_jtag_sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the usb_serial_jtag_JTAG_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_clr:1; + /** serial_jtag_serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_clr:1; + /** serial_jtag_serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the usb_serial_jtag_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_clr:1; + /** serial_jtag_pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the usb_serial_jtag_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_clr:1; + /** serial_jtag_crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the usb_serial_jtag_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_clr:1; + /** serial_jtag_crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the usb_serial_jtag_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_clr:1; + /** serial_jtag_stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the usb_serial_jtag_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_clr:1; + /** serial_jtag_in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the usb_serial_jtag_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_clr:1; + /** serial_jtag_usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the usb_serial_jtag_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_clr:1; + /** serial_jtag_out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the usb_serial_jtag_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_clr:1; + /** serial_jtag_out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the usb_serial_jtag_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_clr:1; + /** serial_jtag_rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the usb_serial_jtag_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_clr:1; + /** serial_jtag_dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the usb_serial_jtag_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_clr:1; + /** serial_jtag_get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the usb_serial_jtag_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_clr:1; + /** serial_jtag_set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the usb_serial_jtag_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** serial_jtag_in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t serial_jtag_in_fifo_cnt:2; + /** serial_jtag_in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t serial_jtag_in_fifo_empty:1; + /** serial_jtag_in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t serial_jtag_in_fifo_full:1; + /** serial_jtag_out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t serial_jtag_out_fifo_cnt:2; + /** serial_jtag_out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t serial_jtag_out_fifo_empty:1; + /** serial_jtag_out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t serial_jtag_out_fifo_full:1; + /** serial_jtag_in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t serial_jtag_in_fifo_reset:1; + /** serial_jtag_out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t serial_jtag_out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** serial_jtag_sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t serial_jtag_sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t serial_jtag_in_ep0_state:2; + /** serial_jtag_in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t serial_jtag_in_ep0_wr_addr:7; + /** serial_jtag_in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t serial_jtag_in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t serial_jtag_in_ep1_state:2; + /** serial_jtag_in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t serial_jtag_in_ep1_wr_addr:7; + /** serial_jtag_in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t serial_jtag_in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t serial_jtag_in_ep2_state:2; + /** serial_jtag_in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t serial_jtag_in_ep2_wr_addr:7; + /** serial_jtag_in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t serial_jtag_in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t serial_jtag_in_ep3_state:2; + /** serial_jtag_in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t serial_jtag_in_ep3_wr_addr:7; + /** serial_jtag_in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t serial_jtag_in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t serial_jtag_out_ep0_state:2; + /** serial_jtag_out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is + * detected, there are usb_serial_jtag_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t serial_jtag_out_ep0_wr_addr:7; + /** serial_jtag_out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t serial_jtag_out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t serial_jtag_out_ep1_state:2; + /** serial_jtag_out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is + * detected, there are usb_serial_jtag_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t serial_jtag_out_ep1_wr_addr:7; + /** serial_jtag_out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t serial_jtag_out_ep1_rd_addr:7; + /** serial_jtag_out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t serial_jtag_out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t serial_jtag_out_ep2_state:2; + /** serial_jtag_out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When usb_serial_jtag_SERIAL_OUT_RECV_PKT_INT is + * detected, there are usb_serial_jtag_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t serial_jtag_out_ep2_wr_addr:7; + /** serial_jtag_out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t serial_jtag_out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bchar_format:8; + /** serial_jtag_bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bparity_type:8; + /** serial_jtag_bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** serial_jtag_usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t serial_jtag_usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + +/** Type of eco_cell_ctrl_48 register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rdn_result_48 : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rdn_result_48:1; + /** serial_jtag_rdn_ena_48 : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rdn_ena_48:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_eco_cell_ctrl_48_reg_t; + +/** Type of eco_cell_ctrl_apb register + * Reserved. + */ +typedef union { + struct { + /** serial_jtag_rdn_result_apb : RO; bitpos: [0]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rdn_result_apb:1; + /** serial_jtag_rdn_ena_apb : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + uint32_t serial_jtag_rdn_ena_apb:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_eco_cell_ctrl_apb_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** serial_jtag_date : R/W; bitpos: [31:0]; default: 34676752; + * register version. + */ + uint32_t serial_jtag_date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct usb_serial_jtag_dev_t { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + volatile usb_serial_jtag_eco_low_48_reg_t eco_low_48; + volatile usb_serial_jtag_eco_high_48_reg_t eco_high_48; + volatile usb_serial_jtag_eco_cell_ctrl_48_reg_t eco_cell_ctrl_48; + volatile usb_serial_jtag_eco_low_apb_reg_t eco_low_apb; + volatile usb_serial_jtag_eco_high_apb_reg_t eco_high_apb; + volatile usb_serial_jtag_eco_cell_ctrl_apb_reg_t eco_cell_ctrl_apb; + volatile usb_serial_jtag_sram_ctrl_reg_t sram_ctrl; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_utmi_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_utmi_struct.h new file mode 100644 index 0000000000..e891217808 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_utmi_struct.h @@ -0,0 +1,231 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13430 + +/** + * Following register description is taken from + * U2OPHYT40LL USB 2.0 OTG PHY specification v2.0 + */ + +typedef union { + struct { + /** clk_gate_rx : R/W; bitpos: [0]; default 2'b0; + * Clock Gating Control Signal for Rx. + * 2'b0 Lower power consumption + * 2'b1 Lowest power consumption mode + * 2'b2 Normal power consumption mode + */ + uint32_t clk_gate_rx: 2; + /** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0; + * Clock Gating Control Signal for Rx. + * 1'b0 Low power consumption mode + * 1'b1 Normal power consumption mode + */ + uint32_t clk_gate_tx: 1; + /** adj_res_fs : Reserved; bitpos: [3]; default: 0; + * Fine tune the 45ohm termination resistor (FS) + * Reserved + */ + uint32_t adj_res_fs: 2; + /** adj_res_hs : R/W; bitpos: [5]; default: 3'b100; + * Fine tune the 45ohm termination resistor (HS) + * 3'b000 40 Ohm + * 3'b100 45 Ohm + * 3'b110 50 Ohm + */ + uint32_t adj_res_hs: 3; + uint32_t reserved_8: 24; + }; + uint32_t val; +} usb_utmi_fc_00_reg_t; + +typedef union { + struct { + /** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010; + * Squelch detection threshold voltage control bits + * 4'b0000 92 mV + * 4'b0010 124 mV + * 4'b0011 152 mV + */ + uint32_t adj_vref_sq: 4; + /** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111; + * Super power saving with reduced output swing mode control bits (for HS mode only) + * 4'b0001 100 mV output swing + * 4'b0011 200 mV output swing + * 4'b0111 300 mV output swing + * 4'b1111 400 mV output swing + */ + uint32_t adj_pw_hs: 4; + uint32_t reserved_8: 24; + }; + uint32_t val; +} usb_utmi_fc_01_reg_t; + +typedef union { + struct { + /** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111 + * Internal bias current adjustment control bits + * 4'b0000 125 uA + * 4'b0111 100 uA + * 4'b1111 78 uA + */ + uint32_t adj_iref_res: 4; + /** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100 + * Output eye shape adjustment control bits + * 3'b000 320 mV + * 3'b100 400 mV + * 3'b111 460 mV + */ + uint32_t adj_vsw_hs: 3; + uint32_t reserved_7: 25; + }; + uint32_t val; +} usb_utmi_fc_02_reg_t; + +typedef union { + struct { + /** adj_pll : R/W; bitpos: [0]; default: 4'b0101 + * PLL adjustment signal + */ + uint32_t adj_pll: 4; + /** adj_osc : R/W; bitpos: [4]; default: 3'b000 + * TX Clock phase adjust signal + */ + uint32_t adj_txclk_phase: 3; + uint32_t reserved_7: 25; + }; + uint32_t val; +} usb_utmi_fc_03_reg_t; + +typedef union { + struct { + /** test_sel : R/W; bitpos: [0]; default: 8'b0 + * The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal. + * In our implementation output of this register is left floating and DTO is driven from Probe module. + * Thus writing to this register has no effect and is renamed to 'reserved' + */ + uint32_t reserved: 8; + uint32_t reserved_8: 24; + }; + uint32_t val; +} usb_utmi_fc_04_reg_t; + +typedef union { + struct { + /** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1 + * RXGAP fix enable + */ + uint32_t rxgap_fix_en: 1; + /** counter_sel : R/W; bitpos: [1]; default: 1'b0 + * SIE_input sample enable + */ + uint32_t counter_sel: 1; + /** clk_sel : R/W; bitpos: [2]; default: 1'b0 + * CLK60_30 source select + */ + uint32_t clk_sel: 1; + /** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0 + * PHY MODE select + */ + uint32_t phy_mode_sel: 1; + /** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0 + * UNI_BIDI signal + */ + uint32_t uni_bidi_i: 1; + /** short_5v : R/W; bitpos: [5]; default: 1'b0 + * SHORT_5V signal + */ + uint32_t short_5v: 1; + /** short_5v_enable : R/W; bitpos: [6]; default: 1'b1 + * SHORT_5V_ENABLE signal + */ + uint32_t short_5v_enable: 1; + /** usable_en : R/W; bitpos: [7]; default: 1'b1 + * compare_begin delay time select + */ + uint32_t usable_en: 1; + uint32_t reserved_8: 24; + }; + uint32_t val; +} usb_utmi_fc_05_reg_t; + +typedef union { + struct { + /** ls_par_en : R/W; bitpos: [0]; default: 1'b0 + * LS mode with parallel enable + */ + uint32_t ls_par_en: 1; + /** det_fseop_en : R/W; bitpos: [1]; default: 1'b0 + * FS EOP detect enable + */ + uint32_t det_fseop_en: 1; + /** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0 + * Dis_preamble enable + */ + uint32_t pre_hphy_lsie: 1; + /** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0 + * LS mode keep alive enable + */ + uint32_t ls_kpalv_en: 1; + /** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100 + * PHY High-SPeed bus turn-around time select + */ + uint32_t hs_tx2rx_dly_cnt_sel: 3; + uint32_t reserved_7: 25; + }; + uint32_t val; +} usb_utmi_fc_06_reg_t; + +typedef union { + struct { + /** cnt_num : R/W; bitpos: [1:0]; default: 2'b00 + * 3 ms counter select + * 00: 392us (Default) + * 01: 682us + * 10: 1.36ms + * 11: 2.72ms + */ + uint32_t cnt_num: 2; + /** clk480_sel : R/W; bitpos: [2]; default: 1'b0 + * CLK_480 output time select + * 0: CLK_480 is valid after a delay time when PLL is locked + * 1: CLK_480 is valid immediately after PLL is locked + */ + uint32_t clk480_sel: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} usb_utmi_fc_07_reg_t; + +typedef struct usb_utmi_dev_t { + volatile usb_utmi_fc_00_reg_t fc_00; + volatile usb_utmi_fc_01_reg_t fc_01; + volatile usb_utmi_fc_02_reg_t fc_02; + volatile usb_utmi_fc_03_reg_t fc_03; + volatile usb_utmi_fc_04_reg_t fc_04; + volatile usb_utmi_fc_05_reg_t fc_05; + volatile usb_utmi_fc_06_reg_t fc_06; + volatile usb_utmi_fc_07_reg_t fc_07; +} usb_utmi_dev_t; + +extern usb_utmi_dev_t USB_UTMI; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_eco5_struct.h new file mode 100644 index 0000000000..a90ba9b8d8 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_eco5_struct.h @@ -0,0 +1,139 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: USB wrapper registers. */ +/** Type of otg_conf register + * USB wrapper configuration registers. + */ +typedef union { + struct { + /** srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ + uint32_t srp_sessend_override:1; + /** srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ + uint32_t srp_sessend_value:1; + /** phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ + uint32_t phy_sel:1; + /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pd:1; + /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ + uint32_t dbnce_fltr_bypass:1; + /** exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ + uint32_t ahb_clk_force_on:1; + /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ + uint32_t phy_clk_force_on:1; + uint32_t reserved_21:1; + /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pu:1; + uint32_t reserved_23:8; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452; + * Date register. + */ + uint32_t usb_wrap_date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct { + volatile usb_wrap_otg_conf_reg_t otg_conf; + uint32_t reserved_004[254]; + volatile usb_wrap_date_reg_t date; +} usb_wrap_dev_t; + +extern usb_wrap_dev_t USB_WRAP; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_reg.h new file mode 100644 index 0000000000..31fbd239ff --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_reg.h @@ -0,0 +1,182 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_WRAP_OTG_CONF_REG register + * USB wrapper configuration registers. + */ +#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0) +/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ +#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0)) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0 +/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ +#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1)) +#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S) +#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_VALUE_S 1 +/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ +#define USB_WRAP_PHY_SEL (BIT(2)) +#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S) +#define USB_WRAP_PHY_SEL_V 0x00000001U +#define USB_WRAP_PHY_SEL_S 2 +/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PD (BIT(3)) +#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S) +#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001U +#define USB_WRAP_DFIFO_FORCE_PD_S 3 +/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ +#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4)) +#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S) +#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001U +#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4 +/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ +#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5)) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5 +/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ +#define USB_WRAP_EXCHG_PINS (BIT(6)) +#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S) +#define USB_WRAP_EXCHG_PINS_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_S 6 +/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ +#define USB_WRAP_VREFH 0x00000003U +#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S) +#define USB_WRAP_VREFH_V 0x00000003U +#define USB_WRAP_VREFH_S 7 +/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ +#define USB_WRAP_VREFL 0x00000003U +#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S) +#define USB_WRAP_VREFL_V 0x00000003U +#define USB_WRAP_VREFL_S 9 +/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ +#define USB_WRAP_VREF_OVERRIDE (BIT(11)) +#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S) +#define USB_WRAP_VREF_OVERRIDE_V 0x00000001U +#define USB_WRAP_VREF_OVERRIDE_S 11 +/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ +#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12)) +#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S) +#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_WRAP_PAD_PULL_OVERRIDE_S 12 +/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DP_PULLUP (BIT(13)) +#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S) +#define USB_WRAP_DP_PULLUP_V 0x00000001U +#define USB_WRAP_DP_PULLUP_S 13 +/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DP_PULLDOWN (BIT(14)) +#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S) +#define USB_WRAP_DP_PULLDOWN_V 0x00000001U +#define USB_WRAP_DP_PULLDOWN_S 14 +/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DM_PULLUP (BIT(15)) +#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S) +#define USB_WRAP_DM_PULLUP_V 0x00000001U +#define USB_WRAP_DM_PULLUP_S 15 +/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DM_PULLDOWN (BIT(16)) +#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S) +#define USB_WRAP_DM_PULLDOWN_V 0x00000001U +#define USB_WRAP_DM_PULLDOWN_S 16 +/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ +#define USB_WRAP_PULLUP_VALUE (BIT(17)) +#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S) +#define USB_WRAP_PULLUP_VALUE_V 0x00000001U +#define USB_WRAP_PULLUP_VALUE_S 17 +/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ +#define USB_WRAP_USB_PAD_ENABLE (BIT(18)) +#define USB_WRAP_USB_PAD_ENABLE_M (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S) +#define USB_WRAP_USB_PAD_ENABLE_V 0x00000001U +#define USB_WRAP_USB_PAD_ENABLE_S 18 +/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ +#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19)) +#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S) +#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_AHB_CLK_FORCE_ON_S 19 +/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ +#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20)) +#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S) +#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_PHY_CLK_FORCE_ON_S 20 +/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PU (BIT(22)) +#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S) +#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001U +#define USB_WRAP_DFIFO_FORCE_PU_S 22 +/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ +#define USB_WRAP_CLK_EN (BIT(31)) +#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S) +#define USB_WRAP_CLK_EN_V 0x00000001U +#define USB_WRAP_CLK_EN_S 31 + +/** USB_WRAP_DATE_REG register + * Date register. + */ +#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc) +/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452; + * Date register. + */ +#define USB_WRAP_USB_WRAP_DATE 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_M (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S) +#define USB_WRAP_USB_WRAP_DATE_V 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_struct.h new file mode 100644 index 0000000000..aa7f0f58e6 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_struct.h @@ -0,0 +1,181 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: USB wrapper registers. */ +/** Type of otg_conf register + * USB wrapper configuration registers. + */ +typedef union { + struct { + /** srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ + uint32_t srp_sessend_override:1; + /** srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ + uint32_t srp_sessend_value:1; + /** phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ + uint32_t phy_sel:1; + /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pd:1; + /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ + uint32_t dbnce_fltr_bypass:1; + /** exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ + uint32_t ahb_clk_force_on:1; + /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ + uint32_t phy_clk_force_on:1; + /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0; + * Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge. + */ + uint32_t phy_tx_edge_sel:1; + /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pu:1; + uint32_t reserved_23:8; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of test_conf register + * TEST relative configuration registers. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable to test the USB pad. + */ + uint32_t test_enable:1; + /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test. + */ + uint32_t test_usb_wrap_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test. + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test. + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 0; + * USB differential rx value in test. + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 0; + * USB D+ rx value in test. + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test. + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_wrap_test_conf_reg_t; + +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452; + * Date register. + */ + uint32_t usb_wrap_date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct usb_wrap_dev_t { + volatile usb_wrap_otg_conf_reg_t otg_conf; + volatile usb_wrap_test_conf_reg_t test_conf; + uint32_t reserved_008[253]; + volatile usb_wrap_date_reg_t date; +} usb_wrap_dev_t; + +extern usb_wrap_dev_t USB_WRAP; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif