From 4300c344cae99895ece0eaad3259c94e77233026 Mon Sep 17 00:00:00 2001 From: Jin Chen Date: Fri, 24 Jan 2025 12:12:01 +0800 Subject: [PATCH] fix(ble): fix rtc freq div error on esp32c61 (cherry picked from commit b7571dd71116252ab63c756eb102bec486e2d47d) Co-authored-by: cjin --- components/bt/controller/esp32c6/bt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index 4b18c60add..5dd632f58c 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -522,12 +522,16 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src) switch (slow_clk_src) { case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source"); +#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND uint32_t chip_version = efuse_hal_chip_revision(); if (chip_version == 0) { modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1)); } else{ modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1)); } +#else + modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1)); +#endif // SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND break; case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");