From 9b7bed2243d7675b7130d3dd8ee212fa08dbbb4a Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 29 Jul 2022 17:07:39 +0800 Subject: [PATCH] Clean IRAM and DRAM address space conversion macros --- components/heap/port/esp32c3/memory_layout.c | 3 +-- components/heap/port/esp32h2/memory_layout.c | 3 +-- components/heap/port/esp32s3/memory_layout.c | 3 +-- components/soc/esp32c3/include/soc/soc.h | 8 ++++---- components/soc/esp32h2/include/soc/soc.h | 8 ++++---- components/soc/esp32s2/include/soc/soc.h | 4 ++++ components/soc/esp32s3/include/soc/soc.h | 4 ++++ .../system/memprot/main/esp32s2/test_memprot_main.c | 3 --- 8 files changed, 19 insertions(+), 17 deletions(-) diff --git a/components/heap/port/esp32c3/memory_layout.c b/components/heap/port/esp32c3/memory_layout.c index 04e0a37a84..110c3861db 100644 --- a/components/heap/port/esp32c3/memory_layout.c +++ b/components/heap/port/esp32c3/memory_layout.c @@ -70,13 +70,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index a34e55c32f..c3def826d2 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -70,13 +70,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 64f0f7f702..5b25b17824 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -59,7 +59,6 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6F0000) const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM @@ -75,7 +74,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), 2, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM #endif diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index afa2b15fa3..574cb8d3b1 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -238,6 +238,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC80000 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 @@ -250,10 +254,6 @@ //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FC80000 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 -#define SOC_MEM_INTERNAL_LOW1 0x40370000 -#define SOC_MEM_INTERNAL_HIGH1 0x403E0000 -#define SOC_MEM_INTERNAL_LOW2 0x600FE000 -#define SOC_MEM_INTERNAL_HIGH2 0x60100000 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index f49133c52c..db5c19720e 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -266,6 +266,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC80000 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 @@ -278,10 +282,6 @@ //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FC80000 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 -#define SOC_MEM_INTERNAL_LOW1 0x40370000 -#define SOC_MEM_INTERNAL_HIGH1 0x403E0000 -#define SOC_MEM_INTERNAL_LOW2 0x600FE000 -#define SOC_MEM_INTERNAL_HIGH2 0x60100000 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index ae4cf0103a..2f62a827a0 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -277,6 +277,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FFB0000 #define SOC_DIRAM_DRAM_HIGH 0x40000000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFB0000 #define SOC_DMA_HIGH 0x40000000 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index cc4d321770..f63b3ec762 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -284,6 +284,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC88000 #define SOC_DIRAM_DRAM_HIGH 0x3FCF0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 diff --git a/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c b/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c index 0dc7bf9c90..523f3029df 100644 --- a/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c +++ b/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c @@ -94,9 +94,6 @@ static uint8_t fnc_call0_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x0 volatile bool g_override_illegal_instruction = false; -#define MAP_DRAM_TO_IRAM(addr) (addr - SOC_DIRAM_DRAM_LOW + SOC_DIRAM_IRAM_LOW) -#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_DIRAM_IRAM_LOW + SOC_DIRAM_DRAM_LOW) - #define SRAM_TEST_BUFFER_SIZE 0x400 #define SRAM_TEST_OFFSET 0x200