diff --git a/components/esp32s2/sleep_modes.c b/components/esp32s2/sleep_modes.c
index fa01026ff1..419ed36665 100644
--- a/components/esp32s2/sleep_modes.c
+++ b/components/esp32s2/sleep_modes.c
@@ -201,6 +201,9 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
         // no-op for esp32s2
     }
 
+    extern void regi2c_analog_cali_reg_read(void);
+    regi2c_analog_cali_reg_read();
+
     if (deep_sleep) {
         if (s_config.wakeup_triggers & RTC_TOUCH_TRIG_EN) {
             touch_wakeup_prepare();
@@ -251,6 +254,9 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     // Restore CPU frequency
     rtc_clk_cpu_freq_set_config(&cpu_freq_config);
 
+    extern void regi2c_analog_cali_reg_write(void);
+    regi2c_analog_cali_reg_write();
+
     // re-enable UART output
     resume_uarts();
 
diff --git a/components/soc/soc/esp32s2/private_include/regi2c_saradc.h b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
index 2345e0a5aa..406d9d2005 100644
--- a/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
@@ -81,3 +81,10 @@
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
 #define I2C_SARADC_TSENS_DAC_LSB 0
+
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+#define REGI2C_ANA_CALI_BYTE_NUM         8
diff --git a/components/soc/src/esp32s2/regi2c_ctrl.c b/components/soc/src/esp32s2/regi2c_ctrl.c
index d7439bc97e..d4ab0c160c 100644
--- a/components/soc/src/esp32s2/regi2c_ctrl.c
+++ b/components/soc/src/esp32s2/regi2c_ctrl.c
@@ -16,6 +16,7 @@
 #include "soc/apb_ctrl_reg.h"
 #include "regi2c_ctrl.h"
 #include "regi2c_brownout.h"
+#include "esp_attr.h"
 
 #define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
 
@@ -164,4 +165,25 @@ void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uin
             | ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
     REG_WRITE(I2C_RTC_CONFIG2, temp);
     while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
-}
\ No newline at end of file
+}
+
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+
+static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
+
+void IRAM_ATTR regi2c_analog_cali_reg_read(void)
+{
+    for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
+        reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
+    }
+}
+
+void IRAM_ATTR regi2c_analog_cali_reg_write(void)
+{
+    for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
+        regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
+    }
+}
diff --git a/components/soc/src/esp32s2/regi2c_ctrl.h b/components/soc/src/esp32s2/regi2c_ctrl.h
index 34c26c6949..d51a64c007 100644
--- a/components/soc/src/esp32s2/regi2c_ctrl.h
+++ b/components/soc/src/esp32s2/regi2c_ctrl.h
@@ -89,6 +89,13 @@ void regi2c_exit_critical(void);
 #define REGI2C_READ(block, reg_add) \
       regi2c_ctrl_read_reg(block, block##_HOSTID,  reg_add)
 
+/**
+ * Restore regi2c analog calibration related configuration registers.
+ * This is a workaround, and is fixed on later chips
+ */
+void regi2c_analog_cali_reg_read(void);
+void regi2c_analog_cali_reg_write(void);
+
 #ifdef __cplusplus
 }
 #endif