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Merge branch 'feature/esp_sys_iram_cleanup_v5.1' into 'release/v5.1'

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esp-system: move uncessary IRAM functions to flash (v5.1)

See merge request espressif/esp-idf!23376
This commit is contained in:
Marius Vikhammer
2023-04-25 09:51:25 +08:00
parent e104fa1904 de33225c31
commit 9d114e30b5
19 changed files with 36 additions and 59 deletions
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2
components/esp_system/linker.lf
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@@ -5,6 +5,8 @@ entries:
panic (noflash) panic (noflash)
panic_handler (noflash) panic_handler (noflash)
panic_arch (noflash) panic_arch (noflash)
cache_err_int:esp_cache_err_get_cpuid (noflash)
reset_reason:esp_reset_reason_get_hint (noflash)
esp_err (noflash) esp_err (noflash)
esp_system_chip:esp_system_abort (noflash) esp_system_chip:esp_system_abort (noflash)

2
components/esp_system/port/soc/esp32/cache_err_int.c
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@@ -67,7 +67,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM); ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
const uint32_t pro_mask = const uint32_t pro_mask =
DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 | DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |

20
components/esp_system/port/soc/esp32/reset_reason.c
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@@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
@@ -103,7 +95,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32c2/cache_err_int.c
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@@ -72,7 +72,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
return 0; return 0;
} }

2
components/esp_system/port/soc/esp32c2/reset_reason.c
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@@ -84,7 +84,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32c3/cache_err_int.c
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@@ -72,7 +72,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
return 0; return 0;
} }

2
components/esp_system/port/soc/esp32c3/reset_reason.c
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@@ -97,7 +97,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32c6/cache_err_int.c
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@@ -52,7 +52,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
return 0; return 0;
} }

4
components/esp_system/port/soc/esp32c6/reset_reason.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -94,7 +94,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32h2/cache_err_int.c
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@@ -52,7 +52,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
return 0; return 0;
} }

2
components/esp_system/port/soc/esp32h2/reset_reason.c
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@@ -94,7 +94,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32h4/cache_err_int.c
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@@ -72,7 +72,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
return 0; return 0;
} }

2
components/esp_system/port/soc/esp32h4/reset_reason.c
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@@ -94,7 +94,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32s2/cache_err_int.c
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@@ -67,7 +67,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM); ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 || if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 ||
REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) { REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) {

20
components/esp_system/port/soc/esp32s2/reset_reason.c
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@@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
@@ -102,7 +94,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/esp_system/port/soc/esp32s3/cache_err_int.c
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@@ -70,7 +70,7 @@ void esp_cache_err_int_init(void)
ESP_INTR_ENABLE(ETS_CACHEERR_INUM); ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
} }
int IRAM_ATTR esp_cache_err_get_cpuid(void) int esp_cache_err_get_cpuid(void)
{ {
if (cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK)) { if (cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK)) {
return PRO_CPU_NUM; return PRO_CPU_NUM;

20
components/esp_system/port/soc/esp32s3/reset_reason.c
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@@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_system.h" #include "esp_system.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
@@ -100,7 +92,7 @@ void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
} }
/* in IRAM, can be called from panic handler */ /* in IRAM, can be called from panic handler */
esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) esp_reset_reason_t esp_reset_reason_get_hint(void)
{ {
uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;

2
components/riscv/linker.lf
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@@ -2,4 +2,6 @@
archive: libriscv.a archive: libriscv.a
entries: entries:
interrupt (noflash_text) interrupt (noflash_text)
interrupt:intr_handler_get (default)
interrupt:intr_handler_set (default)
vectors (noflash_text) vectors (noflash_text)

3
tools/ci/check_copyright_ignore.txt
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@@ -561,13 +561,10 @@ components/esp_system/port/public_compat/cache_err_int.h
components/esp_system/port/public_compat/trax.h components/esp_system/port/public_compat/trax.h
components/esp_system/port/soc/esp32/cache_err_int.h components/esp_system/port/soc/esp32/cache_err_int.h
components/esp_system/port/soc/esp32/intr.c components/esp_system/port/soc/esp32/intr.c
components/esp_system/port/soc/esp32/reset_reason.c
components/esp_system/port/soc/esp32c3/apb_backup_dma.c components/esp_system/port/soc/esp32c3/apb_backup_dma.c
components/esp_system/port/soc/esp32c3/cache_err_int.h components/esp_system/port/soc/esp32c3/cache_err_int.h
components/esp_system/port/soc/esp32s2/cache_err_int.h components/esp_system/port/soc/esp32s2/cache_err_int.h
components/esp_system/port/soc/esp32s2/reset_reason.c
components/esp_system/port/soc/esp32s3/cache_err_int.h components/esp_system/port/soc/esp32s3/cache_err_int.h
components/esp_system/port/soc/esp32s3/reset_reason.c
components/esp_system/test/test_delay.c components/esp_system/test/test_delay.c
components/esp_system/test/test_reset_reason.c components/esp_system/test/test_reset_reason.c
components/esp_system/test/test_stack_check.c components/esp_system/test/test_stack_check.c