diff --git a/Kconfig b/Kconfig index 55d73d2a7c..2553a7ce55 100644 --- a/Kconfig +++ b/Kconfig @@ -144,6 +144,7 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV select IDF_ENV_BRINGUP + select IDF_ENV_FPGA if ESP32H21_SELECTS_REV_MP config IDF_TARGET_ESP32H4 bool diff --git a/components/efuse/esp32h21/esp_efuse_utility.c b/components/efuse/esp32h21/esp_efuse_utility.c index 51dca0e22d..ab94484354 100644 --- a/components/efuse/esp32h21/esp_efuse_utility.c +++ b/components/efuse/esp32h21/esp_efuse_utility.c @@ -21,7 +21,7 @@ extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; /*Range addresses to read blocks*/ const esp_efuse_range_addr_t range_read_addr_blocks[] = { {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT - {EFUSE_RD_MAC_SYS_0_REG, EFUSE_RD_MAC_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_8M + {EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_8M {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 diff --git a/components/esp_hw_support/port/esp32h21/Kconfig.hw_support b/components/esp_hw_support/port/esp32h21/Kconfig.hw_support index 67fa096c88..ac4cd88f8c 100644 --- a/components/esp_hw_support/port/esp32h21/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32h21/Kconfig.hw_support @@ -1,3 +1,14 @@ +comment "NOTE! Support of ESP32-H21 MP is mutually exclusive" +comment "Read the help text of the option below for explanation" + +config ESP32H21_SELECTS_REV_MP + bool "Select ESP32-H21 MP version" + default n + help + Enable this option to select ESP32-H21 MP revision. + MP revisions have some hardware differences with Beta revision. + MP revisions is not compatible with Beta revision. + choice ESP32H21_REV_MIN prompt "Minimum Supported ESP32-H21 Revision" default ESP32H21_REV_MIN_0 diff --git a/components/hal/esp32h21/efuse_hal.c b/components/hal/esp32h21/efuse_hal.c index bf65022155..8f7b83ca48 100644 --- a/components/hal/esp32h21/efuse_hal.c +++ b/components/hal/esp32h21/efuse_hal.c @@ -91,7 +91,7 @@ bool efuse_hal_is_coding_error_in_block(unsigned block) { if (block == 0) { for (unsigned i = 0; i < 5; i++) { - if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { + if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) { return true; } } @@ -99,7 +99,7 @@ bool efuse_hal_is_coding_error_in_block(unsigned block) // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 block--; - uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); + uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4); return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; } return false; diff --git a/components/hal/esp32h21/include/hal/efuse_ll.h b/components/hal/esp32h21/include/hal/efuse_ll.h index 99ac523246..44f821426c 100644 --- a/components/hal/esp32h21/include/hal/efuse_ll.h +++ b/components/hal/esp32h21/include/hal/efuse_ll.h @@ -48,26 +48,6 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) return EFUSE.rd_mac_sys_1.mac_1; } -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) -{ - return EFUSE.rd_mac_sys_2.active_hp_dbias; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) -{ - return EFUSE.rd_mac_sys_2.active_lp_dbias; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbias(void) -{ - return EFUSE.rd_mac_sys_2.dslp_dbias; -} - -__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) -{ - return (EFUSE.rd_mac_sys_3.dbias_vol_gap_sign << 4)|(EFUSE.rd_mac_sys_3.dbias_vol_gap_value2 << 1)|EFUSE.rd_mac_sys_2.dbias_vol_gap_value1; -} - __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { return EFUSE.rd_repeat_data2.secure_boot_en; @@ -76,49 +56,58 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return EFUSE.rd_mac_sys_3.wafer_version_major; + //TODO: [ESP32H21] IDF-11507 + return 0; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return EFUSE.rd_mac_sys_3.wafer_version_minor; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - return EFUSE.rd_mac_sys_3.disable_wafer_version_major; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return EFUSE.rd_sys_part1_data4.blk_version_major; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return EFUSE.rd_sys_part1_data4.blk_version_minor; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - return EFUSE.rd_sys_part1_data4.disable_blk_version_major; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return EFUSE.rd_mac_sys_4.pkg_version; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void) { - return EFUSE.conf.cfg_ecdsa_blk; + //TODO: [ESP32H21] IDF-11507 + return 0; } __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + //TODO: [ESP32H21] IDF-11507 (void) curve; - EFUSE.conf.cfg_ecdsa_blk = efuse_blk; + (void) efuse_blk; } /******************* eFuse control functions *************************/ diff --git a/components/hal/include/hal/apm_hal.h b/components/hal/include/hal/apm_hal.h index 7b68598b12..a9960cbdf2 100644 --- a/components/hal/include/hal/apm_hal.h +++ b/components/hal/include/hal/apm_hal.h @@ -362,7 +362,7 @@ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable); #endif //SOC_IS(ESP32P4) -#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED +#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOCKconfig_APM_SUPPORTED #if SOC_IS(ESP32H4) #include "soc/hp_apm_reg.h" diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 21ee851006..cb1d5014e8 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -25,6 +25,13 @@ if(CONFIG_IDF_TARGET_ESP32P4) else() list(APPEND includes "${target_folder}/register/hw_ver2") endif() +elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H4 IDF-13835 + list(APPEND includes "${target_folder}/register") + if(CONFIG_ESP32H21_SELECTS_REV_MP) + list(APPEND includes "${target_folder}/register/hw_ver_mp") + else() + list(APPEND includes "${target_folder}/register/hw_ver_beta1") + endif() else() if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register") list(APPEND includes "${target_folder}/register") diff --git a/components/soc/esp32h21/register/soc/lp_apm_reg.h b/components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_reg.h similarity index 100% rename from components/soc/esp32h21/register/soc/lp_apm_reg.h rename to components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_reg.h diff --git a/components/soc/esp32h21/register/soc/lp_apm_struct.h b/components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_struct.h similarity index 100% rename from components/soc/esp32h21/register/soc/lp_apm_struct.h rename to components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_struct.h diff --git a/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_reg.h b/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_reg.h new file mode 100644 index 0000000000..91fc38b0ed --- /dev/null +++ b/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_reg.h @@ -0,0 +1,506 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 + +/** LP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) +/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) +#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_S 0 + +/** LP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) +/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) +#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_S 0 + +/** LP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) +/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S) +#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_X_S 0 +/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S) +#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_W_S 1 +/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S) +#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_R_S 2 +/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S) +#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_X_S 4 +/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S) +#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_W_S 5 +/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S) +#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_R_S 6 +/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S) +#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_X_S 8 +/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S) +#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_W_S 9 +/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S) +#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_R_S 10 + +/** LP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) +/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) +#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_S 0 + +/** LP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) +/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) +#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_S 0 + +/** LP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) +/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S) +#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_X_S 0 +/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S) +#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_W_S 1 +/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S) +#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_R_S 2 +/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S) +#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_X_S 4 +/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S) +#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_W_S 5 +/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S) +#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_R_S 6 +/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S) +#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_X_S 8 +/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S) +#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_W_S 9 +/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S) +#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_R_S 10 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xd8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xdc) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0x7fc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_struct.h b/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_struct.h new file mode 100644 index 0000000000..2d68f84ca6 --- /dev/null +++ b/components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_struct.h @@ -0,0 +1,499 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x800, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/efuse_reg.h b/components/soc/esp32h21/register/soc/efuse_reg.h index 2c8d3140da..c3c9fa858e 100644 --- a/components/soc/esp32h21/register/soc/efuse_reg.h +++ b/components/soc/esp32h21/register/soc/efuse_reg.h @@ -13,7 +13,7 @@ extern "C" { #endif /** EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. + * Represents pgm_data0 */ #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; @@ -25,11 +25,11 @@ extern "C" { #define EFUSE_PGM_DATA_0_S 0 /** EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. + * Represents pgm_data1 */ #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. + * Configures the 1th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) @@ -37,11 +37,11 @@ extern "C" { #define EFUSE_PGM_DATA_1_S 0 /** EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. + * Represents pgm_data2 */ #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. + * Configures the 2th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) @@ -49,11 +49,11 @@ extern "C" { #define EFUSE_PGM_DATA_2_S 0 /** EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. + * Represents pgm_data3 */ #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. + * Configures the 3th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_3 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) @@ -61,7 +61,7 @@ extern "C" { #define EFUSE_PGM_DATA_3_S 0 /** EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. + * Represents pgm_data4 */ #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; @@ -73,7 +73,7 @@ extern "C" { #define EFUSE_PGM_DATA_4_S 0 /** EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. + * Represents pgm_data5 */ #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; @@ -85,7 +85,7 @@ extern "C" { #define EFUSE_PGM_DATA_5_S 0 /** EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. + * Represents pgm_data6 */ #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; @@ -97,7 +97,7 @@ extern "C" { #define EFUSE_PGM_DATA_6_S 0 /** EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. + * Represents pgm_data7 */ #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; @@ -109,11 +109,11 @@ extern "C" { #define EFUSE_PGM_DATA_7_S 0 /** EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. + * Represents pgm_check_value0 */ #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) @@ -121,11 +121,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_0_S 0 /** EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. + * Represents pgm_check_value1 */ #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. + * Configures the 1th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) @@ -133,11 +133,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_1_S 0 /** EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. + * Represents pgm_check_value2 */ #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. + * Configures the 2th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) @@ -145,12 +145,14 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_S 0 /** EFUSE_RD_WR_DIS_REG register - * BLOCK0 data register 0. + * Represents rd_wr_dis */ #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * enabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -158,132 +160,133 @@ extern "C" { #define EFUSE_WR_DIS_S 0 /** EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. + * enabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 -/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0; - * Reserved. +/** EFUSE_PVT_GLITCH_EN : RO; bitpos: [7]; default: 0; + * Represents whether to enable PVT power glitch monitor function. + * 1: Enable. + * 0: Disable */ -#define EFUSE_RPT4_RESERVED0_4 (BIT(7)) -#define EFUSE_RPT4_RESERVED0_4_M (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S) -#define EFUSE_RPT4_RESERVED0_4_V 0x00000001U -#define EFUSE_RPT4_RESERVED0_4_S 7 +#define EFUSE_PVT_GLITCH_EN (BIT(7)) +#define EFUSE_PVT_GLITCH_EN_M (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S) +#define EFUSE_PVT_GLITCH_EN_V 0x00000001U +#define EFUSE_PVT_GLITCH_EN_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether icache is disabled or enabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) #define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + * Represents whether to enable power glitch function. */ #define EFUSE_POWERGLITCH_EN (BIT(10)) #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) #define EFUSE_POWERGLITCH_EN_V 0x00000001U #define EFUSE_POWERGLITCH_EN_S 10 -/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled. 1: disabled. 0: enabled. + * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during + * boot_mode_download. + * 1: Disabled + * 0: Enabled */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether TWAI function is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) #define EFUSE_DIS_TWAI_V 0x00000001U #define EFUSE_DIS_TWAI_S 14 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through - * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured + * to 0. For more information, please refer to Chapter Placeholder. + * 1: Enabled + * 0: Disabled */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. - */ -#define EFUSE_USB_DREFH 0x00000003U -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003U -#define EFUSE_USB_DREFH_S 21 -/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. - */ -#define EFUSE_USB_DREFL 0x00000003U -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003U -#define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) #define EFUSE_USB_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_S 25 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not - * functioned. + * Represents whether vdd spi pin is functioned as gpio. + * 1: Functioned + * 0: Not functioned */ #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) @@ -309,74 +312,91 @@ extern "C" { #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 29 -/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0; - * Reserved. +/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [31:30]; default: 0; + * Represents control method of xts pseudo-round anti-dpa attack function. + * 0: Controlled by register + * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes + * calculation. */ -#define EFUSE_RPT4_RESERVED0_0 0x00000003U -#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S) -#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U -#define EFUSE_RPT4_RESERVED0_0_S 30 +#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 30 /** EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0; - * Reserved. +/** EFUSE_IO_LDO_ADJUST : RO; bitpos: [7:0]; default: 0; + * Represents configuration of IO LDO mode and voltage. */ -#define EFUSE_RPT4_RESERVED1_1 0x0000FFFFU -#define EFUSE_RPT4_RESERVED1_1_M (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S) -#define EFUSE_RPT4_RESERVED1_1_V 0x0000FFFFU -#define EFUSE_RPT4_RESERVED1_1_S 0 +#define EFUSE_IO_LDO_ADJUST 0x000000FFU +#define EFUSE_IO_LDO_ADJUST_M (EFUSE_IO_LDO_ADJUST_V << EFUSE_IO_LDO_ADJUST_S) +#define EFUSE_IO_LDO_ADJUST_V 0x000000FFU +#define EFUSE_IO_LDO_ADJUST_S 0 +/** EFUSE_VDD_SPI_LDO_ADJUST : RO; bitpos: [15:8]; default: 0; + * Represents configuration of FLASH LDO mode and voltage. + */ +#define EFUSE_VDD_SPI_LDO_ADJUST 0x000000FFU +#define EFUSE_VDD_SPI_LDO_ADJUST_M (EFUSE_VDD_SPI_LDO_ADJUST_V << EFUSE_VDD_SPI_LDO_ADJUST_S) +#define EFUSE_VDD_SPI_LDO_ADJUST_V 0x000000FFU +#define EFUSE_VDD_SPI_LDO_ADJUST_S 8 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. + * Represents RTC watchdog timeout threshold. + * 0：The originally configured STG0 threshold × 2 + * 1：The originally configured STG0 threshold × 4 + * 2：The originally configured STG0 threshold × 8 + * 3：The originally configured STG0 threshold × 16 */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 0 is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 1 is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 2 is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. + * Represents the purpose of Key0. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_0 0x0000000FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_S 24 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. + * Represents the purpose of Key1. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_1 0x0000000FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) @@ -384,84 +404,105 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_S 28 /** EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. + * Represents the purpose of Key2. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_2 0x0000000FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. + * Represents the purpose of Key3. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_3 0x0000000FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_S 4 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. + * Represents the purpose of Key4. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_4 0x0000000FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_S 8 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. + * Represents the purpose of Key5. See Table tab:efuse-key-purpose. */ #define EFUSE_KEY_PURPOSE_5 0x0000000FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_S 12 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC_DPA_OFF + * 1: Security level is SEC_DPA_LOW + * 2: Security level is SEC_DPA_MIDDLE + * 3: Security level is SEC_DPA_HIGH + * For more information, please refer to Chapter mod:sysreg > Section + * sec:sysreg-anti-dpa-attack-security-control. */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [18]; default: 0; - * Reserved +/** EFUSE_IO_LDO_1P8 : RO; bitpos: [18]; default: 0; + * Represents select IO LDO voltage to 1.8V or 3.3V. + * 1: 1.8V + * 0: 3.3V */ -#define EFUSE_RPT4_RESERVED2_1 (BIT(18)) -#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S) -#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U -#define EFUSE_RPT4_RESERVED2_1_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. +#define EFUSE_IO_LDO_1P8 (BIT(18)) +#define EFUSE_IO_LDO_1P8_M (EFUSE_IO_LDO_1P8_V << EFUSE_IO_LDO_1P8_S) +#define EFUSE_IO_LDO_1P8_V 0x00000001U +#define EFUSE_IO_LDO_1P8_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 0; + * Represents whether defense against DPA attack is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) #define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_S 19 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0; - * Reserved. +/** EFUSE_POWERGLITCH_EN1 : RO; bitpos: [26:22]; default: 0; + * Represents whether to enable power glitch function when chip power on. */ -#define EFUSE_RPT4_RESERVED2_0 0x0000003FU -#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S) -#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU -#define EFUSE_RPT4_RESERVED2_0_S 22 +#define EFUSE_POWERGLITCH_EN1 0x0000001FU +#define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S) +#define EFUSE_POWERGLITCH_EN1_V 0x0000001FU +#define EFUSE_POWERGLITCH_EN1_S 22 +/** EFUSE_DCDC_CCM_EN : RO; bitpos: [27]; default: 0; + * Represents whether change DCDC to CCM mode. + */ +#define EFUSE_DCDC_CCM_EN (BIT(27)) +#define EFUSE_DCDC_CCM_EN_M (EFUSE_DCDC_CCM_EN_V << EFUSE_DCDC_CCM_EN_S) +#define EFUSE_DCDC_CCM_EN_V 0x00000001U +#define EFUSE_DCDC_CCM_EN_S 27 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Represents the flash waiting time after power-up. Measurement unit: ms. + * When the value is less than 15, the waiting time is the programmed value. + * Otherwise, the waiting time is a fixed value, i.e. 30 ms. */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -469,87 +510,105 @@ extern "C" { #define EFUSE_FLASH_TPUW_S 28 /** EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether all download modes are disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether direct boot mode is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Set this bit to disable USB-Serial-JTAG print during rom boot. + * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; - * Reserved. +/** EFUSE_FLASH_LDO_EFUSE_SEL : RO; bitpos: [3]; default: 0; + * Represents whether to select efuse control flash ldo default voltage. + * 1: efuse + * 0: strapping */ -#define EFUSE_RPT4_RESERVED3_5 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) -#define EFUSE_RPT4_RESERVED3_5_V 0x00000001U -#define EFUSE_RPT4_RESERVED3_5_S 3 +#define EFUSE_FLASH_LDO_EFUSE_SEL (BIT(3)) +#define EFUSE_FLASH_LDO_EFUSE_SEL_M (EFUSE_FLASH_LDO_EFUSE_SEL_V << EFUSE_FLASH_LDO_EFUSE_SEL_S) +#define EFUSE_FLASH_LDO_EFUSE_SEL_V 0x00000001U +#define EFUSE_FLASH_LDO_EFUSE_SEL_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-Serial-JTAG download function is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. + * Represents whether security download is enabled. Only UART is supported for + * download. Reading/writing RAM or registers is not supported (i.e. Stub download is + * not supported). + * 1: Enabled + * 0: Disabled */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO8 is reset at low level. + * 2: Enable printing when GPIO8 is reset at high level. + * 3: Force disable printing. */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced + * 0: Not forced */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. + * Represents the security version used by ESP-IDF anti-rollback feature. */ #define EFUSE_SECURE_VERSION 0x0000FFFFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) #define EFUSE_SECURE_VERSION_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; - * Set bits to enable hysteresis function of PAD0~5 + * Represents whether to enable the hysteresis function of pad 0-5. + * 0: Disabled + * 1: Enabled */ #define EFUSE_HYS_EN_PAD0 0x0000003FU #define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) @@ -557,443 +616,267 @@ extern "C" { #define EFUSE_HYS_EN_PAD0_S 26 /** EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; - * Set bits to enable hysteresis function of PAD6~27 + * Represents whether to enable the hysteresis function of pad 6-27. + * 0: Disabled + * 1: Enabled */ #define EFUSE_HYS_EN_PAD1 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) #define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_S 0 -/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0; - * Reserved. +/** EFUSE_FLASH_LDO_POWER_SEL : RO; bitpos: [22]; default: 0; + * Represents which flash LDO is selected. + * 0: FLASH LDO 1P8. + * 1: FLASH LDO 1P2. */ -#define EFUSE_RPT4_RESERVED4_1 0x00000003U -#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) -#define EFUSE_RPT4_RESERVED4_1_V 0x00000003U -#define EFUSE_RPT4_RESERVED4_1_S 22 -/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED4_0 0x000000FFU -#define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) -#define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU -#define EFUSE_RPT4_RESERVED4_0_S 24 +#define EFUSE_FLASH_LDO_POWER_SEL (BIT(22)) +#define EFUSE_FLASH_LDO_POWER_SEL_M (EFUSE_FLASH_LDO_POWER_SEL_V << EFUSE_FLASH_LDO_POWER_SEL_S) +#define EFUSE_FLASH_LDO_POWER_SEL_V 0x00000001U +#define EFUSE_FLASH_LDO_POWER_SEL_S 22 -/** EFUSE_RD_MAC_SYS_0_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS0_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ #define EFUSE_MAC_0 0xFFFFFFFFU #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) #define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -/** EFUSE_RD_MAC_SYS_1_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS1_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ #define EFUSE_MAC_1 0x0000FFFFU #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 /** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. + * Represents the extended bits of MAC address. */ #define EFUSE_MAC_EXT 0x0000FFFFU #define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) #define EFUSE_MAC_EXT_V 0x0000FFFFU #define EFUSE_MAC_EXT_S 16 -/** EFUSE_RD_MAC_SYS_2_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS2_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0; - * Stores RF Calibration data. RXIQ version. - */ -#define EFUSE_RXIQ_VERSION 0x00000007U -#define EFUSE_RXIQ_VERSION_M (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S) -#define EFUSE_RXIQ_VERSION_V 0x00000007U -#define EFUSE_RXIQ_VERSION_S 0 -/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0; - * Stores RF Calibration data. RXIQ data 0. - */ -#define EFUSE_RXIQ_0 0x0000007FU -#define EFUSE_RXIQ_0_M (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S) -#define EFUSE_RXIQ_0_V 0x0000007FU -#define EFUSE_RXIQ_0_S 3 -/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0; - * Stores RF Calibration data. RXIQ data 1. - */ -#define EFUSE_RXIQ_1 0x0000007FU -#define EFUSE_RXIQ_1_M (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S) -#define EFUSE_RXIQ_1_V 0x0000007FU -#define EFUSE_RXIQ_1_S 10 -/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0; - * Stores the PMU active hp dbias. - */ -#define EFUSE_ACTIVE_HP_DBIAS 0x0000001FU -#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) -#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000001FU -#define EFUSE_ACTIVE_HP_DBIAS_S 17 -/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0; - * Stores the PMU active lp dbias. - */ -#define EFUSE_ACTIVE_LP_DBIAS 0x0000001FU -#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) -#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000001FU -#define EFUSE_ACTIVE_LP_DBIAS_S 22 -/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0; - * Stores the PMU sleep dbias. - */ -#define EFUSE_DSLP_DBIAS 0x0000000FU -#define EFUSE_DSLP_DBIAS_M (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S) -#define EFUSE_DSLP_DBIAS_V 0x0000000FU -#define EFUSE_DSLP_DBIAS_S 27 -/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0; - * Stores the low 1 bit of dbias_vol_gap. - */ -#define EFUSE_DBIAS_VOL_GAP_VALUE1 (BIT(31)) -#define EFUSE_DBIAS_VOL_GAP_VALUE1_M (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S) -#define EFUSE_DBIAS_VOL_GAP_VALUE1_V 0x00000001U -#define EFUSE_DBIAS_VOL_GAP_VALUE1_S 31 - -/** EFUSE_RD_MAC_SYS_3_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0; - * Stores the high 3 bits of dbias_vol_gap. - */ -#define EFUSE_DBIAS_VOL_GAP_VALUE2 0x00000007U -#define EFUSE_DBIAS_VOL_GAP_VALUE2_M (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S) -#define EFUSE_DBIAS_VOL_GAP_VALUE2_V 0x00000007U -#define EFUSE_DBIAS_VOL_GAP_VALUE2_S 0 -/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0; - * Stores the sign bit of dbias_vol_gap. - */ -#define EFUSE_DBIAS_VOL_GAP_SIGN (BIT(3)) -#define EFUSE_DBIAS_VOL_GAP_SIGN_M (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S) -#define EFUSE_DBIAS_VOL_GAP_SIGN_V 0x00000001U -#define EFUSE_DBIAS_VOL_GAP_SIGN_S 3 -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0; +#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; * Reserved. */ -#define EFUSE_MAC_RESERVED_2 0x00003FFFU +#define EFUSE_MAC_RESERVED_0 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 + +/** EFUSE_RD_MAC_SYS3_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [3:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0000000FU #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_2_S 4 -/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0; - * Stores the wafer version minor. +#define EFUSE_MAC_RESERVED_2_V 0x0000000FU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_PVT_CELL_SELECT : RO; bitpos: [10:4]; default: 0; + * Represents the selection of Power glitch monitor PVT cell. */ -#define EFUSE_WAFER_VERSION_MINOR 0x00000007U -#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) -#define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U -#define EFUSE_WAFER_VERSION_MINOR_S 18 -/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0; - * Stores the wafer version major. +#define EFUSE_PVT_CELL_SELECT 0x0000007FU +#define EFUSE_PVT_CELL_SELECT_M (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S) +#define EFUSE_PVT_CELL_SELECT_V 0x0000007FU +#define EFUSE_PVT_CELL_SELECT_S 4 +/** EFUSE_MAC_RESERVED_3 : RO; bitpos: [17:11]; default: 0; + * Reserved. */ -#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U -#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) -#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U -#define EFUSE_WAFER_VERSION_MAJOR_S 21 -/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0; - * Disables check of wafer version major. +#define EFUSE_MAC_RESERVED_3 0x0000007FU +#define EFUSE_MAC_RESERVED_3_M (EFUSE_MAC_RESERVED_3_V << EFUSE_MAC_RESERVED_3_S) +#define EFUSE_MAC_RESERVED_3_V 0x0000007FU +#define EFUSE_MAC_RESERVED_3_S 11 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. */ -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23)) -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23 -/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0; - * Stores the flash cap. - */ -#define EFUSE_FLASH_CAP 0x00000007U -#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) -#define EFUSE_FLASH_CAP_V 0x00000007U -#define EFUSE_FLASH_CAP_S 24 -/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0; - * Stores the flash temp. - */ -#define EFUSE_FLASH_TEMP 0x00000003U -#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) -#define EFUSE_FLASH_TEMP_V 0x00000003U -#define EFUSE_FLASH_TEMP_S 27 -/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0; - * Stores the flash vendor. - */ -#define EFUSE_FLASH_VENDOR 0x00000007U -#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) -#define EFUSE_FLASH_VENDOR_V 0x00000007U -#define EFUSE_FLASH_VENDOR_S 29 +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 -/** EFUSE_RD_MAC_SYS_4_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS4_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0; - * Package version +#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_PVT_LIMIT : RO; bitpos: [20:5]; default: 0; + * Represents the threshold of power glitch monitor. */ -#define EFUSE_PKG_VERSION 0x00000007U -#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) -#define EFUSE_PKG_VERSION_V 0x00000007U -#define EFUSE_PKG_VERSION_S 0 -/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0; - * reserved +#define EFUSE_PVT_LIMIT 0x0000FFFFU +#define EFUSE_PVT_LIMIT_M (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S) +#define EFUSE_PVT_LIMIT_V 0x0000FFFFU +#define EFUSE_PVT_LIMIT_S 5 +/** EFUSE_PVT_GLITCH_CHARGE_RESET : RO; bitpos: [21]; default: 0; + * Represents whether to trigger reset or charge pump when PVT power glitch happened. + * 1:Trigger charge pump. + * 0:Trigger reset */ -#define EFUSE_RESERVED_1_131 0x1FFFFFFFU -#define EFUSE_RESERVED_1_131_M (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S) -#define EFUSE_RESERVED_1_131_V 0x1FFFFFFFU -#define EFUSE_RESERVED_1_131_S 3 +#define EFUSE_PVT_GLITCH_CHARGE_RESET (BIT(21)) +#define EFUSE_PVT_GLITCH_CHARGE_RESET_M (EFUSE_PVT_GLITCH_CHARGE_RESET_V << EFUSE_PVT_GLITCH_CHARGE_RESET_S) +#define EFUSE_PVT_GLITCH_CHARGE_RESET_V 0x00000001U +#define EFUSE_PVT_GLITCH_CHARGE_RESET_S 21 +/** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0; + * Represents the configuration of glitch mode. + */ +#define EFUSE_PVT_GLITCH_MODE 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_M (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S) +#define EFUSE_PVT_GLITCH_MODE_V 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_S 22 +/** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [31:24]; default: 0; + * Represents the configuration voltage monitor limit for charge pump. + */ +#define EFUSE_PVT_PUMP_LIMIT 0x000000FFU +#define EFUSE_PVT_PUMP_LIMIT_M (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S) +#define EFUSE_PVT_PUMP_LIMIT_V 0x000000FFU +#define EFUSE_PVT_PUMP_LIMIT_S 24 -/** EFUSE_RD_MAC_SYS_5_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS5_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. +#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0; + * Use to configure charge pump voltage gain. */ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_PUMP_DRV 0x0000000FU +#define EFUSE_PUMP_DRV_M (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S) +#define EFUSE_PUMP_DRV_V 0x0000000FU +#define EFUSE_PUMP_DRV_S 0 +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:4]; default: 0; + * Represents the second 28-bit of zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0x0FFFFFFFU #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 0 +#define EFUSE_SYS_DATA_PART0_2_V 0x0FFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 4 /** EFUSE_RD_SYS_PART1_DATA0_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0; - * reserved +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_RESERVED_2_128 0x00000003U -#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) -#define EFUSE_RESERVED_2_128_V 0x00000003U -#define EFUSE_RESERVED_2_128_S 0 -/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0; - * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 - */ -#define EFUSE_BLK_VERSION_MINOR 0x00000007U -#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) -#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U -#define EFUSE_BLK_VERSION_MINOR_S 2 -/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0; - * BLK_VERSION_MAJOR of BLOCK2 - */ -#define EFUSE_BLK_VERSION_MAJOR 0x00000003U -#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) -#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U -#define EFUSE_BLK_VERSION_MAJOR_S 5 -/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; - * Disables check of blk version major - */ -#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 -/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0; - * Temperature calibration data - */ -#define EFUSE_TEMP_CALIB 0x000001FFU -#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) -#define EFUSE_TEMP_CALIB_V 0x000001FFU -#define EFUSE_TEMP_CALIB_S 8 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 /** EFUSE_RD_SYS_PART1_DATA5_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data5 */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; - * ADC1 calibration data +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15 -/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 /** EFUSE_RD_SYS_PART1_DATA6_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data6 */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; - * ADC1 calibration data +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 -/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 -/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 -/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 /** EFUSE_RD_SYS_PART1_DATA7_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data7 */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; - * ADC1 calibration data +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 -/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 -/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 -/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 -/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 -/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0; - * ADC1 calibration data - */ -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17 -/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_2_245 0x000007FFU -#define EFUSE_RESERVED_2_245_M (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S) -#define EFUSE_RESERVED_2_245_V 0x000007FFU -#define EFUSE_RESERVED_2_245_S 21 +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 /** EFUSE_RD_USR_DATA0_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data0 */ #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA0 0xFFFFFFFFU #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) @@ -1001,11 +884,11 @@ extern "C" { #define EFUSE_USR_DATA0_S 0 /** EFUSE_RD_USR_DATA1_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data1 */ #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA1 0xFFFFFFFFU #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) @@ -1013,11 +896,11 @@ extern "C" { #define EFUSE_USR_DATA1_S 0 /** EFUSE_RD_USR_DATA2_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data2 */ #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA2 0xFFFFFFFFU #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) @@ -1025,11 +908,11 @@ extern "C" { #define EFUSE_USR_DATA2_S 0 /** EFUSE_RD_USR_DATA3_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data3 */ #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA3 0xFFFFFFFFU #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) @@ -1037,11 +920,11 @@ extern "C" { #define EFUSE_USR_DATA3_S 0 /** EFUSE_RD_USR_DATA4_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data4 */ #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA4 0xFFFFFFFFU #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) @@ -1049,11 +932,11 @@ extern "C" { #define EFUSE_USR_DATA4_S 0 /** EFUSE_RD_USR_DATA5_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data5 */ #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA5 0xFFFFFFFFU #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) @@ -1061,49 +944,35 @@ extern "C" { #define EFUSE_USR_DATA5_S 0 /** EFUSE_RD_USR_DATA6_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; - * reserved +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). */ -#define EFUSE_RESERVED_3_192 0x000000FFU -#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) -#define EFUSE_RESERVED_3_192_V 0x000000FFU -#define EFUSE_RESERVED_3_192_S 0 -/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; - * Custom MAC - */ -#define EFUSE_CUSTOM_MAC 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) -#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_S 8 +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 /** EFUSE_RD_USR_DATA7_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; - * Custom MAC +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). */ -#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) -#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_1_S 0 -/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_3_248 0x000000FFU -#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) -#define EFUSE_RESERVED_3_248_V 0x000000FFU -#define EFUSE_RESERVED_3_248_S 24 +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 /** EFUSE_RD_KEY0_DATA0_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data0 */ #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA0 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) @@ -1111,11 +980,11 @@ extern "C" { #define EFUSE_KEY0_DATA0_S 0 /** EFUSE_RD_KEY0_DATA1_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data1 */ #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA1 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) @@ -1123,11 +992,11 @@ extern "C" { #define EFUSE_KEY0_DATA1_S 0 /** EFUSE_RD_KEY0_DATA2_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data2 */ #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA2 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) @@ -1135,11 +1004,11 @@ extern "C" { #define EFUSE_KEY0_DATA2_S 0 /** EFUSE_RD_KEY0_DATA3_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data3 */ #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA3 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) @@ -1147,11 +1016,11 @@ extern "C" { #define EFUSE_KEY0_DATA3_S 0 /** EFUSE_RD_KEY0_DATA4_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data4 */ #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA4 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) @@ -1159,11 +1028,11 @@ extern "C" { #define EFUSE_KEY0_DATA4_S 0 /** EFUSE_RD_KEY0_DATA5_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data5 */ #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA5 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) @@ -1171,11 +1040,11 @@ extern "C" { #define EFUSE_KEY0_DATA5_S 0 /** EFUSE_RD_KEY0_DATA6_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data6 */ #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA6 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) @@ -1183,11 +1052,11 @@ extern "C" { #define EFUSE_KEY0_DATA6_S 0 /** EFUSE_RD_KEY0_DATA7_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data7 */ #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA7 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) @@ -1195,11 +1064,11 @@ extern "C" { #define EFUSE_KEY0_DATA7_S 0 /** EFUSE_RD_KEY1_DATA0_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data0 */ #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA0 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) @@ -1207,11 +1076,11 @@ extern "C" { #define EFUSE_KEY1_DATA0_S 0 /** EFUSE_RD_KEY1_DATA1_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data1 */ #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA1 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) @@ -1219,11 +1088,11 @@ extern "C" { #define EFUSE_KEY1_DATA1_S 0 /** EFUSE_RD_KEY1_DATA2_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data2 */ #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA2 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) @@ -1231,11 +1100,11 @@ extern "C" { #define EFUSE_KEY1_DATA2_S 0 /** EFUSE_RD_KEY1_DATA3_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data3 */ #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA3 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) @@ -1243,11 +1112,11 @@ extern "C" { #define EFUSE_KEY1_DATA3_S 0 /** EFUSE_RD_KEY1_DATA4_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data4 */ #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA4 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) @@ -1255,11 +1124,11 @@ extern "C" { #define EFUSE_KEY1_DATA4_S 0 /** EFUSE_RD_KEY1_DATA5_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data5 */ #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA5 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) @@ -1267,11 +1136,11 @@ extern "C" { #define EFUSE_KEY1_DATA5_S 0 /** EFUSE_RD_KEY1_DATA6_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data6 */ #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA6 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) @@ -1279,11 +1148,11 @@ extern "C" { #define EFUSE_KEY1_DATA6_S 0 /** EFUSE_RD_KEY1_DATA7_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data7 */ #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA7 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) @@ -1291,11 +1160,11 @@ extern "C" { #define EFUSE_KEY1_DATA7_S 0 /** EFUSE_RD_KEY2_DATA0_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data0 */ #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA0 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) @@ -1303,11 +1172,11 @@ extern "C" { #define EFUSE_KEY2_DATA0_S 0 /** EFUSE_RD_KEY2_DATA1_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data1 */ #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA1 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) @@ -1315,11 +1184,11 @@ extern "C" { #define EFUSE_KEY2_DATA1_S 0 /** EFUSE_RD_KEY2_DATA2_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data2 */ #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA2 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) @@ -1327,11 +1196,11 @@ extern "C" { #define EFUSE_KEY2_DATA2_S 0 /** EFUSE_RD_KEY2_DATA3_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data3 */ #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA3 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) @@ -1339,11 +1208,11 @@ extern "C" { #define EFUSE_KEY2_DATA3_S 0 /** EFUSE_RD_KEY2_DATA4_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data4 */ #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA4 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) @@ -1351,11 +1220,11 @@ extern "C" { #define EFUSE_KEY2_DATA4_S 0 /** EFUSE_RD_KEY2_DATA5_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data5 */ #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA5 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) @@ -1363,11 +1232,11 @@ extern "C" { #define EFUSE_KEY2_DATA5_S 0 /** EFUSE_RD_KEY2_DATA6_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data6 */ #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA6 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) @@ -1375,11 +1244,11 @@ extern "C" { #define EFUSE_KEY2_DATA6_S 0 /** EFUSE_RD_KEY2_DATA7_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data7 */ #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA7 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) @@ -1387,11 +1256,11 @@ extern "C" { #define EFUSE_KEY2_DATA7_S 0 /** EFUSE_RD_KEY3_DATA0_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data0 */ #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA0 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) @@ -1399,11 +1268,11 @@ extern "C" { #define EFUSE_KEY3_DATA0_S 0 /** EFUSE_RD_KEY3_DATA1_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data1 */ #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA1 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) @@ -1411,11 +1280,11 @@ extern "C" { #define EFUSE_KEY3_DATA1_S 0 /** EFUSE_RD_KEY3_DATA2_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data2 */ #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA2 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) @@ -1423,11 +1292,11 @@ extern "C" { #define EFUSE_KEY3_DATA2_S 0 /** EFUSE_RD_KEY3_DATA3_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data3 */ #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA3 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) @@ -1435,11 +1304,11 @@ extern "C" { #define EFUSE_KEY3_DATA3_S 0 /** EFUSE_RD_KEY3_DATA4_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data4 */ #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA4 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) @@ -1447,11 +1316,11 @@ extern "C" { #define EFUSE_KEY3_DATA4_S 0 /** EFUSE_RD_KEY3_DATA5_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data5 */ #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA5 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) @@ -1459,11 +1328,11 @@ extern "C" { #define EFUSE_KEY3_DATA5_S 0 /** EFUSE_RD_KEY3_DATA6_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data6 */ #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA6 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) @@ -1471,11 +1340,11 @@ extern "C" { #define EFUSE_KEY3_DATA6_S 0 /** EFUSE_RD_KEY3_DATA7_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data7 */ #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA7 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) @@ -1483,11 +1352,11 @@ extern "C" { #define EFUSE_KEY3_DATA7_S 0 /** EFUSE_RD_KEY4_DATA0_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data0 */ #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA0 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) @@ -1495,11 +1364,11 @@ extern "C" { #define EFUSE_KEY4_DATA0_S 0 /** EFUSE_RD_KEY4_DATA1_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data1 */ #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA1 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) @@ -1507,11 +1376,11 @@ extern "C" { #define EFUSE_KEY4_DATA1_S 0 /** EFUSE_RD_KEY4_DATA2_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data2 */ #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA2 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) @@ -1519,11 +1388,11 @@ extern "C" { #define EFUSE_KEY4_DATA2_S 0 /** EFUSE_RD_KEY4_DATA3_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data3 */ #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA3 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) @@ -1531,11 +1400,11 @@ extern "C" { #define EFUSE_KEY4_DATA3_S 0 /** EFUSE_RD_KEY4_DATA4_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data4 */ #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA4 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) @@ -1543,11 +1412,11 @@ extern "C" { #define EFUSE_KEY4_DATA4_S 0 /** EFUSE_RD_KEY4_DATA5_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data5 */ #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA5 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) @@ -1555,11 +1424,11 @@ extern "C" { #define EFUSE_KEY4_DATA5_S 0 /** EFUSE_RD_KEY4_DATA6_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data6 */ #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA6 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) @@ -1567,11 +1436,11 @@ extern "C" { #define EFUSE_KEY4_DATA6_S 0 /** EFUSE_RD_KEY4_DATA7_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data7 */ #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA7 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) @@ -1579,11 +1448,11 @@ extern "C" { #define EFUSE_KEY4_DATA7_S 0 /** EFUSE_RD_KEY5_DATA0_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data0 */ #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA0 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) @@ -1591,11 +1460,11 @@ extern "C" { #define EFUSE_KEY5_DATA0_S 0 /** EFUSE_RD_KEY5_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data1 */ #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA1 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) @@ -1603,11 +1472,11 @@ extern "C" { #define EFUSE_KEY5_DATA1_S 0 /** EFUSE_RD_KEY5_DATA2_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data2 */ #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA2 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) @@ -1615,11 +1484,11 @@ extern "C" { #define EFUSE_KEY5_DATA2_S 0 /** EFUSE_RD_KEY5_DATA3_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data3 */ #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA3 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) @@ -1627,11 +1496,11 @@ extern "C" { #define EFUSE_KEY5_DATA3_S 0 /** EFUSE_RD_KEY5_DATA4_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data4 */ #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA4 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) @@ -1639,11 +1508,11 @@ extern "C" { #define EFUSE_KEY5_DATA4_S 0 /** EFUSE_RD_KEY5_DATA5_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data5 */ #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA5 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) @@ -1651,11 +1520,11 @@ extern "C" { #define EFUSE_KEY5_DATA5_S 0 /** EFUSE_RD_KEY5_DATA6_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data6 */ #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA6 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) @@ -1663,11 +1532,11 @@ extern "C" { #define EFUSE_KEY5_DATA6_S 0 /** EFUSE_RD_KEY5_DATA7_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data7 */ #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA7 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) @@ -1675,11 +1544,11 @@ extern "C" { #define EFUSE_KEY5_DATA7_S 0 /** EFUSE_RD_SYS_PART2_DATA0_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data0 */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) @@ -1687,11 +1556,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_0_S 0 /** EFUSE_RD_SYS_PART2_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_sys_part2_data1 */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) @@ -1699,11 +1568,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_1_S 0 /** EFUSE_RD_SYS_PART2_DATA2_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data2 */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) @@ -1711,11 +1580,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_2_S 0 /** EFUSE_RD_SYS_PART2_DATA3_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data3 */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) @@ -1723,11 +1592,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_3_S 0 /** EFUSE_RD_SYS_PART2_DATA4_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data4 */ #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -1735,11 +1604,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_4_S 0 /** EFUSE_RD_SYS_PART2_DATA5_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data5 */ #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -1747,11 +1616,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_5_S 0 /** EFUSE_RD_SYS_PART2_DATA6_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data6 */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) @@ -1759,135 +1628,114 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_6_S 0 /** EFUSE_RD_SYS_PART2_DATA7_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data7 */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -/** EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR0_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ #define EFUSE_RD_DIS_ERR 0x0000007FU #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0; - * Reserved. +/** EFUSE_PVT_GLITCH_EN_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_EN */ -#define EFUSE_RPT4_RESERVED0_ERR_4 (BIT(7)) -#define EFUSE_RPT4_RESERVED0_ERR_4_M (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S) -#define EFUSE_RPT4_RESERVED0_ERR_4_V 0x00000001U -#define EFUSE_RPT4_RESERVED0_ERR_4_S 7 +#define EFUSE_PVT_GLITCH_EN_ERR (BIT(7)) +#define EFUSE_PVT_GLITCH_EN_ERR_M (EFUSE_PVT_GLITCH_EN_ERR_V << EFUSE_PVT_GLITCH_EN_ERR_S) +#define EFUSE_PVT_GLITCH_EN_ERR_V 0x00000001U +#define EFUSE_PVT_GLITCH_EN_ERR_S 7 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_ICACHE. + * Represents the programming error of EFUSE_DIS_ICACHE */ #define EFUSE_DIS_ICACHE_ERR (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U #define EFUSE_DIS_ICACHE_ERR_S 8 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 /** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. + * Represents the programming error of EFUSE_POWERGLITCH_EN */ #define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U #define EFUSE_POWERGLITCH_EN_ERR_S 10 -/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_CAN. + * Represents the programming error of EFUSE_DIS_TWAI */ #define EFUSE_DIS_TWAI_ERR (BIT(14)) #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) #define EFUSE_DIS_TWAI_ERR_V 0x00000001U #define EFUSE_DIS_TWAI_ERR_S 14 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_ERR_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; - * Indicates a programming error of USB_DREFH. - */ -#define EFUSE_USB_DREFH_ERR 0x00000003U -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003U -#define EFUSE_USB_DREFH_ERR_S 21 -/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; - * Indicates a programming error of USB_DREFL. - */ -#define EFUSE_USB_DREFL_ERR 0x00000003U -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_DREFL_ERR_S 23 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_EXCHG_PINS. + * Represents the programming error of EFUSE_USB_EXCHG_PINS */ #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_ERR_S 25 /** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of VDD_SPI_AS_GPIO. + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO */ #define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) @@ -1907,452 +1755,508 @@ extern "C" { #define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) #define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 29 -/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; - * Reserved. +/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [31:30]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL */ -#define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U -#define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) -#define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U -#define EFUSE_RPT4_RESERVED0_ERR_0_S 30 +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 30 -/** EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR1_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; - * Reserved. +#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_IO_LDO_ADJUST_ERR : RO; bitpos: [7:0]; default: 0; + * Represents the programming error of EFUSE_IO_LDO_ADJUST */ -#define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU -#define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) -#define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU -#define EFUSE_RPT4_RESERVED1_ERR_0_S 0 +#define EFUSE_IO_LDO_ADJUST_ERR 0x000000FFU +#define EFUSE_IO_LDO_ADJUST_ERR_M (EFUSE_IO_LDO_ADJUST_ERR_V << EFUSE_IO_LDO_ADJUST_ERR_S) +#define EFUSE_IO_LDO_ADJUST_ERR_V 0x000000FFU +#define EFUSE_IO_LDO_ADJUST_ERR_S 0 +/** EFUSE_VDD_SPI_LDO_ADJUST_ERR : RO; bitpos: [15:8]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST + */ +#define EFUSE_VDD_SPI_LDO_ADJUST_ERR 0x000000FFU +#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_M (EFUSE_VDD_SPI_LDO_ADJUST_ERR_V << EFUSE_VDD_SPI_LDO_ADJUST_ERR_S) +#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_V 0x000000FFU +#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_S 8 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. + * Represents the programming error of EFUSE_WDT_DELAY_SEL */ #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/** EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR2_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; - * Reserved. +/** EFUSE_IO_LDO_1P8_ERR : RO; bitpos: [18]; default: 0; + * Represents the programming error of EFUSE_IO_LDO_1P8 */ -#define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) -#define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) -#define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U -#define EFUSE_RPT4_RESERVED2_ERR_1_S 18 +#define EFUSE_IO_LDO_1P8_ERR (BIT(18)) +#define EFUSE_IO_LDO_1P8_ERR_M (EFUSE_IO_LDO_1P8_ERR_V << EFUSE_IO_LDO_1P8_ERR_S) +#define EFUSE_IO_LDO_1P8_ERR_V 0x00000001U +#define EFUSE_IO_LDO_1P8_ERR_S 18 /** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. + * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE */ #define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) #define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; - * Reserved. +/** EFUSE_POWERGLITCH_EN1_ERR : RO; bitpos: [26:22]; default: 0; + * Represents the programming error of EFUSE_POWERGLITCH_EN1 */ -#define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU -#define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) -#define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU -#define EFUSE_RPT4_RESERVED2_ERR_0_S 22 +#define EFUSE_POWERGLITCH_EN1_ERR 0x0000001FU +#define EFUSE_POWERGLITCH_EN1_ERR_M (EFUSE_POWERGLITCH_EN1_ERR_V << EFUSE_POWERGLITCH_EN1_ERR_S) +#define EFUSE_POWERGLITCH_EN1_ERR_V 0x0000001FU +#define EFUSE_POWERGLITCH_EN1_ERR_S 22 +/** EFUSE_DCDC_CCM_EN_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_DCDC_CCM_EN + */ +#define EFUSE_DCDC_CCM_EN_ERR (BIT(27)) +#define EFUSE_DCDC_CCM_EN_ERR_M (EFUSE_DCDC_CCM_EN_ERR_V << EFUSE_DCDC_CCM_EN_ERR_S) +#define EFUSE_DCDC_CCM_EN_ERR_V 0x00000001U +#define EFUSE_DCDC_CCM_EN_ERR_S 27 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ #define EFUSE_FLASH_TPUW_ERR 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_S 28 -/** EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR3_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Indicates a programming error of UART_PRINT_CHANNEL. +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ -#define EFUSE_USB_PRINT_ERR (BIT(2)) -#define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) -#define EFUSE_USB_PRINT_ERR_V 0x00000001U -#define EFUSE_USB_PRINT_ERR_S 2 -/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; - * Reserved. +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_FLASH_LDO_EFUSE_SEL_ERR : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_FLASH_LDO_EFUSE_SEL */ -#define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) -#define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U -#define EFUSE_RPT4_RESERVED3_ERR_5_S 3 +#define EFUSE_FLASH_LDO_EFUSE_SEL_ERR (BIT(3)) +#define EFUSE_FLASH_LDO_EFUSE_SEL_ERR_M (EFUSE_FLASH_LDO_EFUSE_SEL_ERR_V << EFUSE_FLASH_LDO_EFUSE_SEL_ERR_S) +#define EFUSE_FLASH_LDO_EFUSE_SEL_ERR_V 0x00000001U +#define EFUSE_FLASH_LDO_EFUSE_SEL_ERR_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 /** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HYS_EN_PAD0. + * Represents the programming error of EFUSE_HYS_EN_PAD0 */ #define EFUSE_HYS_EN_PAD0_ERR 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_M (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S) #define EFUSE_HYS_EN_PAD0_ERR_V 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_S 26 -/** EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR4_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0; - * Indicates a programming error of HYS_EN_PAD1. + * Represents the programming error of EFUSE_HYS_EN_PAD1 */ #define EFUSE_HYS_EN_PAD1_ERR 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_M (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S) #define EFUSE_HYS_EN_PAD1_ERR_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_S 0 -/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0; - * Reserved. +/** EFUSE_FLASH_LDO_POWER_SEL_ERR : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL */ -#define EFUSE_RPT4_RESERVED4_ERR_1 0x00000003U -#define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) -#define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00000003U -#define EFUSE_RPT4_RESERVED4_ERR_1_S 22 -/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU -#define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) -#define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU -#define EFUSE_RPT4_RESERVED4_ERR_0_S 24 +#define EFUSE_FLASH_LDO_POWER_SEL_ERR (BIT(22)) +#define EFUSE_FLASH_LDO_POWER_SEL_ERR_M (EFUSE_FLASH_LDO_POWER_SEL_ERR_V << EFUSE_FLASH_LDO_POWER_SEL_ERR_S) +#define EFUSE_FLASH_LDO_POWER_SEL_ERR_V 0x00000001U +#define EFUSE_FLASH_LDO_POWER_SEL_ERR_S 22 -/** EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. +/** EFUSE_RD_RS_DATA_ERR0_REG register + * Represents rd_rs_data_err */ -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U -#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 -/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) +#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) +#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_RD_MAC_SYS_FAIL_S 3 +/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ -#define EFUSE_SYS_PART1_NUM 0x00000007U -#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) -#define EFUSE_SYS_PART1_NUM_V 0x00000007U -#define EFUSE_SYS_PART1_NUM_S 4 -/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001U -#define EFUSE_SYS_PART1_FAIL_S 7 -/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 +/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_USR_DATA_FAIL_S 11 -/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) +#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ -#define EFUSE_KEY0_ERR_NUM 0x00000007U -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007U -#define EFUSE_KEY0_ERR_NUM_S 12 -/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 +/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001U -#define EFUSE_KEY0_FAIL_S 15 -/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) +#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY0_DATA_FAIL_S 15 +/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ -#define EFUSE_KEY1_ERR_NUM 0x00000007U -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007U -#define EFUSE_KEY1_ERR_NUM_S 16 -/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 +/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001U -#define EFUSE_KEY1_FAIL_S 19 -/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) +#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY1_DATA_FAIL_S 19 +/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ -#define EFUSE_KEY2_ERR_NUM 0x00000007U -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007U -#define EFUSE_KEY2_ERR_NUM_S 20 -/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 +/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001U -#define EFUSE_KEY2_FAIL_S 23 -/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) +#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY2_DATA_FAIL_S 23 +/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ -#define EFUSE_KEY3_ERR_NUM 0x00000007U -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007U -#define EFUSE_KEY3_ERR_NUM_S 24 -/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 +/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001U -#define EFUSE_KEY3_FAIL_S 27 -/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) +#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY3_DATA_FAIL_S 27 +/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ -#define EFUSE_KEY4_ERR_NUM 0x00000007U -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007U -#define EFUSE_KEY4_ERR_NUM_S 28 -/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 +/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001U -#define EFUSE_KEY4_FAIL_S 31 +#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) +#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY4_DATA_FAIL_S 31 -/** EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. +/** EFUSE_RD_RS_DATA_ERR1_REG register + * Represents rd_rs_data_err */ -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) +/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data */ -#define EFUSE_KEY5_ERR_NUM 0x00000007U -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007U -#define EFUSE_KEY5_ERR_NUM_S 0 -/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 +/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. */ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001U -#define EFUSE_KEY5_FAIL_S 3 -/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) +#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY5_DATA_FAIL_S 3 +/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001U -#define EFUSE_SYS_PART2_FAIL_S 7 +#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38806112; + * Represents eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 /** EFUSE_CLK_REG register * eFuse clcok configuration register. */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2364,109 +2268,91 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) #define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. +/** EFUSE_CFG_ECDSA_L_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key low part output. */ -#define EFUSE_CFG_ECDSA_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) -#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_S 16 +#define EFUSE_CFG_ECDSA_L_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_L_BLK_M (EFUSE_CFG_ECDSA_L_BLK_V << EFUSE_CFG_ECDSA_L_BLK_S) +#define EFUSE_CFG_ECDSA_L_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_L_BLK_S 16 +/** EFUSE_CFG_ECDSA_H_BLK : R/W; bitpos: [23:20]; default: 0; + * Configures which block to use for ECDSA key high part output. + */ +#define EFUSE_CFG_ECDSA_H_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_H_BLK_M (EFUSE_CFG_ECDSA_H_BLK_V << EFUSE_CFG_ECDSA_H_BLK_S) +#define EFUSE_CFG_ECDSA_H_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_H_BLK_S 20 /** EFUSE_STATUS_REG register * eFuse status register. */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 -/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001U -#define EFUSE_OTP_LOAD_SW_S 4 -/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001U -#define EFUSE_OTP_STROBE_SW_S 6 -/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001U -#define EFUSE_OTP_CSB_SW_S 7 -/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001U -#define EFUSE_OTP_PGENB_SW_S 8 -/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U -#define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. + * Represents the number of block valid bit. */ #define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. +/** EFUSE_CUR_ECDSA_L_BLK : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA key low part output. */ -#define EFUSE_CUR_ECDSA_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) -#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_S 20 +#define EFUSE_CUR_ECDSA_L_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_L_BLK_M (EFUSE_CUR_ECDSA_L_BLK_V << EFUSE_CUR_ECDSA_L_BLK_S) +#define EFUSE_CUR_ECDSA_L_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_L_BLK_S 20 +/** EFUSE_CUR_ECDSA_H_BLK : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA key high part output. + */ +#define EFUSE_CUR_ECDSA_H_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_H_BLK_M (EFUSE_CUR_ECDSA_H_BLK_V << EFUSE_CUR_ECDSA_H_BLK_S) +#define EFUSE_CUR_ECDSA_H_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_H_BLK_S 24 /** EFUSE_CMD_REG register * eFuse command register. */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. + * Configures whether to send read commands. + * 1: Send + * 0: No effect */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. + * Configures whether to send programming commands. + * 1: Send + * 0: No effect */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) #define EFUSE_PGM_CMD_V 0x00000001U #define EFUSE_PGM_CMD_S 1 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. */ #define EFUSE_BLK_NUM 0x0000000FU #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) @@ -2478,14 +2364,14 @@ extern "C" { */ #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. + * The raw interrupt status of EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 /** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. + * The raw interrupt status of EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) @@ -2497,14 +2383,14 @@ extern "C" { */ #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. + * The masked interrupt status of EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) #define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. + * The masked interrupt status of EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) @@ -2516,14 +2402,14 @@ extern "C" { */ #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. + * Write 1 to enable EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. + * Write 1 to enable EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) @@ -2535,14 +2421,14 @@ extern "C" { */ #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. + * Write 1 to clear EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. + * Write 1 to clear EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) @@ -2553,8 +2439,8 @@ extern "C" { * Controls the eFuse programming voltage. */ #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. */ #define EFUSE_DAC_CLK_DIV 0x000000FFU #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) @@ -2568,14 +2454,17 @@ extern "C" { #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U #define EFUSE_DAC_CLK_PAD_SEL_S 8 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. */ #define EFUSE_DAC_NUM 0x000000FFU #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2587,28 +2476,29 @@ extern "C" { */ #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_THR_A 0x000000FFU #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) #define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_TRD 0x000000FFU #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) #define EFUSE_TRD_V 0x000000FFU #define EFUSE_TRD_S 8 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_TSUR_A 0x000000FFU #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) #define EFUSE_TSUR_A_V 0x000000FFU #define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; - * Configures the waiting time of reading eFuse memory. +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. */ #define EFUSE_READ_INIT_NUM 0x000000FFU #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) @@ -2620,21 +2510,24 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TSUP_A 0x000000FFU #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) #define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_PWR_ON_NUM 0x0000FFFFU #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 /** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. */ #define EFUSE_THP_A 0x000000FFU #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) @@ -2646,14 +2539,16 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_PWR_OFF_NUM 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 /** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TPGM 0x0000FFFFU #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) @@ -2666,46 +2561,39 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) #define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U #define EFUSE_BYPASS_RS_CORRECTION_S 0 /** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. + * Configures which block number to bypass the Reed-Solomon (RS) correction step. */ #define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) #define EFUSE_UPDATE_V 0x00000001U #define EFUSE_UPDATE_S 12 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TPGM_INACTIVE 0x000000FFU #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) #define EFUSE_TPGM_INACTIVE_V 0x000000FFU #define EFUSE_TPGM_INACTIVE_S 13 -/** EFUSE_DATE_REG register - * eFuse version register. - */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; - * Stores eFuse version. - */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h21/register/soc/efuse_struct.h b/components/soc/esp32h21/register/soc/efuse_struct.h index 6f84cf12a1..9d1503cf1b 100644 --- a/components/soc/esp32h21/register/soc/efuse_struct.h +++ b/components/soc/esp32h21/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,160 +10,45 @@ extern "C" { #endif -/** Group: PGM Data Register */ -/** Type of pgm_data0 register - * Register 0 that stores data to be programmed. +/** Group: program_data registers */ +/** Type of pgm_datan register + * Represents pgm_datan */ typedef union { struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. + /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth 32-bit data to be programmed. */ - uint32_t pgm_data_0:32; + uint32_t pgm_data_n:32; }; uint32_t val; -} efuse_pgm_data0_reg_t; +} efuse_pgm_datan_reg_t; -/** Type of pgm_data1 register - * Register 1 that stores data to be programmed. +/** Type of pgm_check_valuen register + * Represents pgm_check_valuen */ typedef union { struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. + /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth RS code to be programmed. */ - uint32_t pgm_data_1:32; + uint32_t pgm_rs_data_n:32; }; uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Register 2 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Register 3 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Register 4 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Register 5 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Register 6 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Register 7 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - -/** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; +} efuse_pgm_check_valuen_reg_t; -/** Group: Read Data Register */ +/** Group: block0 registers */ /** Type of rd_wr_dis register - * BLOCK0 data register 0. + * Represents rd_wr_dis */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * enabled. + * 1: Disabled + * 0: Enabled */ uint32_t wr_dis:32; }; @@ -171,85 +56,97 @@ typedef union { } efuse_rd_wr_dis_reg_t; /** Type of rd_repeat_data0 register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. + * enabled. + * 1: Disabled + * 0: Enabled */ uint32_t rd_dis:7; - /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0; - * Reserved. + /** pvt_glitch_en : RO; bitpos: [7]; default: 0; + * Represents whether to enable PVT power glitch monitor function. + * 1: Enable. + * 0: Disable */ - uint32_t rpt4_reserved0_4:1; + uint32_t pvt_glitch_en:1; /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether icache is disabled or enabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_usb_jtag:1; /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + * Represents whether to enable power glitch function. */ uint32_t powerglitch_en:1; - /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. - */ - uint32_t dis_usb_serial_jtag:1; + uint32_t reserved_11:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled. 1: disabled. 0: enabled. + * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during + * boot_mode_download. + * 1: Disabled + * 0: Enabled */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether TWAI function is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through - * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured + * to 0. For more information, please refer to Chapter Placeholder. + * 1: Enabled + * 0: Disabled */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled */ uint32_t dis_download_manual_encrypt:1; - /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. - */ - uint32_t usb_drefh:2; - /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. - */ - uint32_t usb_drefl:2; + uint32_t reserved_21:4; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not - * functioned. + * Represents whether vdd spi pin is functioned as gpio. + * 1: Functioned + * 0: Not functioned */ uint32_t vdd_spi_as_gpio:1; /** ecdsa_curve_mode : RO; bitpos: [28:27]; default: 0; @@ -266,54 +163,68 @@ typedef union { * 1: Enabled */ uint32_t ecc_force_const_time:1; - /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; - * Reserved. + /** xts_dpa_pseudo_level : RO; bitpos: [31:30]; default: 0; + * Represents control method of xts pseudo-round anti-dpa attack function. + * 0: Controlled by register + * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes + * calculation. */ - uint32_t rpt4_reserved0_0:2; + uint32_t xts_dpa_pseudo_level:2; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; /** Type of rd_repeat_data1 register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ typedef union { struct { - /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0; - * Reserved. + /** io_ldo_adjust : RO; bitpos: [7:0]; default: 0; + * Represents configuration of IO LDO mode and voltage. */ - uint32_t rpt4_reserved1_1:16; + uint32_t io_ldo_adjust:8; + /** vdd_spi_ldo_adjust : RO; bitpos: [15:8]; default: 0; + * Represents configuration of FLASH LDO mode and voltage. + */ + uint32_t vdd_spi_ldo_adjust:8; /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. + * Represents RTC watchdog timeout threshold. + * 0：The originally configured STG0 threshold × 2 + * 1：The originally configured STG0 threshold × 4 + * 2：The originally configured STG0 threshold × 8 + * 3：The originally configured STG0 threshold × 16 */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 0 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 1 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether revoking Secure Boot key 2 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke2:1; /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. + * Represents the purpose of Key0. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_0:4; /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. + * Represents the purpose of Key1. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_1:4; }; @@ -321,55 +232,73 @@ typedef union { } efuse_rd_repeat_data1_reg_t; /** Type of rd_repeat_data2 register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ typedef union { struct { /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. + * Represents the purpose of Key2. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_2:4; /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. + * Represents the purpose of Key3. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_3:4; /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. + * Represents the purpose of Key4. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_4:4; /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. + * Represents the purpose of Key5. See Table tab:efuse-key-purpose. */ uint32_t key_purpose_5:4; /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC_DPA_OFF + * 1: Security level is SEC_DPA_LOW + * 2: Security level is SEC_DPA_MIDDLE + * 3: Security level is SEC_DPA_HIGH + * For more information, please refer to Chapter mod:sysreg > Section + * sec:sysreg-anti-dpa-attack-security-control. */ uint32_t sec_dpa_level:2; - /** rpt4_reserved2_1 : RO; bitpos: [18]; default: 0; - * Reserved. + /** io_ldo_1p8 : RO; bitpos: [18]; default: 0; + * Represents select IO LDO voltage to 1.8V or 3.3V. + * 1: 1.8V + * 0: 3.3V */ - uint32_t rpt4_reserved2_1:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + uint32_t io_ldo_1p8:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 0; + * Represents whether defense against DPA attack is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t crypt_dpa_enable:1; /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_aggressive_revoke:1; - /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; - * Reserved. + /** powerglitch_en1 : RO; bitpos: [26:22]; default: 0; + * Represents whether to enable power glitch function when chip power on. */ - uint32_t rpt4_reserved2_0:6; + uint32_t powerglitch_en1:5; + /** dcdc_ccm_en : RO; bitpos: [27]; default: 0; + * Represents whether change DCDC to CCM mode. + */ + uint32_t dcdc_ccm_en:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Represents the flash waiting time after power-up. Measurement unit: ms. + * When the value is less than 15, the waiting time is the programmed value. + * Otherwise, the waiting time is a fixed value, i.e. 30 ms. */ uint32_t flash_tpuw:4; }; @@ -377,58 +306,76 @@ typedef union { } efuse_rd_repeat_data2_reg_t; /** Type of rd_repeat_data3 register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether all download modes are disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether direct boot mode is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Set this bit to disable USB-Serial-JTAG print during rom boot. + * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_usb_serial_jtag_rom_print:1; - /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; - * Reserved. + /** flash_ldo_efuse_sel : RO; bitpos: [3]; default: 0; + * Represents whether to select efuse control flash ldo default voltage. + * 1: efuse + * 0: strapping */ - uint32_t rpt4_reserved3_5:1; + uint32_t flash_ldo_efuse_sel:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-Serial-JTAG download function is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. + * Represents whether security download is enabled. Only UART is supported for + * download. Reading/writing RAM or registers is not supported (i.e. Stub download is + * not supported). + * 1: Enabled + * 0: Disabled */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO8 is reset at low level. + * 2: Enable printing when GPIO8 is reset at high level. + * 3: Force disable printing. */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced + * 0: Not forced */ uint32_t force_send_resume:1; /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. + * Represents the security version used by ESP-IDF anti-rollback feature. */ uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; - * Set bits to enable hysteresis function of PAD0~5 + * Represents whether to enable the hysteresis function of pad 0-5. + * 0: Disabled + * 1: Enabled */ uint32_t hys_en_pad0:6; }; @@ -436,1257 +383,344 @@ typedef union { } efuse_rd_repeat_data3_reg_t; /** Type of rd_repeat_data4 register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ typedef union { struct { /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; - * Set bits to enable hysteresis function of PAD6~27 + * Represents whether to enable the hysteresis function of pad 6-27. + * 0: Disabled + * 1: Enabled */ uint32_t hys_en_pad1:22; - /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0; - * Reserved. + /** flash_ldo_power_sel : RO; bitpos: [22]; default: 0; + * Represents which flash LDO is selected. + * 0: FLASH LDO 1P8. + * 1: FLASH LDO 1P2. */ - uint32_t rpt4_reserved4_1:2; - /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4_0:8; + uint32_t flash_ldo_power_sel:1; + uint32_t reserved_23:9; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; + +/** Group: block1 registers */ /** Type of rd_mac_sys_0 register - * BLOCK1 data register $n. + * Represents rd_mac_sys_ */ typedef union { struct { /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ uint32_t mac_0:32; }; uint32_t val; -} efuse_rd_mac_sys_0_reg_t; +} efuse_rd_mac_sys0_reg_t; /** Type of rd_mac_sys_1 register - * BLOCK1 data register $n. + * Represents rd_mac_sys_ */ typedef union { struct { /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ uint32_t mac_1:16; /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. + * Represents the extended bits of MAC address. */ uint32_t mac_ext:16; }; uint32_t val; -} efuse_rd_mac_sys_1_reg_t; +} efuse_rd_mac_sys1_reg_t; /** Type of rd_mac_sys_2 register - * BLOCK1 data register $n. + * Represents rd_mac_sys_ */ typedef union { struct { - /** rxiq_version : RO; bitpos: [2:0]; default: 0; - * Stores RF Calibration data. RXIQ version. - */ - uint32_t rxiq_version:3; - /** rxiq_0 : RO; bitpos: [9:3]; default: 0; - * Stores RF Calibration data. RXIQ data 0. - */ - uint32_t rxiq_0:7; - /** rxiq_1 : RO; bitpos: [16:10]; default: 0; - * Stores RF Calibration data. RXIQ data 1. - */ - uint32_t rxiq_1:7; - /** active_hp_dbias : RO; bitpos: [21:17]; default: 0; - * Stores the PMU active hp dbias. - */ - uint32_t active_hp_dbias:5; - /** active_lp_dbias : RO; bitpos: [26:22]; default: 0; - * Stores the PMU active lp dbias. - */ - uint32_t active_lp_dbias:5; - /** dslp_dbias : RO; bitpos: [30:27]; default: 0; - * Stores the PMU sleep dbias. - */ - uint32_t dslp_dbias:4; - /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0; - * Stores the low 1 bit of dbias_vol_gap. - */ - uint32_t dbias_vol_gap_value1:1; - }; - uint32_t val; -} efuse_rd_mac_sys_2_reg_t; - -/** Type of rd_mac_sys_3 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0; - * Stores the high 3 bits of dbias_vol_gap. - */ - uint32_t dbias_vol_gap_value2:3; - /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0; - * Stores the sign bit of dbias_vol_gap. - */ - uint32_t dbias_vol_gap_sign:1; - /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0; + /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; * Reserved. */ - uint32_t mac_reserved_2:14; - /** wafer_version_minor : RO; bitpos: [20:18]; default: 0; - * Stores the wafer version minor. + uint32_t mac_reserved_0:14; + /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. */ - uint32_t wafer_version_minor:3; - /** wafer_version_major : RO; bitpos: [22:21]; default: 0; - * Stores the wafer version major. - */ - uint32_t wafer_version_major:2; - /** disable_wafer_version_major : RO; bitpos: [23]; default: 0; - * Disables check of wafer version major. - */ - uint32_t disable_wafer_version_major:1; - /** flash_cap : RO; bitpos: [26:24]; default: 0; - * Stores the flash cap. - */ - uint32_t flash_cap:3; - /** flash_temp : RO; bitpos: [28:27]; default: 0; - * Stores the flash temp. - */ - uint32_t flash_temp:2; - /** flash_vendor : RO; bitpos: [31:29]; default: 0; - * Stores the flash vendor. - */ - uint32_t flash_vendor:3; + uint32_t mac_reserved_1:18; }; uint32_t val; -} efuse_rd_mac_sys_3_reg_t; +} efuse_rd_mac_sys2_reg_t; + +/** Type of rd_mac_sys_3 register + * Represents rd_mac_sys_ + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [3:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:4; + /** pvt_cell_select : RO; bitpos: [10:4]; default: 0; + * Represents the selection of Power glitch monitor PVT cell. + */ + uint32_t pvt_cell_select:7; + /** mac_reserved_3 : RO; bitpos: [17:11]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_3:7; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys3_reg_t; /** Type of rd_mac_sys_4 register - * BLOCK1 data register $n. + * Represents rd_mac_sys_ */ typedef union { struct { - /** pkg_version : R; bitpos: [2:0]; default: 0; - * Package version + uint32_t reserved_0:5; + /** pvt_limit : RO; bitpos: [20:5]; default: 0; + * Represents the threshold of power glitch monitor. */ - uint32_t pkg_version:3; - /** reserved_1_131 : R; bitpos: [31:3]; default: 0; - * reserved + uint32_t pvt_limit:16; + /** pvt_glitch_charge_reset : RO; bitpos: [21]; default: 0; + * Represents whether to trigger reset or charge pump when PVT power glitch happened. + * 1:Trigger charge pump. + * 0:Trigger reset */ - uint32_t reserved_1_131:29; + uint32_t pvt_glitch_charge_reset:1; + /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; + * Represents the configuration of glitch mode. + */ + uint32_t pvt_glitch_mode:2; + /** pvt_pump_limit : RO; bitpos: [31:24]; default: 0; + * Represents the configuration voltage monitor limit for charge pump. + */ + uint32_t pvt_pump_limit:8; }; uint32_t val; -} efuse_rd_mac_sys_4_reg_t; +} efuse_rd_mac_sys4_reg_t; /** Type of rd_mac_sys_5 register - * BLOCK1 data register $n. + * Represents rd_mac_sys_ */ typedef union { struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. + /** pump_drv : RO; bitpos: [3:0]; default: 0; + * Use to configure charge pump voltage gain. */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_sys_5_reg_t; - -/** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** optional_unique_id : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data0_reg_t; - -/** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_1:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data1_reg_t; - -/** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_2:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data2_reg_t; - -/** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_3:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data3_reg_t; - -/** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** reserved_2_128 : R; bitpos: [1:0]; default: 0; - * reserved - */ - uint32_t reserved_2_128:2; - /** blk_version_minor : R; bitpos: [4:2]; default: 0; - * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 - */ - uint32_t blk_version_minor:3; - /** blk_version_major : R; bitpos: [6:5]; default: 0; - * BLK_VERSION_MAJOR of BLOCK2 - */ - uint32_t blk_version_major:2; - /** disable_blk_version_major : R; bitpos: [7]; default: 0; - * Disables check of blk version major - */ - uint32_t disable_blk_version_major:1; - /** temp_calib : R; bitpos: [16:8]; default: 0; - * Temperature calibration data - */ - uint32_t temp_calib:9; - /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ave_initcode_atten0:10; - /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ave_initcode_atten1:5; - }; - uint32_t val; -} efuse_rd_sys_part1_data4_reg_t; - -/** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ave_initcode_atten1_1:5; - /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ave_initcode_atten2:10; - /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ave_initcode_atten3:10; - /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten0:7; - }; - uint32_t val; -} efuse_rd_sys_part1_data5_reg_t; - -/** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten0_1:3; - /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten1:10; - /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten2:10; - /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten3:9; - }; - uint32_t val; -} efuse_rd_sys_part1_data6_reg_t; - -/** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_hi_dout_atten3_1:1; - /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ch0_atten0_initcode_diff:4; - /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ch1_atten0_initcode_diff:4; - /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ch2_atten0_initcode_diff:4; - /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ch3_atten0_initcode_diff:4; - /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; - * ADC1 calibration data - */ - uint32_t adc1_ch4_atten0_initcode_diff:4; - /** reserved_2_245 : R; bitpos: [31:21]; default: 0; - * reserved - */ - uint32_t reserved_2_245:11; - }; - uint32_t val; -} efuse_rd_sys_part1_data7_reg_t; - -/** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data0:32; - }; - uint32_t val; -} efuse_rd_usr_data0_reg_t; - -/** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ - uint32_t usr_data1:32; - }; - uint32_t val; -} efuse_rd_usr_data1_reg_t; - -/** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ - uint32_t usr_data2:32; - }; - uint32_t val; -} efuse_rd_usr_data2_reg_t; - -/** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ - uint32_t usr_data3:32; - }; - uint32_t val; -} efuse_rd_usr_data3_reg_t; - -/** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data4:32; - }; - uint32_t val; -} efuse_rd_usr_data4_reg_t; - -/** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + uint32_t pump_drv:4; + /** sys_data_part0_2 : RO; bitpos: [31:4]; default: 0; + * Represents the second 28-bit of zeroth part of system data. */ - uint32_t usr_data5:32; + uint32_t sys_data_part0_2:28; }; uint32_t val; -} efuse_rd_usr_data5_reg_t; +} efuse_rd_mac_sys5_reg_t; -/** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** reserved_3_192 : R; bitpos: [7:0]; default: 0; - * reserved - */ - uint32_t reserved_3_192:8; - /** custom_mac : R; bitpos: [31:8]; default: 0; - * Custom MAC - */ - uint32_t custom_mac:24; - }; - uint32_t val; -} efuse_rd_usr_data6_reg_t; -/** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). +/** Group: block2 registers */ +/** Type of rd_sys_part1_datan register + * Represents rd_sys_part1_datan */ typedef union { struct { - /** custom_mac_1 : R; bitpos: [23:0]; default: 0; - * Custom MAC - */ - uint32_t custom_mac_1:24; - /** reserved_3_248 : R; bitpos: [31:24]; default: 0; - * reserved + /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t reserved_3_248:8; + uint32_t sys_data_part1_n:32; }; uint32_t val; -} efuse_rd_usr_data7_reg_t; +} efuse_rd_sys_part1_datan_reg_t; -/** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ - uint32_t key0_data0:32; - }; - uint32_t val; -} efuse_rd_key0_data0_reg_t; -/** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). +/** Group: block3 registers */ +/** Type of rd_usr_datan register + * Represents rd_usr_datan */ typedef union { struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + /** usr_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). */ - uint32_t key0_data1:32; + uint32_t usr_datan:32; }; uint32_t val; -} efuse_rd_key0_data1_reg_t; +} efuse_rd_usr_datan_reg_t; -/** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ - uint32_t key0_data2:32; - }; - uint32_t val; -} efuse_rd_key0_data2_reg_t; -/** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). +/** Group: block4 registers */ +/** Type of rd_key0_datan register + * Represents rd_key0_datan */ typedef union { struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + /** key0_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. */ - uint32_t key0_data3:32; + uint32_t key0_datan:32; }; uint32_t val; -} efuse_rd_key0_data3_reg_t; +} efuse_rd_key0_datan_reg_t; -/** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ - uint32_t key0_data4:32; - }; - uint32_t val; -} efuse_rd_key0_data4_reg_t; -/** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). +/** Group: block5 registers */ +/** Type of rd_key1_datan register + * Represents rd_key1_datan */ typedef union { struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + /** key1_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. */ - uint32_t key0_data5:32; + uint32_t key1_datan:32; }; uint32_t val; -} efuse_rd_key0_data5_reg_t; +} efuse_rd_key1_datan_reg_t; -/** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; -/** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). +/** Group: block6 registers */ +/** Type of rd_key2_datan register + * Represents rd_key2_datan */ typedef union { struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. + /** key2_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. */ - uint32_t key0_data7:32; + uint32_t key2_datan:32; }; uint32_t val; -} efuse_rd_key0_data7_reg_t; +} efuse_rd_key2_datan_reg_t; -/** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - uint32_t key1_data0:32; - }; - uint32_t val; -} efuse_rd_key1_data0_reg_t; -/** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). +/** Group: block7 registers */ +/** Type of rd_key3_datan register + * Represents rd_key3_datan */ typedef union { struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. + /** key3_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. */ - uint32_t key1_data1:32; + uint32_t key3_datan:32; }; uint32_t val; -} efuse_rd_key1_data1_reg_t; +} efuse_rd_key3_datan_reg_t; -/** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; -/** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). +/** Group: block8 registers */ +/** Type of rd_key4_datan register + * Represents rd_key4_datan */ typedef union { struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. + /** key4_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. */ - uint32_t key1_data3:32; + uint32_t key4_datan:32; }; uint32_t val; -} efuse_rd_key1_data3_reg_t; +} efuse_rd_key4_datan_reg_t; -/** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; -/** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). +/** Group: block9 registers */ +/** Type of rd_key5_datan register + * Represents rd_key5_datan */ typedef union { struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. + /** key5_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. */ - uint32_t key1_data5:32; + uint32_t key5_datan:32; }; uint32_t val; -} efuse_rd_key1_data5_reg_t; +} efuse_rd_key5_datan_reg_t; -/** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; - -/** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - uint32_t key2_data0:32; - }; - uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; - -/** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - uint32_t key3_data0:32; - }; - uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; - -/** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - uint32_t key4_data0:32; - }; - uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; - -/** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - uint32_t key5_data0:32; - }; - uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; - -/** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_0:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_6:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data6_reg_t; -/** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). +/** Group: block10 registers */ +/** Type of rd_sys_part2_datan register + * Represents rd_sys_part2_datan */ typedef union { struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. */ - uint32_t sys_data_part2_7:32; + uint32_t sys_data_part2_n:32; }; uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; +} efuse_rd_sys_part2_datan_reg_t; -/** Group: Report Register */ -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. +/** Group: block0 error report registers */ +/** Type of rd_repeat_data_err0 register + * Represents rd_repeat_data_err */ typedef union { struct { /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ uint32_t rd_dis_err:7; - /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0; - * Reserved. + /** pvt_glitch_en_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_EN */ - uint32_t rpt4_reserved0_err_4:1; + uint32_t pvt_glitch_en_err:1; /** dis_icache_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_ICACHE. + * Represents the programming error of EFUSE_DIS_ICACHE */ uint32_t dis_icache_err:1; /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ uint32_t dis_usb_jtag_err:1; /** powerglitch_en_err : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. + * Represents the programming error of EFUSE_POWERGLITCH_EN */ uint32_t powerglitch_en_err:1; - /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE. - */ - uint32_t dis_usb_serial_jtag_err:1; + uint32_t reserved_11:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ uint32_t dis_force_download_err:1; /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ uint32_t spi_download_mspi_dis_err:1; /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_CAN. + * Represents the programming error of EFUSE_DIS_TWAI */ uint32_t dis_twai_err:1; /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ uint32_t jtag_sel_enable_err:1; /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ uint32_t soft_dis_jtag_err:3; /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ uint32_t dis_pad_jtag_err:1; /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ uint32_t dis_download_manual_encrypt_err:1; - /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; - * Indicates a programming error of USB_DREFH. - */ - uint32_t usb_drefh_err:2; - /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; - * Indicates a programming error of USB_DREFL. - */ - uint32_t usb_drefl_err:2; + uint32_t reserved_21:4; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_EXCHG_PINS. + * Represents the programming error of EFUSE_USB_EXCHG_PINS */ uint32_t usb_exchg_pins_err:1; /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of VDD_SPI_AS_GPIO. + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO */ uint32_t vdd_spi_as_gpio_err:1; /** ecdsa_curve_mode_err : RO; bitpos: [28:27]; default: 0; @@ -1697,313 +731,373 @@ typedef union { * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ uint32_t ecc_force_const_time_err:1; - /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; - * Reserved. + /** xts_dpa_pseudo_level_err : RO; bitpos: [31:30]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL */ - uint32_t rpt4_reserved0_err_0:2; + uint32_t xts_dpa_pseudo_level_err:2; }; uint32_t val; -} efuse_rd_repeat_err0_reg_t; +} efuse_rd_repeat_data_err0_reg_t; -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. +/** Type of rd_repeat_data_err1 register + * Represents rd_repeat_data_err */ typedef union { struct { - /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; - * Reserved. + /** io_ldo_adjust_err : RO; bitpos: [7:0]; default: 0; + * Represents the programming error of EFUSE_IO_LDO_ADJUST */ - uint32_t rpt4_reserved1_err_0:16; + uint32_t io_ldo_adjust_err:8; + /** vdd_spi_ldo_adjust_err : RO; bitpos: [15:8]; default: 0; + * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST + */ + uint32_t vdd_spi_ldo_adjust_err:8; /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. + * Represents the programming error of EFUSE_WDT_DELAY_SEL */ uint32_t wdt_delay_sel_err:2; /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ uint32_t spi_boot_crypt_cnt_err:3; /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ uint32_t secure_boot_key_revoke0_err:1; /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ uint32_t secure_boot_key_revoke1_err:1; /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ uint32_t secure_boot_key_revoke2_err:1; /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ uint32_t key_purpose_0_err:4; /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ uint32_t key_purpose_1_err:4; }; uint32_t val; -} efuse_rd_repeat_err1_reg_t; +} efuse_rd_repeat_data_err1_reg_t; -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. +/** Type of rd_repeat_data_err2 register + * Represents rd_repeat_data_err */ typedef union { struct { /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ uint32_t key_purpose_2_err:4; /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ uint32_t key_purpose_3_err:4; /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ uint32_t key_purpose_4_err:4; /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ uint32_t key_purpose_5_err:4; /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ uint32_t sec_dpa_level_err:2; - /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; - * Reserved. + /** io_ldo_1p8_err : RO; bitpos: [18]; default: 0; + * Represents the programming error of EFUSE_IO_LDO_1P8 */ - uint32_t rpt4_reserved2_err_1:1; + uint32_t io_ldo_1p8_err:1; /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. + * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE */ uint32_t crypt_dpa_enable_err:1; /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ uint32_t secure_boot_en_err:1; /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ uint32_t secure_boot_aggressive_revoke_err:1; - /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; - * Reserved. + /** powerglitch_en1_err : RO; bitpos: [26:22]; default: 0; + * Represents the programming error of EFUSE_POWERGLITCH_EN1 */ - uint32_t rpt4_reserved2_err_0:6; + uint32_t powerglitch_en1_err:5; + /** dcdc_ccm_en_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_DCDC_CCM_EN + */ + uint32_t dcdc_ccm_en_err:1; /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ uint32_t flash_tpuw_err:4; }; uint32_t val; -} efuse_rd_repeat_err2_reg_t; +} efuse_rd_repeat_data_err2_reg_t; -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. +/** Type of rd_repeat_data_err3 register + * Represents rd_repeat_data_err */ typedef union { struct { /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ uint32_t dis_download_mode_err:1; /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ uint32_t dis_direct_boot_err:1; - /** usb_print_err : RO; bitpos: [2]; default: 0; - * Indicates a programming error of UART_PRINT_CHANNEL. + /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ - uint32_t usb_print_err:1; - /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; - * Reserved. + uint32_t dis_usb_serial_jtag_rom_print_err:1; + /** flash_ldo_efuse_sel_err : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_FLASH_LDO_EFUSE_SEL */ - uint32_t rpt4_reserved3_err_5:1; + uint32_t flash_ldo_efuse_sel_err:1; /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ uint32_t dis_usb_serial_jtag_download_mode_err:1; /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ uint32_t enable_security_download_err:1; /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ uint32_t uart_print_control_err:2; /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ uint32_t force_send_resume_err:1; /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ uint32_t secure_version_err:16; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ uint32_t secure_boot_disable_fast_wake_err:1; /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HYS_EN_PAD0. + * Represents the programming error of EFUSE_HYS_EN_PAD0 */ uint32_t hys_en_pad0_err:6; }; uint32_t val; -} efuse_rd_repeat_err3_reg_t; +} efuse_rd_repeat_data_err3_reg_t; -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. +/** Type of rd_repeat_data_err4 register + * Represents rd_repeat_data_err */ typedef union { struct { /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0; - * Indicates a programming error of HYS_EN_PAD1. + * Represents the programming error of EFUSE_HYS_EN_PAD1 */ uint32_t hys_en_pad1_err:22; - /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0; - * Reserved. + /** flash_ldo_power_sel_err : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL */ - uint32_t rpt4_reserved4_err_1:2; - /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4_err_0:8; + uint32_t flash_ldo_power_sel_err:1; + uint32_t reserved_23:9; }; uint32_t val; -} efuse_rd_repeat_err4_reg_t; +} efuse_rd_repeat_data_err4_reg_t; -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. + +/** Group: RS block error report registers */ +/** Type of rd_rs_data_err0 register + * Represents rd_rs_data_err */ typedef union { struct { - /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** rd_mac_sys__err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys_ */ - uint32_t mac_spi_8m_err_num:3; - /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_mac_sys__err_num:3; + /** rd_mac_sys__fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys_ is reliable + * 1: Means that programming rd_mac_sys_ failed and the number of error bytes is over 6. */ - uint32_t mac_spi_8m_fail:1; - /** sys_part1_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_mac_sys__fail:1; + /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ - uint32_t sys_part1_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_sys_part1_data_err_num:3; + /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_sys_part1_data_fail:1; + /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. + uint32_t rd_usr_data_err_num:3; + /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_usr_data_fail:1; + /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. + uint32_t rd_key0_data_err_num:3; + /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key0_data_fail:1; + /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. + uint32_t rd_key1_data_err_num:3; + /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key1_data_fail:1; + /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. + uint32_t rd_key2_data_err_num:3; + /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key2_data_fail:1; + /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. + uint32_t rd_key3_data_err_num:3; + /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key3_data_fail:1; + /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. + uint32_t rd_key4_data_err_num:3; + /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ - uint32_t key4_fail:1; + uint32_t rd_key4_data_fail:1; }; uint32_t val; -} efuse_rd_rs_err0_reg_t; +} efuse_rd_rs_data_err0_reg_t; -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. +/** Type of rd_rs_data_err1 register + * Represents rd_rs_data_err */ typedef union { struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. + uint32_t rd_key5_data_err_num:3; + /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key5_data_fail:1; + /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_sys_part2_data_err_num:3; + /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ - uint32_t sys_part2_fail:1; + uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_8:24; }; uint32_t val; -} efuse_rd_rs_err1_reg_t; +} efuse_rd_rs_data_err1_reg_t; -/** Group: Configuration Register */ +/** Group: EFUSE Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 38806112; + * Represents eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +/** Group: EFUSE Clock Registers */ /** Type of clk register * eFuse clcok configuration register. */ typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -2011,54 +1105,40 @@ typedef union { uint32_t val; } efuse_clk_reg_t; + +/** Group: EFUSE Configure Registers */ /** Type of conf register * eFuse operation mode configuration register */ typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ uint32_t op_code:16; - /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. + /** cfg_ecdsa_l_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key low part output. */ - uint32_t cfg_ecdsa_blk:4; - uint32_t reserved_20:12; + uint32_t cfg_ecdsa_l_blk:4; + /** cfg_ecdsa_h_blk : R/W; bitpos: [23:20]; default: 0; + * Configures which block to use for ECDSA key high part output. + */ + uint32_t cfg_ecdsa_h_blk:4; + uint32_t reserved_24:8; }; uint32_t val; } efuse_conf_reg_t; -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - /** Type of dac_conf register * Controls the eFuse programming voltage. */ typedef union { struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. + /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. */ uint32_t dac_clk_div:8; /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; @@ -2066,11 +1146,14 @@ typedef union { */ uint32_t dac_clk_pad_sel:1; /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -2084,19 +1167,20 @@ typedef union { typedef union { struct { /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. */ uint32_t thr_a:8; /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. */ uint32_t trd:8; /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. */ uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 15; - * Configures the waiting time of reading eFuse memory. + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. */ uint32_t read_init_num:8; }; @@ -2109,15 +1193,18 @@ typedef union { typedef union { struct { /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. */ uint32_t tsup_a:8; /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ uint32_t pwr_on_num:16; /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. */ uint32_t thp_a:8; }; @@ -2130,11 +1217,13 @@ typedef union { typedef union { struct { /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ uint32_t pwr_off_num:16; /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. */ uint32_t tpgm:16; }; @@ -2148,19 +1237,24 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. + * Configures which block number to bypass the Reed-Solomon (RS) correction step. */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. */ uint32_t tpgm_inactive:8; uint32_t reserved_21:11; @@ -2169,66 +1263,79 @@ typedef union { } efuse_wr_tim_conf0_rs_bypass_reg_t; -/** Group: Status Register */ +/** Group: EFUSE Status Registers */ /** Type of status register * eFuse status register. */ typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ uint32_t state:4; - /** otp_load_sw : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - uint32_t otp_load_sw:1; - /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - uint32_t otp_vddq_c_sync2:1; - /** otp_strobe_sw : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - uint32_t otp_strobe_sw:1; - /** otp_csb_sw : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - uint32_t otp_csb_sw:1; - /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - uint32_t otp_pgenb_sw:1; - /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - uint32_t otp_vddq_is_sw:1; + uint32_t reserved_4:6; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. + * Represents the number of block valid bit. */ uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. + /** cur_ecdsa_l_blk : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA key low part output. */ - uint32_t cur_ecdsa_blk:4; - uint32_t reserved_24:8; + uint32_t cur_ecdsa_l_blk:4; + /** cur_ecdsa_h_blk : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA key high part output. + */ + uint32_t cur_ecdsa_h_blk:4; + uint32_t reserved_28:4; }; uint32_t val; } efuse_status_reg_t; -/** Group: Interrupt Register */ +/** Group: EFUSE Command Registers */ +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to send read commands. + * 1: Send + * 0: No effect + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Configures whether to send programming commands. + * 1: Send + * 0: No effect + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + + +/** Group: Interrupt Registers */ /** Type of int_raw register * eFuse raw interrupt register. */ typedef union { struct { /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. + * The raw interrupt status of EFUSE_READ_DONE_INT. */ uint32_t read_done_int_raw:1; /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. + * The raw interrupt status of EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_raw:1; uint32_t reserved_2:30; @@ -2242,11 +1349,11 @@ typedef union { typedef union { struct { /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. + * The masked interrupt status of EFUSE_READ_DONE_INT. */ uint32_t read_done_int_st:1; /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. + * The masked interrupt status of EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_st:1; uint32_t reserved_2:30; @@ -2260,11 +1367,11 @@ typedef union { typedef union { struct { /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. + * Write 1 to enable EFUSE_READ_DONE_INT. */ uint32_t read_done_int_ena:1; /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. + * Write 1 to enable EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_ena:1; uint32_t reserved_2:30; @@ -2278,11 +1385,11 @@ typedef union { typedef union { struct { /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. + * Write 1 to clear EFUSE_READ_DONE_INT. */ uint32_t read_done_int_clr:1; /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. + * Write 1 to clear EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_clr:1; uint32_t reserved_2:30; @@ -2291,126 +1398,39 @@ typedef union { } efuse_int_clr_reg_t; -/** Group: Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35684640; - * Stores eFuse version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_pgm_datan_reg_t pgm_datan[8]; + volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; volatile efuse_rd_wr_dis_reg_t rd_wr_dis; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; - volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; - volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; - volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; - volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; - volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; - volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; - volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; - volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; - volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; - volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; - volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; - volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; - volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; - volatile efuse_rd_usr_data0_reg_t rd_usr_data0; - volatile efuse_rd_usr_data1_reg_t rd_usr_data1; - volatile efuse_rd_usr_data2_reg_t rd_usr_data2; - volatile efuse_rd_usr_data3_reg_t rd_usr_data3; - volatile efuse_rd_usr_data4_reg_t rd_usr_data4; - volatile efuse_rd_usr_data5_reg_t rd_usr_data5; - volatile efuse_rd_usr_data6_reg_t rd_usr_data6; - volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; - uint32_t reserved_190[12]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; + volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; + volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; + volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; + volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; + volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; + volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; + volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; + volatile efuse_date_reg_t date; + uint32_t reserved_19c[11]; volatile efuse_clk_reg_t clk; volatile efuse_conf_reg_t conf; volatile efuse_status_reg_t status; @@ -2424,13 +1444,12 @@ typedef struct { volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; - volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; #ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +_Static_assert(sizeof(efuse_dev_t) == 0x1fc, "Invalid size of efuse_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/io_mux_struct.h b/components/soc/esp32h21/register/soc/io_mux_struct.h index 56daf6fc22..8d7d468505 100644 --- a/components/soc/esp32h21/register/soc/io_mux_struct.h +++ b/components/soc/esp32h21/register/soc/io_mux_struct.h @@ -115,7 +115,7 @@ typedef union { */ typedef union { struct { - /** reg_date : R/W; bitpos: [27:0]; default: 36770416; + /** reg_date : R/W; bitpos: [27:0]; default: 38806096; * Version control register */ uint32_t reg_date:28; @@ -127,7 +127,7 @@ typedef union { typedef struct { volatile io_mux_gpio_reg_t gpio[26]; - uint32_t reserved_074[101]; + uint32_t reserved_068[101]; volatile io_mux_date_reg_t date; } io_mux_dev_t; diff --git a/components/soc/esp32h21/register/soc/lp_aon_reg.h b/components/soc/esp32h21/register/soc/lp_aon_reg.h index 726e391d7e..45dbc2ce19 100644 --- a/components/soc/esp32h21/register/soc/lp_aon_reg.h +++ b/components/soc/esp32h21/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -251,6 +251,13 @@ extern "C" { * need_des */ #define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO_EN (BIT(27)) +#define LP_AON_IO_MUX_PULL_LDO_EN_M (LP_AON_IO_MUX_PULL_LDO_EN_V << LP_AON_IO_MUX_PULL_LDO_EN_S) +#define LP_AON_IO_MUX_PULL_LDO_EN_V 0x00000001U +#define LP_AON_IO_MUX_PULL_LDO_EN_S 27 /** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; * need_des */ @@ -450,7 +457,7 @@ extern "C" { * need_des */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37781648; +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352; * need_des */ #define LP_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/lp_aon_struct.h b/components/soc/esp32h21/register/soc/lp_aon_struct.h index 951d8cfc5d..f1dcc49172 100644 --- a/components/soc/esp32h21/register/soc/lp_aon_struct.h +++ b/components/soc/esp32h21/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -246,7 +246,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:28; + uint32_t reserved_0:27; + /** aon_io_mux_pull_ldo_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t aon_io_mux_pull_ldo_en:1; /** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; * need_des */ @@ -431,7 +435,7 @@ typedef union { */ typedef union { struct { - /** aon_date : R/W; bitpos: [30:0]; default: 37781648; + /** date : R/W; bitpos: [30:0]; default: 38814352; * need_des */ uint32_t aon_date:31; diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_reg.h b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h index a1c3f6dfe5..567537a5d1 100644 --- a/components/soc/esp32h21/register/soc/lp_clkrst_reg.h +++ b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -407,11 +407,96 @@ extern "C" { #define LP_CLKRST_DAC_XTAL32K_V 0x00000007U #define LP_CLKRST_DAC_XTAL32K_S 29 +/** LP_CLKRST_CALI0_REG register + * need_des + */ +#define LP_CLKRST_CALI0_REG (DR_REG_LP_CLKRST_BASE + 0x38) +/** LP_CLKRST_LP_CALI_DIV_CYCLE : R/W; bitpos: [7:0]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_CYCLE 0x000000FFU +#define LP_CLKRST_LP_CALI_DIV_CYCLE_M (LP_CLKRST_LP_CALI_DIV_CYCLE_V << LP_CLKRST_LP_CALI_DIV_CYCLE_S) +#define LP_CLKRST_LP_CALI_DIV_CYCLE_V 0x000000FFU +#define LP_CLKRST_LP_CALI_DIV_CYCLE_S 0 +/** LP_CLKRST_LP_CALI_FULL_CNT_DONE : RO; bitpos: [8]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE (BIT(8)) +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_M (LP_CLKRST_LP_CALI_FULL_CNT_DONE_V << LP_CLKRST_LP_CALI_FULL_CNT_DONE_S) +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_V 0x00000001U +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_S 8 +/** LP_CLKRST_LP_CALI_DIV_CALI_CNT : RO; bitpos: [24:9]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_M (LP_CLKRST_LP_CALI_DIV_CALI_CNT_V << LP_CLKRST_LP_CALI_DIV_CALI_CNT_S) +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_S 9 +/** LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE (BIT(25)) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V 0x00000001U +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S 25 +/** LP_CLKRST_LP_CALI_DIV_NUM : RO; bitpos: [31:26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUM 0x0000003FU +#define LP_CLKRST_LP_CALI_DIV_NUM_M (LP_CLKRST_LP_CALI_DIV_NUM_V << LP_CLKRST_LP_CALI_DIV_NUM_S) +#define LP_CLKRST_LP_CALI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_CALI_DIV_NUM_S 26 + +/** LP_CLKRST_CALI1_REG register + * need_des + */ +#define LP_CLKRST_CALI1_REG (DR_REG_LP_CLKRST_BASE + 0x3c) +/** LP_CLKRST_LP_CALI_DIV_NUMERATOR : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_S) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_S 0 +/** LP_CLKRST_LP_CALI_DIV_DENOMINATOR : RO; bitpos: [31:16]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_M (LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V << LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S) +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S 16 + +/** LP_CLKRST_CALI2_REG register + * need_des + */ +#define LP_CLKRST_CALI2_REG (DR_REG_LP_CLKRST_BASE + 0x40) +/** LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD : R/W; bitpos: [8:0]; default: 255; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD 0x000001FFU +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_M (LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V << LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S) +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V 0x000001FFU +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S 0 +/** LP_CLKRST_LP_CALI_DIV_SLP_VAL : R/W; bitpos: [30:15]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_M (LP_CLKRST_LP_CALI_DIV_SLP_VAL_V << LP_CLKRST_LP_CALI_DIV_SLP_VAL_S) +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_S 15 +/** LP_CLKRST_LP_CALI_DIV_TIMER_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN (BIT(31)) +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_M (LP_CLKRST_LP_CALI_DIV_TIMER_EN_V << LP_CLKRST_LP_CALI_DIV_TIMER_EN_S) +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_V 0x00000001U +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_S 31 + /** LP_CLKRST_DATE_REG register * need_des */ #define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) -/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37782064; +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 38806112; * need_des */ #define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_struct.h b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h index 4e5754ae46..8a323aa2bc 100644 --- a/components/soc/esp32h21/register/soc/lp_clkrst_struct.h +++ b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -323,19 +323,87 @@ typedef union { uint32_t val; } lp_clkrst_xtal32k_reg_t; -/** Type of clkrst_date register +/** Type of cali0 register * need_des */ typedef union { struct { - /** clkrst_clkrst_date : R/W; bitpos: [30:0]; default: 37782064; + /** lp_cali_div_cycle : R/W; bitpos: [7:0]; default: 1; * need_des */ - uint32_t clkrst_clkrst_date:31; - /** clkrst_clk_en : R/W; bitpos: [31]; default: 0; + uint32_t lp_cali_div_cycle:8; + /** lp_cali_full_cnt_done : RO; bitpos: [8]; default: 0; * need_des */ - uint32_t clkrst_clk_en:1; + uint32_t lp_cali_full_cnt_done:1; + /** lp_cali_div_cali_cnt : RO; bitpos: [24:9]; default: 0; + * need_des + */ + uint32_t lp_cali_div_cali_cnt:16; + /** lp_cali_div_numerator_type : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_cali_div_numerator_type:1; + /** lp_cali_div_num : RO; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t lp_cali_div_num:6; + }; + uint32_t val; +} lp_clkrst_cali0_reg_t; + +/** Type of cali1 register + * need_des + */ +typedef union { + struct { + /** lp_cali_div_numerator : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cali_div_numerator:16; + /** lp_cali_div_denominator : RO; bitpos: [31:16]; default: 0; + * need_des + */ + uint32_t lp_cali_div_denominator:16; + }; + uint32_t val; +} lp_clkrst_cali1_reg_t; + +/** Type of cali2 register + * need_des + */ +typedef union { + struct { + /** lp_cali_div_wait_pwr_good : R/W; bitpos: [8:0]; default: 255; + * need_des + */ + uint32_t lp_cali_div_wait_pwr_good:9; + uint32_t reserved_9:6; + /** lp_cali_div_slp_val : R/W; bitpos: [30:15]; default: 1; + * need_des + */ + uint32_t lp_cali_div_slp_val:16; + /** lp_cali_div_timer_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cali_div_timer_en:1; + }; + uint32_t val; +} lp_clkrst_cali2_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 38806112; + * need_des + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; }; uint32_t val; } lp_clkrst_date_reg_t; @@ -354,7 +422,11 @@ typedef struct { volatile lp_clkrst_lpmem_force_reg_t lpmem_force; volatile lp_clkrst_lpperi_reg_t lpperi; volatile lp_clkrst_xtal32k_reg_t xtal32k; - uint32_t reserved_030[243]; + uint32_t reserved_030[2]; + volatile lp_clkrst_cali0_reg_t cali0; + volatile lp_clkrst_cali1_reg_t cali1; + volatile lp_clkrst_cali2_reg_t cali2; + uint32_t reserved_044[238]; volatile lp_clkrst_date_reg_t date; } lp_clkrst_dev_t; diff --git a/components/soc/esp32h21/register/soc/pmu_reg.h b/components/soc/esp32h21/register/soc/pmu_reg.h index 7f6a61fda8..96e1d694b2 100644 --- a/components/soc/esp32h21/register/soc/pmu_reg.h +++ b/components/soc/esp32h21/register/soc/pmu_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -476,7 +476,7 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) -/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; * need_des */ #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU @@ -505,10 +505,13 @@ extern "C" { /** PMU_HP_MODEM_DIG_POWER_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) /** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU #define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S) @@ -516,6 +519,7 @@ extern "C" { #define PMU_HP_MODEM_VDD_FLASH_MODE_S 18 /** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) #define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) @@ -523,6 +527,7 @@ extern "C" { #define PMU_HP_MODEM_HP_MEM_DSLP_S 22 /** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) @@ -530,6 +535,7 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 /** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) @@ -537,6 +543,7 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 /** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28)) #define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S) @@ -544,6 +551,7 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) @@ -551,6 +559,7 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) #define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) @@ -558,6 +567,7 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 /** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) #define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) @@ -566,10 +576,13 @@ extern "C" { /** PMU_HP_MODEM_ICG_HP_FUNC_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) /** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) @@ -578,10 +591,13 @@ extern "C" { /** PMU_HP_MODEM_ICG_HP_APB_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) /** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU #define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) @@ -590,10 +606,13 @@ extern "C" { /** PMU_HP_MODEM_ICG_MODEM_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) /** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) @@ -602,10 +621,13 @@ extern "C" { /** PMU_HP_MODEM_HP_SYS_CNTL_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) /** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) #define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) @@ -613,6 +635,7 @@ extern "C" { #define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 /** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) @@ -620,6 +643,7 @@ extern "C" { #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 /** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) @@ -627,6 +651,7 @@ extern "C" { #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 /** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) @@ -634,6 +659,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 /** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) #define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) @@ -641,6 +667,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 /** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) #define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) @@ -649,10 +676,13 @@ extern "C" { /** PMU_HP_MODEM_HP_CK_POWER_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) /** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) #define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) @@ -660,6 +690,7 @@ extern "C" { #define PMU_HP_MODEM_I2C_ISO_EN_S 26 /** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) #define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) @@ -667,6 +698,7 @@ extern "C" { #define PMU_HP_MODEM_I2C_RETENTION_S 27 /** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) #define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) @@ -674,6 +706,7 @@ extern "C" { #define PMU_HP_MODEM_XPD_BB_I2C_S 28 /** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) #define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) @@ -681,6 +714,7 @@ extern "C" { #define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 /** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) #define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) @@ -689,10 +723,13 @@ extern "C" { /** PMU_HP_MODEM_BIAS_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) /** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9)) #define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S) @@ -700,6 +737,7 @@ extern "C" { #define PMU_HP_MODEM_DCDC_CCM_ENB_S 9 /** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10)) #define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S) @@ -707,6 +745,7 @@ extern "C" { #define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10 /** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U #define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S) @@ -714,6 +753,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11 /** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU #define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S) @@ -721,6 +761,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13 /** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DCM_VSET 0x0000001FU #define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) @@ -728,6 +769,7 @@ extern "C" { #define PMU_HP_MODEM_DCM_VSET_S 17 /** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DCM_MODE 0x00000003U #define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) @@ -735,6 +777,7 @@ extern "C" { #define PMU_HP_MODEM_DCM_MODE_S 22 /** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_TRX (BIT(24)) #define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S) @@ -742,6 +785,7 @@ extern "C" { #define PMU_HP_MODEM_XPD_TRX_S 24 /** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_BIAS (BIT(25)) #define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) @@ -749,6 +793,7 @@ extern "C" { #define PMU_HP_MODEM_XPD_BIAS_S 25 /** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29)) #define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S) @@ -756,6 +801,7 @@ extern "C" { #define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29 /** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_PD_CUR (BIT(30)) #define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) @@ -763,6 +809,7 @@ extern "C" { #define PMU_HP_MODEM_PD_CUR_S 30 /** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) #define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) @@ -771,10 +818,13 @@ extern "C" { /** PMU_HP_MODEM_BACKUP_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) /** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) @@ -782,6 +832,7 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 /** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) @@ -789,6 +840,7 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 /** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) @@ -796,6 +848,7 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 /** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) #define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) @@ -804,10 +857,13 @@ extern "C" { /** PMU_HP_MODEM_BACKUP_CLK_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) /** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) @@ -816,10 +872,13 @@ extern "C" { /** PMU_HP_MODEM_SYSCLK_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) /** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) @@ -827,6 +886,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 /** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) @@ -834,6 +894,7 @@ extern "C" { #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 /** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) @@ -841,6 +902,7 @@ extern "C" { #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 /** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) #define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) @@ -848,6 +910,7 @@ extern "C" { #define PMU_HP_MODEM_ICG_SLP_SEL_S 29 /** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) @@ -856,10 +919,13 @@ extern "C" { /** PMU_HP_MODEM_HP_REGULATOR0_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) /** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0)) #define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) @@ -867,6 +933,7 @@ extern "C" { #define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) @@ -874,6 +941,7 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) @@ -881,6 +949,7 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 /** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) #define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) @@ -888,6 +957,7 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) @@ -895,6 +965,7 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) @@ -902,6 +973,7 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 /** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) @@ -910,10 +982,13 @@ extern "C" { /** PMU_HP_MODEM_HP_REGULATOR1_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) -/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) @@ -922,10 +997,13 @@ extern "C" { /** PMU_HP_MODEM_XTAL_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) /** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_XTALX2 (BIT(30)) #define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S) @@ -933,6 +1011,7 @@ extern "C" { #define PMU_HP_MODEM_XPD_XTALX2_S 30 /** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_MODEM_XPD_XTAL (BIT(31)) #define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) @@ -1376,7 +1455,7 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) -/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; * need_des */ #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU @@ -1450,10 +1529,13 @@ extern "C" { /** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) /** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU #define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) @@ -1542,10 +1624,13 @@ extern "C" { /** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register * need_des + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) /** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; * need_des + * This field is only for internal debugging purposes. Do not use it in applications. */ #define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU #define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) @@ -2666,12 +2751,12 @@ extern "C" { #define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) #define PMU_FLASH1P8_STANDBY_V 0x00000001U #define PMU_FLASH1P8_STANDBY_S 25 -/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; +/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; * need_des */ -#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST 0x0000000FU #define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) -#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000000FU #define PMU_FLASH1P8_POWER_ADJUST_S 26 /** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; * need_des @@ -2755,12 +2840,12 @@ extern "C" { #define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) #define PMU_FLASH1P2_STANDBY_V 0x00000001U #define PMU_FLASH1P2_STANDBY_S 25 -/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; +/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; * need_des */ -#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST 0x0000000FU #define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) -#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000000FU #define PMU_FLASH1P2_POWER_ADJUST_S 26 /** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; * need_des @@ -2898,12 +2983,12 @@ extern "C" { #define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) #define PMU_IO_STANDBY_V 0x00000001U #define PMU_IO_STANDBY_S 25 -/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; +/** PMU_IO_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0; * need_des */ -#define PMU_IO_POWER_ADJUST 0x0000001FU +#define PMU_IO_POWER_ADJUST 0x0000000FU #define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) -#define PMU_IO_POWER_ADJUST_V 0x0000001FU +#define PMU_IO_POWER_ADJUST_V 0x0000000FU #define PMU_IO_POWER_ADJUST_S 26 /** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; * need_des @@ -2936,7 +3021,7 @@ extern "C" { * need_des */ #define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) -/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 384; * need_des */ #define PMU_WAIT_XTL_STABLE 0x0000FFFFU @@ -4136,10 +4221,43 @@ extern "C" { #define PMU_DCDC_RDY_CLR_V 0x00000001U #define PMU_DCDC_RDY_CLR_S 31 +/** PMU_DCM_BOOST_CTRL_REG register + * need_des + */ +#define PMU_DCM_BOOST_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_DCDC_BOOST_CCM_CTRLEN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_DCDC_BOOST_CCM_CTRLEN (BIT(24)) +#define PMU_DCDC_BOOST_CCM_CTRLEN_M (PMU_DCDC_BOOST_CCM_CTRLEN_V << PMU_DCDC_BOOST_CCM_CTRLEN_S) +#define PMU_DCDC_BOOST_CCM_CTRLEN_V 0x00000001U +#define PMU_DCDC_BOOST_CCM_CTRLEN_S 24 +/** PMU_DCDC_BOOST_CCM_ENB : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define PMU_DCDC_BOOST_CCM_ENB (BIT(25)) +#define PMU_DCDC_BOOST_CCM_ENB_M (PMU_DCDC_BOOST_CCM_ENB_V << PMU_DCDC_BOOST_CCM_ENB_S) +#define PMU_DCDC_BOOST_CCM_ENB_V 0x00000001U +#define PMU_DCDC_BOOST_CCM_ENB_S 25 +/** PMU_DCDC_BOOST_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_DCDC_BOOST_EN (BIT(26)) +#define PMU_DCDC_BOOST_EN_M (PMU_DCDC_BOOST_EN_V << PMU_DCDC_BOOST_EN_S) +#define PMU_DCDC_BOOST_EN_V 0x00000001U +#define PMU_DCDC_BOOST_EN_S 26 +/** PMU_DCDC_BOOST_DREG : R/W; bitpos: [31:27]; default: 23; + * need_des + */ +#define PMU_DCDC_BOOST_DREG 0x0000001FU +#define PMU_DCDC_BOOST_DREG_M (PMU_DCDC_BOOST_DREG_V << PMU_DCDC_BOOST_DREG_S) +#define PMU_DCDC_BOOST_DREG_V 0x0000001FU +#define PMU_DCDC_BOOST_DREG_S 27 + /** PMU_TOUCH_PWR_CTRL_REG register * need_des */ -#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) +#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1c0) /** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -4169,11 +4287,30 @@ extern "C" { #define PMU_TOUCH_FORCE_DONE_V 0x00000001U #define PMU_TOUCH_FORCE_DONE_S 31 +/** PMU_BLE_BANDGAP_CTRL_REG register + * need_des + */ +#define PMU_BLE_BANDGAP_CTRL_REG (DR_REG_PMU_BASE + 0x1c4) +/** PMU_EXT_OCODE : R/W; bitpos: [30:23]; default: 120; + * need_des + */ +#define PMU_EXT_OCODE 0x000000FFU +#define PMU_EXT_OCODE_M (PMU_EXT_OCODE_V << PMU_EXT_OCODE_S) +#define PMU_EXT_OCODE_V 0x000000FFU +#define PMU_EXT_OCODE_S 23 +/** PMU_EXT_FORCE_OCODE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_EXT_FORCE_OCODE (BIT(31)) +#define PMU_EXT_FORCE_OCODE_M (PMU_EXT_FORCE_OCODE_V << PMU_EXT_FORCE_OCODE_S) +#define PMU_EXT_FORCE_OCODE_V 0x00000001U +#define PMU_EXT_FORCE_OCODE_S 31 + /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38814336; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/pmu_struct.h b/components/soc/esp32h21/register/soc/pmu_struct.h index 5f77c3317b..b64bdff7d7 100644 --- a/components/soc/esp32h21/register/soc/pmu_struct.h +++ b/components/soc/esp32h21/register/soc/pmu_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -960,6 +960,32 @@ typedef union uint32_t val; } pmu_dcm_ctrl_reg_t; +/** Type of dcm_boost_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** dcdc_boost_ccm_ctrlen : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t dcdc_boost_ccm_ctrlen:1; + /** dcdc_boost_ccm_enb : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t dcdc_boost_ccm_enb:1; + /** dcdc_boost_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t dcdc_boost_en:1; + /** dcdc_boost_dreg : R/W; bitpos: [31:27]; default: 23; + * need_des + */ + uint32_t dcdc_boost_dreg:5; + }; + uint32_t val; +} pmu_dcm_boost_ctrl_reg_t; + typedef union { struct @@ -973,6 +999,24 @@ typedef union volatile uint32_t val; } pmu_touch_pwr_ctrl_reg_t; +/** Type of ble_bandgap_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ext_ocode : R/W; bitpos: [30:23]; default: 120; + * need_des + */ + uint32_t ext_ocode:8; + /** ext_force_ocode : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_force_ocode:1; + }; + uint32_t val; +} pmu_ble_bandgap_ctrl_reg_t; + typedef struct pmu_dev_t { volatile pmu_hp_hw_regmap_t hp_sys[3]; @@ -993,9 +1037,11 @@ typedef struct pmu_dev_t volatile pmu_clk_state2_reg_t clk_state2; volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl; volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; + volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl; - uint32_t reserved[143]; + uint32_t reserved[141]; union { @@ -1013,7 +1059,7 @@ extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_BLE_BANDGAP_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/pmu_struct_mp.h b/components/soc/esp32h21/register/soc/pmu_struct_mp.h new file mode 100644 index 0000000000..5411c6eff1 --- /dev/null +++ b/components/soc/esp32h21/register/soc/pmu_struct_mp.h @@ -0,0 +1,3001 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_active_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_flash_mode:4; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_peri_pd_en:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** hp_active_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t hp_active_dcdc_ccm_enb:1; + /** hp_active_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_dcdc_clear_rdy:1; + /** hp_active_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 3; + * need_des + */ + uint32_t hp_active_dig_pmu_dpcur_bias:2; + /** hp_active_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 6; + * need_des + */ + uint32_t hp_active_dig_pmu_dsfmos:4; + /** hp_active_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t hp_active_dcm_vset:5; + /** hp_active_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t hp_active_dcm_mode:2; + /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_trx:1; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + uint32_t reserved_26:3; + /** hp_active_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_discnnt_dig_rtc:1; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:6; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:5; + /** hp_modem2active_backup_mode : R/W; bitpos: [27:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:5; + uint32_t reserved_28:1; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_active_hp_power_det_bypass:1; + uint32_t reserved_1:3; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtalx2:1; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_sleep_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_flash_mode:4; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_peri_pd_en:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** hp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t hp_sleep_dcdc_ccm_enb:1; + /** hp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcdc_clear_rdy:1; + /** hp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; + * need_des + */ + uint32_t hp_sleep_dig_pmu_dpcur_bias:2; + /** hp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; + * need_des + */ + uint32_t hp_sleep_dig_pmu_dsfmos:4; + /** hp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t hp_sleep_dcm_vset:5; + /** hp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcm_mode:2; + /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_trx:1; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + uint32_t reserved_26:3; + /** hp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_discnnt_dig_rtc:1; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + uint32_t reserved_10:6; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [24:20]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:5; + /** hp_active2sleep_backup_mode : R/W; bitpos: [29:25]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:5; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_power_det_bypass:1; + uint32_t reserved_1:15; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtalx2:1; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** hp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_io_mode:4; + /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_bod_source_sel:1; + /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_vddbat_mode:2; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_lppll:1; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtalx2:1; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** lp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t lp_sleep_vdd_io_mode:4; + /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_bod_source_sel:1; + /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_vddbat_mode:2; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_lppll:1; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** lp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t lp_sleep_dcdc_ccm_enb:1; + /** lp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_sleep_dcdc_clear_rdy:1; + /** lp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; + * need_des + */ + uint32_t lp_sleep_dig_pmu_dpcur_bias:2; + /** lp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; + * need_des + */ + uint32_t lp_sleep_dig_pmu_dsfmos:4; + /** lp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t lp_sleep_dcm_vset:5; + /** lp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t lp_sleep_dcm_mode:2; + uint32_t reserved_24:1; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + uint32_t reserved_26:3; + /** lp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_discnnt_dig_rtc:1; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + /** tie_low_global_xtalx2_icg : WT; bitpos: [7]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtalx2_icg:1; + /** tie_low_xpd_xtalx2 : WT; bitpos: [8]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtalx2:1; + uint32_t reserved_9:14; + /** tie_high_xtalx2 : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t tie_high_xtalx2:1; + /** tie_high_global_xtalx2_icg : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtalx2_icg:1; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** tie_high_dig_pad_slp_sel : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_dig_pad_slp_sel:1; + /** tie_low_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_low_dig_pad_slp_sel:1; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_wait_timer2 register + * need_des + */ +typedef union { + struct { + /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t dg_lp_iso_wait_timer:8; + /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; + * need_des + */ + uint32_t dg_lp_rst_wait_timer:8; + /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; + * need_des + */ + uint32_t dg_hp_iso_wait_timer:8; + /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t dg_hp_rst_wait_timer:8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpperi_reserve register + * need_des + */ +typedef union { + struct { + /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_peri_reset:1; + /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_peri_iso:1; + /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_peri_pu:1; + /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_reset:1; + /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_iso:1; + /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_peri_pd:1; + /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_mask:5; + uint32_t reserved_11:16; + /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpperi_reserve_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_flash1p8_ldo register + * need_des + */ +typedef union { + struct { + /** flash1p8_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t flash1p8_ldo_rdy:1; + /** flash1p8_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_xpd:1; + /** flash1p8_sw_en_thru : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_thru:1; + /** flash1p8_sw_en_standby : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_standby:1; + /** flash1p8_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_power_adjust:1; + /** flash1p8_sw_en_endet : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_endet:1; + uint32_t reserved_6:16; + /** flash1p8_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash1p8_bypass_ldo_rdy:1; + /** flash1p8_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash1p8_xpd:1; + /** flash1p8_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t flash1p8_thru:1; + /** flash1p8_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t flash1p8_standby:1; + /** flash1p8_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t flash1p8_power_adjust:4; + uint32_t reserved_30:1; + /** flash1p8_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash1p8_endet:1; + }; + uint32_t val; +} pmu_power_flash1p8_ldo_reg_t; + +/** Type of power_flash1p2_ldo register + * need_des + */ +typedef union { + struct { + /** flash1p2_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t flash1p2_ldo_rdy:1; + /** flash1p2_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_xpd:1; + /** flash1p2_sw_en_thru : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_thru:1; + /** flash1p2_sw_en_standby : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_standby:1; + /** flash1p2_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_power_adjust:1; + /** flash1p2_sw_en_endet : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_endet:1; + uint32_t reserved_6:16; + /** flash1p2_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash1p2_bypass_ldo_rdy:1; + /** flash1p2_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash1p2_xpd:1; + /** flash1p2_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t flash1p2_thru:1; + /** flash1p2_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t flash1p2_standby:1; + /** flash1p2_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t flash1p2_power_adjust:4; + uint32_t reserved_30:1; + /** flash1p2_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash1p2_endet:1; + }; + uint32_t val; +} pmu_power_flash1p2_ldo_reg_t; + +/** Type of power_vdd_flash register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** flash_ldo_sw_en_tiel : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_en_tiel:1; + /** flash_ldo_power_sel : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash_ldo_power_sel:1; + /** flash_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_en_power_sel:1; + /** flash_ldo_wait_target : R/W; bitpos: [28:25]; default: 15; + * need_des + */ + uint32_t flash_ldo_wait_target:4; + /** flash_ldo_tiel_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t flash_ldo_tiel_en:1; + /** flash_ldo_tiel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t flash_ldo_tiel:1; + /** flash_ldo_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_update:1; + }; + uint32_t val; +} pmu_power_vdd_flash_reg_t; + +/** Type of power_io_ldo register + * need_des + */ +typedef union { + struct { + /** io_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t io_ldo_rdy:1; + /** io_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t io_sw_en_xpd:1; + uint32_t reserved_2:1; + /** io_sw_en_thru : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t io_sw_en_thru:1; + /** io_sw_en_standby : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t io_sw_en_standby:1; + /** io_sw_en_power_adjust : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t io_sw_en_power_adjust:1; + /** io_sw_en_endet : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t io_sw_en_endet:1; + uint32_t reserved_7:15; + /** io_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t io_bypass_ldo_rdy:1; + /** io_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t io_xpd:1; + /** io_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t io_thru:1; + /** io_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t io_standby:1; + /** io_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t io_power_adjust:4; + uint32_t reserved_30:1; + /** io_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_endet:1; + }; + uint32_t val; +} pmu_power_io_ldo_reg_t; + +/** Type of power_vdd_io register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** io_ldo_power_sel : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t io_ldo_power_sel:1; + /** io_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t io_ldo_sw_en_power_sel:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pmu_power_vdd_io_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 384; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** ana_wait_clk_sel : R/W; bitpos: [15]; default: 0; + * need_des + */ + uint32_t ana_wait_clk_sel:1; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** xpd_force_rftx : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t xpd_force_rftx:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_rftx_i2c:1; + /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_i2c:1; + /** xpd_rfpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_rfpll:1; + /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_force_rfpll:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of vddbat_cfg register + * need_des + */ +typedef union { + struct { + /** vddbat_mode : RO; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t vddbat_mode:2; + uint32_t reserved_2:29; + /** vddbat_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vddbat_sw_update:1; + }; + uint32_t val; +} pmu_vddbat_cfg_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 256; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 1; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of dcm_ctrl register + * need_des + */ +typedef union { + struct { + /** dsfmos_use_por : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t dsfmos_use_por:1; + uint32_t reserved_1:21; + /** dcdc_dcm_update : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t dcdc_dcm_update:1; + /** dcdc_pcur_limit : R/W; bitpos: [25:23]; default: 1; + * need_des + */ + uint32_t dcdc_pcur_limit:3; + /** dcdc_bias_cal_done : RO; bitpos: [26]; default: 1; + * need_des + */ + uint32_t dcdc_bias_cal_done:1; + /** dcdc_ccm_sw_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t dcdc_ccm_sw_en:1; + /** dcdc_vcm_enb : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dcdc_vcm_enb:1; + /** dcdc_ccm_rdy : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t dcdc_ccm_rdy:1; + /** dcdc_vcm_rdy : RO; bitpos: [30]; default: 1; + * need_des + */ + uint32_t dcdc_vcm_rdy:1; + /** dcdc_rdy_clr : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dcdc_rdy_clr:1; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +/** Type of dcm_boost_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** dcdc_boost_ccm_ctrlen : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t dcdc_boost_ccm_ctrlen:1; + /** dcdc_boost_ccm_enb : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t dcdc_boost_ccm_enb:1; + /** dcdc_boost_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t dcdc_boost_en:1; + /** dcdc_boost_dreg : R/W; bitpos: [31:27]; default: 23; + * need_des + */ + uint32_t dcdc_boost_dreg:5; + }; + uint32_t val; +} pmu_dcm_boost_ctrl_reg_t; + +/** Type of touch_pwr_ctrl register + * need_des + */ +typedef union { + struct { + /** touch_sleep_cycles : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t touch_sleep_cycles:16; + uint32_t reserved_16:5; + /** touch_wait_cycles : R/W; bitpos: [29:21]; default: 0; + * need_des + */ + uint32_t touch_wait_cycles:9; + /** touch_sleep_timer_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t touch_sleep_timer_en:1; + /** touch_force_done : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t touch_force_done:1; + }; + uint32_t val; +} pmu_touch_pwr_ctrl_reg_t; + +/** Type of ble_bandgap_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ext_ocode : R/W; bitpos: [30:23]; default: 120; + * need_des + */ + uint32_t ext_ocode:8; + /** ext_force_ocode : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_force_ocode:1; + }; + uint32_t val; +} pmu_ble_bandgap_ctrl_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 38814336; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 1; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + uint32_t reserved_034[13]; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + uint32_t reserved_0a4; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + uint32_t reserved_0b0; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_wait_timer2_reg_t power_wait_timer2; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_flash1p8_ldo_reg_t power_flash1p8_ldo; + volatile pmu_power_flash1p2_ldo_reg_t power_flash1p2_ldo; + volatile pmu_power_vdd_flash_reg_t power_vdd_flash; + volatile pmu_power_io_ldo_reg_t power_io_ldo; + volatile pmu_power_vdd_io_reg_t power_vdd_io; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_vddbat_cfg_reg_t vddbat_cfg; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl; + volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; + volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl; + uint32_t reserved_1c8[141]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/spi_flash/esp32h21/Kconfig.flash_freq b/components/spi_flash/esp32h21/Kconfig.flash_freq index c100eede1d..4109c78217 100644 --- a/components/spi_flash/esp32h21/Kconfig.flash_freq +++ b/components/spi_flash/esp32h21/Kconfig.flash_freq @@ -6,6 +6,7 @@ choice ESPTOOLPY_FLASHFREQ bool "48 MHz" config ESPTOOLPY_FLASHFREQ_32M bool "32 MHz" + depends on IDF_ENV_FPGA config ESPTOOLPY_FLASHFREQ_24M bool "24 MHz" endchoice diff --git a/components/spi_flash/esp32h4/Kconfig.flash_freq b/components/spi_flash/esp32h4/Kconfig.flash_freq index c100eede1d..4109c78217 100644 --- a/components/spi_flash/esp32h4/Kconfig.flash_freq +++ b/components/spi_flash/esp32h4/Kconfig.flash_freq @@ -6,6 +6,7 @@ choice ESPTOOLPY_FLASHFREQ bool "48 MHz" config ESPTOOLPY_FLASHFREQ_32M bool "32 MHz" + depends on IDF_ENV_FPGA config ESPTOOLPY_FLASHFREQ_24M bool "24 MHz" endchoice diff --git a/tools/ci/check_public_headers.py b/tools/ci/check_public_headers.py index 72b4fefdb9..c47dd65e4a 100644 --- a/tools/ci/check_public_headers.py +++ b/tools/ci/check_public_headers.py @@ -15,10 +15,6 @@ import subprocess import tempfile from threading import Event from threading import Thread -from typing import List -from typing import Optional -from typing import Set -from typing import Tuple from typing import Union @@ -38,7 +34,7 @@ class HeaderFailedBuildError(HeaderFailed): self.compiler = compiler def __str__(self) -> str: - return 'Header Build Error with {}'.format(self.compiler) + return f'Header Build Error with {self.compiler}' class HeaderFailedPreprocessError(HeaderFailed): @@ -63,17 +59,17 @@ class HeaderFailedContainsStaticAssert(HeaderFailed): # Creates a temp file and returns both output as a string and a file name # -def exec_cmd_to_temp_file(what: List, suffix: str = '') -> Tuple[int, str, str, str, str]: +def exec_cmd_to_temp_file(what: list, suffix: str = '') -> tuple[int, str, str, str, str]: out_file = tempfile.NamedTemporaryFile(suffix=suffix, delete=False) rc, out, err, cmd = exec_cmd(what, out_file) - with open(out_file.name, 'r', encoding='utf-8') as f: + with open(out_file.name, encoding='utf-8') as f: out = f.read() return rc, out, err, out_file.name, cmd def exec_cmd( - what: List, out_file: Union['tempfile._TemporaryFileWrapper[bytes]', int] = subprocess.PIPE -) -> Tuple[int, str, str, str]: + what: list, out_file: Union['tempfile._TemporaryFileWrapper[bytes]', int] = subprocess.PIPE +) -> tuple[int, str, str, str]: p = subprocess.Popen(what, stdin=subprocess.PIPE, stdout=out_file, stderr=subprocess.PIPE) output_b, err_b = p.communicate() rc = p.returncode @@ -87,9 +83,9 @@ class PublicHeaderChecker: if self.verbose or debug: print(message) - def __init__(self, verbose: bool = False, jobs: int = 1, prefix: Optional[str] = None) -> None: - self.gcc = '{}gcc'.format(prefix) - self.gpp = '{}g++'.format(prefix) + def __init__(self, verbose: bool = False, jobs: int = 1, prefix: str | None = None) -> None: + self.gcc = f'{prefix}gcc' + self.gpp = f'{prefix}g++' self.verbose = verbose self.jobs = jobs self.prefix = prefix @@ -100,10 +96,13 @@ class PublicHeaderChecker: self.static_assert = re.compile(r'(_Static_assert|static_assert)') self.defines_assert = re.compile(r'#define[ \t]+ESP_STATIC_ASSERT') self.auto_soc_header = re.compile( - r'components/soc/esp[a-z0-9_]+(?:/\w+)?/(include|register)/(soc|modem|hw_ver\d+/soc)/[a-zA-Z0-9_]+.h' + r'components/soc/esp[a-z0-9_]+(?:/\w+)?/' + r'(include|register)/' + r'(soc|modem|hw_ver(?:\d+|_[A-Za-z0-9]+)/soc)/' + r'[a-zA-Z0-9_]+\.h$' ) self.assembly_nocode = r'^\s*(\.file|\.text|\.ident|\.option|\.attribute|(\.section)?).*$' - self.check_threads: List[Thread] = [] + self.check_threads: list[Thread] = [] self.stdc = '--std=c99' self.stdcpp = '--std=c++17' @@ -134,14 +133,14 @@ class PublicHeaderChecker: try: self.check_one_header(task, num) except HeaderFailed as e: - self.failed_queue.put('{}: Failed! {}'.format(task, e)) + self.failed_queue.put(f'{task}: Failed! {e}') except Exception as e: # Makes sure any unexpected exceptions causes the program to terminate - self.failed_queue.put('{}: Failed! {}'.format(task, e)) + self.failed_queue.put(f'{task}: Failed! {e}') self.terminate.set() raise - def get_failed(self) -> List: + def get_failed(self) -> list: return list(self.failed_queue.queue) def join(self) -> None: @@ -166,9 +165,9 @@ class PublicHeaderChecker: if not re.sub(self.assembly_nocode, '', out, flags=re.M).isspace(): raise HeaderFailedContainsCode() return # Header OK: produced zero code - self.log('{}: FAILED: compilation issue'.format(header), True) + self.log(f'{header}: FAILED: compilation issue', True) self.log(err, True) - self.log('\nCompilation command failed:\n{}\n'.format(cmd), True) + self.log(f'\nCompilation command failed:\n{cmd}\n', True) raise HeaderFailedBuildError(compiler) # Checks one header using preprocessing and parsing @@ -214,7 +213,7 @@ class PublicHeaderChecker: # Normalize the potential A//B, A/./B, A/../A, from the name normalized_path = os.path.normpath(header) if grp and not re.search(self.defines_assert, out) and not re.search(self.auto_soc_header, normalized_path): - self.log('{}: FAILED: contains {}. Please use ESP_STATIC_ASSERT'.format(header, grp.group(1)), True) + self.log(f'{header}: FAILED: contains {grp.group(1)}. Please use ESP_STATIC_ASSERT', True) raise HeaderFailedContainsStaticAssert() try: # compile with C++, check for errors, outputs for a temp file @@ -222,32 +221,32 @@ class PublicHeaderChecker: if rc != 0: if re.search(self.error_macro, err): if re.search(self.error_orphan_kconfig, err): - self.log('{}: CONFIG_VARS_USED_WHILE_SDKCONFIG_NOT_INCLUDED'.format(header), True) + self.log(f'{header}: CONFIG_VARS_USED_WHILE_SDKCONFIG_NOT_INCLUDED', True) raise HeaderFailedSdkconfig() - self.log('{}: Error directive failure: OK'.format(header)) + self.log(f'{header}: Error directive failure: OK') return - self.log('{}: FAILED: compilation issue'.format(header), True) + self.log(f'{header}: FAILED: compilation issue', True) self.log(err, True) - self.log('\nCompilation command failed:\n{}\n'.format(cmd), True) + self.log(f'\nCompilation command failed:\n{cmd}\n', True) raise HeaderFailedPreprocessError() # compile with C compiler, outputs to another temp file rc, _, err, c_out_file, _ = exec_cmd_to_temp_file([self.gcc, self.stdc] + all_compilation_flags) if rc != 0: - self.log('{} FAILED: compilation in C (while C++ compilation passes)'.format(header)) + self.log(f'{header} FAILED: compilation in C (while C++ compilation passes)') raise HeaderFailedPreprocessError() # diff the two outputs rc, diff, err, _ = exec_cmd(['diff', c_out_file, cpp_out_file]) if not diff or diff.isspace(): if not cpp_out or cpp_out.isspace(): - self.log('{} The same, but empty out - OK'.format(header)) + self.log(f'{header} The same, but empty out - OK') return - self.log('{} FAILED C and C++ preprocessor output is the same!'.format(header), True) + self.log(f'{header} FAILED C and C++ preprocessor output is the same!', True) raise HeaderFailedCppGuardMissing() if re.search(self.extern_c, diff): - self.log('{} extern C present in the diff'.format(header)) + self.log(f'{header} extern C present in the diff') # now check the extern "C" is really in the unprocessed header if re.search(self.extern_c, out): - self.log('{} extern C present in the actual header, too - OK'.format(header)) + self.log(f'{header} extern C present in the actual header, too - OK') return # at this point we know that the header itself is missing extern-C, so we need to check if it # contains an actual *code* we remove all preprocessor's directive to check if there's any code @@ -255,19 +254,17 @@ class PublicHeaderChecker: macros = re.compile(r'(?m)^\s*#(?:.*\\\r?\n)*.*$') # Matches multiline preprocessor directives without_macros = macros.sub('', out) if without_macros.isspace(): - self.log("{} Header doesn't need extern-C, it's all just macros - OK".format(header)) + self.log(f"{header} Header doesn't need extern-C, it's all just macros - OK") return # at this point we know that the header is not only composed of macro definitions, but could # just contain some "harmless" macro calls let's remove them and check again macros_calls = r'(.*?)ESP_STATIC_ASSERT[^;]+;' # static assert macro only, we could add more if needed without_macros = re.sub(macros_calls, '', without_macros, flags=re.DOTALL) if without_macros.isspace(): - self.log( - "{} Header doesn't need extern-C, it's all macros definitions and calls - OK".format(header) - ) + self.log(f"{header} Header doesn't need extern-C, it's all macros definitions and calls - OK") return - self.log('{} Different but no extern C - FAILED'.format(header), True) + self.log(f'{header} Different but no extern C - FAILED', True) raise HeaderFailedCppGuardMissing() finally: os.unlink(cpp_out_file) @@ -277,9 +274,7 @@ class PublicHeaderChecker: pass # Get compilation data from an example to list all public header files - def list_public_headers( - self, ignore_dirs: List, ignore_files: Union[List, Set], only_dir: Optional[str] = None - ) -> None: + def list_public_headers(self, ignore_dirs: list, ignore_files: list | set, only_dir: str | None = None) -> None: idf_path = os.getenv('IDF_PATH') if idf_path is None: raise RuntimeError("Environment variable 'IDF_PATH' wasn't set.") @@ -294,13 +289,13 @@ class PublicHeaderChecker: ['idf.py', '-B', build_dir, f'-DSDKCONFIG={sdkconfig}', '-DCOMPONENTS=', 'reconfigure'], cwd=project_dir ) - def get_std(json: List, extension: str) -> str: + def get_std(json: list, extension: str) -> str: # compile commands for the files with specified extension, containing C(XX) standard flag command = [c for c in j if c['file'].endswith('.' + extension) and '-std=' in c['command']][0] return str([s for s in command['command'].split() if 'std=' in s][0]) # grab the std flag build_commands_json = os.path.join(build_dir, 'compile_commands.json') - with open(build_commands_json, 'r', encoding='utf-8') as f: + with open(build_commands_json, encoding='utf-8') as f: j = json.load(f) self.stdc = get_std(j, 'c') self.stdcpp = get_std(j, 'cpp') @@ -337,10 +332,10 @@ class PublicHeaderChecker: if only_dir is not None and not os.path.relpath(d, idf_path).startswith( os.path.relpath(only_dir, idf_path) ): - self.log('{} - directory ignored (not in "{}")'.format(d, only_dir)) + self.log(f'{d} - directory ignored (not in "{only_dir}")') continue if os.path.relpath(d, idf_path).startswith(tuple(ignore_dirs)): - self.log('{} - directory ignored'.format(d)) + self.log(f'{d} - directory ignored') continue for root, dirnames, filenames in os.walk(d): for filename in fnmatch.filter(filenames, '*.h'): @@ -352,10 +347,10 @@ class PublicHeaderChecker: for file_name in all_include_files: rel_path_file = os.path.relpath(file_name, idf_path) if any([os.path.commonprefix([d, rel_path_file]) == d for d in ignore_dirs]): - self.log('{} - file ignored (inside ignore dir)'.format(file_name)) + self.log(f'{file_name} - file ignored (inside ignore dir)') continue if rel_path_file in ignore_files: - self.log('{} - file ignored'.format(file_name)) + self.log(f'{file_name} - file ignored') continue files_to_check.append(file_name) # removes duplicates and places headers to a work queue @@ -410,7 +405,7 @@ def check_all_headers() -> None: # process excluded files and dirs exclude_file = os.path.join(os.path.dirname(__file__), args.exclude_file) - with open(exclude_file, 'r', encoding='utf-8') as f: + with open(exclude_file, encoding='utf-8') as f: lines = [line.rstrip() for line in f] ignore_files = [] ignore_dirs = []