ci: add more build test for esp32-s3

components/bootloader/Kconfig.projbuild

@@ -255,8 +255,8 @@ menu "Bootloader config"
         depends on BOOTLOADER_APP_ANTI_ROLLBACK
         range 1 32 if IDF_TARGET_ESP32
         default 32 if IDF_TARGET_ESP32
-        range 1 16 if IDF_TARGET_ESP32S2
+        range 1 16
-        default 16 if IDF_TARGET_ESP32S2
+        default 16
         help
             The size of the efuse secure version field.
             Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.

components/bootloader/subproject/main/ld/esp32s3/bootloader.ld

@@ -25,15 +25,17 @@ SECTIONS
      *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
     *liblog.a:(.literal .text .literal.* .text.*)
     *libgcc.a:(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_clock.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
     *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
@@ -43,6 +45,8 @@ SECTIONS
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
     *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libsoc.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/bootloader_support/src/bootloader_random_esp32s3.c

@@ -20,6 +20,9 @@ static const char *TAG = "bootloader_random";
 void bootloader_random_enable(void)
 {
     ESP_LOGW(TAG, "RNG for ESP32-S3 not currently supported"); // IDF-1878
+    // Don't forget to remove the following line
+    // *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    // In the bootloader.ld when RNG support is ready for ESP32-S3
 }
 
 void bootloader_random_disable(void)

components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld

@@ -7,6 +7,7 @@ PROVIDE ( g_ticks_per_us_pro = g_ticks_per_us );
 PROVIDE ( g_rom_flashchip = SPI_flashchip_data );
 PROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data );
 PROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg );
+PROVIDE ( esp_rom_spiflash_read_status = SPI_read_status );
 PROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high );
 PROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read );
 PROVIDE ( esp_rom_spiflash_write = SPIWrite );

components/esp_system/test/test_intr_alloc.c

@@ -19,6 +19,8 @@
 #include "driver/timer.h"
 #include "sdkconfig.h"
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+
 #define TIMER_DIVIDER   16               /*!< Hardware timer clock divider */
 #define TIMER_SCALE    (TIMER_BASE_CLK / TIMER_DIVIDER)  /*!< used to calculate counter value */
 #define TIMER_INTERVAL0_SEC   (3.4179)   /*!< test interval for timer 0 */
@@ -354,3 +356,4 @@ TEST_CASE("alloc and free isr handle on different core", "[intr_alloc]")
 }
 
 #endif
+#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)

components/esp_system/test/test_sleep.c

@@ -31,6 +31,7 @@
 #include "esp32s3/rom/rtc.h"
 #endif
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 
 #define ESP_EXT0_WAKEUP_LEVEL_LOW 0
 #define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
@@ -527,3 +528,5 @@ static void check_time_deepsleep(void)
 }
 
 TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep);
+
+#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)

tools/ci/config/build.yml

@@ -201,6 +201,12 @@ build_test_apps_esp32s2:
   variables:
     IDF_TARGET: esp32s2
 
+build_test_apps_esp32s3:
+  extends: .build_test_apps
+  parallel: 8
+  variables:
+    IDF_TARGET: esp32s3
+
 .build_component_ut:
   extends: .build_test_apps
   variables:

tools/test_apps/build_system/rsource_test/main/port/esp32s3/Kconfig

@@ -0,0 +1 @@
+rsource "../../../Kconfig.extra"

tools/test_apps/protocols/esp_netif/build_config/README.md

@@ -1,3 +1,6 @@
+| Supported Targets | ESP32 | ESP32-S2 |
+| ----------------- | ----- | -------- |
+
 # Build only test for C++/C configuration
 
 This test application aims to exercise different configuration options using standard espressif initialization pattern:

tools/test_apps/protocols/mqtt/build_test/README.md

@@ -1,3 +1,6 @@
+| Supported Targets | ESP32 | ESP32-S2 |
+| ----------------- | ----- | -------- |
+
 # Build only test for C++
 
 This test app ensures that calling all mqtt-client API could be called from C++ 

tools/test_apps/protocols/mqtt/publish_connect_test/README.md

@@ -1,3 +1,6 @@
+| Supported Targets | ESP32 | ESP32-S2 |
+| ----------------- | ----- | -------- |
+
 # ESP-MQTT advanced publish and connect test project
 
 Main purpose of this application is to test the MQTT library to correctly publish and receive messages (of different size and sequences) over different transports. 

tools/unit-test-app/configs/default_s3

@@ -0,0 +1,3 @@
+# This config is split between targets since different component needs to be included
+CONFIG_IDF_TARGET="esp32s3"
+TEST_COMPONENTS=freertos esp32s3 esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs

tools/unit-test-app/configs/release_s3

@@ -0,0 +1,5 @@
+CONFIG_IDF_TARGET="esp32s3"
+TEST_COMPONENTS=freertos esp32s3 esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y