esp32c3: format and clean up interrupt and os port code

components/esp_common/src/int_wdt.c

@@ -1,9 +1,9 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -12,14 +12,14 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "sdkconfig.h"
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdbool.h>
+#include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
-#include <esp_types.h>
+#include "esp_types.h"
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
 #include "esp_attr.h"
@@ -29,6 +29,7 @@
 #include "driver/periph_ctrl.h"
 #include "esp_int_wdt.h"
 #include "esp_private/system_internal.h"
+#include "hal/cpu_hal.h"
 #include "hal/timer_types.h"
 #include "hal/wdt_hal.h"
 #include "hal/interrupt_controller_hal.h"
@@ -45,7 +46,7 @@ static wdt_hal_context_t iwdt_context;
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
 /*
- * This parameter is indicates the response time of Interrupt watchdog to
+ * This parameter is used to indicate the response time of Interrupt watchdog to
  * identify the live lock.
  */
 #define IWDT_LIVELOCK_TIMEOUT_MS    (20)
@@ -58,8 +59,9 @@ extern uint32_t _l4_intr_livelock_counter, _l4_intr_livelock_max;
 //Not static; the ISR assembly checks this.
 bool int_wdt_app_cpu_ticked = false;
 
-static void IRAM_ATTR tick_hook(void) {
+static void IRAM_ATTR tick_hook(void)
-    if (xPortGetCoreID()!=0) {
+{
+    if (cpu_hal_get_core_id() != 0) {
         int_wdt_app_cpu_ticked = true;
     } else {
         //Only feed wdt if app cpu also ticked.
@@ -82,9 +84,10 @@ static void IRAM_ATTR tick_hook(void) {
     }
 }
 #else
-static void IRAM_ATTR tick_hook(void) {
+static void IRAM_ATTR tick_hook(void)
+{
 #if !CONFIG_FREERTOS_UNICORE
-    if (xPortGetCoreID()!=0) {
+    if (cpu_hal_get_core_id() != 0) {
         return;
     }
 #endif
@@ -99,15 +102,13 @@ static void IRAM_ATTR tick_hook(void) {
 #endif
 
 
-void esp_int_wdt_init(void) {
+void esp_int_wdt_init(void)
+{
     periph_module_enable(PERIPH_TIMG1_MODULE);
     //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
     //it to their actual value.
     wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
     wdt_hal_write_protect_disable(&iwdt_context);
-    //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
-    //it to their actual value.
-
     //1st stage timeout: interrupt
     wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
     //2nd stage timeout: reset system
@@ -120,16 +121,13 @@ void esp_int_wdt_init(void) {
 void esp_int_wdt_cpu_init(void)
 {
     assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
-    esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
+    esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
     ESP_INTR_DISABLE(WDT_INT_NUM);
-    intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
+    intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
 
-    /* Set the type and priority to cache error interrupts, if supported. */
+    /* Set the type and priority to watch dog interrupts */
-#if SOC_INTERRUPT_TYPE_CAN_SET
+#if SOC_CPU_HAS_FLEXIBLE_INTC
     interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
-#endif
-
-#if SOC_INTERRUPT_LEVEL_CAN_SET
     interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 #endif
 
@@ -146,9 +144,9 @@ void esp_int_wdt_cpu_init(void)
     }
 #endif
 
-    //We do not register a handler for the interrupt because it is interrupt level 4 which
+    // We do not register a handler for the watchdog interrupt because:
-    //is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
+    // 1. Interrupt level 4 on Xtensa architecture is not servicable from C
-    //this interrupt.
+    // 2. Instead, we set the entry of watchdog interrupt to the panic handler, see riscv/vector.S and xtensa_vectors.S
     ESP_INTR_ENABLE(WDT_INT_NUM);
 }
 

components/esp_system/include/esp_intr_alloc.h

@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,8 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#ifndef __ESP_INTR_ALLOC_H__
+#pragma once
-#define __ESP_INTR_ALLOC_H__
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -306,11 +305,18 @@ void esp_intr_enable_source(int inum);
  */
 void esp_intr_disable_source(int inum);
 
+/**
+ * @brief Get the lowest interrupt level from the flags
+ * @param flags The same flags that pass to `esp_intr_alloc_intrstatus` API
+ */
+static inline int esp_intr_flags_to_level(int flags)
+{
+    return __builtin_ffs((flags & ESP_INTR_FLAG_LEVELMASK) >> 1) + 1;
+}
+
 /**@}*/
 
 
 #ifdef __cplusplus
 }
 #endif
-
-#endif

components/esp_system/intr_alloc.c

@@ -1,9 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -12,7 +12,6 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "sdkconfig.h"
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -21,6 +20,7 @@
 #include <esp_types.h>
 #include <limits.h>
 #include <assert.h>
+#include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_err.h"
@@ -49,6 +49,7 @@ output within a critical region, which can lead to weird effects like e.g. the i
 being triggered, that is why it is separate from the normal LOG* scheme.
 */
 // #define DEBUG_INT_ALLOC_DECISIONS
+
 #ifdef DEBUG_INT_ALLOC_DECISIONS
 # define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
 #else
@@ -246,7 +247,8 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
     }
     //check if edge/level type matches what we want
     if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
-        (((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {        ALCHLOG("....Unusable: incompatible trigger type");
+        (((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {
+        ALCHLOG("....Unusable: incompatible trigger type");
         return false;
     }
 #endif
@@ -587,8 +589,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
 
 #ifdef SOC_CPU_HAS_FLEXIBLE_INTC
     //Extract the level from the interrupt passed flags
-    int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1;
+    int level = esp_intr_flags_to_level(flags);
-
     interrupt_controller_hal_set_int_level(intr, level);
 
     if (flags & ESP_INTR_FLAG_EDGE) {

components/freertos/port/riscv/port.c

@@ -124,7 +124,6 @@ void vPortEnterCritical(void)
     uxCriticalNesting++;
 
     if (uxCriticalNesting == 1) {
-        //portDISABLE_INTERRUPTS();
         uxSavedInterruptState = state;
     }
 }
@@ -135,7 +134,6 @@ void vPortExitCritical(void)
         uxCriticalNesting--;
         if (uxCriticalNesting == 0) {
             portEXIT_CRITICAL_NESTED(uxSavedInterruptState);
-            //portENABLE_INTERRUPTS();
         }
     }
 }
@@ -169,8 +167,7 @@ void prvTaskExitError(void)
     defined, then stop here so application writers can catch the error. */
     configASSERT(uxCriticalNesting == ~0UL);
     portDISABLE_INTERRUPTS();
-    for (;;)
+    abort();
-        ;
 }
 
 /* Clear current interrupt mask and set given mask */

components/soc/esp32c3/include/soc/soc_caps.h

@@ -43,7 +43,6 @@
 #include "rmt_caps.h"
 #include "spi_caps.h"
 #include "uart_caps.h"
-#include "int_caps.h"
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
 #define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP32-C3 */