espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-01 19:54:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

feat(regi2c): add regi2c support for esp32h21

Browse Source
This commit is contained in:
Song Ruo Jing
2025-02-27 20:17:09 +08:00
parent 79d503f267
commit 9ef152c220
21 changed files with 356 additions and 311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
View File

@@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
regi2c_ctrl_ll_master_configure_clock();
}

1
components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
View File

@@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
regi2c_ctrl_ll_master_configure_clock();
}

4
components/bootloader_support/src/esp32h21/bootloader_esp32h21.c
View File

@@ -89,8 +89,8 @@ static inline void bootloader_hardware_init(void)
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
//TODO: [ESP32H21] IDF-11550, regi2c atomic clock
regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-11548 Remove this?
regi2c_ctrl_ll_master_configure_clock();
}

120
components/esp_rom/patches/esp_rom_regi2c_esp32h21.c
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,73 +8,16 @@
#include "soc/i2c_ana_mst_reg.h"
#include "hal/regi2c_ctrl_ll.h"
/**
* BB - 0x67 - BIT0
* TXRF - 0x6B - BIT1
* SDM - 0x63 - BIT2
* PLL - 0x62 - BIT3
* BIAS - 0x6A - BIT4
* BBPLL - 0x66 - BIT5
* ULP - 0x61 - BIT6
* SAR - 0x69 - BIT7
* PMU - 0x6d - BIT8
*/
#define REGI2C_BIAS_MST_SEL (BIT(8))
#define REGI2C_BBPLL_MST_SEL (BIT(9))
#define REGI2C_ULP_CAL_MST_SEL (BIT(10))
#define REGI2C_SAR_I2C_MST_SEL (BIT(11))
#define REGI2C_DIG_REG_MST_SEL (BIT(12))
#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M)
#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M)
#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M)
#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M)
#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M)
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
#define REGI2C_RTC_BUSY (BIT(25))
#define REGI2C_RTC_BUSY_M (BIT(25))
#define REGI2C_RTC_BUSY_V 0x1
#define REGI2C_RTC_BUSY_S 25
#define REGI2C_RTC_WR_CNTL (BIT(24))
#define REGI2C_RTC_WR_CNTL_M (BIT(24))
#define REGI2C_RTC_WR_CNTL_V 0x1
#define REGI2C_RTC_WR_CNTL_S 24
#define REGI2C_RTC_DATA 0x000000FF
#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
#define REGI2C_RTC_DATA_V 0xFF
#define REGI2C_RTC_DATA_S 16
#define REGI2C_RTC_ADDR 0x000000FF
#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
#define REGI2C_RTC_ADDR_V 0xFF
#define REGI2C_RTC_ADDR_S 8
#define REGI2C_RTC_SLAVE_ID 0x000000FF
#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
#define REGI2C_RTC_SLAVE_ID_V 0xFF
#define REGI2C_RTC_SLAVE_ID_S 0
/* SLAVE */
#define REGI2C_BBPLL (0x66)
#define REGI2C_BBPLL_HOSTID 0
#define REGI2C_BIAS (0x6a)
#define REGI2C_BIAS_HOSTID 0
#define REGI2C_PMU (0x6d)
#define REGI2C_PMU_HOSTID 0
#define REGI2C_ULP_CAL (0x61)
#define REGI2C_ULP_CAL_HOSTID 0
#define REGI2C_SAR_I2C (0x69)
#define REGI2C_SAR_I2C_HOSTID 0
#define REGI2C_BBPLL 0x66 // regi2c_bbpll.h
#define REGI2C_BBTOP 0x67
#define REGI2C_DCDC 0x6D // regi2c_pmu.h
#define REGI2C_PERIF 0x69 // regi2c_saradc.h
#define REGI2C_RFPLL 0x62
#define REGI2C_SDM 0x63
#define REGI2C_TXTOP 0x6B
#define REGI2C_ULP 0x61 // regi2c_lp_bias.h
#define REGI2C_BIAS 0x6A // regi2c_bias.h
/* SLAVE END */
@@ -86,32 +29,43 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
{
uint32_t i2c_sel = 0;
regi2c_ctrl_ll_master_enable_clock(true);
assert(regi2c_ctrl_ll_master_is_clock_enabled());
/* Before config I2C register, enable corresponding slave. */
switch (block) {
case REGI2C_BBPLL:
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_BIAS :
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
case REGI2C_BBTOP:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_PMU:
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
case REGI2C_DCDC:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PMU_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PMU_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_ULP_CAL:
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
case REGI2C_PERIF:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_SAR_I2C:
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
case REGI2C_RFPLL:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_SDM:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_TXTOP:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_TXTOP_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_TXTOP_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
case REGI2C_ULP:
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M);
break;
}
return (uint8_t)(i2c_sel ? 0 : 1);
}

2
components/hal/esp32/include/hal/regi2c_ctrl_ll.h
View File

@@ -50,7 +50,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h
View File

@@ -69,7 +69,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h
View File

@@ -49,7 +49,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
View File

@@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
View File

@@ -108,7 +108,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
View File

@@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
View File

@@ -104,7 +104,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

43
components/hal/esp32h21/include/hal/regi2c_ctrl_ll.h
View File

@@ -6,14 +6,14 @@
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include <stdint.h>
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#include "soc/i2c_ana_mst_reg.h"
#include "soc/pmu_reg.h"
//TODO: [ESP32H21] IDF-11550, inherit from h2
#include "modem/modem_lpcon_struct.h"
#ifdef __cplusplus
extern "C" {
@@ -22,25 +22,42 @@ extern "C" {
/**
* @brief Enable analog I2C master clock
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
{
//TODO: [ESP32H21] IDF-11550
MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
/**
* @brief Check whether analog I2C master clock is enabled
*/
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
{
return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
}
/**
* @brief Reset analog I2C master
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
{
//TODO: [ESP32H21] IDF-11550
MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
/**
* @brief Force enable analog I2C master clock
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
{
//TODO: [ESP32H21] IDF-11550
MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
}
/**
@@ -56,8 +73,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
{
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
}
/**
@@ -65,8 +82,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
{
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
}
/**
@@ -76,7 +93,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
*/
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
{
return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
}
/**
@@ -88,7 +105,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h
View File

@@ -55,7 +55,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h
View File

@@ -124,7 +124,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h
View File

@@ -48,7 +48,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

2
components/hal/esp32s3/include/hal/regi2c_ctrl_ll.h
View File

@@ -41,7 +41,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{

8
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
View File

@@ -99,6 +99,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_REG_I2C_SUPPORTED
bool
default y
config SOC_AES_SUPPORTED
bool
default y
@@ -906,3 +910,7 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
bool
default y

2
components/soc/esp32h21/include/soc/regi2c_defs.h
View File

@@ -9,7 +9,7 @@
#include "esp_bit_defs.h"
/* Analog function control register */
// I2C_MST_ANA_CONF0_REG
// I2C_ANA_MST_ANA_CONF0_REG
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))

4
components/soc/esp32h21/include/soc/soc_caps.h
View File

@@ -64,7 +64,7 @@
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503
#define SOC_MODEM_CLOCK_SUPPORTED 1
// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550
#define SOC_REG_I2C_SUPPORTED 1
// #define SOC_PHY_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566
// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601
@@ -552,6 +552,8 @@
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)

418
components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,213 +7,279 @@
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11858
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY_V 0x1
#define I2C_ANA_MST_I2C0_BUSY_S 25
/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S))
#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF
#define I2C_ANA_MST_I2C0_CTRL_S 0
#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
/*description: .*/
#define I2C_MST_I2C0_CTRL 0x01FFFFFFU
#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S)
#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU
#define I2C_MST_I2C0_CTRL_S 0
/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25))
#define I2C_ANA_MST_I2C1_BUSY_V 0x1
#define I2C_ANA_MST_I2C1_BUSY_S 25
/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
/*description: .*/
#define I2C_MST_I2C0_BUSY (BIT(25))
#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S)
#define I2C_MST_I2C0_BUSY_V 0x00000001U
#define I2C_MST_I2C0_BUSY_S 25
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S))
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
#define I2C_ANA_MST_I2C1_CTRL_S 0
#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/
#define I2C_MST_I2C1_CTRL 0x01FFFFFFU
#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S)
#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU
#define I2C_MST_I2C1_CTRL_S 0
/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/
#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S))
#define I2C_ANA_MST_I2C0_STATUS_V 0xFF
#define I2C_ANA_MST_I2C0_STATUS_S 24
/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: .*/
#define I2C_MST_I2C1_BUSY (BIT(25))
#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S)
#define I2C_MST_I2C1_BUSY_V 0x00000001U
#define I2C_MST_I2C1_BUSY_S 25
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S))
#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF
#define I2C_ANA_MST_I2C0_CONF_S 0
#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC)
/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/
#define I2C_MST_I2C0_CONF 0x00FFFFFFU
#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S)
#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU
#define I2C_MST_I2C0_CONF_S 0
/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S))
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
#define I2C_ANA_MST_I2C1_STATUS_S 24
/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: .*/
#define I2C_MST_I2C0_STATUS 0x000000FFU
#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S)
#define I2C_MST_I2C0_STATUS_V 0x000000FFU
#define I2C_MST_I2C0_STATUS_S 24
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S))
#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF
#define I2C_ANA_MST_I2C1_CONF_S 0
#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_CONF 0x00FFFFFFU
#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S)
#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU
#define I2C_MST_I2C1_CONF_S 0
/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C1_STATUS 0x000000FFU
#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S)
#define I2C_MST_I2C1_STATUS_V 0x000000FFU
#define I2C_MST_I2C1_STATUS_S 24
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n * 4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/
/* description: .*/
#define I2C_MST_BURST_CTRL 0xFFFFFFFFU
#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S)
#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU
#define I2C_MST_BURST_CTRL_S 0
#define REGI2C_RTC_BUSY (BIT(25))
#define REGI2C_RTC_BUSY_M (BIT(25))
#define REGI2C_RTC_BUSY_V 0x1
#define REGI2C_RTC_BUSY_S 25
#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST_BURST_DONE (BIT(0))
#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S)
#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U
#define I2C_MST_I2C_MST_BURST_DONE_S 0
/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S)
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/
/* description: .*/
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S)
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2
/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/
/* description: .*/
#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU
#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S)
#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU
#define I2C_MST_BURST_TIMEOUT_CNT_S 3
#define REGI2C_RTC_WR_CNTL (BIT(24))
#define REGI2C_RTC_WR_CNTL_M (BIT(24))
#define REGI2C_RTC_WR_CNTL_V 0x1
#define REGI2C_RTC_WR_CNTL_S 24
#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF0 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S)
#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF0_S 0
/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS0 0x000000FFU
#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S)
#define I2C_MST_ANA_STATUS0_V 0x000000FFU
#define I2C_MST_ANA_STATUS0_S 24
#define REGI2C_RTC_DATA 0x000000FF
#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
#define REGI2C_RTC_DATA_V 0xFF
#define REGI2C_RTC_DATA_S 16
#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF1 0x00FFFFFFU
#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S)
#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF1_S 0
/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS1 0x000000FFU
#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S)
#define I2C_MST_ANA_STATUS1_V 0x000000FFU
#define I2C_MST_ANA_STATUS1_S 24
#define REGI2C_RTC_ADDR 0x000000FF
#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
#define REGI2C_RTC_ADDR_V 0xFF
#define REGI2C_RTC_ADDR_S 8
#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_CONF2 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S)
#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU
#define I2C_MST_ANA_CONF2_S 0
/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/
/* description: .*/
#define I2C_MST_ANA_STATUS2 0x000000FFU
#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S)
#define I2C_MST_ANA_STATUS2_V 0x000000FFU
#define I2C_MST_ANA_STATUS2_S 24
#define REGI2C_RTC_SLAVE_ID 0x000000FF
#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
#define REGI2C_RTC_SLAVE_ID_V 0xFF
#define REGI2C_RTC_SLAVE_ID_S 0
#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/* I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S)
#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0
/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
/* description: .*/
#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S)
#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6
#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFF
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M ((I2C_ANA_MST_I2C_MST_BURST_CTRL_V)<<(I2C_ANA_MST_I2C_MST_BURST_CTRL_S))
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFF
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0
#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
/* I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
/*description: .*/
#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S)
#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFF
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S))
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0xFFF
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20
/* I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S)
#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (BIT(2))
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x1
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2
/* I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (BIT(1))
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x1
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/* I2C_ANA_MST_I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0))
#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (BIT(0))
#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x1
#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0
#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/* I2C_ANA_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/
#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S)
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_ANA_STATUS0_V)<<(I2C_ANA_MST_ANA_STATUS0_S))
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
#define I2C_ANA_MST_ANA_STATUS0_S 24
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
/*description: .*/
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/
/* description: .*/
#define I2C_MST_ARBITER_DIS (BIT(11))
#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S)
#define I2C_MST_ARBITER_DIS_V 0x00000001U
#define I2C_MST_ARBITER_DIS_S 11
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF0_S 0
#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
/* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/
#define I2C_MST_NOUSE 0xFFFFFFFFU
#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S)
#define I2C_MST_NOUSE_V 0xFFFFFFFFU
#define I2C_MST_NOUSE_S 0
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_ANA_STATUS1_V)<<(I2C_ANA_MST_ANA_STATUS1_S))
#define I2C_ANA_MST_ANA_STATUS1_V 0xFF
#define I2C_ANA_MST_ANA_STATUS1_S 24
/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
/*description: .*/
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF1_S 0
/* bit0 : test_i2c
bit1 : ana_dig_ch0
bit2 : BB_TOP_I2C
bit3 : TXTOP_I2C
bit4 : SDM_I2C
bit5 : PLL_I2C
bit6 : BIAS_I2C
bit7 : BB_PLL_I2C
bit8 : ULP_I2C
bit9 : PERIF_I2C
bit10 : PMU_I2C
*/
#define REGI2C_CONF1_BBTOP_SEL (BIT(2))
#define REGI2C_CONF1_TXTOP_SEL (BIT(3))
#define REGI2C_CONF1_SDM_SEL (BIT(4))
#define REGI2C_CONF1_PLL_SEL (BIT(5))
#define REGI2C_CONF1_BIAS_SEL (BIT(6))
#define REGI2C_CONF1_BBPLL_SEL (BIT(7))
#define REGI2C_CONF1_ULP_SEL (BIT(8))
#define REGI2C_CONF1_PERIF_SEL (BIT(9))
#define REGI2C_CONF1_PMU_SEL (BIT(10))
#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/* I2C_ANA_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/
#define I2C_MST_DATE 0x0FFFFFFFU
#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S)
#define I2C_MST_DATE_V 0x0FFFFFFFU
#define I2C_MST_DATE_S 0
/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_ANA_STATUS2_V)<<(I2C_ANA_MST_ANA_STATUS2_S))
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
#define I2C_ANA_MST_ANA_STATUS2_S 24
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
/*description: .*/
#define I2C_MST_CLK_EN (BIT(28))
#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S)
#define I2C_MST_CLK_EN_V 0x00000001U
#define I2C_MST_CLK_EN_S 28
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF2_S 0
/* bit4 : BB_TOP_I2C
bit5 : TXTOP_I2C
bit6 : SDM_I2C
bit7 : PLL_I2C
bit8 : BIAS_I2C
bit9 : BB_PLL_I2C
bit10 : ULP_I2C
bit11 : PERIF_I2C
bit12 : PMU_I2C
*/
#define REGI2C_CONF2_BBTOP_SEL (BIT(4))
#define REGI2C_CONF2_TXTOP_SEL (BIT(5))
#define REGI2C_CONF2_SDM_SEL (BIT(6))
#define REGI2C_CONF2_PLL_SEL (BIT(7))
#define REGI2C_CONF2_BIAS_SEL (BIT(8))
#define REGI2C_CONF2_BBPLL_SEL (BIT(9))
#define REGI2C_CONF2_ULP_SEL (BIT(10))
#define REGI2C_CONF2_PERIF_SEL (BIT(11))
#define REGI2C_CONF2_PMU_SEL (BIT(12))
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S))
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
/*description: .*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S))
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
/*description: .*/
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C)
/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: .*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
#define I2C_ANA_MST_ARBITER_DIS_S 11
/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
/*description: .*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S))
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
/*description: .*/
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S))
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
#define I2C_ANA_MST_I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
/* I2C_ANA_MST_I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFF
#define I2C_ANA_MST_I2C_MST_NOUSE_M ((I2C_ANA_MST_I2C_MST_NOUSE_V)<<(I2C_ANA_MST_I2C_MST_NOUSE_S))
#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFF
#define I2C_ANA_MST_I2C_MST_NOUSE_S 0
#define I2C_ANA_MST_I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/* I2C_ANA_MST_I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
/*description: .*/
#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28))
#define I2C_ANA_MST_I2C_MST_CLK_EN_M (BIT(28))
#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x1
#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28
/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
/*description: .*/
#define I2C_ANA_MST_DATE 0x0FFFFFFF
#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S))
#define I2C_ANA_MST_DATE_V 0xFFFFFFF
#define I2C_ANA_MST_DATE_S 0
#ifdef __cplusplus
}

2
components/soc/esp32h21/register/soc/reg_base.h
View File

@@ -47,6 +47,7 @@
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_LP_APM0_BASE 0x60099800
#define DR_REG_I2C_ANA_MST_BASE 0x600AD800
#define DR_REG_PMU_BASE 0x600B0000
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_LP_TIMER_BASE 0x600B0C00
@@ -61,5 +62,4 @@
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000
#define DR_REG_I2C_ANA_MST_BASE 0x600AD800 //TODO: [ESP32H21] IDF-11550, need check
#define PWDET_CONF_REG 0x600A0810 //TODO: [ESP32H21] IDF-11589, IDF-11592, need check