From 7643f77225857b357811ec6afa2f0c4475994a40 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 24 Mar 2025 22:11:20 +0800 Subject: [PATCH] feat(esp_hw_support): enable auto clock gating for multi peripherals --- components/esp_system/port/soc/esp32p4/clk.c | 23 ++++++++++++++++++- components/hal/esp32p4/include/hal/adc_ll.h | 16 +++++++++++++ components/hal/esp32p4/include/hal/emac_ll.h | 11 ++++++++- components/hal/esp32p4/include/hal/l2mem_ll.h | 13 +++++++++++ 4 files changed, 61 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 06974d098c..8b94ede3f5 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,10 +32,12 @@ #include "soc/usb_serial_jtag_reg.h" #include "soc/trace_struct.h" +#include "hal/adc_ll.h" #include "hal/aes_ll.h" #include "hal/assist_debug_ll.h" #include "hal/ds_ll.h" #include "hal/ecc_ll.h" +#include "hal/emac_ll.h" #include "hal/etm_ll.h" #include "hal/gdma_ll.h" #include "hal/hmac_ll.h" @@ -248,6 +250,25 @@ __attribute__((weak)) void esp_perip_clk_init(void) || (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) || (rst_reason == RESET_REASON_CORE_SW) || (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART) ) { + // Not gate HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON since the hardware will not automatically ungate when DMA accesses L2 MEM. + REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON + | HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON); + _adc_ll_sar1_clock_force_en(false); + _adc_ll_sar2_clock_force_en(false); + _emac_ll_clock_force_en(false); + // hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp // but at core reset and above, we will also disable HP modules' clock gating to save power consumption _gdma_ll_enable_bus_clock(0, false); diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h index f3634b33ed..7bec239818 100644 --- a/components/hal/esp32p4/include/hal/adc_ll.h +++ b/components/hal/esp32p4/include/hal/adc_ll.h @@ -494,6 +494,22 @@ static inline uint32_t adc_ll_pwdet_get_cct(void) Common setting ---------------------------------------------------------------*/ +static inline void _adc_ll_sar1_clock_force_en(bool enable) +{ + HP_SYS_CLKRST.clk_force_on_ctrl0.reg_sar1_clk_force_on = enable; +} + +// HP_SYS_CLKRST.clk_force_on_ctrl0 are shared registers, so this function must be used in an atomic way +#define adc_ll_sar1_clock_force_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_sar1_clock_force_en(__VA_ARGS__) + +static inline void _adc_ll_sar2_clock_force_en(bool enable) +{ + HP_SYS_CLKRST.clk_force_on_ctrl0.reg_sar2_clk_force_on = enable; +} + +// HP_SYS_CLKRST.clk_force_on_ctrl0 are shared registers, so this function must be used in an atomic way +#define adc_ll_sar2_clock_force_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_sar2_clock_force_en(__VA_ARGS__) + /** * @brief Enable the ADC clock * @param enable true to enable, false to disable diff --git a/components/hal/esp32p4/include/hal/emac_ll.h b/components/hal/esp32p4/include/hal/emac_ll.h index b06b57ddb0..00cd9369c0 100644 --- a/components/hal/esp32p4/include/hal/emac_ll.h +++ b/components/hal/esp32p4/include/hal/emac_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -594,6 +594,15 @@ static inline void emac_ll_enable_bus_clock(int group_id, bool enable) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define emac_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_enable_bus_clock(__VA_ARGS__) +static inline void _emac_ll_clock_force_en(bool enable) +{ + HP_SYS_CLKRST.clk_force_on_ctrl0.reg_gmac_tx_clk_force_on = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define emac_ll_clock_force_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _emac_ll_clock_force_en(__VA_ARGS__) + /** * @brief Reset the EMAC module * diff --git a/components/hal/esp32p4/include/hal/l2mem_ll.h b/components/hal/esp32p4/include/hal/l2mem_ll.h index 6275051d59..892d871070 100644 --- a/components/hal/esp32p4/include/hal/l2mem_ll.h +++ b/components/hal/esp32p4/include/hal/l2mem_ll.h @@ -8,6 +8,7 @@ #include #include #include "soc/hp_system_struct.h" +#include "soc/hp_sys_clkrst_struct.h" #ifdef __cplusplus extern "C" { @@ -26,6 +27,18 @@ static inline void l2mem_ll_enable_ahb_burst_buffer(bool en_read, bool en_write) HP_SYSTEM.l2_mem_ahb_buffer_ctrl.l2_mem_ahb_wrbuffer_en = en_write; } +/** + * @brief Force enable the clock of L2 memory. + * @param enable True to force enable L2 memory clock. + */ +static inline void _l2mem_ll_clock_force_en(bool enable) +{ + HP_SYS_CLKRST.clk_force_on_ctrl0.reg_l2mem_mem_clk_force_on = enable; +} + +// HP_SYS_CLKRST.soc_clk_ctrl2 are shared registers, so this function must be used in an atomic way +#define l2mem_ll_clock_force_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _l2mem_ll_clock_force_en(__VA_ARGS__) + #ifdef __cplusplus } #endif