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feat(timer): refator timer group driver

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1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
This commit is contained in:
chenjianqiang
2019-07-15 14:21:36 +08:00
parent 8c3cb232f0
commit 9f9da9ec96
27 changed files with 1460 additions and 331 deletions
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components/esp32/int_wdt.c
+2 -2
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@@ -93,8 +93,8 @@ void esp_int_wdt_init(void) {
timer_ll_wdt_feed(&TIMERG1);
timer_ll_wdt_set_protect(&TIMERG1, true);
timer_ll_intr_status_clear(&TIMERG1, TIMER_INTR_WDT);
timer_group_intr_enable(TIMER_GROUP_1, TIMER_INTR_WDT);
timer_ll_wdt_clear_intr_status(&TIMERG1);
timer_ll_wdt_enable_intr(&TIMERG1);
}
void esp_int_wdt_cpu_init(void)
components/esp32/panic.c
+1 -1
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@@ -313,7 +313,7 @@ void panicHandler(XtExcFrame *frame)
disableAllWdts();
if (frame->exccause == PANIC_RSN_INTWDT_CPU0 ||
frame->exccause == PANIC_RSN_INTWDT_CPU1) {
timer_group_clr_intr_sta_in_isr(TIMER_GROUP_1, TIMER_INTR_WDT);
timer_ll_wdt_clear_intr_status(&TIMERG1);
}
#if CONFIG_ESP32_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE
components/esp32/task_wdt.c
+1 -1
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@@ -143,7 +143,7 @@ static void task_wdt_isr(void *arg)
timer_ll_wdt_feed(&TIMERG0);
timer_ll_wdt_set_protect(&TIMERG0, true);
//Acknowledge interrupt
timer_group_clr_intr_sta_in_isr(TIMER_GROUP_0, TIMER_INTR_WDT);
timer_ll_wdt_clear_intr_status(&TIMERG0);
//We are taking a spinlock while doing I/O (ESP_EARLY_LOGE) here. Normally, that is a pretty
//bad thing, possibly (temporarily) hanging up the 2nd core and stopping FreeRTOS. In this case,
//something bad already happened and reporting this is considered more important
components/esp32/test/test_intr_alloc.c
+4 -4
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@@ -58,19 +58,19 @@ static void timer_isr(void *arg)
int timer_idx = (int)arg;
count[timer_idx]++;
if (timer_idx==0) {
timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_enable_alarm_in_isr(TIMER_GROUP_0, TIMER_0);
}
if (timer_idx==1) {
timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_1);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_1);
timer_group_enable_alarm_in_isr(TIMER_GROUP_0, TIMER_1);
}
if (timer_idx==2) {
timer_group_intr_clr_in_isr(TIMER_GROUP_1, TIMER_0);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_1, TIMER_0);
timer_group_enable_alarm_in_isr(TIMER_GROUP_1, TIMER_0);
}
if (timer_idx==3) {
timer_group_intr_clr_in_isr(TIMER_GROUP_1, TIMER_1);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_1, TIMER_1);
timer_group_enable_alarm_in_isr(TIMER_GROUP_1, TIMER_1);
}
// ets_printf("int %d\n", timer_idx);
components/esp32/test/test_reset_reason.c
+2 -2
View File
@@ -280,12 +280,12 @@ static void timer_group_test_first_stage(void)
//Start timer
timer_start(TIMER_GROUP_0, TIMER_0);
//Waiting for timer_group to generate an interrupt
while( !(timer_group_intr_get_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
loop_cnt++ < 100) {
vTaskDelay(200);
}
//TIMERG0.int_raw.t0 == 1 means an interruption has occurred
TEST_ASSERT(timer_group_intr_get_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
TEST_ASSERT(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
esp_restart();
}