fix(spi): correct some signals and dummy bits docs

This commit is contained in:
wanlei
2023-12-06 16:05:36 +08:00
committed by Wan Lei
parent 41b8238cf3
commit a0e8f75336
4 changed files with 59 additions and 50 deletions

View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -12,29 +12,30 @@
*/ */
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{ {
.spiclk_out = SPICLK_OUT_MUX_IDX, // MSPI has dedicated iomux pins
.spiclk_in = 0,/* SPI clock is not an input signal*/ .spiclk_out = -1,
.spid_out = SPID_OUT_IDX, .spiclk_in = -1,
.spiq_out = SPIQ_OUT_IDX, .spid_out = -1,
.spiwp_out = SPIWP_OUT_IDX, .spiq_out = -1,
.spihd_out = SPIHD_OUT_IDX, .spiwp_out = -1,
.spid_in = SPID_IN_IDX, .spihd_out = -1,
.spiq_in = SPIQ_IN_IDX, .spid_in = -1,
.spiwp_in = SPIWP_IN_IDX, .spiq_in = -1,
.spihd_in = SPIHD_IN_IDX, .spiwp_in = -1,
.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ .spihd_in = -1,
.spics_in = 0,/* SPI cs is not an input signal*/ .spics_out = {-1},
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, .spics_in = -1,
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, .spiclk_iomux_pin = -1,
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, .spid_iomux_pin = -1,
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, .spiq_iomux_pin = -1,
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, .spiwp_iomux_pin = -1,
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, .spihd_iomux_pin = -1,
.irq = ETS_SPI1_INTR_SOURCE, .spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1, .irq_dma = -1,
.module = PERIPH_SPI_MODULE, .module = -1,
.hw = (spi_dev_t *) &SPIMEM1, .hw = NULL,
.func = SPI_FUNC_NUM, .func = -1,
}, { }, {
.spiclk_out = FSPICLK_OUT_IDX, .spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX, .spiclk_in = FSPICLK_IN_IDX,

View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -12,29 +12,30 @@
*/ */
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{ {
.spiclk_out = SPICLK_OUT_IDX, // MSPI has dedicated iomux pins
.spiclk_in = 0,/* SPI clock is not an input signal*/ .spiclk_out = -1,
.spid_out = SPID_OUT_IDX, .spiclk_in = -1,
.spiq_out = SPIQ_OUT_IDX, .spid_out = -1,
.spiwp_out = SPIWP_OUT_IDX, .spiq_out = -1,
.spihd_out = SPIHD_OUT_IDX, .spiwp_out = -1,
.spid_in = SPID_IN_IDX, .spihd_out = -1,
.spiq_in = SPIQ_IN_IDX, .spid_in = -1,
.spiwp_in = SPIWP_IN_IDX, .spiq_in = -1,
.spihd_in = SPIHD_IN_IDX, .spiwp_in = -1,
.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ .spihd_in = -1,
.spics_in = 0,/* SPI cs is not an input signal*/ .spics_out = {-1},
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, .spics_in = -1,
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, .spiclk_iomux_pin = -1,
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, .spid_iomux_pin = -1,
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, .spiq_iomux_pin = -1,
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, .spiwp_iomux_pin = -1,
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, .spihd_iomux_pin = -1,
.irq = ETS_SPI1_INTR_SOURCE, .spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1, .irq_dma = -1,
.module = PERIPH_SPI_MODULE, .module = -1,
.hw = (spi_dev_t *) &SPIMEM1, .hw = NULL,
.func = SPI_FUNC_NUM, .func = -1,
}, { }, {
.spiclk_out = FSPICLK_OUT_IDX, .spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX, .spiclk_in = FSPICLK_IN_IDX,

View File

@ -44,10 +44,17 @@ should exist):
to/read from. For other commands with this phase, they are meaningless, but still have to to/read from. For other commands with this phase, they are meaningless, but still have to
exist in the transaction. exist in the transaction.
- Dummy: 8-bit, floating, optional .. only:: esp32s2
This phase is the turn around time between the master and the slave on the bus, and also - Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional
provides enough time for the slave to prepare the data to send to master.
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
.. only:: not esp32s2
- Dummy: 8-bit, floating, optional
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
- Data: variable length, the direction is also determined by the command. - Data: variable length, the direction is also determined by the command.

View File

@ -1 +1 @@
.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst .. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst