From a2580b3f361a6531e3d4cc2ea89ccb1e3c9945ff Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Wed, 19 Apr 2023 10:34:39 +0530 Subject: [PATCH] esp_hw_support: Update memory ptr location/property checks - to acknowledge the unused DCACHE added to DRAM for ESP32-S3 - For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000). - But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal` check on that memory pointer, it fails as the address block from 0x3C000000 corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW. (E.g. freertos - If the IDLE task stack buffer gets allocated from this region, the firmware will abort due to this failure). - Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible` have been updated to acknowledge this memory as a part of the DRAM. Co-authored-by: Mahavir Jain --- components/soc/include/soc/soc_memory_types.h | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/components/soc/include/soc/soc_memory_types.h b/components/soc/include/soc/soc_memory_types.h index cf0d7ff11e..915912d00b 100644 --- a/components/soc/include/soc/soc_memory_types.h +++ b/components/soc/include/soc/soc_memory_types.h @@ -74,6 +74,15 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p) #else r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_HIGH)); #endif +#endif +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * Though this memory lies in the external memory vaddr, it is no different + * from the internal RAM in terms of hardware attributes. It is a part of + * the internal RAM when added to the heap and is byte-accessible .*/ + r |= (ip >= SOC_DROM_LOW && ip < (SOC_DROM_LOW + 0x4000)); #endif return r; } @@ -87,6 +96,15 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) { * for single core configuration (where it gets added to system heap) following * additional check is required */ r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH); +#endif +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * Though this memory lies in the external memory vaddr, it is no different + * from the internal RAM in terms of hardware attributes and it is a part of + * the internal RAM when added to the heap.*/ + r |= ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < (SOC_DROM_LOW + 0x4000)); #endif return r; } @@ -109,7 +127,18 @@ inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) { } inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) { - return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH); + uint32_t drom_start_addr = SOC_DROM_LOW; +#if CONFIG_ESP32S3_DATA_CACHE_16KB + /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is + * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB + * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000). + * The drom_start_addr has to be moved by 0x4000 (16kB) to accomodate + * this addition. */ + drom_start_addr += 0x4000; +#endif + + return ((intptr_t)p >= drom_start_addr && (intptr_t)p < SOC_DROM_HIGH); + } inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {