Merge branch 'feature/esp32h2_adds_adc_calib_efuses' into 'master'

feat(efuse): Adds efuse ADC calibration data for ESP32H2

See merge request espressif/esp-idf!26305

components/efuse/esp32h2/esp_efuse_table.c

@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 6b9b5b452050328626d767c44e489b8d
+// md5_digest_table e3fb625011fff48d5d8b7569075d0bb3
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -243,6 +243,62 @@ static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
 };
 
+static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of TEMP_CALIB,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
@@ -553,6 +609,62 @@ static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
     {EFUSE_BLK2, 135, 1}, 	 // [] Disables check of blk version major,
 };
 
+static const esp_efuse_desc_t TEMP_CALIB[] = {
+    {EFUSE_BLK2, 136, 9}, 	 // [] Temperature calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 145, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 155, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 165, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 175, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK2, 185, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK2, 195, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK2, 205, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK2, 215, 10}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 225, 4}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 229, 4}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 233, 4}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 237, 4}, 	 // [] ADC1 calibration data,
+};
+
+static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 241, 4}, 	 // [] ADC1 calibration data,
+};
+
 static const esp_efuse_desc_t USER_DATA[] = {
     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
@@ -878,6 +990,76 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
+    &WR_DIS_TEMP_CALIB[0],    		// [] wr_dis of TEMP_CALIB
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
     &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
@@ -1264,6 +1446,76 @@ const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
+    &TEMP_CALIB[0],    		// [] Temperature calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &ADC1_AVE_INITCODE_ATTEN0[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &ADC1_AVE_INITCODE_ATTEN1[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &ADC1_AVE_INITCODE_ATTEN2[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &ADC1_AVE_INITCODE_ATTEN3[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
+    &ADC1_HI_DOUT_ATTEN0[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
+    &ADC1_HI_DOUT_ATTEN1[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
+    &ADC1_HI_DOUT_ATTEN2[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
+    &ADC1_HI_DOUT_ATTEN3[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] ADC1 calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] ADC1 calibration data
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL

components/efuse/esp32h2/esp_efuse_table.csv

@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 4df10f83de85f2d830b7c466aabb28e7
+# This file was generated by regtools.py based on the efuses.yaml file with the version: b69ddcfb39a412df490e3facbbfb46b2
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -68,6 +68,20 @@ WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis
 WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MINOR
 WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MAJOR
 WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  21,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
+WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,  21,   1, [] wr_dis of TEMP_CALIB
+WR_DIS.ADC1_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+WR_DIS.ADC1_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+WR_DIS.ADC1_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+WR_DIS.ADC1_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+WR_DIS.ADC1_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
+WR_DIS.ADC1_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
+WR_DIS.ADC1_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
+WR_DIS.ADC1_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
+WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
 WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
 WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
 WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -150,6 +164,20 @@ OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Option
 BLK_VERSION_MINOR,                               EFUSE_BLK2, 130,   3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
 BLK_VERSION_MAJOR,                               EFUSE_BLK2, 133,   2, [] BLK_VERSION_MAJOR of BLOCK2
 DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK2, 135,   1, [] Disables check of blk version major
+TEMP_CALIB,                                      EFUSE_BLK2, 136,   9, [] Temperature calibration data
+ADC1_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 145,  10, [] ADC1 calibration data
+ADC1_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 155,  10, [] ADC1 calibration data
+ADC1_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 165,  10, [] ADC1 calibration data
+ADC1_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 175,  10, [] ADC1 calibration data
+ADC1_HI_DOUT_ATTEN0,                             EFUSE_BLK2, 185,  10, [] ADC1 calibration data
+ADC1_HI_DOUT_ATTEN1,                             EFUSE_BLK2, 195,  10, [] ADC1 calibration data
+ADC1_HI_DOUT_ATTEN2,                             EFUSE_BLK2, 205,  10, [] ADC1 calibration data
+ADC1_HI_DOUT_ATTEN3,                             EFUSE_BLK2, 215,  10, [] ADC1 calibration data
+ADC1_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 225,   4, [] ADC1 calibration data
+ADC1_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 229,   4, [] ADC1 calibration data
+ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 233,   4, [] ADC1 calibration data
+ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 237,   4, [] ADC1 calibration data
+ADC1_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 241,   4, [] ADC1 calibration data
 USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
 USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
 KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data

components/efuse/esp32h2/include/esp_efuse_table.h

@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table 6b9b5b452050328626d767c44e489b8d
+// md5_digest_table e3fb625011fff48d5d8b7569075d0bb3
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -83,6 +83,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
 #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -185,6 +199,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
 extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];

components/soc/esp32h2/include/soc/efuse_reg.h

@@ -796,49 +796,147 @@ extern "C" {
 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
-/** EFUSE_RESERVED_2_136 : R; bitpos: [31:8]; default: 0;
+/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0;
- *  reserved
+ *  Temperature calibration data
  */
-#define EFUSE_RESERVED_2_136    0x00FFFFFFU
+#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_RESERVED_2_136_M  (EFUSE_RESERVED_2_136_V << EFUSE_RESERVED_2_136_S)
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_RESERVED_2_136_V  0x00FFFFFFU
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_RESERVED_2_136_S  8
+#define EFUSE_TEMP_CALIB_S  8
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  17
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  27
 
 /** EFUSE_RD_SYS_PART1_DATA5_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
- *  Stores the fifth 32 bits of the first part of system data.
+ *  ADC1 calibration data
  */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1    0x0000001FU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V  0x0000001FU
-#define EFUSE_SYS_DATA_PART1_5_S  0
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  5
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  15
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  25
 
 /** EFUSE_RD_SYS_PART1_DATA6_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
+/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
- *  Stores the sixth 32 bits of the first part of system data.
+ *  ADC1 calibration data
  */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1    0x00000007U
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V  0x00000007U
-#define EFUSE_SYS_DATA_PART1_6_S  0
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  3
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  13
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  23
 
 /** EFUSE_RD_SYS_PART1_DATA7_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
+/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
- *  Stores the seventh 32 bits of the first part of system data.
+ *  ADC1 calibration data
  */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1    (BIT(0))
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V  0x00000001U
-#define EFUSE_SYS_DATA_PART1_7_S  0
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  1
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  5
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  9
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  13
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  17
+/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_245    0x000007FFU
+#define EFUSE_RESERVED_2_245_M  (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S)
+#define EFUSE_RESERVED_2_245_V  0x000007FFU
+#define EFUSE_RESERVED_2_245_S  21
 
 /** EFUSE_RD_USR_DATA0_REG register
  *  Register $n of BLOCK3 (user).

components/soc/esp32h2/include/soc/efuse_struct.h

@@ -636,10 +636,18 @@ typedef union {
          *  Disables check of blk version major
          */
         uint32_t disable_blk_version_major:1;
-        /** reserved_2_136 : R; bitpos: [31:8]; default: 0;
+        /** temp_calib : R; bitpos: [16:8]; default: 0;
-         *  reserved
+         *  Temperature calibration data
          */
-        uint32_t reserved_2_136:24;
+        uint32_t temp_calib:9;
+        /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten1:5;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data4_reg_t;
@@ -649,10 +657,22 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
+        /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
-         *  Stores the fifth 32 bits of the first part of system data.
+         *  ADC1 calibration data
          */
-        uint32_t sys_data_part1_5:32;
+        uint32_t adc1_ave_initcode_atten1_1:5;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten0:7;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data5_reg_t;
@@ -662,10 +682,22 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
+        /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
-         *  Stores the sixth 32 bits of the first part of system data.
+         *  ADC1 calibration data
          */
-        uint32_t sys_data_part1_6:32;
+        uint32_t adc1_hi_dout_atten0_1:3;
+        /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten1:10;
+        /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten3:9;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data6_reg_t;
@@ -675,10 +707,34 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
+        /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
-         *  Stores the seventh 32 bits of the first part of system data.
+         *  ADC1 calibration data
          */
-        uint32_t sys_data_part1_7:32;
+        uint32_t adc1_hi_dout_atten3_1:1;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** reserved_2_245 : R; bitpos: [31:21]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_245:11;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data7_reg_t;