Fix live lock in bt isr immediately

components/bt/bt.c

@@ -984,7 +984,7 @@ static void hli_queue_setup_pinned_to_core(int core_id)
 esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 {
 
-    ets_printf("\n BT version: high level int 0510\n");
+    ets_printf("\n BT version: high level int 0605\n");
     esp_err_t err;
     uint32_t btdm_cfg_mask = 0;
 

components/bt/hli_vectors.S

@@ -42,19 +42,20 @@ xt_highint4:
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
     /*
-    Here, Timer2 is used to count a little time.
+    Here, Timer2 is used to count a little time(50 us).
     The subsequent dram0 write operation is blocked due to live lock, which will
     cause timer2 to timeout and trigger a l5 interrupt.
     */
     rsr.ccount  a0
-    addmi   a0, a0, (240*50)
+    addmi   a0, a0, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
     wsr     a0, CCOMPARE2
 
     /* Enable Timer 2 interrupt */
     rsr     a0, INTENABLE
     extui   a0, a0, 16, 1
     bnez    a0, 1f
-    rsr     a0, INTENABLE
+    movi    a0, 0
+    xsr     a0, INTENABLE     // disable all interrupts
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
@@ -89,7 +90,8 @@ xt_highint4:
     s32i    a2, a0, 24
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
-    rsr     a0, INTENABLE
+    movi    a0, 0
+    xsr     a0, INTENABLE
     movi    a2, ~(1<<16)
     and     a0, a2, a0
     wsr     a0, INTENABLE

components/esp32/dport_panic_highint_hdl.S

@@ -72,10 +72,13 @@ xt_highint5:
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
     /* Timer 2 interrupt */
+    rsr     a0, INTENABLE
+    extui   a0, a0, 16, 1
+    beqz    a0, 1f
     rsr     a0, INTERRUPT
     extui   a0, a0, 16, 1
     bnez    a0, .handle_multicore_debug_int
-
+1:
     /* See if we're here for the tg1 watchdog interrupt */
     rsr     a0, INTERRUPT
     extui   a0, a0, ETS_T1_WDT_INUM, 1
@@ -181,6 +184,10 @@ xt_highint5:
 
     wsr     a2, depc                        /* temp storage */
 
+    rsr.ccount  a2
+    addmi   a2, a2, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
+    wsr     a2, CCOMPARE2
+
     /* Enable Integration Mode */
     movi    a2, ERI_ADDR(APB_ITCTRL)
     rer     a0, a2

components/esp32/int_wdt.c

@@ -115,7 +115,7 @@ void esp_int_wdt_init() {
 #define _SYM2STR(x)     # x
 #define SYM2STR(x)      _SYM2STR(x)
     uint32_t eriadrs, scratch = 0, immediate = 0;
-    if (xPortGetCoreID() == PRO_CPU_NUM) {
+    if (xPortGetCoreID() != CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE) {
         __asm__ __volatile__ (
                 /* Enable Xtensa Debug Module Integration Mode */
                 "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"

components/freertos/xtensa_vector_defaults.S

@@ -35,14 +35,24 @@ _xt_debugexception:
 
 #define XT_DEBUGCAUSE_DI        (5)
 
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+#if (CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE == 0)
     getcoreid   a0
     beqz    a0, 1f
+#elif (CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE == 1)
+    getcoreid   a0
+    bnez    a0, 1f
+#else
+    j       1f
+#endif
 
     rsr     a0, DEBUGCAUSE
     extui   a0, a0, XT_DEBUGCAUSE_DI, 1
     bnez    a0, _xt_debug_di_exc
+1:
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
 
-1:  movi    a0,PANIC_RSN_DEBUGEXCEPTION
+    movi    a0,PANIC_RSN_DEBUGEXCEPTION
     wsr     a0,EXCCAUSE
     /* _xt_panic assumes a level 1 exception. As we're
        crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
@@ -54,10 +64,47 @@ _xt_debugexception:
     call0   _xt_panic                       /* does not return */
     rfi     XCHAL_DEBUGLEVEL
 
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
     .align  4
 _xt_debug_di_exc:
 
-    movi    a0, 1234
+/*  After testing,
+    In 80 MHz, it will task 5us to loop 45 times;
+    In 160 MHz, it will task 5us to loop 90 times;
+    In 240 MHz, it will task 5us to loop 135 times;*/
+#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 54
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 108
+# else
+    movi    a0, 135
+# endif
+
+#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 135
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 189
+# else
+    movi    a0, 243
+# endif
+
+#else
+    movi    a0, 243
+#endif
+
+
 1:  addi    a0, a0, -1
     .rept   4
     nop
@@ -66,6 +113,7 @@ _xt_debug_di_exc:
 
     rsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL
     rfi     XCHAL_DEBUGLEVEL
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
 
 #endif /* Debug exception */