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mspi: support 120MHz Quad Flash and PSRAM on ESP32S3
This commit is contained in:
Armando
@@ -5,42 +5,52 @@
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*/
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#pragma once
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//Octal FLASH: core clock 160M, module clock 40M, DTR mode
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//FLASH: core clock 160M, module clock 40M, DTR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 8
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 2
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//Octal FLASH: core clock 160M, module clock 80M, DTR mode
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//FLASH: core clock 160M, module clock 80M, DTR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 1
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//Octal FLASH: core clock 240M, module clock 120M, DTR mode
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//FLASH: core clock 240M, module clock 120M, DTR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1
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//Octal FLASH: core clock 160M, module clock 80M, STR mode
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//FLASH: core clock 160M, module clock 80M, STR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 8
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 2
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//Octal FLASH: core clock 120M, module clock 120M, STR mode
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//FLASH: core clock 120M, module clock 120M, STR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2
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//Octal FLASH: core clock 240M, module clock 120M, STR mode
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//FLASH: core clock 240M, module clock 120M, STR mode
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#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}}
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#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12
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#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2
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//Octal PSRAM: core clock 80M, module clock 40M, DTR mode
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//PSRAM: core clock 80M, module clock 40M, DTR mode
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#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 1}, {3, 0, 1}, {1, 0, 1}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 2}, {3, 0, 2}}
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#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 12
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#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 4
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//Octal PSRAM: core clock 160M, module clock 80M, DTR mode
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//PSRAM: core clock 160M, module clock 80M, DTR mode
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#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}}
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#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14
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#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 1
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//PSRAM: core clock 240M, module clock 120M, STR mode
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#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}}
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#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12
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#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2
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//PSRAM: core clock 120M, module clock 120M, STR mode
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#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}}
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#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12
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#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2
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@@ -14,17 +14,28 @@
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#include "soc/spi_mem_reg.h"
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#include "spi_timing_config.h"
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#define OPI_PSRAM_SYNC_READ 0x0000
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#define OPI_PSRAM_SYNC_WRITE 0x8080
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#define OCT_PSRAM_RD_DUMMY_NUM (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_NUM (2*(5-1))
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#define OPI_PSRAM_SYNC_READ 0x0000
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#define OPI_PSRAM_SYNC_WRITE 0x8080
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#define OCT_PSRAM_RD_DUMMY_NUM (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_NUM (2*(5-1))
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#define QPI_PSRAM_FAST_READ 0XEB
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#define QPI_PSRAM_WRITE 0X38
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#define QPI_PSRAM_FAST_READ_DUMMY 6
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/////////////////////////////////////////TIMING TUNING IS NEEDED//////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING //If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code
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#define MULTI_LINE_MASK_OCT_FLASH (SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT)
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#define MULTI_LINE_MASK_QUAD_FLASH (SPI_MEM_FASTRD_MODE | SPI_MEM_FREAD_DUAL | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_QIO)
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#define SPI_FLASH_QIO_MODE (SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE)
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#define SPI_FLASH_QUAD_MODE (SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE)
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#define SPI_FLASH_DIO_MODE (SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE)
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#define SPI_FLASH_DUAL_MODE (SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE)
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#define SPI_FLASH_FAST_MODE (SPI_MEM_FASTRD_MODE)
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#define SPI_FLASH_SLOW_MODE 0
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spi_timing_config_core_clock_t IRAM_ATTR spi_timing_config_get_core_clock(void)
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#define NOT_INIT_INT 127
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//-------------------------------------MSPI Clock Setting-------------------------------------//
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spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void)
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{
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switch (SPI_TIMING_CORE_CLOCK_MHZ) {
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case 80:
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@@ -40,7 +51,7 @@ spi_timing_config_core_clock_t IRAM_ATTR spi_timing_config_get_core_clock(void)
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}
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}
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void IRAM_ATTR spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock)
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void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock)
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{
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uint32_t reg_val = 0;
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@@ -64,8 +75,7 @@ void IRAM_ATTR spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_conf
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REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
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}
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//-------------------------------------FLASH timing tuning-------------------------------------//
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void IRAM_ATTR spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
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void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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assert(freqdiv > 0);
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if (freqdiv == 1) {
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@@ -76,7 +86,43 @@ void IRAM_ATTR spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqd
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}
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}
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void IRAM_ATTR spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
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}
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}
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/////////////////////////////////////////TIMING TUNING IS NEEDED//////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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//If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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#if !CONFIG_ESPTOOLPY_OCT_FLASH
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static uint8_t s_rom_flash_extra_dummy[2] = {NOT_INIT_INT, NOT_INIT_INT};
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#endif
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#if CONFIG_SPIRAM_MODE_QUAD
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static uint8_t s_psram_extra_dummy;
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extern void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation);
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#endif
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//-------------------------------------FLASH timing tuning register config-------------------------------------//
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void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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uint32_t reg_val = 0;
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reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
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@@ -90,8 +136,9 @@ void IRAM_ATTR spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t
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REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
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}
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void IRAM_ATTR spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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#if CONFIG_ESPTOOLPY_OCT_FLASH
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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@@ -101,20 +148,50 @@ void IRAM_ATTR spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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}
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//-------------------------------------PSRAM timing tuning-------------------------------------//
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void IRAM_ATTR spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
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#else
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/**
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* The `SPI_MEM_TIMING_CALI_REG` register is only used for OPI on 728
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* Here we only need to update this global variable for extra dummy. Since we use the ROM Flash API, which will set the dummy based on this.
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* We only initialise the SPI0. And leave the SPI1 for flash driver to configure.
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*/
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if (s_rom_flash_extra_dummy[spi_num] == NOT_INIT_INT) {
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s_rom_flash_extra_dummy[spi_num] = g_rom_spiflash_dummy_len_plus[spi_num];
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}
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g_rom_spiflash_dummy_len_plus[spi_num] = s_rom_flash_extra_dummy[spi_num] + extra_dummy;
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uint32_t dummy;
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uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
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if (ctrl_reg & MULTI_LINE_MASK_OCT_FLASH) {
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abort();
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}
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switch (ctrl_reg & MULTI_LINE_MASK_QUAD_FLASH) {
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case SPI_FLASH_QIO_MODE:
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dummy = SPI1_R_QIO_DUMMY_CYCLELEN;
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break;
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case SPI_FLASH_QUAD_MODE:
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dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
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break;
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case SPI_FLASH_DIO_MODE:
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dummy = SPI1_R_DIO_DUMMY_CYCLELEN;
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break;
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case SPI_FLASH_DUAL_MODE:
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dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
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break;
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case SPI_FLASH_FAST_MODE:
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dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
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break;
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case SPI_FLASH_SLOW_MODE:
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dummy = 0;
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break;
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default:
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abort();
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}
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy + g_rom_spiflash_dummy_len_plus[spi_num], SPI_MEM_USR_DUMMY_CYCLELEN_S);
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#endif
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}
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void IRAM_ATTR spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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//-------------------------------------PSRAM timing tuning register config-------------------------------------//
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void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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uint32_t reg_val = 0;
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reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
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@@ -128,8 +205,9 @@ void IRAM_ATTR spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t
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REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
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}
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void IRAM_ATTR spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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@@ -139,10 +217,14 @@ void IRAM_ATTR spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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#elif CONFIG_SPIRAM_MODE_QUAD
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SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M);
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SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S);
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#endif
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}
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//-------------------------------------------FLASH/PSRAM Read/Write------------------------------------------//
|
||||
void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
{
|
||||
#if CONFIG_ESPTOOLPY_OCT_FLASH
|
||||
// note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state.
|
||||
@@ -153,27 +235,34 @@ void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf,
|
||||
}
|
||||
esp_rom_opiflash_read_raw(addr, buf, len);
|
||||
#else
|
||||
abort();
|
||||
esp_rom_spiflash_read(addr, (uint32_t *)buf, len);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
{
|
||||
#if CONFIG_SPIRAM_MODE_OCT
|
||||
esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
|
||||
OPI_PSRAM_SYNC_WRITE, 16,
|
||||
addr, 32,
|
||||
OCT_PSRAM_WR_DUMMY_NUM,
|
||||
buf, 8 * len,
|
||||
buf, len * 8,
|
||||
NULL, 0,
|
||||
BIT(1),
|
||||
false);
|
||||
#else
|
||||
abort();
|
||||
#elif CONFIG_SPIRAM_MODE_QUAD
|
||||
psram_exec_cmd(spi_num, 0,
|
||||
QPI_PSRAM_WRITE, 8,
|
||||
addr, 24,
|
||||
0,
|
||||
buf, len * 8,
|
||||
NULL, 0,
|
||||
SPI_MEM_CS1_DIS_M,
|
||||
false);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
{
|
||||
#if CONFIG_SPIRAM_MODE_OCT
|
||||
for (int i = 0; i < 16; i++) {
|
||||
@@ -184,15 +273,22 @@ static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t
|
||||
addr, 32,
|
||||
OCT_PSRAM_RD_DUMMY_NUM,
|
||||
NULL, 0,
|
||||
buf, 8 * len,
|
||||
buf, len * 8,
|
||||
BIT(1),
|
||||
false);
|
||||
#else
|
||||
abort();
|
||||
#elif CONFIG_SPIRAM_MODE_QUAD
|
||||
psram_exec_cmd(spi_num, 0,
|
||||
QPI_PSRAM_FAST_READ, 8,
|
||||
addr, 24,
|
||||
QPI_PSRAM_FAST_READ_DUMMY + s_psram_extra_dummy,
|
||||
NULL, 0,
|
||||
buf, len * 8,
|
||||
SPI_MEM_CS1_DIS_M,
|
||||
false);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
|
||||
static void s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
|
||||
{
|
||||
while (len) {
|
||||
uint32_t length = MIN(len, 32);
|
||||
@@ -207,14 +303,58 @@ static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
{
|
||||
s_psram_execution(spi_num, buf, addr, len, false);
|
||||
}
|
||||
|
||||
void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
void spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
|
||||
{
|
||||
s_psram_execution(spi_num, buf, addr, len, true);
|
||||
}
|
||||
|
||||
|
||||
/*-------------------------------------------------------------------------------------------------
|
||||
* SPI1 Timing Tuning APIs
|
||||
* These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for
|
||||
* configuring SPI1 timing tuning related registers to find best tuning parameter
|
||||
*-------------------------------------------------------------------------------------------------*/
|
||||
void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num)
|
||||
{
|
||||
/**
|
||||
* 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless
|
||||
* SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning
|
||||
* 2. We use SPI1 to get the best Flash timing tuning (mode and num) config
|
||||
*/
|
||||
spi_timing_config_flash_set_din_mode_num(0, din_mode, din_num);
|
||||
}
|
||||
|
||||
void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy)
|
||||
{
|
||||
spi_timing_config_flash_set_extra_dummy(1, extra_dummy);
|
||||
}
|
||||
|
||||
void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num)
|
||||
{
|
||||
/**
|
||||
* 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless
|
||||
* SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning
|
||||
* 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config
|
||||
*/
|
||||
spi_timing_config_psram_set_din_mode_num(0, din_mode, din_num);
|
||||
}
|
||||
|
||||
void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy)
|
||||
{
|
||||
#if CONFIG_SPIRAM_MODE_OCT
|
||||
//On 728, for SPI1, flash and psram share the extra dummy register
|
||||
spi_timing_config_flash_set_extra_dummy(1, extra_dummy);
|
||||
#elif CONFIG_SPIRAM_MODE_QUAD
|
||||
//Update this `s_psram_extra_dummy`, the `s_psram_read_data` will set dummy according to this `s_psram_extra_dummy`
|
||||
s_psram_extra_dummy = extra_dummy;
|
||||
SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_USR_DUMMY); // dummy en
|
||||
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(1), SPI_MEM_USR_DUMMY_CYCLELEN_V, extra_dummy - 1, SPI_MEM_USR_DUMMY_CYCLELEN_S);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
|
||||
|
||||
@@ -18,81 +18,163 @@ extern "C" {
|
||||
|
||||
#define SPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num
|
||||
#define SPI_TIMING_TEST_DATA_LEN 64
|
||||
|
||||
#define SPI_TIMING_PSRAM_TEST_DATA_ADDR 0
|
||||
#define SPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET
|
||||
/**
|
||||
* @note BACKGOURND:
|
||||
*
|
||||
* The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock:
|
||||
*
|
||||
* PLL ----| |---- FLASH Module Clock
|
||||
* XTAL ----|----> Core Clock ---->|
|
||||
* RTC8M ----| |---- PSRAM Module Clock
|
||||
*
|
||||
*
|
||||
* DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled.
|
||||
* Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ...
|
||||
*
|
||||
* Module with speed lower than 120M SDR doesn't need to be tuned
|
||||
*
|
||||
* @note LIMITATION:
|
||||
* How to determine the core clock on 728. There are 2 limitations.
|
||||
*
|
||||
* 1. MSPI FLASH and PSRAM share the core clock register. Therefore:
|
||||
* SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
*
|
||||
* 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
|
||||
*/
|
||||
//--------------------------------------FLASH Sampling Mode --------------------------------------//
|
||||
#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR)
|
||||
#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || !CONFIG_ESPTOOLPY_OCT_FLASH)
|
||||
//--------------------------------------FLASH Module Clock --------------------------------------//
|
||||
#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
|
||||
#define SPI_TIMING_FLASH_MODULE_CLOCK 20
|
||||
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
|
||||
#define SPI_TIMING_FLASH_MODULE_CLOCK 40
|
||||
#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
|
||||
#define SPI_TIMING_FLASH_MODULE_CLOCK 80
|
||||
#else //CONFIG_ESPTOOLPY_FLASHFREQ_120M
|
||||
#define SPI_TIMING_FLASH_MODULE_CLOCK 120
|
||||
#endif
|
||||
//------------------------------------FLASH Needs Tuning or not-------------------------------------//
|
||||
#if SPI_TIMING_FLASH_DTR_MODE
|
||||
#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 40)
|
||||
#elif SPI_TIMING_FLASH_STR_MODE
|
||||
#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 80)
|
||||
#endif
|
||||
|
||||
//-------------------------------------------FLASH Operation Mode and Corresponding Timing Tuning Parameter Table --------------------------------------//
|
||||
#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR)
|
||||
#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || !CONFIG_ESPTOOLPY_OCT_FLASH)
|
||||
//--------------------------------------PSRAM Sampling Mode --------------------------------------//
|
||||
#define SPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT
|
||||
#define SPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT
|
||||
//--------------------------------------PSRAM Module Clock --------------------------------------//
|
||||
#if CONFIG_ESP32S3_SPIRAM_SUPPORT
|
||||
#if CONFIG_SPIRAM_SPEED_40M
|
||||
#define SPI_TIMING_PSRAM_MODULE_CLOCK 40
|
||||
#elif CONFIG_SPIRAM_SPEED_80M
|
||||
#define SPI_TIMING_PSRAM_MODULE_CLOCK 80
|
||||
#else //CONFIG_SPIRAM_SPEED_120M
|
||||
#define SPI_TIMING_PSRAM_MODULE_CLOCK 120
|
||||
#endif
|
||||
#else //Disable PSRAM
|
||||
#define SPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `SPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter
|
||||
#endif
|
||||
//------------------------------------PSRAM Needs Tuning or not-------------------------------------//
|
||||
#if SPI_TIMING_PSRAM_DTR_MODE
|
||||
#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 40)
|
||||
#elif SPI_TIMING_PSRAM_STR_MODE
|
||||
#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 80)
|
||||
#endif
|
||||
|
||||
/* Determine A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ*/
|
||||
//OCTAL FLASH
|
||||
#if CONFIG_ESPTOOLPY_OCT_FLASH
|
||||
|
||||
//OCT FLASH 80M DTR
|
||||
/**
|
||||
* @note Define A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
*/
|
||||
/**
|
||||
* Due to MSPI core clock is used by both MSPI Flash and PSRAM clock,
|
||||
* define the STR/DTR mode here for selecting the core clock:
|
||||
* @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2
|
||||
*/
|
||||
#if (SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE)
|
||||
#define SPI_TIMING_CORE_CLOCK_DIV 2
|
||||
#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE || !CONFIG_ESP32S3_SPIRAM_SUPPORT))
|
||||
#define SPI_TIMING_CORE_CLOCK_DIV 1
|
||||
#endif
|
||||
|
||||
///////////////////////////////////// FLASH CORE CLOCK /////////////////////////////////////
|
||||
//FLASH 80M DTR
|
||||
#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
|
||||
#endif
|
||||
|
||||
//OCT FLASH 120M DTR
|
||||
//FLASH 120M DTR
|
||||
#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
|
||||
#endif
|
||||
|
||||
//OCT FLASH 120M STR
|
||||
//FLASH 120M STR
|
||||
#if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
|
||||
#if (SPI_TIMING_CORE_CLOCK_DIV == 2)
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
|
||||
#elif (SPI_TIMING_CORE_CLOCK_DIV == 1)
|
||||
#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120
|
||||
#endif
|
||||
#endif //FLASH 120M STR
|
||||
|
||||
#endif //#if CONFIG_ESPTOOLPY_OCT_FLASH
|
||||
/* QUAD FLASH Operation Mode should be added here if needed */
|
||||
|
||||
|
||||
//---------------------------------------PSRAM Operation Mode and Corresponding Timing Tuning Parameter Table--------------------------------------//
|
||||
#define SPI_TIMING_PSRAM_DTR_MODE 1 //Currently we only support DTR Octal PSRAM
|
||||
#define SPI_TIMING_PSRAM_STR_MODE 0
|
||||
|
||||
//OCTAL PSRAM
|
||||
#if CONFIG_SPIRAM_MODE_OCT
|
||||
|
||||
//OCT 80M PSRAM
|
||||
///////////////////////////////////// PSRAM CORE CLOCK /////////////////////////////////////
|
||||
//PSRAM 80M DTR
|
||||
#if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M
|
||||
#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160
|
||||
#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160
|
||||
#endif
|
||||
|
||||
#endif //#if CONFIG_SPIRAM_MODE_OCT
|
||||
/* QUAD PSRAM Operation Mode should be added here if needed */
|
||||
|
||||
|
||||
//------------------------------------------Get the timing tuning config-----------------------------------------------//
|
||||
#ifdef SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
//FLASH needs tuning, and it expects this core clock: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
#define SPI_TIMING_FLASH_NEEDS_TUNING 1
|
||||
//PSRAM 120M STR
|
||||
#if SPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M
|
||||
#if (SPI_TIMING_CORE_CLOCK_DIV == 2)
|
||||
#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240
|
||||
#elif (SPI_TIMING_CORE_CLOCK_DIV == 1)
|
||||
#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120
|
||||
#endif
|
||||
#endif //PSRAM 120M STR
|
||||
|
||||
#ifdef SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
//PSRAM needs tuning, and it expects this core clock: SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
#define SPI_TIMING_PSRAM_NEEDS_TUNING 1
|
||||
#endif
|
||||
|
||||
//If both FLASH and PSRAM need tuning, the core clock should be same
|
||||
//------------------------------------------Determine the Core Clock-----------------------------------------------//
|
||||
/**
|
||||
* @note
|
||||
* Limitation 1:
|
||||
* On 728, MSPI FLASH and PSRAM share the core clock register. Therefore,
|
||||
* the expected CORE CLOCK frequencies should be the same.
|
||||
*/
|
||||
#if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
|
||||
_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported");
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
|
||||
//If only FLASH needs tuning, the core clock could be as FLASH expected
|
||||
//If only FLASH needs tuning, the core clock COULD be as FLASH expected
|
||||
#elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
|
||||
|
||||
//If only PSRAM needs tuning, the core clock could be as PSRAM expected
|
||||
//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected
|
||||
#elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
_Static_assert(SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
|
||||
|
||||
#else
|
||||
#define SPI_TIMING_CORE_CLOCK_MHZ 80
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @note
|
||||
* Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
|
||||
*/
|
||||
#define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n))
|
||||
|
||||
#if SPI_TIMING_FLASH_DTR_MODE
|
||||
_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
|
||||
#endif
|
||||
#if SPI_TIMING_PSRAM_DTR_MODE
|
||||
_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
|
||||
#endif
|
||||
|
||||
|
||||
//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
|
||||
#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
|
||||
(spi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
|
||||
@@ -151,6 +233,15 @@ void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dumm
|
||||
void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len);
|
||||
void spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len);
|
||||
|
||||
/*-------------------------------------------------------------------------------------------------
|
||||
* SPI1 Timing Tuning APIs
|
||||
* These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for
|
||||
* configuring SPI1 timing tuning related registers to find best tuning parameter
|
||||
*-------------------------------------------------------------------------------------------------*/
|
||||
void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num);
|
||||
void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy);
|
||||
void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num);
|
||||
void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user