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Merge branch 'feat/mspi_suspend_p4_eco5' into 'master'

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feat(spi_flash): Support flash suspend on esp32p4 resivion 3

Closes IDF-13511

See merge request espressif/esp-idf!42104
This commit is contained in:
C.S.M
2025-09-30 15:14:09 +08:00
parent 19cc026b0c f022b67486
commit a417158514
14 changed files with 3005 additions and 651 deletions
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15
components/esp_hal_mspi/esp32p4/include/hal/spimem_flash_ll.h
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@@ -30,6 +30,7 @@
#include "hal/efuse_hal.h" #include "hal/efuse_hal.h"
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "hal/clk_tree_ll.h" #include "hal/clk_tree_ll.h"
#include "hal/config.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -230,6 +231,20 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
dev->sus_status.flash_per_dly_128 = 1; dev->sus_status.flash_per_dly_128 = 1;
} }
#if (HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300)
/**
* Configure the delay after Resume
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
*/
static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_per = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
}
#endif
/** /**
* Configure the cs hold delay time(used to set the minimum CS high time tSHSL) * Configure the cs hold delay time(used to set the minimum CS high time tSHSL)
* *

2
components/esp_hal_mspi/spi_flash_hal_iram.c
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@@ -155,9 +155,11 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host)
uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0);
spimem_flash_ll_set_sus_delay(dev, tsus); spimem_flash_ll_set_sus_delay(dev, tsus);
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#if (HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300) && SOC_IS(ESP32P4)
// trs = ceil(ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); // trs = ceil(ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles);
uint32_t trs = (ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->trs_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); uint32_t trs = (ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->trs_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0);
spimem_flash_ll_set_rs_delay(dev, trs); spimem_flash_ll_set_rs_delay(dev, trs);
#endif
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
// tshsl2 = ceil(SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() * 0.001); // tshsl2 = ceil(SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() * 0.001);
uint32_t tshsl2 = (SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() / 1000) + ((SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz()) % 1000 != 0); uint32_t tshsl2 = (SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() / 1000) + ((SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz()) % 1000 != 0);

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -1591,6 +1591,10 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool bool
default y default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool bool
default y default y

1
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -593,6 +593,7 @@
#define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1) #define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1) #define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1) #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1)

144
components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h
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@@ -33,8 +33,9 @@ extern "C" {
#define SPI1_MEM_C_SLV_ST_S 4 #define SPI1_MEM_C_SLV_ST_S 4
/** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; /** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
* In user mode, it is set to indicate that program/erase operation will be triggered. * In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the * The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable. * operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_PE (BIT(17)) #define SPI1_MEM_C_FLASH_PE (BIT(17))
#define SPI1_MEM_C_FLASH_PE_M (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S) #define SPI1_MEM_C_FLASH_PE_M (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S)
@@ -51,6 +52,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; /** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation * Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable. * done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_HPM (BIT(19)) #define SPI1_MEM_C_FLASH_HPM (BIT(19))
#define SPI1_MEM_C_FLASH_HPM_M (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S) #define SPI1_MEM_C_FLASH_HPM_M (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S)
@@ -60,6 +62,7 @@ extern "C" {
* This bit combined with reg_resandres bit releases Flash from the power-down state * This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once * or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable. * the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_RES (BIT(20)) #define SPI1_MEM_C_FLASH_RES (BIT(20))
#define SPI1_MEM_C_FLASH_RES_M (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S) #define SPI1_MEM_C_FLASH_RES_M (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S)
@@ -68,6 +71,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; /** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set. * Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable. * The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_DP (BIT(21)) #define SPI1_MEM_C_FLASH_DP (BIT(21))
#define SPI1_MEM_C_FLASH_DP_M (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S) #define SPI1_MEM_C_FLASH_DP_M (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S)
@@ -76,6 +80,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; /** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The * Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable. * bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_CE (BIT(22)) #define SPI1_MEM_C_FLASH_CE (BIT(22))
#define SPI1_MEM_C_FLASH_CE_M (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S) #define SPI1_MEM_C_FLASH_CE_M (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S)
@@ -84,6 +89,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; /** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is * Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_BE (BIT(23)) #define SPI1_MEM_C_FLASH_BE (BIT(23))
#define SPI1_MEM_C_FLASH_BE_M (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S) #define SPI1_MEM_C_FLASH_BE_M (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S)
@@ -92,6 +98,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; /** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_SE (BIT(24)) #define SPI1_MEM_C_FLASH_SE (BIT(24))
#define SPI1_MEM_C_FLASH_SE_M (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S) #define SPI1_MEM_C_FLASH_SE_M (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S)
@@ -101,6 +108,7 @@ extern "C" {
* Page program enable(1 byte ~256 bytes data to be programmed). Page program * Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the * operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable. * operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_PP (BIT(25)) #define SPI1_MEM_C_FLASH_PP (BIT(25))
#define SPI1_MEM_C_FLASH_PP_M (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S) #define SPI1_MEM_C_FLASH_PP_M (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S)
@@ -109,6 +117,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; /** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the * Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable. * bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_WRSR (BIT(26)) #define SPI1_MEM_C_FLASH_WRSR (BIT(26))
#define SPI1_MEM_C_FLASH_WRSR_M (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S) #define SPI1_MEM_C_FLASH_WRSR_M (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S)
@@ -117,6 +126,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; /** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is * Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_RDSR (BIT(27)) #define SPI1_MEM_C_FLASH_RDSR (BIT(27))
#define SPI1_MEM_C_FLASH_RDSR_M (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S) #define SPI1_MEM_C_FLASH_RDSR_M (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S)
@@ -125,6 +135,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; /** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable. * cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_RDID (BIT(28)) #define SPI1_MEM_C_FLASH_RDID (BIT(28))
#define SPI1_MEM_C_FLASH_RDID_M (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S) #define SPI1_MEM_C_FLASH_RDID_M (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S)
@@ -133,6 +144,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; /** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The * Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_WRDI (BIT(29)) #define SPI1_MEM_C_FLASH_WRDI (BIT(29))
#define SPI1_MEM_C_FLASH_WRDI_M (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S) #define SPI1_MEM_C_FLASH_WRDI_M (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S)
@@ -141,6 +153,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; /** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit * Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable. * will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_WREN (BIT(30)) #define SPI1_MEM_C_FLASH_WREN (BIT(30))
#define SPI1_MEM_C_FLASH_WREN_M (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S) #define SPI1_MEM_C_FLASH_WREN_M (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S)
@@ -149,6 +162,7 @@ extern "C" {
/** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; /** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The * Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FLASH_READ (BIT(31)) #define SPI1_MEM_C_FLASH_READ (BIT(31))
#define SPI1_MEM_C_FLASH_READ_M (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S) #define SPI1_MEM_C_FLASH_READ_M (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S)
@@ -226,6 +240,7 @@ extern "C" {
/** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0; /** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active * For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low. * low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_C_FCS_CRC_EN (BIT(10))
#define SPI1_MEM_C_FCS_CRC_EN_M (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S) #define SPI1_MEM_C_FCS_CRC_EN_M (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S)
@@ -233,14 +248,15 @@ extern "C" {
#define SPI1_MEM_C_FCS_CRC_EN_S 10 #define SPI1_MEM_C_FCS_CRC_EN_S 10
/** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0; /** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_TX_CRC_EN (BIT(11)) #define SPI1_MEM_C_TX_CRC_EN (BIT(11))
#define SPI1_MEM_C_TX_CRC_EN_M (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S) #define SPI1_MEM_C_TX_CRC_EN_M (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S)
#define SPI1_MEM_C_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_C_TX_CRC_EN_V 0x00000001U
#define SPI1_MEM_C_TX_CRC_EN_S 11 #define SPI1_MEM_C_TX_CRC_EN_S 11
/** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; /** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
* This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
* and spi1_mem_c_fread_dout. 1: enable 0: disable. * and spi_mem_fread_dout. 1: enable 0: disable.
*/ */
#define SPI1_MEM_C_FASTRD_MODE (BIT(13)) #define SPI1_MEM_C_FASTRD_MODE (BIT(13))
#define SPI1_MEM_C_FASTRD_MODE_M (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S) #define SPI1_MEM_C_FASTRD_MODE_M (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S)
@@ -255,7 +271,8 @@ extern "C" {
#define SPI1_MEM_C_FREAD_DUAL_S 14 #define SPI1_MEM_C_FREAD_DUAL_S 14
/** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1; /** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with
* spi1_mem_c_flash_res bit. 1: enable 0: disable. * spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_RESANDRES (BIT(15)) #define SPI1_MEM_C_RESANDRES (BIT(15))
#define SPI1_MEM_C_RESANDRES_M (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S) #define SPI1_MEM_C_RESANDRES_M (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S)
@@ -292,6 +309,7 @@ extern "C" {
/** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0; /** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0: * two bytes data will be written to status register when it is set. 1: enable 0:
* disable. * disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_WRSR_2B (BIT(22)) #define SPI1_MEM_C_WRSR_2B (BIT(22))
#define SPI1_MEM_C_WRSR_2B_M (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S) #define SPI1_MEM_C_WRSR_2B_M (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S)
@@ -328,13 +346,30 @@ extern "C" {
#define SPI1_MEM_C_CLK_MODE_V 0x00000003U #define SPI1_MEM_C_CLK_MODE_V 0x00000003U
#define SPI1_MEM_C_CLK_MODE_S 0 #define SPI1_MEM_C_CLK_MODE_S 0
/** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; /** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] *
* SPI_CLK cycles. * 512) SPI_CLK cycles.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES 0x000003FFU
#define SPI1_MEM_C_CS_HOLD_DLY_RES_M (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S) #define SPI1_MEM_C_CS_HOLD_DLY_RES_M (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S)
#define SPI1_MEM_C_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES_V 0x000003FFU
#define SPI1_MEM_C_CS_HOLD_DLY_RES_S 2 #define SPI1_MEM_C_CS_HOLD_DLY_RES_S 2
/** SPI1_MEM_C_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511;
* After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
#define SPI1_MEM_C_CS_HOLD_DLY_PER 0x000001FFU
#define SPI1_MEM_C_CS_HOLD_DLY_PER_M (SPI1_MEM_C_CS_HOLD_DLY_PER_V << SPI1_MEM_C_CS_HOLD_DLY_PER_S)
#define SPI1_MEM_C_CS_HOLD_DLY_PER_V 0x000001FFU
#define SPI1_MEM_C_CS_HOLD_DLY_PER_S 12
/** SPI1_MEM_C_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN (BIT(23))
#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S)
#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V 0x00000001U
#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S 23
/** SPI1_MEM_C_CTRL2_REG register /** SPI1_MEM_C_CTRL2_REG register
* SPI1 control2 register. * SPI1 control2 register.
@@ -353,22 +388,22 @@ extern "C" {
*/ */
#define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14) #define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14)
/** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; /** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi1_mem_c_clkcnt_N. * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N.
*/ */
#define SPI1_MEM_C_CLKCNT_L 0x000000FFU #define SPI1_MEM_C_CLKCNT_L 0x000000FFU
#define SPI1_MEM_C_CLKCNT_L_M (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S) #define SPI1_MEM_C_CLKCNT_L_M (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S)
#define SPI1_MEM_C_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_L_V 0x000000FFU
#define SPI1_MEM_C_CLKCNT_L_S 0 #define SPI1_MEM_C_CLKCNT_L_S 0
/** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; /** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1).
*/ */
#define SPI1_MEM_C_CLKCNT_H 0x000000FFU #define SPI1_MEM_C_CLKCNT_H 0x000000FFU
#define SPI1_MEM_C_CLKCNT_H_M (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S) #define SPI1_MEM_C_CLKCNT_H_M (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S)
#define SPI1_MEM_C_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_H_V 0x000000FFU
#define SPI1_MEM_C_CLKCNT_H_S 8 #define SPI1_MEM_C_CLKCNT_H_S 8
/** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; /** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi1_mem_c_clkcnt_N+1) * system/(SPI1_MEM_C_CLKCNT_N+1)
*/ */
#define SPI1_MEM_C_CLKCNT_N 0x000000FFU #define SPI1_MEM_C_CLKCNT_N 0x000000FFU
#define SPI1_MEM_C_CLKCNT_N_M (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S) #define SPI1_MEM_C_CLKCNT_N_M (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S)
@@ -387,7 +422,7 @@ extern "C" {
*/ */
#define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18) #define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18)
/** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; /** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
* the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/ */
#define SPI1_MEM_C_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_C_CK_OUT_EDGE (BIT(9))
#define SPI1_MEM_C_CK_OUT_EDGE_M (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S) #define SPI1_MEM_C_CK_OUT_EDGE_M (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S)
@@ -422,16 +457,18 @@ extern "C" {
#define SPI1_MEM_C_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_C_FWRITE_QIO_V 0x00000001U
#define SPI1_MEM_C_FWRITE_QIO_S 15 #define SPI1_MEM_C_FWRITE_QIO_S 15
/** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0; /** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
* read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_USR_MISO_HIGHPART (BIT(24)) #define SPI1_MEM_C_USR_MISO_HIGHPART (BIT(24))
#define SPI1_MEM_C_USR_MISO_HIGHPART_M (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S) #define SPI1_MEM_C_USR_MISO_HIGHPART_M (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S)
#define SPI1_MEM_C_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_C_USR_MISO_HIGHPART_V 0x00000001U
#define SPI1_MEM_C_USR_MISO_HIGHPART_S 24 #define SPI1_MEM_C_USR_MISO_HIGHPART_S 24
/** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0; /** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
* write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_USR_MOSI_HIGHPART (BIT(25)) #define SPI1_MEM_C_USR_MOSI_HIGHPART (BIT(25))
#define SPI1_MEM_C_USR_MOSI_HIGHPART_M (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S) #define SPI1_MEM_C_USR_MOSI_HIGHPART_M (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S)
@@ -485,7 +522,7 @@ extern "C" {
*/ */
#define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c) #define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c)
/** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; /** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be * The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1). * (cycle_num-1).
*/ */
#define SPI1_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU #define SPI1_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU
@@ -548,14 +585,15 @@ extern "C" {
*/ */
#define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c) #define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c)
/** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0; /** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/ */
#define SPI1_MEM_C_STATUS 0x0000FFFFU #define SPI1_MEM_C_STATUS 0x0000FFFFU
#define SPI1_MEM_C_STATUS_M (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S) #define SPI1_MEM_C_STATUS_M (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S)
#define SPI1_MEM_C_STATUS_V 0x0000FFFFU #define SPI1_MEM_C_STATUS_V 0x0000FFFFU
#define SPI1_MEM_C_STATUS_S 0 #define SPI1_MEM_C_STATUS_S 0
/** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; /** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_WB_MODE 0x000000FFU #define SPI1_MEM_C_WB_MODE 0x000000FFU
#define SPI1_MEM_C_WB_MODE_M (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S) #define SPI1_MEM_C_WB_MODE_M (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S)
@@ -599,10 +637,13 @@ extern "C" {
/** SPI1_MEM_C_TX_CRC_REG register /** SPI1_MEM_C_TX_CRC_REG register
* SPI1 TX CRC data register. * SPI1 TX CRC data register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/ */
#define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38) #define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38)
/** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; /** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
* For SPI1, the value of crc32. * For SPI1, the value of crc32.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_TX_CRC_DATA 0xFFFFFFFFU #define SPI1_MEM_C_TX_CRC_DATA 0xFFFFFFFFU
#define SPI1_MEM_C_TX_CRC_DATA_M (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S) #define SPI1_MEM_C_TX_CRC_DATA_M (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S)
@@ -611,10 +652,13 @@ extern "C" {
/** SPI1_MEM_C_CACHE_FCTRL_REG register /** SPI1_MEM_C_CACHE_FCTRL_REG register
* SPI1 bit mode control register. * SPI1 bit mode control register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/ */
#define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c) #define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c)
/** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; /** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1))
#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S) #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S)
@@ -622,7 +666,8 @@ extern "C" {
#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S 1
/** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; /** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi1_mem_c_fread_dio. * spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FDIN_DUAL (BIT(3)) #define SPI1_MEM_C_FDIN_DUAL (BIT(3))
#define SPI1_MEM_C_FDIN_DUAL_M (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S) #define SPI1_MEM_C_FDIN_DUAL_M (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S)
@@ -630,7 +675,8 @@ extern "C" {
#define SPI1_MEM_C_FDIN_DUAL_S 3 #define SPI1_MEM_C_FDIN_DUAL_S 3
/** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; /** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_C_FDOUT_DUAL (BIT(4))
#define SPI1_MEM_C_FDOUT_DUAL_M (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S) #define SPI1_MEM_C_FDOUT_DUAL_M (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S)
@@ -638,7 +684,8 @@ extern "C" {
#define SPI1_MEM_C_FDOUT_DUAL_S 4 #define SPI1_MEM_C_FDOUT_DUAL_S 4
/** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; /** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FADDR_DUAL (BIT(5)) #define SPI1_MEM_C_FADDR_DUAL (BIT(5))
#define SPI1_MEM_C_FADDR_DUAL_M (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S) #define SPI1_MEM_C_FADDR_DUAL_M (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S)
@@ -646,7 +693,8 @@ extern "C" {
#define SPI1_MEM_C_FADDR_DUAL_S 5 #define SPI1_MEM_C_FADDR_DUAL_S 5
/** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; /** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FDIN_QUAD (BIT(6)) #define SPI1_MEM_C_FDIN_QUAD (BIT(6))
#define SPI1_MEM_C_FDIN_QUAD_M (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S) #define SPI1_MEM_C_FDIN_QUAD_M (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S)
@@ -654,7 +702,8 @@ extern "C" {
#define SPI1_MEM_C_FDIN_QUAD_S 6 #define SPI1_MEM_C_FDIN_QUAD_S 6
/** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; /** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_C_FDOUT_QUAD (BIT(7))
#define SPI1_MEM_C_FDOUT_QUAD_M (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S) #define SPI1_MEM_C_FDOUT_QUAD_M (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S)
@@ -662,7 +711,8 @@ extern "C" {
#define SPI1_MEM_C_FDOUT_QUAD_S 7 #define SPI1_MEM_C_FDOUT_QUAD_S 7
/** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; /** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_C_FADDR_QUAD (BIT(8)) #define SPI1_MEM_C_FADDR_QUAD (BIT(8))
#define SPI1_MEM_C_FADDR_QUAD_M (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S) #define SPI1_MEM_C_FADDR_QUAD_M (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S)
@@ -891,8 +941,8 @@ extern "C" {
#define SPI1_MEM_C_WAITI_ADDR_EN_S 2 #define SPI1_MEM_C_WAITI_ADDR_EN_S 2
/** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; /** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
* When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is
* (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active
* SPI1_MEM_C_WAITI_ADDR_EN is cleared. * when SPI1_MEM_C_WAITI_ADDR_EN is cleared.
*/ */
#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN 0x00000003U
#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S) #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S)
@@ -1010,8 +1060,8 @@ extern "C" {
#define SPI1_MEM_C_PES_END_EN_V 0x00000001U #define SPI1_MEM_C_PES_END_EN_V 0x00000001U
#define SPI1_MEM_C_PES_END_EN_S 24 #define SPI1_MEM_C_PES_END_EN_S 24
/** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; /** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
* When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times,
* will be treated as check pass. * it will be treated as check pass.
*/ */
#define SPI1_MEM_C_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_C_SUS_TIMEOUT_CNT 0x0000007FU
#define SPI1_MEM_C_SUS_TIMEOUT_CNT_M (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S) #define SPI1_MEM_C_SUS_TIMEOUT_CNT_M (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S)
@@ -1059,8 +1109,8 @@ extern "C" {
#define SPI1_MEM_C_WAIT_PESR_CMD_2B_S 1 #define SPI1_MEM_C_WAIT_PESR_CMD_2B_S 1
/** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; /** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after HPM command is sent. * cycles after HPM command is sent.
*/ */
#define SPI1_MEM_C_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_C_FLASH_HPM_DLY_128 (BIT(2))
#define SPI1_MEM_C_FLASH_HPM_DLY_128_M (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S) #define SPI1_MEM_C_FLASH_HPM_DLY_128_M (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S)
@@ -1068,8 +1118,8 @@ extern "C" {
#define SPI1_MEM_C_FLASH_HPM_DLY_128_S 2 #define SPI1_MEM_C_FLASH_HPM_DLY_128_S 2
/** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; /** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after RES command is sent. * cycles after RES command is sent.
*/ */
#define SPI1_MEM_C_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_C_FLASH_RES_DLY_128 (BIT(3))
#define SPI1_MEM_C_FLASH_RES_DLY_128_M (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S) #define SPI1_MEM_C_FLASH_RES_DLY_128_M (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S)
@@ -1077,8 +1127,8 @@ extern "C" {
#define SPI1_MEM_C_FLASH_RES_DLY_128_S 3 #define SPI1_MEM_C_FLASH_RES_DLY_128_S 3
/** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; /** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after DP command is sent. * cycles after DP command is sent.
*/ */
#define SPI1_MEM_C_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_C_FLASH_DP_DLY_128 (BIT(4))
#define SPI1_MEM_C_FLASH_DP_DLY_128_M (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S) #define SPI1_MEM_C_FLASH_DP_DLY_128_M (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S)
@@ -1086,9 +1136,9 @@ extern "C" {
#define SPI1_MEM_C_FLASH_DP_DLY_128_S 4 #define SPI1_MEM_C_FLASH_DP_DLY_128_S 4
/** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; /** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
* Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
* SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
* sent. * command is sent.
*/ */
#define SPI1_MEM_C_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_C_FLASH_PER_DLY_128 (BIT(5))
#define SPI1_MEM_C_FLASH_PER_DLY_128_M (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S) #define SPI1_MEM_C_FLASH_PER_DLY_128_M (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S)
@@ -1096,9 +1146,9 @@ extern "C" {
#define SPI1_MEM_C_FLASH_PER_DLY_128_S 5 #define SPI1_MEM_C_FLASH_PER_DLY_128_S 5
/** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; /** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
* Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
* SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
* sent. * command is sent.
*/ */
#define SPI1_MEM_C_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_C_FLASH_PES_DLY_128 (BIT(6))
#define SPI1_MEM_C_FLASH_PES_DLY_128_M (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S) #define SPI1_MEM_C_FLASH_PES_DLY_128_M (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S)
@@ -1242,16 +1292,16 @@ extern "C" {
#define SPI1_MEM_C_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_PES_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_C_PES_END_INT_RAW_S 1 #define SPI1_MEM_C_PES_END_INT_RAW_S 1
/** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; /** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when
* is sent and flash is already idle. 0: Others. * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
*/ */
#define SPI1_MEM_C_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_C_WPE_END_INT_RAW (BIT(2))
#define SPI1_MEM_C_WPE_END_INT_RAW_M (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S) #define SPI1_MEM_C_WPE_END_INT_RAW_M (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S)
#define SPI1_MEM_C_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_WPE_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_C_WPE_END_INT_RAW_S 2 #define SPI1_MEM_C_WPE_END_INT_RAW_S 2
/** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; /** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
* changed from non idle state to idle state. It means that SPI_CS raises high. 0: * is changed from non idle state to idle state. It means that SPI_CS raises high. 0:
* Others * Others
*/ */
#define SPI1_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) #define SPI1_MEM_C_SLV_ST_END_INT_RAW (BIT(3))
@@ -1259,8 +1309,8 @@ extern "C" {
#define SPI1_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_C_SLV_ST_END_INT_RAW_S 3 #define SPI1_MEM_C_SLV_ST_END_INT_RAW_S 3
/** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; /** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
* changed from non idle state to idle state. 0: Others. * is changed from non idle state to idle state. 0: Others.
*/ */
#define SPI1_MEM_C_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_C_MST_ST_END_INT_RAW (BIT(4))
#define SPI1_MEM_C_MST_ST_END_INT_RAW_M (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S) #define SPI1_MEM_C_MST_ST_END_INT_RAW_M (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S)
@@ -1379,8 +1429,8 @@ extern "C" {
#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S 14 #define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S 14
/** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; /** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS. * negative edge of SPI_DQS.
*/ */
#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP (BIT(21)) #define SPI1_MEM_C_FMEM_DDR_DQS_LOOP (BIT(21))
@@ -1468,7 +1518,7 @@ extern "C" {
* Version control register * Version control register
*/ */
#define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc) #define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc)
/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128; /** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 38801712;
* Version control register * Version control register
*/ */
#define SPI1_MEM_C_DATE 0x0FFFFFFFU #define SPI1_MEM_C_DATE 0x0FFFFFFFU

138
components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h
View File

@@ -29,8 +29,9 @@ typedef union {
uint32_t reserved_8:9; uint32_t reserved_8:9;
/** flash_pe : R/W/SC; bitpos: [17]; default: 0; /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
* In user mode, it is set to indicate that program/erase operation will be triggered. * In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the * The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable. * operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_pe:1; uint32_t flash_pe:1;
/** usr : R/W/SC; bitpos: [18]; default: 0; /** usr : R/W/SC; bitpos: [18]; default: 0;
@@ -41,68 +42,81 @@ typedef union {
/** flash_hpm : R/W/SC; bitpos: [19]; default: 0; /** flash_hpm : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation * Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable. * done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_hpm:1; uint32_t flash_hpm:1;
/** flash_res : R/W/SC; bitpos: [20]; default: 0; /** flash_res : R/W/SC; bitpos: [20]; default: 0;
* This bit combined with reg_resandres bit releases Flash from the power-down state * This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once * or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable. * the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_res:1; uint32_t flash_res:1;
/** flash_dp : R/W/SC; bitpos: [21]; default: 0; /** flash_dp : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set. * Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable. * The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_dp:1; uint32_t flash_dp:1;
/** flash_ce : R/W/SC; bitpos: [22]; default: 0; /** flash_ce : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The * Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable. * bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_ce:1; uint32_t flash_ce:1;
/** flash_be : R/W/SC; bitpos: [23]; default: 0; /** flash_be : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is * Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_be:1; uint32_t flash_be:1;
/** flash_se : R/W/SC; bitpos: [24]; default: 0; /** flash_se : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_se:1; uint32_t flash_se:1;
/** flash_pp : R/W/SC; bitpos: [25]; default: 0; /** flash_pp : R/W/SC; bitpos: [25]; default: 0;
* Page program enable(1 byte ~256 bytes data to be programmed). Page program * Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the * operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable. * operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_pp:1; uint32_t flash_pp:1;
/** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the * Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable. * bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wrsr:1; uint32_t flash_wrsr:1;
/** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is * Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_rdsr:1; uint32_t flash_rdsr:1;
/** flash_rdid : R/W/SC; bitpos: [28]; default: 0; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable. * cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_rdid:1; uint32_t flash_rdid:1;
/** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The * Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wrdi:1; uint32_t flash_wrdi:1;
/** flash_wren : R/W/SC; bitpos: [30]; default: 0; /** flash_wren : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit * Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable. * will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wren:1; uint32_t flash_wren:1;
/** flash_read : R/W/SC; bitpos: [31]; default: 0; /** flash_read : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The * Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_read:1; uint32_t flash_read:1;
}; };
@@ -130,7 +144,7 @@ typedef union {
struct { struct {
uint32_t reserved_0:9; uint32_t reserved_0:9;
/** ck_out_edge : R/W; bitpos: [9]; default: 0; /** ck_out_edge : R/W; bitpos: [9]; default: 0;
* the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/ */
uint32_t ck_out_edge:1; uint32_t ck_out_edge:1;
uint32_t reserved_10:2; uint32_t reserved_10:2;
@@ -152,13 +166,15 @@ typedef union {
uint32_t fwrite_qio:1; uint32_t fwrite_qio:1;
uint32_t reserved_16:8; uint32_t reserved_16:8;
/** usr_miso_highpart : HRO; bitpos: [24]; default: 0; /** usr_miso_highpart : HRO; bitpos: [24]; default: 0;
* read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t usr_miso_highpart:1; uint32_t usr_miso_highpart:1;
/** usr_mosi_highpart : HRO; bitpos: [25]; default: 0; /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0;
* write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t usr_mosi_highpart:1; uint32_t usr_mosi_highpart:1;
/** usr_dummy_idle : R/W; bitpos: [26]; default: 0; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
@@ -195,7 +211,7 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
* The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be * The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1). * (cycle_num-1).
*/ */
uint32_t usr_dummy_cyclelen:6; uint32_t usr_dummy_cyclelen:6;
@@ -268,16 +284,18 @@ typedef union {
/** fcs_crc_en : HRO; bitpos: [10]; default: 0; /** fcs_crc_en : HRO; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active * For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low. * low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fcs_crc_en:1; uint32_t fcs_crc_en:1;
/** tx_crc_en : HRO; bitpos: [11]; default: 0; /** tx_crc_en : HRO; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t tx_crc_en:1; uint32_t tx_crc_en:1;
uint32_t reserved_12:1; uint32_t reserved_12:1;
/** fastrd_mode : R/W; bitpos: [13]; default: 1; /** fastrd_mode : R/W; bitpos: [13]; default: 1;
* This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
* and spi1_mem_c_fread_dout. 1: enable 0: disable. * and spi_mem_fread_dout. 1: enable 0: disable.
*/ */
uint32_t fastrd_mode:1; uint32_t fastrd_mode:1;
/** fread_dual : R/W; bitpos: [14]; default: 0; /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -286,7 +304,8 @@ typedef union {
uint32_t fread_dual:1; uint32_t fread_dual:1;
/** resandres : R/W; bitpos: [15]; default: 1; /** resandres : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with
* spi1_mem_c_flash_res bit. 1: enable 0: disable. * spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t resandres:1; uint32_t resandres:1;
uint32_t reserved_16:2; uint32_t reserved_16:2;
@@ -309,6 +328,7 @@ typedef union {
/** wrsr_2b : R/W; bitpos: [22]; default: 0; /** wrsr_2b : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0: * two bytes data will be written to status register when it is set. 1: enable 0:
* disable. * disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t wrsr_2b:1; uint32_t wrsr_2b:1;
/** fread_dio : R/W; bitpos: [23]; default: 0; /** fread_dio : R/W; bitpos: [23]; default: 0;
@@ -338,11 +358,23 @@ typedef union {
*/ */
uint32_t clk_mode:2; uint32_t clk_mode:2;
/** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] *
* SPI_CLK cycles. * 512) SPI_CLK cycles.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t cs_hold_dly_res:10; uint32_t cs_hold_dly_res:10;
uint32_t reserved_12:20; /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511;
* After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
uint32_t cs_hold_dly_per:9;
uint32_t reserved_21:2;
/** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
uint32_t cs_hold_dly_per_en:1;
uint32_t reserved_24:8;
}; };
uint32_t val; uint32_t val;
} spi1_mem_c_ctrl1_reg_t; } spi1_mem_c_ctrl1_reg_t;
@@ -367,16 +399,16 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** clkcnt_l : R/W; bitpos: [7:0]; default: 3; /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi1_mem_c_clkcnt_N. * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N.
*/ */
uint32_t clkcnt_l:8; uint32_t clkcnt_l:8;
/** clkcnt_h : R/W; bitpos: [15:8]; default: 1; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1).
*/ */
uint32_t clkcnt_h:8; uint32_t clkcnt_h:8;
/** clkcnt_n : R/W; bitpos: [23:16]; default: 3; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi1_mem_c_clkcnt_N+1) * system/(SPI1_MEM_C_CLKCNT_N+1)
*/ */
uint32_t clkcnt_n:8; uint32_t clkcnt_n:8;
uint32_t reserved_24:7; uint32_t reserved_24:7;
@@ -422,11 +454,12 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** status : R/W/SS; bitpos: [15:0]; default: 0; /** status : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/ */
uint32_t status:16; uint32_t status:16;
/** wb_mode : R/W; bitpos: [23:16]; default: 0; /** wb_mode : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t wb_mode:8; uint32_t wb_mode:8;
uint32_t reserved_24:8; uint32_t reserved_24:8;
@@ -471,37 +504,44 @@ typedef union {
uint32_t reserved_0:1; uint32_t reserved_0:1;
/** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t cache_usr_addr_4byte:1; uint32_t cache_usr_addr_4byte:1;
uint32_t reserved_2:1; uint32_t reserved_2:1;
/** fdin_dual : R/W; bitpos: [3]; default: 0; /** fdin_dual : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi1_mem_c_fread_dio. * spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdin_dual:1; uint32_t fdin_dual:1;
/** fdout_dual : R/W; bitpos: [4]; default: 0; /** fdout_dual : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdout_dual:1; uint32_t fdout_dual:1;
/** faddr_dual : R/W; bitpos: [5]; default: 0; /** faddr_dual : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t faddr_dual:1; uint32_t faddr_dual:1;
/** fdin_quad : R/W; bitpos: [6]; default: 0; /** fdin_quad : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdin_quad:1; uint32_t fdin_quad:1;
/** fdout_quad : R/W; bitpos: [7]; default: 0; /** fdout_quad : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdout_quad:1; uint32_t fdout_quad:1;
/** faddr_quad : R/W; bitpos: [8]; default: 0; /** faddr_quad : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_c_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t faddr_quad:1; uint32_t faddr_quad:1;
uint32_t reserved_9:23; uint32_t reserved_9:23;
@@ -531,8 +571,8 @@ typedef union {
uint32_t waiti_addr_en:1; uint32_t waiti_addr_en:1;
/** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
* When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is
* (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active
* SPI1_MEM_C_WAITI_ADDR_EN is cleared. * when SPI1_MEM_C_WAITI_ADDR_EN is cleared.
*/ */
uint32_t waiti_addr_cyclelen:2; uint32_t waiti_addr_cyclelen:2;
uint32_t reserved_5:4; uint32_t reserved_5:4;
@@ -613,8 +653,8 @@ typedef union {
*/ */
uint32_t pes_end_en:1; uint32_t pes_end_en:1;
/** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
* When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times,
* will be treated as check pass. * it will be treated as check pass.
*/ */
uint32_t sus_timeout_cnt:7; uint32_t sus_timeout_cnt:7;
}; };
@@ -655,34 +695,34 @@ typedef union {
uint32_t wait_pesr_cmd_2b:1; uint32_t wait_pesr_cmd_2b:1;
/** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after HPM command is sent. * cycles after HPM command is sent.
*/ */
uint32_t flash_hpm_dly_128:1; uint32_t flash_hpm_dly_128:1;
/** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after RES command is sent. * cycles after RES command is sent.
*/ */
uint32_t flash_res_dly_128:1; uint32_t flash_res_dly_128:1;
/** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
* 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
* command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after DP command is sent. * cycles after DP command is sent.
*/ */
uint32_t flash_dp_dly_128:1; uint32_t flash_dp_dly_128:1;
/** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
* Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
* SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
* sent. * command is sent.
*/ */
uint32_t flash_per_dly_128:1; uint32_t flash_per_dly_128:1;
/** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
* Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
* SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
* sent. * command is sent.
*/ */
uint32_t flash_pes_dly_128:1; uint32_t flash_pes_dly_128:1;
/** spi0_lock_en : R/W; bitpos: [7]; default: 0; /** spi0_lock_en : R/W; bitpos: [7]; default: 0;
@@ -739,8 +779,8 @@ typedef union {
uint32_t fmem_usr_ddr_dqs_thd:7; uint32_t fmem_usr_ddr_dqs_thd:7;
/** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS. * negative edge of SPI_DQS.
*/ */
uint32_t fmem_ddr_dqs_loop:1; uint32_t fmem_ddr_dqs_loop:1;
@@ -801,12 +841,14 @@ typedef union {
struct { struct {
/** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295;
* For SPI1, the value of crc32. * For SPI1, the value of crc32.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t tx_crc_data:32; uint32_t tx_crc_data:32;
}; };
uint32_t val; uint32_t val;
} spi1_mem_c_tx_crc_reg_t; } spi1_mem_c_tx_crc_reg_t;
/** Group: Interrupt registers */ /** Group: Interrupt registers */
/** Type of int_ena register /** Type of int_ena register
* SPI1 interrupt enable register * SPI1 interrupt enable register
@@ -894,19 +936,19 @@ typedef union {
*/ */
uint32_t pes_end_int_raw:1; uint32_t pes_end_int_raw:1;
/** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when
* is sent and flash is already idle. 0: Others. * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
*/ */
uint32_t wpe_end_int_raw:1; uint32_t wpe_end_int_raw:1;
/** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
* changed from non idle state to idle state. It means that SPI_CS raises high. 0: * is changed from non idle state to idle state. It means that SPI_CS raises high. 0:
* Others * Others
*/ */
uint32_t slv_st_end_int_raw:1; uint32_t slv_st_end_int_raw:1;
/** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
* changed from non idle state to idle state. 0: Others. * is changed from non idle state to idle state. 0: Others.
*/ */
uint32_t mst_st_end_int_raw:1; uint32_t mst_st_end_int_raw:1;
uint32_t reserved_5:5; uint32_t reserved_5:5;
@@ -985,7 +1027,7 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** date : R/W; bitpos: [27:0]; default: 35660128; /** date : R/W; bitpos: [27:0]; default: 38801712;
* Version control register * Version control register
*/ */
uint32_t date:28; uint32_t date:28;

139
components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h
View File

@@ -33,8 +33,9 @@ extern "C" {
#define SPI1_MEM_S_SLV_ST_S 4 #define SPI1_MEM_S_SLV_ST_S 4
/** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; /** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
* In user mode, it is set to indicate that program/erase operation will be triggered. * In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the * The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable. * operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_PE (BIT(17)) #define SPI1_MEM_S_FLASH_PE (BIT(17))
#define SPI1_MEM_S_FLASH_PE_M (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S) #define SPI1_MEM_S_FLASH_PE_M (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S)
@@ -51,6 +52,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; /** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation * Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable. * done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_HPM (BIT(19)) #define SPI1_MEM_S_FLASH_HPM (BIT(19))
#define SPI1_MEM_S_FLASH_HPM_M (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S) #define SPI1_MEM_S_FLASH_HPM_M (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S)
@@ -60,6 +62,7 @@ extern "C" {
* This bit combined with reg_resandres bit releases Flash from the power-down state * This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once * or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable. * the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_RES (BIT(20)) #define SPI1_MEM_S_FLASH_RES (BIT(20))
#define SPI1_MEM_S_FLASH_RES_M (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S) #define SPI1_MEM_S_FLASH_RES_M (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S)
@@ -68,6 +71,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; /** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set. * Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable. * The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_DP (BIT(21)) #define SPI1_MEM_S_FLASH_DP (BIT(21))
#define SPI1_MEM_S_FLASH_DP_M (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S) #define SPI1_MEM_S_FLASH_DP_M (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S)
@@ -76,6 +80,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; /** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The * Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable. * bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_CE (BIT(22)) #define SPI1_MEM_S_FLASH_CE (BIT(22))
#define SPI1_MEM_S_FLASH_CE_M (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S) #define SPI1_MEM_S_FLASH_CE_M (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S)
@@ -84,6 +89,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; /** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is * Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_BE (BIT(23)) #define SPI1_MEM_S_FLASH_BE (BIT(23))
#define SPI1_MEM_S_FLASH_BE_M (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S) #define SPI1_MEM_S_FLASH_BE_M (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S)
@@ -92,6 +98,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; /** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_SE (BIT(24)) #define SPI1_MEM_S_FLASH_SE (BIT(24))
#define SPI1_MEM_S_FLASH_SE_M (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S) #define SPI1_MEM_S_FLASH_SE_M (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S)
@@ -101,6 +108,7 @@ extern "C" {
* Page program enable(1 byte ~256 bytes data to be programmed). Page program * Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the * operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable. * operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_PP (BIT(25)) #define SPI1_MEM_S_FLASH_PP (BIT(25))
#define SPI1_MEM_S_FLASH_PP_M (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S) #define SPI1_MEM_S_FLASH_PP_M (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S)
@@ -109,6 +117,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; /** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the * Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable. * bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_WRSR (BIT(26)) #define SPI1_MEM_S_FLASH_WRSR (BIT(26))
#define SPI1_MEM_S_FLASH_WRSR_M (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S) #define SPI1_MEM_S_FLASH_WRSR_M (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S)
@@ -117,6 +126,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; /** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is * Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_RDSR (BIT(27)) #define SPI1_MEM_S_FLASH_RDSR (BIT(27))
#define SPI1_MEM_S_FLASH_RDSR_M (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S) #define SPI1_MEM_S_FLASH_RDSR_M (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S)
@@ -125,6 +135,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; /** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable. * cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_RDID (BIT(28)) #define SPI1_MEM_S_FLASH_RDID (BIT(28))
#define SPI1_MEM_S_FLASH_RDID_M (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S) #define SPI1_MEM_S_FLASH_RDID_M (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S)
@@ -133,6 +144,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; /** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The * Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_WRDI (BIT(29)) #define SPI1_MEM_S_FLASH_WRDI (BIT(29))
#define SPI1_MEM_S_FLASH_WRDI_M (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S) #define SPI1_MEM_S_FLASH_WRDI_M (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S)
@@ -141,6 +153,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; /** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit * Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable. * will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_WREN (BIT(30)) #define SPI1_MEM_S_FLASH_WREN (BIT(30))
#define SPI1_MEM_S_FLASH_WREN_M (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S) #define SPI1_MEM_S_FLASH_WREN_M (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S)
@@ -149,6 +162,7 @@ extern "C" {
/** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; /** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The * Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FLASH_READ (BIT(31)) #define SPI1_MEM_S_FLASH_READ (BIT(31))
#define SPI1_MEM_S_FLASH_READ_M (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S) #define SPI1_MEM_S_FLASH_READ_M (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S)
@@ -226,6 +240,7 @@ extern "C" {
/** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; /** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active * For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low. * low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_S_FCS_CRC_EN (BIT(10))
#define SPI1_MEM_S_FCS_CRC_EN_M (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S) #define SPI1_MEM_S_FCS_CRC_EN_M (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S)
@@ -233,14 +248,15 @@ extern "C" {
#define SPI1_MEM_S_FCS_CRC_EN_S 10 #define SPI1_MEM_S_FCS_CRC_EN_S 10
/** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0; /** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_TX_CRC_EN (BIT(11)) #define SPI1_MEM_S_TX_CRC_EN (BIT(11))
#define SPI1_MEM_S_TX_CRC_EN_M (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S) #define SPI1_MEM_S_TX_CRC_EN_M (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S)
#define SPI1_MEM_S_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_S_TX_CRC_EN_V 0x00000001U
#define SPI1_MEM_S_TX_CRC_EN_S 11 #define SPI1_MEM_S_TX_CRC_EN_S 11
/** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; /** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
* This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
* and spi1_mem_s_fread_dout. 1: enable 0: disable. * and spi_mem_fread_dout. 1: enable 0: disable.
*/ */
#define SPI1_MEM_S_FASTRD_MODE (BIT(13)) #define SPI1_MEM_S_FASTRD_MODE (BIT(13))
#define SPI1_MEM_S_FASTRD_MODE_M (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S) #define SPI1_MEM_S_FASTRD_MODE_M (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S)
@@ -255,7 +271,8 @@ extern "C" {
#define SPI1_MEM_S_FREAD_DUAL_S 14 #define SPI1_MEM_S_FREAD_DUAL_S 14
/** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1; /** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with
* spi1_mem_s_flash_res bit. 1: enable 0: disable. * spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_RESANDRES (BIT(15)) #define SPI1_MEM_S_RESANDRES (BIT(15))
#define SPI1_MEM_S_RESANDRES_M (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S) #define SPI1_MEM_S_RESANDRES_M (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S)
@@ -292,6 +309,7 @@ extern "C" {
/** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0; /** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0: * two bytes data will be written to status register when it is set. 1: enable 0:
* disable. * disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_WRSR_2B (BIT(22)) #define SPI1_MEM_S_WRSR_2B (BIT(22))
#define SPI1_MEM_S_WRSR_2B_M (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S) #define SPI1_MEM_S_WRSR_2B_M (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S)
@@ -328,13 +346,30 @@ extern "C" {
#define SPI1_MEM_S_CLK_MODE_V 0x00000003U #define SPI1_MEM_S_CLK_MODE_V 0x00000003U
#define SPI1_MEM_S_CLK_MODE_S 0 #define SPI1_MEM_S_CLK_MODE_S 0
/** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; /** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] *
* SPI_CLK cycles. * 512) SPI_CLK cycles.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES 0x000003FFU
#define SPI1_MEM_S_CS_HOLD_DLY_RES_M (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S) #define SPI1_MEM_S_CS_HOLD_DLY_RES_M (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S)
#define SPI1_MEM_S_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES_V 0x000003FFU
#define SPI1_MEM_S_CS_HOLD_DLY_RES_S 2 #define SPI1_MEM_S_CS_HOLD_DLY_RES_S 2
/** SPI1_MEM_S_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511;
* After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
#define SPI1_MEM_S_CS_HOLD_DLY_PER 0x000001FFU
#define SPI1_MEM_S_CS_HOLD_DLY_PER_M (SPI1_MEM_S_CS_HOLD_DLY_PER_V << SPI1_MEM_S_CS_HOLD_DLY_PER_S)
#define SPI1_MEM_S_CS_HOLD_DLY_PER_V 0x000001FFU
#define SPI1_MEM_S_CS_HOLD_DLY_PER_S 12
/** SPI1_MEM_S_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN (BIT(23))
#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S)
#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V 0x00000001U
#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S 23
/** SPI1_MEM_S_CTRL2_REG register /** SPI1_MEM_S_CTRL2_REG register
* SPI1 control2 register. * SPI1 control2 register.
@@ -353,22 +388,22 @@ extern "C" {
*/ */
#define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14) #define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
/** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; /** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi1_mem_s_clkcnt_N. * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N.
*/ */
#define SPI1_MEM_S_CLKCNT_L 0x000000FFU #define SPI1_MEM_S_CLKCNT_L 0x000000FFU
#define SPI1_MEM_S_CLKCNT_L_M (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S) #define SPI1_MEM_S_CLKCNT_L_M (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S)
#define SPI1_MEM_S_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_L_V 0x000000FFU
#define SPI1_MEM_S_CLKCNT_L_S 0 #define SPI1_MEM_S_CLKCNT_L_S 0
/** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; /** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1).
*/ */
#define SPI1_MEM_S_CLKCNT_H 0x000000FFU #define SPI1_MEM_S_CLKCNT_H 0x000000FFU
#define SPI1_MEM_S_CLKCNT_H_M (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S) #define SPI1_MEM_S_CLKCNT_H_M (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S)
#define SPI1_MEM_S_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_H_V 0x000000FFU
#define SPI1_MEM_S_CLKCNT_H_S 8 #define SPI1_MEM_S_CLKCNT_H_S 8
/** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; /** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi1_mem_s_clkcnt_N+1) * system/(SPI1_MEM_S_CLKCNT_N+1)
*/ */
#define SPI1_MEM_S_CLKCNT_N 0x000000FFU #define SPI1_MEM_S_CLKCNT_N 0x000000FFU
#define SPI1_MEM_S_CLKCNT_N_M (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S) #define SPI1_MEM_S_CLKCNT_N_M (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S)
@@ -387,7 +422,7 @@ extern "C" {
*/ */
#define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18) #define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
/** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; /** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
* the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/ */
#define SPI1_MEM_S_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_S_CK_OUT_EDGE (BIT(9))
#define SPI1_MEM_S_CK_OUT_EDGE_M (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S) #define SPI1_MEM_S_CK_OUT_EDGE_M (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S)
@@ -422,7 +457,7 @@ extern "C" {
#define SPI1_MEM_S_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_S_FWRITE_QIO_V 0x00000001U
#define SPI1_MEM_S_FWRITE_QIO_S 15 #define SPI1_MEM_S_FWRITE_QIO_S 15
/** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; /** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
* read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
*/ */
#define SPI1_MEM_S_USR_MISO_HIGHPART (BIT(24)) #define SPI1_MEM_S_USR_MISO_HIGHPART (BIT(24))
@@ -430,7 +465,7 @@ extern "C" {
#define SPI1_MEM_S_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_S_USR_MISO_HIGHPART_V 0x00000001U
#define SPI1_MEM_S_USR_MISO_HIGHPART_S 24 #define SPI1_MEM_S_USR_MISO_HIGHPART_S 24
/** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; /** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
* write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
*/ */
#define SPI1_MEM_S_USR_MOSI_HIGHPART (BIT(25)) #define SPI1_MEM_S_USR_MOSI_HIGHPART (BIT(25))
@@ -485,7 +520,7 @@ extern "C" {
*/ */
#define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c) #define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
/** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; /** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be * The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1). * (cycle_num-1).
*/ */
#define SPI1_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU #define SPI1_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU
@@ -548,14 +583,15 @@ extern "C" {
*/ */
#define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c) #define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
/** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0; /** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/ */
#define SPI1_MEM_S_STATUS 0x0000FFFFU #define SPI1_MEM_S_STATUS 0x0000FFFFU
#define SPI1_MEM_S_STATUS_M (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S) #define SPI1_MEM_S_STATUS_M (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S)
#define SPI1_MEM_S_STATUS_V 0x0000FFFFU #define SPI1_MEM_S_STATUS_V 0x0000FFFFU
#define SPI1_MEM_S_STATUS_S 0 #define SPI1_MEM_S_STATUS_S 0
/** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; /** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_WB_MODE 0x000000FFU #define SPI1_MEM_S_WB_MODE 0x000000FFU
#define SPI1_MEM_S_WB_MODE_M (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S) #define SPI1_MEM_S_WB_MODE_M (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S)
@@ -611,10 +647,13 @@ extern "C" {
/** SPI1_MEM_S_CACHE_FCTRL_REG register /** SPI1_MEM_S_CACHE_FCTRL_REG register
* SPI1 bit mode control register. * SPI1 bit mode control register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/ */
#define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c) #define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
/** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; /** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1))
#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S) #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S)
@@ -622,7 +661,8 @@ extern "C" {
#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S 1
/** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; /** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi1_mem_s_fread_dio. * spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FDIN_DUAL (BIT(3)) #define SPI1_MEM_S_FDIN_DUAL (BIT(3))
#define SPI1_MEM_S_FDIN_DUAL_M (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S) #define SPI1_MEM_S_FDIN_DUAL_M (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S)
@@ -630,7 +670,8 @@ extern "C" {
#define SPI1_MEM_S_FDIN_DUAL_S 3 #define SPI1_MEM_S_FDIN_DUAL_S 3
/** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; /** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_S_FDOUT_DUAL (BIT(4))
#define SPI1_MEM_S_FDOUT_DUAL_M (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S) #define SPI1_MEM_S_FDOUT_DUAL_M (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S)
@@ -638,7 +679,8 @@ extern "C" {
#define SPI1_MEM_S_FDOUT_DUAL_S 4 #define SPI1_MEM_S_FDOUT_DUAL_S 4
/** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; /** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FADDR_DUAL (BIT(5)) #define SPI1_MEM_S_FADDR_DUAL (BIT(5))
#define SPI1_MEM_S_FADDR_DUAL_M (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S) #define SPI1_MEM_S_FADDR_DUAL_M (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S)
@@ -646,7 +688,8 @@ extern "C" {
#define SPI1_MEM_S_FADDR_DUAL_S 5 #define SPI1_MEM_S_FADDR_DUAL_S 5
/** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; /** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FDIN_QUAD (BIT(6)) #define SPI1_MEM_S_FDIN_QUAD (BIT(6))
#define SPI1_MEM_S_FDIN_QUAD_M (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S) #define SPI1_MEM_S_FDIN_QUAD_M (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S)
@@ -654,7 +697,8 @@ extern "C" {
#define SPI1_MEM_S_FDIN_QUAD_S 6 #define SPI1_MEM_S_FDIN_QUAD_S 6
/** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; /** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_S_FDOUT_QUAD (BIT(7))
#define SPI1_MEM_S_FDOUT_QUAD_M (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S) #define SPI1_MEM_S_FDOUT_QUAD_M (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S)
@@ -662,7 +706,8 @@ extern "C" {
#define SPI1_MEM_S_FDOUT_QUAD_S 7 #define SPI1_MEM_S_FDOUT_QUAD_S 7
/** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; /** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
#define SPI1_MEM_S_FADDR_QUAD (BIT(8)) #define SPI1_MEM_S_FADDR_QUAD (BIT(8))
#define SPI1_MEM_S_FADDR_QUAD_M (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S) #define SPI1_MEM_S_FADDR_QUAD_M (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S)
@@ -891,8 +936,8 @@ extern "C" {
#define SPI1_MEM_S_WAITI_ADDR_EN_S 2 #define SPI1_MEM_S_WAITI_ADDR_EN_S 2
/** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; /** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
* When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is
* (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active
* SPI1_MEM_S_WAITI_ADDR_EN is cleared. * when SPI1_MEM_S_WAITI_ADDR_EN is cleared.
*/ */
#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN 0x00000003U
#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S) #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S)
@@ -1010,8 +1055,8 @@ extern "C" {
#define SPI1_MEM_S_PES_END_EN_V 0x00000001U #define SPI1_MEM_S_PES_END_EN_V 0x00000001U
#define SPI1_MEM_S_PES_END_EN_S 24 #define SPI1_MEM_S_PES_END_EN_S 24
/** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; /** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
* When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times,
* will be treated as check pass. * it will be treated as check pass.
*/ */
#define SPI1_MEM_S_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_S_SUS_TIMEOUT_CNT 0x0000007FU
#define SPI1_MEM_S_SUS_TIMEOUT_CNT_M (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S) #define SPI1_MEM_S_SUS_TIMEOUT_CNT_M (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S)
@@ -1059,8 +1104,8 @@ extern "C" {
#define SPI1_MEM_S_WAIT_PESR_CMD_2B_S 1 #define SPI1_MEM_S_WAIT_PESR_CMD_2B_S 1
/** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; /** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after HPM command is sent. * cycles after HPM command is sent.
*/ */
#define SPI1_MEM_S_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_S_FLASH_HPM_DLY_128 (BIT(2))
#define SPI1_MEM_S_FLASH_HPM_DLY_128_M (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S) #define SPI1_MEM_S_FLASH_HPM_DLY_128_M (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S)
@@ -1068,8 +1113,8 @@ extern "C" {
#define SPI1_MEM_S_FLASH_HPM_DLY_128_S 2 #define SPI1_MEM_S_FLASH_HPM_DLY_128_S 2
/** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; /** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after RES command is sent. * cycles after RES command is sent.
*/ */
#define SPI1_MEM_S_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_S_FLASH_RES_DLY_128 (BIT(3))
#define SPI1_MEM_S_FLASH_RES_DLY_128_M (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S) #define SPI1_MEM_S_FLASH_RES_DLY_128_M (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S)
@@ -1077,8 +1122,8 @@ extern "C" {
#define SPI1_MEM_S_FLASH_RES_DLY_128_S 3 #define SPI1_MEM_S_FLASH_RES_DLY_128_S 3
/** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; /** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after DP command is sent. * cycles after DP command is sent.
*/ */
#define SPI1_MEM_S_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_S_FLASH_DP_DLY_128 (BIT(4))
#define SPI1_MEM_S_FLASH_DP_DLY_128_M (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S) #define SPI1_MEM_S_FLASH_DP_DLY_128_M (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S)
@@ -1086,9 +1131,9 @@ extern "C" {
#define SPI1_MEM_S_FLASH_DP_DLY_128_S 4 #define SPI1_MEM_S_FLASH_DP_DLY_128_S 4
/** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; /** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
* Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
* SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
* sent. * command is sent.
*/ */
#define SPI1_MEM_S_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_S_FLASH_PER_DLY_128 (BIT(5))
#define SPI1_MEM_S_FLASH_PER_DLY_128_M (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S) #define SPI1_MEM_S_FLASH_PER_DLY_128_M (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S)
@@ -1096,9 +1141,9 @@ extern "C" {
#define SPI1_MEM_S_FLASH_PER_DLY_128_S 5 #define SPI1_MEM_S_FLASH_PER_DLY_128_S 5
/** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; /** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
* Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
* SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
* sent. * command is sent.
*/ */
#define SPI1_MEM_S_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_S_FLASH_PES_DLY_128 (BIT(6))
#define SPI1_MEM_S_FLASH_PES_DLY_128_M (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S) #define SPI1_MEM_S_FLASH_PES_DLY_128_M (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S)
@@ -1242,16 +1287,16 @@ extern "C" {
#define SPI1_MEM_S_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_PES_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_S_PES_END_INT_RAW_S 1 #define SPI1_MEM_S_PES_END_INT_RAW_S 1
/** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; /** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when
* is sent and flash is already idle. 0: Others. * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
*/ */
#define SPI1_MEM_S_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_S_WPE_END_INT_RAW (BIT(2))
#define SPI1_MEM_S_WPE_END_INT_RAW_M (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S) #define SPI1_MEM_S_WPE_END_INT_RAW_M (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S)
#define SPI1_MEM_S_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_WPE_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_S_WPE_END_INT_RAW_S 2 #define SPI1_MEM_S_WPE_END_INT_RAW_S 2
/** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; /** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
* changed from non idle state to idle state. It means that SPI_CS raises high. 0: * is changed from non idle state to idle state. It means that SPI_CS raises high. 0:
* Others * Others
*/ */
#define SPI1_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) #define SPI1_MEM_S_SLV_ST_END_INT_RAW (BIT(3))
@@ -1259,8 +1304,8 @@ extern "C" {
#define SPI1_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U
#define SPI1_MEM_S_SLV_ST_END_INT_RAW_S 3 #define SPI1_MEM_S_SLV_ST_END_INT_RAW_S 3
/** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; /** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
* changed from non idle state to idle state. 0: Others. * is changed from non idle state to idle state. 0: Others.
*/ */
#define SPI1_MEM_S_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_S_MST_ST_END_INT_RAW (BIT(4))
#define SPI1_MEM_S_MST_ST_END_INT_RAW_M (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S) #define SPI1_MEM_S_MST_ST_END_INT_RAW_M (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S)
@@ -1379,8 +1424,8 @@ extern "C" {
#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 #define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S 14
/** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; /** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS. * negative edge of SPI_DQS.
*/ */
#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) #define SPI1_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21))
@@ -1468,7 +1513,7 @@ extern "C" {
* Version control register * Version control register
*/ */
#define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc) #define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216; /** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 38801712;
* Version control register * Version control register
*/ */
#define SPI1_MEM_S_DATE 0x0FFFFFFFU #define SPI1_MEM_S_DATE 0x0FFFFFFFU

134
components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h
View File

@@ -29,8 +29,9 @@ typedef union {
uint32_t reserved_8:9; uint32_t reserved_8:9;
/** flash_pe : R/W/SC; bitpos: [17]; default: 0; /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
* In user mode, it is set to indicate that program/erase operation will be triggered. * In user mode, it is set to indicate that program/erase operation will be triggered.
* The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the * The bit is combined with spi_mem_usr bit. The bit will be cleared once the
* operation done.1: enable 0: disable. * operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_pe:1; uint32_t flash_pe:1;
/** usr : R/W/SC; bitpos: [18]; default: 0; /** usr : R/W/SC; bitpos: [18]; default: 0;
@@ -41,68 +42,81 @@ typedef union {
/** flash_hpm : R/W/SC; bitpos: [19]; default: 0; /** flash_hpm : R/W/SC; bitpos: [19]; default: 0;
* Drive Flash into high performance mode. The bit will be cleared once the operation * Drive Flash into high performance mode. The bit will be cleared once the operation
* done.1: enable 0: disable. * done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_hpm:1; uint32_t flash_hpm:1;
/** flash_res : R/W/SC; bitpos: [20]; default: 0; /** flash_res : R/W/SC; bitpos: [20]; default: 0;
* This bit combined with reg_resandres bit releases Flash from the power-down state * This bit combined with reg_resandres bit releases Flash from the power-down state
* or high performance mode and obtains the devices ID. The bit will be cleared once * or high performance mode and obtains the devices ID. The bit will be cleared once
* the operation done.1: enable 0: disable. * the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_res:1; uint32_t flash_res:1;
/** flash_dp : R/W/SC; bitpos: [21]; default: 0; /** flash_dp : R/W/SC; bitpos: [21]; default: 0;
* Drive Flash into power down. An operation will be triggered when the bit is set. * Drive Flash into power down. An operation will be triggered when the bit is set.
* The bit will be cleared once the operation done.1: enable 0: disable. * The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_dp:1; uint32_t flash_dp:1;
/** flash_ce : R/W/SC; bitpos: [22]; default: 0; /** flash_ce : R/W/SC; bitpos: [22]; default: 0;
* Chip erase enable. Chip erase operation will be triggered when the bit is set. The * Chip erase enable. Chip erase operation will be triggered when the bit is set. The
* bit will be cleared once the operation done.1: enable 0: disable. * bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_ce:1; uint32_t flash_ce:1;
/** flash_be : R/W/SC; bitpos: [23]; default: 0; /** flash_be : R/W/SC; bitpos: [23]; default: 0;
* Block erase enable(32KB) . Block erase operation will be triggered when the bit is * Block erase enable(32KB) . Block erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_be:1; uint32_t flash_be:1;
/** flash_se : R/W/SC; bitpos: [24]; default: 0; /** flash_se : R/W/SC; bitpos: [24]; default: 0;
* Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_se:1; uint32_t flash_se:1;
/** flash_pp : R/W/SC; bitpos: [25]; default: 0; /** flash_pp : R/W/SC; bitpos: [25]; default: 0;
* Page program enable(1 byte ~256 bytes data to be programmed). Page program * Page program enable(1 byte ~256 bytes data to be programmed). Page program
* operation will be triggered when the bit is set. The bit will be cleared once the * operation will be triggered when the bit is set. The bit will be cleared once the
* operation done .1: enable 0: disable. * operation done .1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_pp:1; uint32_t flash_pp:1;
/** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0;
* Write status register enable. Write status operation will be triggered when the * Write status register enable. Write status operation will be triggered when the
* bit is set. The bit will be cleared once the operation done.1: enable 0: disable. * bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wrsr:1; uint32_t flash_wrsr:1;
/** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0;
* Read status register-1. Read status operation will be triggered when the bit is * Read status register-1. Read status operation will be triggered when the bit is
* set. The bit will be cleared once the operation done.1: enable 0: disable. * set. The bit will be cleared once the operation done.1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_rdsr:1; uint32_t flash_rdsr:1;
/** flash_rdid : R/W/SC; bitpos: [28]; default: 0; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0;
* Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
* cleared once the operation done. 1: enable 0: disable. * cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_rdid:1; uint32_t flash_rdid:1;
/** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0;
* Write flash disable. Write disable command will be sent when the bit is set. The * Write flash disable. Write disable command will be sent when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wrdi:1; uint32_t flash_wrdi:1;
/** flash_wren : R/W/SC; bitpos: [30]; default: 0; /** flash_wren : R/W/SC; bitpos: [30]; default: 0;
* Write flash enable. Write enable command will be sent when the bit is set. The bit * Write flash enable. Write enable command will be sent when the bit is set. The bit
* will be cleared once the operation done. 1: enable 0: disable. * will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_wren:1; uint32_t flash_wren:1;
/** flash_read : R/W/SC; bitpos: [31]; default: 0; /** flash_read : R/W/SC; bitpos: [31]; default: 0;
* Read flash enable. Read flash operation will be triggered when the bit is set. The * Read flash enable. Read flash operation will be triggered when the bit is set. The
* bit will be cleared once the operation done. 1: enable 0: disable. * bit will be cleared once the operation done. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t flash_read:1; uint32_t flash_read:1;
}; };
@@ -130,7 +144,7 @@ typedef union {
struct { struct {
uint32_t reserved_0:9; uint32_t reserved_0:9;
/** ck_out_edge : R/W; bitpos: [9]; default: 0; /** ck_out_edge : R/W; bitpos: [9]; default: 0;
* the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/ */
uint32_t ck_out_edge:1; uint32_t ck_out_edge:1;
uint32_t reserved_10:2; uint32_t reserved_10:2;
@@ -152,12 +166,12 @@ typedef union {
uint32_t fwrite_qio:1; uint32_t fwrite_qio:1;
uint32_t reserved_16:8; uint32_t reserved_16:8;
/** usr_miso_highpart : R/W; bitpos: [24]; default: 0; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
* read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
*/ */
uint32_t usr_miso_highpart:1; uint32_t usr_miso_highpart:1;
/** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
* write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
* enable 0: disable. * enable 0: disable.
*/ */
uint32_t usr_mosi_highpart:1; uint32_t usr_mosi_highpart:1;
@@ -195,7 +209,7 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
* The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be * The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1). * (cycle_num-1).
*/ */
uint32_t usr_dummy_cyclelen:6; uint32_t usr_dummy_cyclelen:6;
@@ -268,16 +282,18 @@ typedef union {
/** fcs_crc_en : R/W; bitpos: [10]; default: 0; /** fcs_crc_en : R/W; bitpos: [10]; default: 0;
* For SPI1, initialize crc32 module before writing encrypted data to flash. Active * For SPI1, initialize crc32 module before writing encrypted data to flash. Active
* low. * low.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fcs_crc_en:1; uint32_t fcs_crc_en:1;
/** tx_crc_en : R/W; bitpos: [11]; default: 0; /** tx_crc_en : R/W; bitpos: [11]; default: 0;
* For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t tx_crc_en:1; uint32_t tx_crc_en:1;
uint32_t reserved_12:1; uint32_t reserved_12:1;
/** fastrd_mode : R/W; bitpos: [13]; default: 1; /** fastrd_mode : R/W; bitpos: [13]; default: 1;
* This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
* and spi1_mem_s_fread_dout. 1: enable 0: disable. * and spi_mem_fread_dout. 1: enable 0: disable.
*/ */
uint32_t fastrd_mode:1; uint32_t fastrd_mode:1;
/** fread_dual : R/W; bitpos: [14]; default: 0; /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -286,7 +302,8 @@ typedef union {
uint32_t fread_dual:1; uint32_t fread_dual:1;
/** resandres : R/W; bitpos: [15]; default: 1; /** resandres : R/W; bitpos: [15]; default: 1;
* The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with
* spi1_mem_s_flash_res bit. 1: enable 0: disable. * spi_mem_flash_res bit. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t resandres:1; uint32_t resandres:1;
uint32_t reserved_16:2; uint32_t reserved_16:2;
@@ -309,6 +326,7 @@ typedef union {
/** wrsr_2b : R/W; bitpos: [22]; default: 0; /** wrsr_2b : R/W; bitpos: [22]; default: 0;
* two bytes data will be written to status register when it is set. 1: enable 0: * two bytes data will be written to status register when it is set. 1: enable 0:
* disable. * disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t wrsr_2b:1; uint32_t wrsr_2b:1;
/** fread_dio : R/W; bitpos: [23]; default: 0; /** fread_dio : R/W; bitpos: [23]; default: 0;
@@ -338,11 +356,23 @@ typedef union {
*/ */
uint32_t clk_mode:2; uint32_t clk_mode:2;
/** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] *
* SPI_CLK cycles. * 512) SPI_CLK cycles.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t cs_hold_dly_res:10; uint32_t cs_hold_dly_res:10;
uint32_t reserved_12:20; /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511;
* After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128)
* SPI_CLK cycles.
*/
uint32_t cs_hold_dly_per:9;
uint32_t reserved_21:2;
/** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0;
* 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for
* pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per .
*/
uint32_t cs_hold_dly_per_en:1;
uint32_t reserved_24:8;
}; };
uint32_t val; uint32_t val;
} spi1_mem_s_ctrl1_reg_t; } spi1_mem_s_ctrl1_reg_t;
@@ -367,16 +397,16 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** clkcnt_l : R/W; bitpos: [7:0]; default: 3; /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi1_mem_s_clkcnt_N. * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N.
*/ */
uint32_t clkcnt_l:8; uint32_t clkcnt_l:8;
/** clkcnt_h : R/W; bitpos: [15:8]; default: 1; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1).
*/ */
uint32_t clkcnt_h:8; uint32_t clkcnt_h:8;
/** clkcnt_n : R/W; bitpos: [23:16]; default: 3; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi1_mem_s_clkcnt_N+1) * system/(SPI1_MEM_S_CLKCNT_N+1)
*/ */
uint32_t clkcnt_n:8; uint32_t clkcnt_n:8;
uint32_t reserved_24:7; uint32_t reserved_24:7;
@@ -422,11 +452,12 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** status : R/W/SS; bitpos: [15:0]; default: 0; /** status : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/ */
uint32_t status:16; uint32_t status:16;
/** wb_mode : R/W; bitpos: [23:16]; default: 0; /** wb_mode : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t wb_mode:8; uint32_t wb_mode:8;
uint32_t reserved_24:8; uint32_t reserved_24:8;
@@ -471,37 +502,44 @@ typedef union {
uint32_t reserved_0:1; uint32_t reserved_0:1;
/** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t cache_usr_addr_4byte:1; uint32_t cache_usr_addr_4byte:1;
uint32_t reserved_2:1; uint32_t reserved_2:1;
/** fdin_dual : R/W; bitpos: [3]; default: 0; /** fdin_dual : R/W; bitpos: [3]; default: 0;
* For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
* spi1_mem_s_fread_dio. * spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdin_dual:1; uint32_t fdin_dual:1;
/** fdout_dual : R/W; bitpos: [4]; default: 0; /** fdout_dual : R/W; bitpos: [4]; default: 0;
* For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdout_dual:1; uint32_t fdout_dual:1;
/** faddr_dual : R/W; bitpos: [5]; default: 0; /** faddr_dual : R/W; bitpos: [5]; default: 0;
* For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_dio. * with spi_mem_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t faddr_dual:1; uint32_t faddr_dual:1;
/** fdin_quad : R/W; bitpos: [6]; default: 0; /** fdin_quad : R/W; bitpos: [6]; default: 0;
* For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdin_quad:1; uint32_t fdin_quad:1;
/** fdout_quad : R/W; bitpos: [7]; default: 0; /** fdout_quad : R/W; bitpos: [7]; default: 0;
* For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t fdout_quad:1; uint32_t fdout_quad:1;
/** faddr_quad : R/W; bitpos: [8]; default: 0; /** faddr_quad : R/W; bitpos: [8]; default: 0;
* For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same
* with spi1_mem_s_fread_qio. * with spi_mem_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t faddr_quad:1; uint32_t faddr_quad:1;
uint32_t reserved_9:23; uint32_t reserved_9:23;
@@ -531,8 +569,8 @@ typedef union {
uint32_t waiti_addr_en:1; uint32_t waiti_addr_en:1;
/** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
* When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is
* (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active
* SPI1_MEM_S_WAITI_ADDR_EN is cleared. * when SPI1_MEM_S_WAITI_ADDR_EN is cleared.
*/ */
uint32_t waiti_addr_cyclelen:2; uint32_t waiti_addr_cyclelen:2;
uint32_t reserved_5:4; uint32_t reserved_5:4;
@@ -613,8 +651,8 @@ typedef union {
*/ */
uint32_t pes_end_en:1; uint32_t pes_end_en:1;
/** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
* When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times,
* will be treated as check pass. * it will be treated as check pass.
*/ */
uint32_t sus_timeout_cnt:7; uint32_t sus_timeout_cnt:7;
}; };
@@ -655,34 +693,34 @@ typedef union {
uint32_t wait_pesr_cmd_2b:1; uint32_t wait_pesr_cmd_2b:1;
/** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after HPM command is sent. * cycles after HPM command is sent.
*/ */
uint32_t flash_hpm_dly_128:1; uint32_t flash_hpm_dly_128:1;
/** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after RES command is sent. * cycles after RES command is sent.
*/ */
uint32_t flash_res_dly_128:1; uint32_t flash_res_dly_128:1;
/** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
* 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
* command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
* after DP command is sent. * cycles after DP command is sent.
*/ */
uint32_t flash_dp_dly_128:1; uint32_t flash_dp_dly_128:1;
/** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
* Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
* SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
* sent. * command is sent.
*/ */
uint32_t flash_per_dly_128:1; uint32_t flash_per_dly_128:1;
/** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
* Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
* (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
* SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
* sent. * command is sent.
*/ */
uint32_t flash_pes_dly_128:1; uint32_t flash_pes_dly_128:1;
/** spi0_lock_en : R/W; bitpos: [7]; default: 0; /** spi0_lock_en : R/W; bitpos: [7]; default: 0;
@@ -739,8 +777,8 @@ typedef union {
uint32_t fmem_usr_ddr_dqs_thd:7; uint32_t fmem_usr_ddr_dqs_thd:7;
/** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS. * negative edge of SPI_DQS.
*/ */
uint32_t fmem_ddr_dqs_loop:1; uint32_t fmem_ddr_dqs_loop:1;
@@ -1105,19 +1143,19 @@ typedef union {
*/ */
uint32_t pes_end_int_raw:1; uint32_t pes_end_int_raw:1;
/** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when
* is sent and flash is already idle. 0: Others. * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
*/ */
uint32_t wpe_end_int_raw:1; uint32_t wpe_end_int_raw:1;
/** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
* changed from non idle state to idle state. It means that SPI_CS raises high. 0: * is changed from non idle state to idle state. It means that SPI_CS raises high. 0:
* Others * Others
*/ */
uint32_t slv_st_end_int_raw:1; uint32_t slv_st_end_int_raw:1;
/** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
* changed from non idle state to idle state. 0: Others. * is changed from non idle state to idle state. 0: Others.
*/ */
uint32_t mst_st_end_int_raw:1; uint32_t mst_st_end_int_raw:1;
uint32_t reserved_5:5; uint32_t reserved_5:5;
@@ -1196,7 +1234,7 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** date : R/W; bitpos: [27:0]; default: 34673216; /** date : R/W; bitpos: [27:0]; default: 38801712;
* Version control register * Version control register
*/ */
uint32_t date:28; uint32_t date:28;

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components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h
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components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h
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components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h
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components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h
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@@ -180,11 +180,7 @@ typedef union {
* 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
*/ */
uint32_t aw_size0_1_support_en:1; uint32_t aw_size0_1_support_en:1;
/** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; uint32_t reserved_23:1;
* 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
* Reply AXI read data to AXI bus when all the read data is available.
*/
uint32_t axi_rdata_back_fast:1;
/** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
* 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
* when there is a ECC error in AXI read data. The ECC error information is recorded * when there is a ECC error in AXI read data. The ECC error information is recorded
@@ -200,9 +196,9 @@ typedef union {
*/ */
uint32_t mem_aw_splice_en:1; uint32_t mem_aw_splice_en:1;
/** mem_ram0_en : HRO; bitpos: [27]; default: 1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
* When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be * When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 1, only EXT_RAM0 will be
* accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 * accessed. When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 0, only EXT_RAM1
* will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * will be accessed. When spi_mem_s_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be
* accessed at the same time. * accessed at the same time.
*/ */
uint32_t mem_ram0_en:1; uint32_t mem_ram0_en:1;
@@ -287,12 +283,24 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
uint32_t reserved_0:7; uint32_t reserved_0:4;
/** mem_fsub_pin : R/W; bitpos: [7]; default: 0; /** mem_dq_oe_ctrl : R/W; bitpos: [4]; default: 1;
* For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable.
*/
uint32_t mem_dq_oe_ctrl:1;
/** mem_ck_oe_ctrl : R/W; bitpos: [5]; default: 1;
* For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable.
*/
uint32_t mem_ck_oe_ctrl:1;
/** mem_cs_oe_ctrl : R/W; bitpos: [6]; default: 1;
* For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable.
*/
uint32_t mem_cs_oe_ctrl:1;
/** mem_fsub_pin : HRO; bitpos: [7]; default: 0;
* For SPI0, flash is connected to SUBPINs. * For SPI0, flash is connected to SUBPINs.
*/ */
uint32_t mem_fsub_pin:1; uint32_t mem_fsub_pin:1;
/** mem_ssub_pin : R/W; bitpos: [8]; default: 0; /** mem_ssub_pin : HRO; bitpos: [8]; default: 0;
* For SPI0, sram is connected to SUBPINs. * For SPI0, sram is connected to SUBPINs.
*/ */
uint32_t mem_ssub_pin:1; uint32_t mem_ssub_pin:1;
@@ -316,47 +324,81 @@ typedef union {
struct { struct {
/** mem_axi_req_en : R/W; bitpos: [0]; default: 0; /** mem_axi_req_en : R/W; bitpos: [0]; default: 0;
* For SPI0, AXI master access enable, 1: enable, 0:disable. * For SPI0, AXI master access enable, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_axi_req_en:1; uint32_t mem_axi_req_en:1;
/** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0;
* For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_usr_addr_4byte:1; uint32_t mem_cache_usr_addr_4byte:1;
/** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0;
* For SPI0, cache read flash for user define command, 1: enable, 0:disable. * For SPI0, cache read flash for user define command, 1: enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_flash_usr_cmd:1; uint32_t mem_cache_flash_usr_cmd:1;
/** mem_fdin_dual : R/W; bitpos: [3]; default: 0; /** mem_fdin_dual : R/W; bitpos: [3]; default: 0;
* For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
* same with spi_mem_s_fread_dio. * same with spi_mem_s_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_fdin_dual:1; uint32_t mem_fdin_dual:1;
/** mem_fdout_dual : R/W; bitpos: [4]; default: 0; /** mem_fdout_dual : R/W; bitpos: [4]; default: 0;
* For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
* same with spi_mem_s_fread_dio. * same with spi_mem_s_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_fdout_dual:1; uint32_t mem_fdout_dual:1;
/** mem_faddr_dual : R/W; bitpos: [5]; default: 0; /** mem_faddr_dual : R/W; bitpos: [5]; default: 0;
* For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
* the same with spi_mem_s_fread_dio. * the same with spi_mem_s_fread_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_faddr_dual:1; uint32_t mem_faddr_dual:1;
/** mem_fdin_quad : R/W; bitpos: [6]; default: 0; /** mem_fdin_quad : R/W; bitpos: [6]; default: 0;
* For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
* same with spi_mem_s_fread_qio. * same with spi_mem_s_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_fdin_quad:1; uint32_t mem_fdin_quad:1;
/** mem_fdout_quad : R/W; bitpos: [7]; default: 0; /** mem_fdout_quad : R/W; bitpos: [7]; default: 0;
* For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the
* same with spi_mem_s_fread_qio. * same with spi_mem_s_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_fdout_quad:1; uint32_t mem_fdout_quad:1;
/** mem_faddr_quad : R/W; bitpos: [8]; default: 0; /** mem_faddr_quad : R/W; bitpos: [8]; default: 0;
* For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
* the same with spi_mem_s_fread_qio. * the same with spi_mem_s_fread_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_faddr_quad:1; uint32_t mem_faddr_quad:1;
uint32_t reserved_9:21; /** mem_arb_wei_en : R/W; bitpos: [9]; default: 0;
* To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0:
* disable.
*/
uint32_t mem_arb_wei_en:1;
/** mem_arb_req0_pri : R/W; bitpos: [10]; default: 0;
* To set AXI read priority in SPI0 arbiter. The larger the value, the greater the
* priority.
*/
uint32_t mem_arb_req0_pri:1;
/** mem_arb_req1_pri : R/W; bitpos: [11]; default: 0;
* To set AXI write priority in SPI0 arbiter. The larger the value, the greater the
* priority.
*/
uint32_t mem_arb_req1_pri:1;
/** mem_arb_req0_wei : R/W; bitpos: [15:12]; default: 0;
* To set AXI read priority weight in SPI0 arbiter. While the priority are same, the
* larger the value, the greater the weight.
*/
uint32_t mem_arb_req0_wei:4;
/** mem_arb_req1_wei : R/W; bitpos: [19:16]; default: 0;
* To set AXI write priority weight in SPI0 arbiter. While the priority are same, the
* larger the value, the greater the weight.
*/
uint32_t mem_arb_req1_wei:4;
uint32_t reserved_20:10;
/** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1;
* Set this bit to check AXI read/write the same address region. * Set this bit to check AXI read/write the same address region.
*/ */
@@ -462,16 +504,16 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_s_clkcnt_N. * In the master mode it must be equal to spi_mem_s_CLKCNT_N.
*/ */
uint32_t mem_clkcnt_l:8; uint32_t mem_clkcnt_l:8;
/** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1). * In the master mode it must be floor((spi_mem_s_CLKCNT_N+1)/2-1).
*/ */
uint32_t mem_clkcnt_h:8; uint32_t mem_clkcnt_h:8;
/** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is * In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is
* system/(spi_mem_s_clkcnt_N+1) * system/(spi_mem_s_CLKCNT_N+1)
*/ */
uint32_t mem_clkcnt_n:8; uint32_t mem_clkcnt_n:8;
uint32_t reserved_24:7; uint32_t reserved_24:7;
@@ -490,22 +532,26 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3;
* For SPI0 external RAM interface, it must be equal to spi_mem_s_clkcnt_N. * For SPI0 external RAM interface, it must be equal to spi_mem_s_SCLKCNT_N.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sclkcnt_l:8; uint32_t mem_sclkcnt_l:8;
/** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1;
* For SPI0 external RAM interface, it must be floor((spi_mem_s_clkcnt_N+1)/2-1). * For SPI0 external RAM interface, it must be floor((spi_mem_s_SCLKCNT_N+1)/2-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sclkcnt_h:8; uint32_t mem_sclkcnt_h:8;
/** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3;
* For SPI0 external RAM interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk * For SPI0 external RAM interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk
* frequency is system/(spi_mem_s_clkcnt_N+1) * frequency is system/(spi_mem_s_SCLKCNT_N+1)
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sclkcnt_n:8; uint32_t mem_sclkcnt_n:8;
uint32_t reserved_24:7; uint32_t reserved_24:7;
/** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0;
* For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk * For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk
* is divided from system clock. * is divided from system clock.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sclk_equ_sysclk:1; uint32_t mem_sclk_equ_sysclk:1;
}; };
@@ -544,7 +590,7 @@ typedef union {
uint32_t mem_cs_setup:1; uint32_t mem_cs_setup:1;
uint32_t reserved_8:1; uint32_t reserved_8:1;
/** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
* The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. * The bit combined with spi_mem_s_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
*/ */
uint32_t mem_ck_out_edge:1; uint32_t mem_ck_out_edge:1;
uint32_t reserved_10:16; uint32_t reserved_10:16;
@@ -611,6 +657,7 @@ typedef union {
uint32_t reserved_0:16; uint32_t reserved_0:16;
/** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi_mem_s_fastrd_mode bit. * Mode bits in the flash fast read mode it is combined with spi_mem_s_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_wb_mode:8; uint32_t mem_wb_mode:8;
uint32_t reserved_24:8; uint32_t reserved_24:8;
@@ -628,52 +675,63 @@ typedef union {
/** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0;
* For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1:
* enable, 0:disable. * enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_usr_saddr_4byte:1; uint32_t mem_cache_usr_saddr_4byte:1;
/** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0;
* For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_usr_sram_dio:1; uint32_t mem_usr_sram_dio:1;
/** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0;
* For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_usr_sram_qio:1; uint32_t mem_usr_sram_qio:1;
/** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0;
* For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write
* operations. * operations.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_usr_wr_sram_dummy:1; uint32_t mem_usr_wr_sram_dummy:1;
/** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1;
* For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
* operations. * operations.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_usr_rd_sram_dummy:1; uint32_t mem_usr_rd_sram_dummy:1;
/** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1;
* For SPI0, In the external RAM mode cache read external RAM for user define command. * For SPI0, In the external RAM mode cache read external RAM for user define command.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_rcmd:1; uint32_t mem_cache_sram_usr_rcmd:1;
/** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1;
* For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase.
* The register value shall be (bit_num-1). * The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sram_rdummy_cyclelen:6; uint32_t mem_sram_rdummy_cyclelen:6;
uint32_t reserved_12:2; uint32_t reserved_12:2;
/** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23;
* For SPI0, In the external RAM mode, it is the length in bits of address phase. The * For SPI0, In the external RAM mode, it is the length in bits of address phase. The
* register value shall be (bit_num-1). * register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sram_addr_bitlen:6; uint32_t mem_sram_addr_bitlen:6;
/** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1;
* For SPI0, In the external RAM mode cache write sram for user define command * For SPI0, In the external RAM mode cache write sram for user define command
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_wcmd:1; uint32_t mem_cache_sram_usr_wcmd:1;
/** mem_sram_oct : R/W; bitpos: [21]; default: 0; /** mem_sram_oct : R/W; bitpos: [21]; default: 0;
* reserved * reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sram_oct:1; uint32_t mem_sram_oct:1;
/** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1;
* For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase.
* The register value shall be (bit_num-1). * The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sram_wdummy_cyclelen:6; uint32_t mem_sram_wdummy_cyclelen:6;
uint32_t reserved_28:4; uint32_t reserved_28:4;
@@ -690,73 +748,88 @@ typedef union {
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
* SPI clock is always on. * SPI clock is always on.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sclk_mode:2; uint32_t mem_sclk_mode:2;
/** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0;
* Mode bits in the external RAM fast read mode it is combined with * Mode bits in the external RAM fast read mode it is combined with
* spi_mem_s_fastrd_mode bit. * spi_mem_s_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_swb_mode:8; uint32_t mem_swb_mode:8;
/** mem_sdin_dual : R/W; bitpos: [10]; default: 0; /** mem_sdin_dual : R/W; bitpos: [10]; default: 0;
* For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is
* the same with spi_mem_s_usr_sram_dio. * the same with spi_mem_s_usr_sram_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdin_dual:1; uint32_t mem_sdin_dual:1;
/** mem_sdout_dual : R/W; bitpos: [11]; default: 0; /** mem_sdout_dual : R/W; bitpos: [11]; default: 0;
* For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit
* is the same with spi_mem_s_usr_sram_dio. * is the same with spi_mem_s_usr_sram_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdout_dual:1; uint32_t mem_sdout_dual:1;
/** mem_saddr_dual : R/W; bitpos: [12]; default: 0; /** mem_saddr_dual : R/W; bitpos: [12]; default: 0;
* For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
* bit is the same with spi_mem_s_usr_sram_dio. * bit is the same with spi_mem_s_usr_sram_dio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_saddr_dual:1; uint32_t mem_saddr_dual:1;
uint32_t reserved_13:1; uint32_t reserved_13:1;
/** mem_sdin_quad : R/W; bitpos: [14]; default: 0; /** mem_sdin_quad : R/W; bitpos: [14]; default: 0;
* For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is
* the same with spi_mem_s_usr_sram_qio. * the same with spi_mem_s_usr_sram_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdin_quad:1; uint32_t mem_sdin_quad:1;
/** mem_sdout_quad : R/W; bitpos: [15]; default: 0; /** mem_sdout_quad : R/W; bitpos: [15]; default: 0;
* For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit
* is the same with spi_mem_s_usr_sram_qio. * is the same with spi_mem_s_usr_sram_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdout_quad:1; uint32_t mem_sdout_quad:1;
/** mem_saddr_quad : R/W; bitpos: [16]; default: 0; /** mem_saddr_quad : R/W; bitpos: [16]; default: 0;
* For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
* bit is the same with spi_mem_s_usr_sram_qio. * bit is the same with spi_mem_s_usr_sram_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_saddr_quad:1; uint32_t mem_saddr_quad:1;
/** mem_scmd_quad : R/W; bitpos: [17]; default: 0; /** mem_scmd_quad : R/W; bitpos: [17]; default: 0;
* For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is
* the same with spi_mem_s_usr_sram_qio. * the same with spi_mem_s_usr_sram_qio.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_scmd_quad:1; uint32_t mem_scmd_quad:1;
/** mem_sdin_oct : R/W; bitpos: [18]; default: 0; /** mem_sdin_oct : R/W; bitpos: [18]; default: 0;
* For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdin_oct:1; uint32_t mem_sdin_oct:1;
/** mem_sdout_oct : R/W; bitpos: [19]; default: 0; /** mem_sdout_oct : R/W; bitpos: [19]; default: 0;
* For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdout_oct:1; uint32_t mem_sdout_oct:1;
/** mem_saddr_oct : R/W; bitpos: [20]; default: 0; /** mem_saddr_oct : R/W; bitpos: [20]; default: 0;
* For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_saddr_oct:1; uint32_t mem_saddr_oct:1;
/** mem_scmd_oct : R/W; bitpos: [21]; default: 0; /** mem_scmd_oct : R/W; bitpos: [21]; default: 0;
* For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_scmd_oct:1; uint32_t mem_scmd_oct:1;
/** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1;
* In the dummy phase of a MSPI read data transfer when accesses to external RAM, the * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the
* signal level of SPI bus is output by the MSPI controller. * signal level of SPI bus is output by the MSPI controller.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdummy_rin:1; uint32_t mem_sdummy_rin:1;
/** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1;
* In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the
* signal level of SPI bus is output by the MSPI controller. * signal level of SPI bus is output by the MSPI controller.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdummy_wout:1; uint32_t mem_sdummy_wout:1;
/** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0;
@@ -771,10 +844,12 @@ typedef union {
uint32_t smem_wdummy_always_out:1; uint32_t smem_wdummy_always_out:1;
/** mem_sdin_hex : R/W; bitpos: [26]; default: 0; /** mem_sdin_hex : R/W; bitpos: [26]; default: 0;
* For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdin_hex:1; uint32_t mem_sdin_hex:1;
/** mem_sdout_hex : R/W; bitpos: [27]; default: 0; /** mem_sdout_hex : R/W; bitpos: [27]; default: 0;
* For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_sdout_hex:1; uint32_t mem_sdout_hex:1;
uint32_t reserved_28:2; uint32_t reserved_28:2;
@@ -800,12 +875,14 @@ typedef union {
/** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0;
* For SPI0,When cache mode is enable it is the read command value of command phase * For SPI0,When cache mode is enable it is the read command value of command phase
* for sram. * for sram.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_rd_cmd_value:16; uint32_t mem_cache_sram_usr_rd_cmd_value:16;
uint32_t reserved_16:12; uint32_t reserved_16:12;
/** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0;
* For SPI0,When cache mode is enable it is the length in bits of command phase for * For SPI0,When cache mode is enable it is the length in bits of command phase for
* sram. The register value shall be (bit_num-1). * sram. The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4;
}; };
@@ -820,12 +897,14 @@ typedef union {
/** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0;
* For SPI0,When cache mode is enable it is the write command value of command phase * For SPI0,When cache mode is enable it is the write command value of command phase
* for sram. * for sram.
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_wr_cmd_value:16; uint32_t mem_cache_sram_usr_wr_cmd_value:16;
uint32_t reserved_16:12; uint32_t reserved_16:12;
/** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0;
* For SPI0,When cache mode is enable it is the in bits of command phase for sram. * For SPI0,When cache mode is enable it is the in bits of command phase for sram.
* The register value shall be (bit_num-1). * The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4;
}; };
@@ -877,7 +956,7 @@ typedef union {
uint32_t smem_usr_ddr_dqs_thd:7; uint32_t smem_usr_ddr_dqs_thd:7;
/** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or * spi0_slv_st is in spi_mem_s_DIN state. It is used when there is no SPI_DQS signal or
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS. * negative edge of SPI_DQS.
*/ */
@@ -942,7 +1021,7 @@ typedef union {
*/ */
uint32_t smem_cs_hold_time:5; uint32_t smem_cs_hold_time:5;
/** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3;
* SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * spi_mem_s_smem_CS_HOLD_TIME + spi_mem_s_smem_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
* cycles in ECC mode when accessed external RAM. * cycles in ECC mode when accessed external RAM.
*/ */
uint32_t smem_ecc_cs_hold_time:3; uint32_t smem_ecc_cs_hold_time:3;
@@ -959,7 +1038,7 @@ typedef union {
uint32_t reserved_17:8; uint32_t reserved_17:8;
/** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
* These bits are used to set the minimum CS high time tSHSL between SPI burst * These bits are used to set the minimum CS high time tSHSL between SPI burst
* transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) * transfer when accesses to external RAM. tSHSL is (spi_mem_s_smem_CS_HOLD_DELAY[5:0] + 1)
* MSPI core clock cycles. * MSPI core clock cycles.
*/ */
uint32_t smem_cs_hold_delay:6; uint32_t smem_cs_hold_delay:6;
@@ -981,11 +1060,11 @@ typedef union {
typedef union { typedef union {
struct { struct {
uint32_t reserved_0:7; uint32_t reserved_0:7;
/** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4;
* The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
*/ */
uint32_t mem_lock_delay_time:5; uint32_t mem_lock_delay_time:12;
uint32_t reserved_12:20; uint32_t reserved_19:13;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_fsm_reg_t; } spi_mem_s_fsm_reg_t;
@@ -1026,9 +1105,17 @@ typedef union {
* The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
*/ */
uint32_t mem_axi_waddr_err_int__ena:1; uint32_t mem_axi_waddr_err_int__ena:1;
uint32_t reserved_10:18; uint32_t reserved_10:16;
/** mem_rx_trans_ovf_int_ena : R/W; bitpos: [26]; default: 0;
* The enable bit for spi_mem_s_RX_TRANS_OVF_INT interrupt.
*/
uint32_t mem_rx_trans_ovf_int_ena:1;
/** mem_tx_trans_udf_int_ena : R/W; bitpos: [27]; default: 0;
* The enable bit for spi_mem_s_TX_TRANS_UDF_INT interrupt.
*/
uint32_t mem_tx_trans_udf_int_ena:1;
/** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0;
* The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. * The enable bit for spi_mem_s_DQS0_AFIFO_OVF_INT interrupt.
*/ */
uint32_t mem_dqs0_afifo_ovf_int_ena:1; uint32_t mem_dqs0_afifo_ovf_int_ena:1;
/** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0;
@@ -1081,7 +1168,15 @@ typedef union {
* The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
*/ */
uint32_t mem_axi_waddr_err_int_clr:1; uint32_t mem_axi_waddr_err_int_clr:1;
uint32_t reserved_10:18; uint32_t reserved_10:16;
/** mem_rx_trans_ovf_int_clr : WT; bitpos: [26]; default: 0;
* The clear bit for spi_mem_s_RX_TRANS_OVF_INT interrupt.
*/
uint32_t mem_rx_trans_ovf_int_clr:1;
/** mem_tx_trans_udf_int_clr : WT; bitpos: [27]; default: 0;
* The clear bit for spi_mem_s_TX_TRANS_UDF_INT interrupt.
*/
uint32_t mem_tx_trans_udf_int_clr:1;
/** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0;
* The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
*/ */
@@ -1152,7 +1247,17 @@ typedef union {
* address is invalid by compared to MMU configuration. 0: Others. * address is invalid by compared to MMU configuration. 0: Others.
*/ */
uint32_t mem_axi_waddr_err_int_raw:1; uint32_t mem_axi_waddr_err_int_raw:1;
uint32_t reserved_10:18; uint32_t reserved_10:16;
/** mem_rx_trans_ovf_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* The raw bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx fifo
* to spi bus is overrflow.
*/
uint32_t mem_rx_trans_ovf_int_raw:1;
/** mem_tx_trans_udf_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* The raw bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo
* to spi bus is underflow.
*/
uint32_t mem_tx_trans_udf_int_raw:1;
/** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
* connected to SPI_DQS1 is overflow. * connected to SPI_DQS1 is overflow.
@@ -1211,7 +1316,15 @@ typedef union {
* The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt.
*/ */
uint32_t mem_axi_waddr_err_int_st:1; uint32_t mem_axi_waddr_err_int_st:1;
uint32_t reserved_10:18; uint32_t reserved_10:16;
/** mem_rx_trans_ovf_int_st : RO; bitpos: [26]; default: 0;
* The status bit for spi_mem_s_RX_TRANS_OVF_INT interrupt.
*/
uint32_t mem_rx_trans_ovf_int_st:1;
/** mem_tx_trans_udf_int_st : RO; bitpos: [27]; default: 0;
* The status bit for spi_mem_s_TX_TRANS_UDF_INT interrupt.
*/
uint32_t mem_tx_trans_udf_int_st:1;
/** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0;
* The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt.
*/ */
@@ -1233,62 +1346,175 @@ typedef union {
} spi_mem_s_int_st_reg_t; } spi_mem_s_int_st_reg_t;
/** Group: DLL debug and configuration registers */
/** Type of mem_dll_dly_db register
* MSPI DLL function and debug configuration register
*/
typedef union {
struct {
/** mem_dll_db_cfg_vld_cnt : R/W; bitpos: [7:0]; default: 0;
* Configures the end time of the debug window.
*/
uint32_t mem_dll_db_cfg_vld_cnt:8;
/** mem_dll_db_cnt_mode_sel : R/W; bitpos: [11:8]; default: 0;
* [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift
* wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0].
* [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0].
*/
uint32_t mem_dll_db_cnt_mode_sel:4;
/** mem_dll_db_cnt_clr : R/W; bitpos: [12]; default: 0;
* Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get
* ready for debug. 0: No debug.
*/
uint32_t mem_dll_db_cnt_clr:1;
/** mem_dll_din_dly_sel : R/W; bitpos: [13]; default: 0;
* Configures the din channel. 1: Use delayed data. 0: Do not use delayed data.
*/
uint32_t mem_dll_din_dly_sel:1;
uint32_t reserved_14:18;
};
uint32_t val;
} spi_mem_s_dll_dly_db_reg_t;
/** Group: DLL debug status registers */
/** Type of mem_dll_db_st0 register
* MSPI DLL debug status0 register
*/
typedef union {
struct {
/** mem_db_fifo_cnt_h : RO; bitpos: [31:0]; default: 0;
* Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes
* during the debug window. db_fifo_cnt[63:32]
*/
uint32_t mem_db_fifo_cnt_h:32;
};
uint32_t val;
} spi_mem_s_dll_db_st0_reg_t;
/** Type of mem_dll_db_st1 register
* MSPI DLL debug status1 register
*/
typedef union {
struct {
/** mem_db_fifo_cnt_l : RO; bitpos: [31:0]; default: 0;
* Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes
* during the debug window. db_fifo_cnt[31:0]
*/
uint32_t mem_db_fifo_cnt_l:32;
};
uint32_t val;
} spi_mem_s_dll_db_st1_reg_t;
/** Group: PMS control and configuration registers */ /** Group: PMS control and configuration registers */
/** Type of fmem_pmsn_attr register /** Type of fmem_pms0_attr register
* MSPI flash PMS section $n attribute register * MSPI flash PMS section $n attribute register
*/ */
typedef union { typedef union {
struct { struct {
/** fmem_pms_rd_attr : R/W; bitpos: [0]; default: 1; /** fmem_pms0_rd_attr : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
*/ */
uint32_t fmem_pms_rd_attr:1; uint32_t fmem_pms0_rd_attr:1;
/** fmem_pms_wr_attr : R/W; bitpos: [1]; default: 1; /** fmem_pms0_wr_attr : R/W; bitpos: [1]; default: 1;
* 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed.
*/ */
uint32_t fmem_pms_wr_attr:1; uint32_t fmem_pms0_wr_attr:1;
/** fmem_pms_ecc : R/W; bitpos: [2]; default: 0; /** fmem_pms0_ecc : R/W; bitpos: [2]; default: 0;
* SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
* PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and * section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and
* SPI_MEM_S_FMEM_PMS$n_SIZE_REG. * spi_mem_s_fmem_PMS0_SIZE_REG.
*/ */
uint32_t fmem_pms_ecc:1; uint32_t fmem_pms0_ecc:1;
uint32_t reserved_3:29; /** fmem_pms0_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed.
*/
uint32_t fmem_pms0_nonsecure_rd_attr:1;
/** fmem_pms0_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed.
*/
uint32_t fmem_pms0_nonsecure_wr_attr:1;
/** fmem_pms0_nonsecure_ecc : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and
* spi_mem_s_fmem_PMS0_SIZE_REG.
*/
uint32_t fmem_pms0_nonsecure_ecc:1;
uint32_t reserved_6:26;
};
uint32_t val;
} spi_mem_s_fmem_pms0_attr_reg_t;
/** Type of fmem_pmsn_attr register
* SPI1 flash PMS section n attribute register
*/
typedef union {
struct {
/** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section n read accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_rd_attr:1;
/** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1;
* 1: SPI1 flash PMS section n write accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_wr_attr:1;
/** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
* SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
* section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and
* spi_mem_s_fmem_PMSn_SIZE_REG.
*/
uint32_t fmem_pmsn_ecc:1;
/** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_nonsecure_rd_attr:1;
/** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_nonsecure_wr_attr:1;
/** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and
* spi_mem_s_fmem_PMSn_SIZE_REG.
*/
uint32_t fmem_pmsn_nonsecure_ecc:1;
uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_fmem_pmsn_attr_reg_t; } spi_mem_s_fmem_pmsn_attr_reg_t;
/** Type of fmem_pmsn_addr register /** Type of fmem_pmsn_addr register
* SPI1 flash PMS section $n start address register * SPI1 flash PMS section n start address register
*/ */
typedef union { typedef union {
struct { struct {
/** fmem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0;
* SPI1 flash PMS section $n start address value * SPI1 flash PMS section n start address value
*/ */
uint32_t fmem_pms_addr_s:27; uint32_t fmem_pmsn_addr_s:27;
uint32_t reserved_27:5; uint32_t reserved_27:5;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_fmem_pmsn_addr_reg_t; } spi_mem_s_fmem_pmsn_addr_reg_t;
/** Type of fmem_pmsn_size register /** Type of fmem_pmsn_size register
* SPI1 flash PMS section $n start address register * SPI1 flash PMS section n start address register
*/ */
typedef union { typedef union {
struct { struct {
/** fmem_pms_size : R/W; bitpos: [14:0]; default: 4096; /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
* SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, * SPI1 flash PMS section n address region is (spi_mem_s_fmem_PMSn_ADDR_S,
* SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) * spi_mem_s_fmem_PMSn_ADDR_S + spi_mem_s_fmem_PMSn_SIZE)
*/ */
uint32_t fmem_pms_size:15; uint32_t fmem_pmsn_size:15;
uint32_t reserved_15:17; uint32_t reserved_15:17;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_fmem_pmsn_size_reg_t; } spi_mem_s_fmem_pmsn_size_reg_t;
/** Type of smem_pmsn_attr register /** Type of smem_pmsn_attr register
* SPI1 flash PMS section $n start address register * SPI1 external RAM PMS section n attribute register
*/ */
typedef union { typedef union {
struct { struct {
@@ -1306,18 +1532,32 @@ typedef union {
* SPI_MEM_S_SMEM_PMS$n_SIZE_REG. * SPI_MEM_S_SMEM_PMS$n_SIZE_REG.
*/ */
uint32_t smem_pms_ecc:1; uint32_t smem_pms_ecc:1;
uint32_t reserved_3:29; /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed.
*/
uint32_t smem_pmsn_nonsecure_rd_attr:1;
/** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed.
*/
uint32_t smem_pmsn_nonsecure_wr_attr:1;
/** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section n is configured by registers
* spi_mem_s_smem_PMSn_ADDR_REG and spi_mem_s_smem_PMSn_SIZE_REG.
*/
uint32_t smem_pmsn_nonsecure_ecc:1;
uint32_t reserved_6:26;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_smem_pmsn_attr_reg_t; } spi_mem_s_smem_pmsn_attr_reg_t;
/** Type of smem_pmsn_addr register /** Type of smem_pmsn_addr register
* SPI1 external RAM PMS section $n start address register * SPI1 external RAM PMS section n start address register
*/ */
typedef union { typedef union {
struct { struct {
/** smem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0;
* SPI1 external RAM PMS section $n start address value * SPI1 external RAM PMS section n start address value
*/ */
uint32_t smem_pms_addr_s:27; uint32_t smem_pms_addr_s:27;
uint32_t reserved_27:5; uint32_t reserved_27:5;
@@ -1326,7 +1566,7 @@ typedef union {
} spi_mem_s_smem_pmsn_addr_reg_t; } spi_mem_s_smem_pmsn_addr_reg_t;
/** Type of smem_pmsn_size register /** Type of smem_pmsn_size register
* SPI1 external RAM PMS section $n start address register * SPI1 external RAM PMS section n start address register
*/ */
typedef union { typedef union {
struct { struct {
@@ -1347,7 +1587,7 @@ typedef union {
struct { struct {
/** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
* This bits show the first SPI1 access error address. It is cleared by when * This bits show the first SPI1 access error address. It is cleared by when
* SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. * spi_mem_s_PMS_REJECT_INT_CLR bit is set.
*/ */
uint32_t mem_reject_addr:27; uint32_t mem_reject_addr:27;
/** mem_pm_en : R/W; bitpos: [27]; default: 0; /** mem_pm_en : R/W; bitpos: [27]; default: 0;
@@ -1356,22 +1596,22 @@ typedef union {
uint32_t mem_pm_en:1; uint32_t mem_pm_en:1;
/** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
* 1: SPI1 write access error. 0: No write access error. It is cleared by when * 1: SPI1 write access error. 0: No write access error. It is cleared by when
* SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. * spi_mem_s_PMS_REJECT_INT_CLR bit is set.
*/ */
uint32_t mem_pms_ld:1; uint32_t mem_pms_ld:1;
/** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
* 1: SPI1 read access error. 0: No read access error. It is cleared by when * 1: SPI1 read access error. 0: No read access error. It is cleared by when
* SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. * spi_mem_s_PMS_REJECT_INT_CLR bit is set.
*/ */
uint32_t mem_pms_st:1; uint32_t mem_pms_st:1;
/** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
* 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
* cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. * cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set.
*/ */
uint32_t mem_pms_multi_hit:1; uint32_t mem_pms_multi_hit:1;
/** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
* 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
* error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. * error. It is cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set.
*/ */
uint32_t mem_pms_ivd:1; uint32_t mem_pms_ivd:1;
}; };
@@ -1388,11 +1628,11 @@ typedef union {
uint32_t reserved_0:5; uint32_t reserved_0:5;
/** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0;
* This bits show the error times of MSPI ECC read. It is cleared by when * This bits show the error times of MSPI ECC read. It is cleared by when
* SPI_MEM_S_ECC_ERR_INT_CLR bit is set. * spi_mem_s_ECC_ERR_INT_CLR bit is set.
*/ */
uint32_t mem_ecc_err_cnt:6; uint32_t mem_ecc_err_cnt:6;
/** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10;
* Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. * Set the error times of MSPI ECC read to generate MSPI spi_mem_s_ECC_ERR_INT interrupt.
*/ */
uint32_t fmem_ecc_err_int_num:6; uint32_t fmem_ecc_err_int_num:6;
/** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0;
@@ -1416,9 +1656,9 @@ typedef union {
uint32_t mem_usr_ecc_addr_en:1; uint32_t mem_usr_ecc_addr_en:1;
uint32_t reserved_22:2; uint32_t reserved_22:2;
/** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1;
* 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is * 1: The error information in spi_mem_s_ECC_ERR_BITS and spi_mem_s_ECC_ERR_ADDR is
* updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and * updated when there is an ECC error. 0: spi_mem_s_ECC_ERR_BITS and
* SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. * spi_mem_s_ECC_ERR_ADDR record the first ECC error information.
*/ */
uint32_t mem_ecc_continue_record_err_en:1; uint32_t mem_ecc_continue_record_err_en:1;
/** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0;
@@ -1437,7 +1677,7 @@ typedef union {
struct { struct {
/** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
* This bits show the first MSPI ECC error address. It is cleared by when * This bits show the first MSPI ECC error address. It is cleared by when
* SPI_MEM_S_ECC_ERR_INT_CLR bit is set. * spi_mem_s_ECC_ERR_INT_CLR bit is set.
*/ */
uint32_t mem_ecc_err_addr:27; uint32_t mem_ecc_err_addr:27;
uint32_t reserved_27:5; uint32_t reserved_27:5;
@@ -2279,13 +2519,13 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** xts_physical_address : R/W; bitpos: [25:0]; default: 0; /** xts_physical_address : R/W; bitpos: [29:0]; default: 0;
* This bits stores the physical-address parameter which will be used in manual * This bits stores the physical-address parameter which will be used in manual
* encryption calculation. This value should aligned with byte number decided by * encryption calculation. This value should aligned with byte number decided by
* line-size parameter. * line-size parameter.
*/ */
uint32_t xts_physical_address:26; uint32_t xts_physical_address:30;
uint32_t reserved_26:6; uint32_t reserved_30:2;
}; };
uint32_t val; uint32_t val;
} spi_mem_s_xts_physical_address_reg_t; } spi_mem_s_xts_physical_address_reg_t;
@@ -2364,7 +2604,7 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** xts_date : R/W; bitpos: [29:0]; default: 538972176; /** xts_date : R/W; bitpos: [29:0]; default: 539035911;
* This bits stores the last modified-time of manual encryption feature. * This bits stores the last modified-time of manual encryption feature.
*/ */
uint32_t xts_date:30; uint32_t xts_date:30;
@@ -2421,17 +2661,23 @@ typedef union {
* controlled by rtc. * controlled by rtc.
*/ */
uint32_t mmu_mem_force_pu:1; uint32_t mmu_mem_force_pu:1;
uint32_t reserved_3:13; /** mmu_page_size : R/W; bitpos: [4:3]; default: 0;
* 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
*/
uint32_t mmu_page_size:2;
uint32_t reserved_5:11;
/** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896;
* MMU PSRAM aux control register * MMU PSRAM aux control register
*/ */
uint32_t mem_aux_ctrl:14; uint32_t mem_aux_ctrl:14;
/** mem_rdn_ena : R/W; bitpos: [30]; default: 0; /** mem_rdn_ena : R/W; bitpos: [30]; default: 0;
* ECO register enable bit * ECO register enable bit
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_rdn_ena:1; uint32_t mem_rdn_ena:1;
/** mem_rdn_result : RO; bitpos: [31]; default: 0; /** mem_rdn_result : RO; bitpos: [31]; default: 0;
* MSPI module clock domain and AXI clock domain ECO register result register * MSPI module clock domain and AXI clock domain ECO register result register
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_rdn_result:1; uint32_t mem_rdn_result:1;
}; };
@@ -2468,6 +2714,37 @@ typedef union {
} spi_mem_s_dpa_ctrl_reg_t; } spi_mem_s_dpa_ctrl_reg_t;
/** Group: External mem cryption PSEUDO registers */
/** Type of mem_xts_pseudo_round_conf register
* SPI memory cryption PSEUDO register
*/
typedef union {
struct {
/** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0;
* Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo
* and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo.
* 2'b11: crypto with pseudo.
*/
uint32_t mem_mode_pseudo:2;
/** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7;
* xts aes peseudo function base round that must be performed.
*/
uint32_t mem_pseudo_rng_cnt:3;
/** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2;
* xts aes peseudo function base round that must be performed.
*/
uint32_t mem_pseudo_base:4;
/** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2;
* xts aes peseudo function increment round that will be performed randomly between 0 &
* 2**(inc+1).
*/
uint32_t mem_pseudo_inc:2;
uint32_t reserved_11:21;
};
uint32_t val;
} spi_mem_s_xts_pseudo_round_conf_reg_t;
/** Group: ECO registers */ /** Group: ECO registers */
/** Type of mem_registerrnd_eco_high register /** Type of mem_registerrnd_eco_high register
* MSPI ECO high register * MSPI ECO high register
@@ -2476,6 +2753,7 @@ typedef union {
struct { struct {
/** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892;
* ECO high register * ECO high register
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_registerrnd_eco_high:32; uint32_t mem_registerrnd_eco_high:32;
}; };
@@ -2489,6 +2767,7 @@ typedef union {
struct { struct {
/** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892;
* ECO low register * ECO low register
* This field is only for internal debugging purposes. Do not use it in applications.
*/ */
uint32_t mem_registerrnd_eco_low:32; uint32_t mem_registerrnd_eco_low:32;
}; };
@@ -2502,7 +2781,7 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** mem_date : R/W; bitpos: [27:0]; default: 36712704; /** mem_date : R/W; bitpos: [27:0]; default: 38801984;
* SPI0 register version. * SPI0 register version.
*/ */
uint32_t mem_date:28; uint32_t mem_date:28;
@@ -2542,8 +2821,12 @@ typedef struct spi_mem_s_dev_t {
uint32_t reserved_0d0; uint32_t reserved_0d0;
volatile spi_mem_s_ddr_reg_t mem_ddr; volatile spi_mem_s_ddr_reg_t mem_ddr;
volatile spi_mem_s_smem_ddr_reg_t smem_ddr; volatile spi_mem_s_smem_ddr_reg_t smem_ddr;
uint32_t reserved_0dc[9]; volatile spi_mem_s_dll_dly_db_reg_t mem_dll_dly_db;
volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; volatile spi_mem_s_dll_db_st0_reg_t mem_dll_db_st0;
volatile spi_mem_s_dll_db_st1_reg_t mem_dll_db_st1;
uint32_t reserved_0e8[6];
volatile spi_mem_s_fmem_pms0_attr_reg_t fmem_pms0_attr;
volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[3];
volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
@@ -2587,7 +2870,8 @@ typedef struct spi_mem_s_dev_t {
volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index; volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index;
volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl; volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl;
uint32_t reserved_38c[25]; volatile spi_mem_s_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf;
uint32_t reserved_390[24];
volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high;
volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low;
uint32_t reserved_3f8; uint32_t reserved_3f8;

2
components/spi_flash/Kconfig
View File

@@ -113,7 +113,7 @@ menu "Main Flash configuration"
int "SPI flash tRS value (refer to chapter AC CHARACTERISTICS)" int "SPI flash tRS value (refer to chapter AC CHARACTERISTICS)"
default 50 default 50
range 20 200 range 20 200
depends on SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR depends on SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR && (!ESP32P4_SELECTS_REV_LESS_V3)
help help
This config is used for setting Trs parameter. Trs means CS Latency Between Resume And Next Suspend. This config is used for setting Trs parameter. Trs means CS Latency Between Resume And Next Suspend.
You can refer to the chapter of AC CHARACTERISTICS of flash datasheet. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.

4
components/spi_flash/esp_flash_spi_init.c
View File

@@ -138,7 +138,9 @@ esp_flash_t *esp_flash_default_chip = NULL;
} }
#define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US #define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define TRS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US #define TRS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US
#endif
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
#endif // Other target #endif // Other target
@@ -527,12 +529,14 @@ esp_err_t esp_flash_init_default_chip(void)
cfg.tsus_val = TSUS_VAL_SUSPEND; cfg.tsus_val = TSUS_VAL_SUSPEND;
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if (TRS_VAL_SUSPEND > 400 || TRS_VAL_SUSPEND < 20) { if (TRS_VAL_SUSPEND > 400 || TRS_VAL_SUSPEND < 20) {
// Assume that the TRS value cannot larger than 400 (because the performance might be really bad) // Assume that the TRS value cannot larger than 400 (because the performance might be really bad)
// And value cannot smaller than 20 (never see that small tsus value, might be wrong) // And value cannot smaller than 20 (never see that small tsus value, might be wrong)
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
cfg.trs_val = TRS_VAL_SUSPEND; cfg.trs_val = TRS_VAL_SUSPEND;
#endif
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#endif // CONFIG_SPI_FLASH_AUTO_SUSPEND #endif // CONFIG_SPI_FLASH_AUTO_SUSPEND