From ec5176e95a7813e37132af88ef85e115f378c130 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 10 Apr 2025 18:08:37 +0800 Subject: [PATCH 1/3] fix(gpio): IO7 is not a LP IO anymore on C5 ECO2 chip --- .../test_apps/gpio/main/test_rtcio.h | 4 +- components/hal/esp32c5/include/hal/i2c_ll.h | 8 +- .../hal/esp32c5/include/hal/rtc_io_ll.h | 14 +- components/soc/esp32c5/i2c_periph.c | 15 +- .../esp32c5/include/soc/Kconfig.soc_caps.in | 6 +- .../soc/esp32c5/include/soc/rtc_io_channel.h | 3 - components/soc/esp32c5/include/soc/soc_caps.h | 10 +- .../soc/esp32c5/register/soc/gpio_ext_reg.h | 1629 ++-- .../esp32c5/register/soc/gpio_ext_struct.h | 299 +- .../soc/esp32c5/register/soc/gpio_reg.h | 6578 ++++++++--------- .../soc/esp32c5/register/soc/gpio_struct.h | 1126 +-- .../soc/esp32c5/register/soc/io_mux_reg.h | 31 +- .../soc/esp32c5/register/soc/lp_gpio_reg.h | 638 +- .../soc/esp32c5/register/soc/lp_gpio_struct.h | 233 +- .../soc/esp32c5/register/soc/lp_iomux_reg.h | 668 +- .../esp32c5/register/soc/lp_iomux_struct.h | 83 +- components/soc/esp32c5/rtc_io_periph.c | 2 +- components/ulp/lp_core/lp_core_i2c.c | 12 +- .../peripherals/gpio/esp32c5.inc | 6 +- .../peripherals/gpio/esp32c5.inc | 6 +- .../system/deep_sleep/main/Kconfig.projbuild | 14 +- 21 files changed, 4822 insertions(+), 6563 deletions(-) diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index e3518e7428..bec0d96baa 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -96,7 +96,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_21, //GPIO21 }; #define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6 -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 +#elif CONFIG_IDF_TARGET_ESP32C6 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 #define TEST_GPIO_PIN_COUNT 8 @@ -146,7 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_14, //GPIO14 GPIO_NUM_15, //GPIO15 }; -#elif CONFIG_IDF_TARGET_ESP32C61 +#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 #define TEST_GPIO_PIN_COUNT 7 diff --git a/components/hal/esp32c5/include/hal/i2c_ll.h b/components/hal/esp32c5/include/hal/i2c_ll.h index 7078981a6e..3553b98847 100644 --- a/components/hal/esp32c5/include/hal/i2c_ll.h +++ b/components/hal/esp32c5/include/hal/i2c_ll.h @@ -82,11 +82,11 @@ typedef enum { // Record for Pins usage logs -#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#7" -#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#6" +#define LP_I2C_SCL_PIN_ERR_LOG "SCL pin can only be configured as GPIO#3" +#define LP_I2C_SDA_PIN_ERR_LOG "SDA pin can only be configured as GPIO#2" -#define LP_I2C_SDA_IOMUX_PAD 6 -#define LP_I2C_SCL_IOMUX_PAD 7 +#define LP_I2C_SDA_IOMUX_PAD 2 +#define LP_I2C_SCL_IOMUX_PAD 3 /** * @brief Calculate I2C bus frequency diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index 0a1104d7d5..8210382195 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -101,7 +101,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num)); + LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); } /** @@ -111,7 +111,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num)); + LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); } /** @@ -123,9 +123,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num)); + LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); } else { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num)); + LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); } } @@ -157,7 +157,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num) */ static inline uint32_t rtcio_ll_get_level(int rtcio_num) { - return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, in_data_next) >> rtcio_num) & 0x1; + return (LP_GPIO.in.in_data_next >> rtcio_num) & 0x1; } /** @@ -428,7 +428,7 @@ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) */ static inline uint32_t rtcio_ll_get_interrupt_status(void) { - return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, status_interrupt); + return LP_GPIO.status.status_interrupt; } /** @@ -436,7 +436,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff); + LP_GPIO.status_w1tc.status_w1tc = 0x7F; } #ifdef __cplusplus diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c index fb20be89e3..6ae52cb0cf 100644 --- a/components/soc/esp32c5/i2c_periph.c +++ b/components/soc/esp32c5/i2c_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,15 +7,7 @@ #include "soc/i2c_periph.h" #include "soc/gpio_sig_map.h" -/* - Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc -*/ -typedef enum { - LP_I2C_MUX_FUNC = 0, - LP_GPIO_MUX_FUNC = 1, - LP_IO_MUX_FUNC_NUM = 2, - LP_MUX_FUNC_NOT_USED = 0xFF, -} lp_io_mux_func_t; +#define LP_I2C_MUX_FUNC (3) static_assert(SOC_I2C_NUM == (SOC_HP_I2C_NUM + SOC_LP_I2C_NUM)); @@ -26,7 +18,6 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { .sda_in_sig = I2CEXT0_SDA_IN_IDX, .scl_out_sig = I2CEXT0_SCL_OUT_IDX, .scl_in_sig = I2CEXT0_SCL_IN_IDX, - .iomux_func = (uint8_t)LP_MUX_FUNC_NOT_USED, .irq = ETS_I2C_EXT0_INTR_SOURCE, }, /* LP_I2C_NUM_0*/ @@ -35,7 +26,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { .sda_in_sig = 0, .scl_out_sig = 0, .scl_in_sig = 0, - .iomux_func = (uint8_t)LP_I2C_MUX_FUNC, + .iomux_func = LP_I2C_MUX_FUNC, .irq = ETS_LP_I2C_INTR_SOURCE, }, }; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index bd9dcc55ce..cb1e80430a 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -541,11 +541,11 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT int - default 8 + default 7 config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex - default 0x0000000001FFFF00 + default 0x0000000001FFFF80 config SOC_GPIO_SUPPORT_FORCE_HOLD bool @@ -565,7 +565,7 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM config SOC_RTCIO_PIN_COUNT int - default 8 + default 7 config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED bool diff --git a/components/soc/esp32c5/include/soc/rtc_io_channel.h b/components/soc/esp32c5/include/soc/rtc_io_channel.h index df2120f045..36b9b5f80e 100644 --- a/components/soc/esp32c5/include/soc/rtc_io_channel.h +++ b/components/soc/esp32c5/include/soc/rtc_io_channel.h @@ -26,6 +26,3 @@ #define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 #define RTCIO_CHANNEL_6_GPIO_NUM 6 - -#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 -#define RTCIO_CHANNEL_7_GPIO_NUM 7 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 1df6ef263d..4cc70e312b 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -223,11 +223,11 @@ #define SOC_GPIO_IN_RANGE_MAX 28 #define SOC_GPIO_OUT_RANGE_MAX 28 -#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) -#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8) +#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) +#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7) -// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28) -#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) @@ -241,7 +241,7 @@ #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ -#define SOC_RTCIO_PIN_COUNT 8 +#define SOC_RTCIO_PIN_COUNT 7 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) * when the pins are switched to RTC function. diff --git a/components/soc/esp32c5/register/soc/gpio_ext_reg.h b/components/soc/esp32c5/register/soc/gpio_ext_reg.h index e3af8b4f34..74ede57af5 100644 --- a/components/soc/esp32c5/register/soc/gpio_ext_reg.h +++ b/components/soc/esp32c5/register/soc/gpio_ext_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,26 +11,15 @@ extern "C" { #endif -/** GPIO_EXT_CLOCK_GATE_REG register - * Clock Gating Configure Register - */ -#define GPIO_EXT_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x0) -/** GPIO_EXT_CLK_EN : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ -#define GPIO_EXT_CLK_EN (BIT(0)) -#define GPIO_EXT_CLK_EN_M (GPIO_EXT_CLK_EN_V << GPIO_EXT_CLK_EN_S) -#define GPIO_EXT_CLK_EN_V 0x00000001U -#define GPIO_EXT_CLK_EN_S 0 - /** GPIO_EXT_SIGMADELTA_MISC_REG register * MISC Register */ #define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x4) /** GPIO_EXT_SIGMADELTA_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the clock for sigma delta modulation.\\ - * 0: Not enable\\ - * 1: Enable\\%\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. + * Configures whether or not to enable the clock for sigma delta modulation. + * 0: Not enable + * 1: Enable + * %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. */ #define GPIO_EXT_SIGMADELTA_CLK_EN (BIT(0)) #define GPIO_EXT_SIGMADELTA_CLK_EN_M (GPIO_EXT_SIGMADELTA_CLK_EN_V << GPIO_EXT_SIGMADELTA_CLK_EN_S) @@ -42,14 +31,14 @@ extern "C" { */ #define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x8) /** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * Configures the duty cycle of sigma delta modulation output. \\ + * Configures the duty cycle of sigma delta modulation output. */ #define GPIO_EXT_SD0_IN 0x000000FFU #define GPIO_EXT_SD0_IN_M (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S) #define GPIO_EXT_SD0_IN_V 0x000000FFU #define GPIO_EXT_SD0_IN_S 0 /** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * Configures the divider value to divide IO MUX operating clock. \\ + * Configures the divider value to divide IO MUX operating clock. */ #define GPIO_EXT_SD0_PRESCALE 0x000000FFU #define GPIO_EXT_SD0_PRESCALE_M (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S) @@ -61,14 +50,14 @@ extern "C" { */ #define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0xc) /** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0; - * Configures the duty cycle of sigma delta modulation output. \\ + * Configures the duty cycle of sigma delta modulation output. */ #define GPIO_EXT_SD1_IN 0x000000FFU #define GPIO_EXT_SD1_IN_M (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S) #define GPIO_EXT_SD1_IN_V 0x000000FFU #define GPIO_EXT_SD1_IN_S 0 /** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * Configures the divider value to divide IO MUX operating clock. \\ + * Configures the divider value to divide IO MUX operating clock. */ #define GPIO_EXT_SD1_PRESCALE 0x000000FFU #define GPIO_EXT_SD1_PRESCALE_M (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S) @@ -80,14 +69,14 @@ extern "C" { */ #define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x10) /** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0; - * Configures the duty cycle of sigma delta modulation output. \\ + * Configures the duty cycle of sigma delta modulation output. */ #define GPIO_EXT_SD2_IN 0x000000FFU #define GPIO_EXT_SD2_IN_M (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S) #define GPIO_EXT_SD2_IN_V 0x000000FFU #define GPIO_EXT_SD2_IN_S 0 /** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * Configures the divider value to divide IO MUX operating clock. \\ + * Configures the divider value to divide IO MUX operating clock. */ #define GPIO_EXT_SD2_PRESCALE 0x000000FFU #define GPIO_EXT_SD2_PRESCALE_M (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S) @@ -99,14 +88,14 @@ extern "C" { */ #define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0x14) /** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0; - * Configures the duty cycle of sigma delta modulation output. \\ + * Configures the duty cycle of sigma delta modulation output. */ #define GPIO_EXT_SD3_IN 0x000000FFU #define GPIO_EXT_SD3_IN_M (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S) #define GPIO_EXT_SD3_IN_V 0x000000FFU #define GPIO_EXT_SD3_IN_S 0 /** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * Configures the divider value to divide IO MUX operating clock. \\ + * Configures the divider value to divide IO MUX operating clock. */ #define GPIO_EXT_SD3_PRESCALE 0x000000FFU #define GPIO_EXT_SD3_PRESCALE_M (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S) @@ -118,31 +107,31 @@ extern "C" { */ #define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58) /** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the function of analog PAD voltage comparator. + * 0: Disable + * 1: Enable */ #define GPIO_EXT_XPD_COMP_0 (BIT(0)) #define GPIO_EXT_XPD_COMP_0_M (GPIO_EXT_XPD_COMP_0_V << GPIO_EXT_XPD_COMP_0_S) #define GPIO_EXT_XPD_COMP_0_V 0x00000001U #define GPIO_EXT_XPD_COMP_0_S 0 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * Configures the reference voltage for analog PAD voltage comparator.. + * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8(GPIO8: need + * be reviewd) PAD can be used as a regular GPIO + * 1: Reference voltage is the voltage on the GPIO8 PAD */ #define GPIO_EXT_MODE_COMP_0 (BIT(1)) #define GPIO_EXT_MODE_COMP_0_M (GPIO_EXT_MODE_COMP_0_V << GPIO_EXT_MODE_COMP_0_S) #define GPIO_EXT_MODE_COMP_0_V 0x00000001U #define GPIO_EXT_MODE_COMP_0_S 1 /** GPIO_EXT_DREF_COMP_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * …...\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * Configures the internal reference voltage for analog PAD voltage coparator. + * 0: Internal reference voltage is 0 * VDDPST1(VDDPST1: need be reviewed) + * 1: Internal reference voltage is 0.1 * VDDPST1 + * ...... + * 6: Internal reference voltage is 0.6 * VDDPST1 + * 7: Internal reference voltage is 0.7 * VDDPST1 */ #define GPIO_EXT_DREF_COMP_0 0x00000007U #define GPIO_EXT_DREF_COMP_0_M (GPIO_EXT_DREF_COMP_0_V << GPIO_EXT_DREF_COMP_0_S) @@ -155,8 +144,8 @@ extern "C" { #define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c) /** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0; * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * comparator. + * Measurement unit: IO MUX operating clock cycle */ #define GPIO_EXT_ZERO_DET_FILTER_CNT_0 0xFFFFFFFFU #define GPIO_EXT_ZERO_DET_FILTER_CNT_0_M (GPIO_EXT_ZERO_DET_FILTER_CNT_0_V << GPIO_EXT_ZERO_DET_FILTER_CNT_0_S) @@ -168,22 +157,22 @@ extern "C" { */ #define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0xd8) /** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 0 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable channel 0 of Glitch Filter. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_FILTER_CH0_EN (BIT(0)) #define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) #define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U #define GPIO_EXT_FILTER_CH0_EN_S 0 /** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ #define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU #define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) @@ -191,8 +180,9 @@ extern "C" { #define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 /** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH0_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH0_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ #define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU #define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) @@ -200,8 +190,8 @@ extern "C" { #define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 /** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ #define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU #define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) @@ -212,338 +202,345 @@ extern "C" { * Glitch Filter Configure Register of Channel1 */ #define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0xdc) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 1 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 1 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH1_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH1_EN_M (GPIO_EXT_FILTER_CH1_EN_V << GPIO_EXT_FILTER_CH1_EN_S) +#define GPIO_EXT_FILTER_CH1_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH1_EN_S 0 +/** GPIO_EXT_FILTER_CH1_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH1_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH1_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH1_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_M (GPIO_EXT_FILTER_CH1_WINDOW_THRES_V << GPIO_EXT_FILTER_CH1_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH1_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH2_REG register * Glitch Filter Configure Register of Channel2 */ #define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0xe0) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 2 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 2 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH2_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH2_EN_M (GPIO_EXT_FILTER_CH2_EN_V << GPIO_EXT_FILTER_CH2_EN_S) +#define GPIO_EXT_FILTER_CH2_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH2_EN_S 0 +/** GPIO_EXT_FILTER_CH2_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH2_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH2_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH2_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_M (GPIO_EXT_FILTER_CH2_WINDOW_THRES_V << GPIO_EXT_FILTER_CH2_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH2_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH3_REG register * Glitch Filter Configure Register of Channel3 */ #define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0xe4) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 3 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH3_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 3 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH3_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH3_EN_M (GPIO_EXT_FILTER_CH3_EN_V << GPIO_EXT_FILTER_CH3_EN_S) +#define GPIO_EXT_FILTER_CH3_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH3_EN_S 0 +/** GPIO_EXT_FILTER_CH3_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH3_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH3_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH3_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_M (GPIO_EXT_FILTER_CH3_WINDOW_THRES_V << GPIO_EXT_FILTER_CH3_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH3_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH4_REG register * Glitch Filter Configure Register of Channel4 */ #define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0xe8) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 4 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH4_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 4 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH4_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH4_EN_M (GPIO_EXT_FILTER_CH4_EN_V << GPIO_EXT_FILTER_CH4_EN_S) +#define GPIO_EXT_FILTER_CH4_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH4_EN_S 0 +/** GPIO_EXT_FILTER_CH4_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH4_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH4_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH4_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_M (GPIO_EXT_FILTER_CH4_WINDOW_THRES_V << GPIO_EXT_FILTER_CH4_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH4_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH5_REG register * Glitch Filter Configure Register of Channel5 */ #define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0xec) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 5 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH5_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 5 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH5_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH5_EN_M (GPIO_EXT_FILTER_CH5_EN_V << GPIO_EXT_FILTER_CH5_EN_S) +#define GPIO_EXT_FILTER_CH5_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH5_EN_S 0 +/** GPIO_EXT_FILTER_CH5_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH5_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH5_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH5_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_M (GPIO_EXT_FILTER_CH5_WINDOW_THRES_V << GPIO_EXT_FILTER_CH5_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH5_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH6_REG register * Glitch Filter Configure Register of Channel6 */ #define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0xf0) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 6 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH6_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 6 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH6_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH6_EN_M (GPIO_EXT_FILTER_CH6_EN_V << GPIO_EXT_FILTER_CH6_EN_S) +#define GPIO_EXT_FILTER_CH6_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH6_EN_S 0 +/** GPIO_EXT_FILTER_CH6_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH6_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH6_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH6_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_M (GPIO_EXT_FILTER_CH6_WINDOW_THRES_V << GPIO_EXT_FILTER_CH6_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH6_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_S 14 /** GPIO_EXT_GLITCH_FILTER_CH7_REG register * Glitch Filter Configure Register of Channel7 */ #define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0xf4) -/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel 7 of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ +/** GPIO_EXT_FILTER_CH7_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable channel 7 of Glitch Filter. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) -#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) -#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U -#define GPIO_EXT_FILTER_CH0_EN_S 0 -/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +#define GPIO_EXT_FILTER_CH7_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH7_EN_M (GPIO_EXT_FILTER_CH7_EN_V << GPIO_EXT_FILTER_CH7_EN_S) +#define GPIO_EXT_FILTER_CH7_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH7_EN_S 0 +/** GPIO_EXT_FILTER_CH7_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH7_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CH7_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CH7_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 8 -/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_M (GPIO_EXT_FILTER_CH7_WINDOW_THRES_V << GPIO_EXT_FILTER_CH7_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_S 8 +/** GPIO_EXT_FILTER_CH7_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 14 +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_S 14 /** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register - * Etm Config register of Channel0 + * ETM configuration register for channel 0 */ #define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118) /** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ #define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) #define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 /** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) #define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) @@ -551,338 +548,293 @@ extern "C" { #define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register - * Etm Config register of Channel1 + * ETM configuration register for channel 1 */ #define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S) +#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register - * Etm Config register of Channel2 + * ETM configuration register for channel 2 */ #define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S) +#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register - * Etm Config register of Channel3 + * ETM configuration register for channel 3 */ #define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S) +#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register - * Etm Config register of Channel4 + * ETM configuration register for channel 4 */ #define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S) +#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register - * Etm Config register of Channel5 + * ETM configuration register for channel 5 */ #define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S) +#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register - * Etm Config register of Channel6 + * ETM configuration register for channel 6 */ #define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S) +#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register - * Etm Config register of Channel7 + * ETM configuration register for channel 7 */ #define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ +/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ -#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) -#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S) +#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7 /** GPIO_EXT_ETM_TASK_P0_CFG_REG register * GPIO selection register 0 for ETM */ #define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158) /** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO0. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO0 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) #define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO0_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO1. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO1 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) #define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO1_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO2. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO2 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) #define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO2_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO3. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO3 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) #define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO3_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO4. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO4 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) @@ -894,145 +846,100 @@ extern "C" { */ #define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c) /** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO5. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO5 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) #define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO5_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO6. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO6 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) #define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO6_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO7. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO7 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) #define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO7_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO8. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO8 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) #define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO8_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO9. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO9 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) @@ -1044,145 +951,100 @@ extern "C" { */ #define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160) /** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO10. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO10 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) #define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO10_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO11. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO11 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) #define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO11_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO12. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO12 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) #define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO12_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO13. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO13 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) #define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO13_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO14. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO14 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) @@ -1194,145 +1056,100 @@ extern "C" { */ #define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164) /** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO15. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO15 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) #define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO15_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO16. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO16 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) #define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO16_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO17. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO17 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) #define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO17_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO18. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO18 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) #define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO18_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO19. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO19 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) @@ -1344,145 +1161,100 @@ extern "C" { */ #define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168) /** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO20. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO20 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) #define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO20_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO21. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO21 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) #define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO21_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO22. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO22 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) #define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO22_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO23. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO23 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) #define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO23_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO24. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO24 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) @@ -1494,116 +1266,80 @@ extern "C" { */ #define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x16c) /** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO25. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO25 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) #define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO25_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO26. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO26 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) #define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO26_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO27_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO27. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO27_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO27_SEL_M (GPIO_EXT_ETM_TASK_GPIO27_SEL_V << GPIO_EXT_ETM_TASK_GPIO27_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO27_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO27_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO27_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO27 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO27_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO27_EN_M (GPIO_EXT_ETM_TASK_GPIO27_EN_V << GPIO_EXT_ETM_TASK_GPIO27_EN_S) #define GPIO_EXT_ETM_TASK_GPIO27_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO27_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO28_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO28. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ #define GPIO_EXT_ETM_TASK_GPIO28_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO28_SEL_M (GPIO_EXT_ETM_TASK_GPIO28_SEL_V << GPIO_EXT_ETM_TASK_GPIO28_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO28_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO28_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO28_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO28 to response ETM task. + * 0: Not enable + * 1: Enable */ #define GPIO_EXT_ETM_TASK_GPIO28_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO28_EN_M (GPIO_EXT_ETM_TASK_GPIO28_EN_V << GPIO_EXT_ETM_TASK_GPIO28_EN_S) @@ -1716,11 +1452,14 @@ extern "C" { /** GPIO_EXT_PIN_CTRL_REG register * Clock Output Configuration Register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0) /** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0; * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. * CLK_OUT_out1 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define GPIO_EXT_CLK_OUT1 0x0000001FU #define GPIO_EXT_CLK_OUT1_M (GPIO_EXT_CLK_OUT1_V << GPIO_EXT_CLK_OUT1_S) @@ -1729,6 +1468,7 @@ extern "C" { /** GPIO_EXT_CLK_OUT2 : R/W; bitpos: [9:5]; default: 0; * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. * CLK_OUT_out2 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define GPIO_EXT_CLK_OUT2 0x0000001FU #define GPIO_EXT_CLK_OUT2_M (GPIO_EXT_CLK_OUT2_V << GPIO_EXT_CLK_OUT2_S) @@ -1737,6 +1477,7 @@ extern "C" { /** GPIO_EXT_CLK_OUT3 : R/W; bitpos: [14:10]; default: 0; * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. * CLK_OUT_out3 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define GPIO_EXT_CLK_OUT3 0x0000001FU #define GPIO_EXT_CLK_OUT3_M (GPIO_EXT_CLK_OUT3_V << GPIO_EXT_CLK_OUT3_S) @@ -1744,10 +1485,10 @@ extern "C" { #define GPIO_EXT_CLK_OUT3_S 10 /** GPIO_EXT_VERSION_REG register - * Version Control Register + * Version control register */ #define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc) -/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 36774208; +/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37815040; * Version control register. */ #define GPIO_EXT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/gpio_ext_struct.h b/components/soc/esp32c5/register/soc/gpio_ext_struct.h index 19b033c2b6..c8c7873d23 100644 --- a/components/soc/esp32c5/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32c5/register/soc/gpio_ext_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,21 +10,6 @@ extern "C" { #endif -/** Group: Clock gate Register */ -/** Type of clock_gate register - * Clock Gating Configure Register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ - uint32_t clk_en: 1; - uint32_t reserved_1: 31; - }; - uint32_t val; -} gpio_ext_clock_gate_reg_t; - /** Group: SDM Configure Registers */ /** Type of sigmadelta_misc register * MISC Register @@ -32,9 +17,10 @@ typedef union { typedef union { struct { /** sigmadelta_clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the clock for sigma delta modulation.\\ - * 0: Not enable\\ - * 1: Enable\\%\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. + * Configures whether or not to enable the clock for sigma delta modulation. + * 0: Not enable + * 1: Enable + * %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved. */ uint32_t sigmadelta_clk_en: 1; uint32_t reserved_1: 31; @@ -48,11 +34,11 @@ typedef union { typedef union { struct { /** sdn_in : R/W; bitpos: [7:0]; default: 0; - * Configures the duty cycle of sigma delta modulation output. \\ + * Configures the duty cycle of sigma delta modulation output. */ uint32_t sdn_in: 8; /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; - * Configures the divider value to divide IO MUX operating clock. \\ + * Configures the divider value to divide IO MUX operating clock. */ uint32_t sdn_prescale: 8; uint32_t reserved_16: 16; @@ -67,28 +53,28 @@ typedef union { typedef union { struct { /** xpd_comp_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether to enable the function of analog PAD voltage comparator. + * 0: Disable + * 1: Enable */ - uint32_t xpd_comp_0: 1; + uint32_t xpd_comp_0:1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * Configures the reference voltage for analog PAD voltage comparator.. + * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8(GPIO8: need + * be reviewd) PAD can be used as a regular GPIO + * 1: Reference voltage is the voltage on the GPIO8 PAD */ - uint32_t mode_comp_0: 1; + uint32_t mode_comp_0:1; /** dref_comp_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * …...\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * Configures the internal reference voltage for analog PAD voltage coparator. + * 0: Internal reference voltage is 0 * VDDPST1(VDDPST1: need be reviewed) + * 1: Internal reference voltage is 0.1 * VDDPST1 + * ...... + * 6: Internal reference voltage is 0.6 * VDDPST1 + * 7: Internal reference voltage is 0.7 * VDDPST1 */ - uint32_t dref_comp_0: 3; - uint32_t reserved_5: 27; + uint32_t dref_comp_0:3; + uint32_t reserved_5:27; }; uint32_t val; } gpio_ext_pad_comp_config_0_reg_t; @@ -100,8 +86,8 @@ typedef union { struct { /** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0; * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * comparator. + * Measurement unit: IO MUX operating clock cycle */ uint32_t zero_det_filter_cnt_0: 32; }; @@ -116,19 +102,22 @@ typedef union { /** clk_out1 : R/W; bitpos: [4:0]; default: 0; * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. * CLK_OUT_out1 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t clk_out1: 5; + uint32_t clk_out1:5; /** clk_out2 : R/W; bitpos: [9:5]; default: 0; * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. * CLK_OUT_out2 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t clk_out2: 5; + uint32_t clk_out2:5; /** clk_out3 : R/W; bitpos: [14:10]; default: 0; * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. * CLK_OUT_out3 can be found in peripheral output signals. + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t clk_out3: 5; - uint32_t reserved_15: 17; + uint32_t clk_out3:5; + uint32_t reserved_15:17; }; uint32_t val; } gpio_ext_pin_ctrl_reg_t; @@ -140,32 +129,33 @@ typedef union { typedef union { struct { /** filter_chn_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable channel n of Glitch Filter.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable channel n of Glitch Filter. + * 0: Not enable + * 1: Enable */ uint32_t filter_chn_en: 1; /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0; - * Configures to select the input GPIO for Glitch Filter. \\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ + * Configures to select the input GPIO for Glitch Filter. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ uint32_t filter_chn_input_io_num: 6; uint32_t reserved_7: 1; /** filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0; * Configures the window threshold for Glitch Filter. The window threshold should be - * less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\ - * Measurement unit: IO MUX operating clock cycle\\ + * less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH. + * %see DOC-4768 + * Measurement unit: IO MUX operating clock cycle */ uint32_t filter_chn_window_thres: 6; /** filter_chn_window_width : R/W; bitpos: [19:14]; default: 0; * Configures the window width for Glitch Filter. The effective value of window width - * is 0 ~ 63. \\ - * Measurement unit: IO MUX operating clock cycle\\ + * is 0 ~ 63. + * Measurement unit: IO MUX operating clock cycle */ uint32_t filter_chn_window_width: 6; uint32_t reserved_20: 12; @@ -179,24 +169,24 @@ typedef union { */ typedef union { struct { - /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * 29 ~ 63: Reserved\\ + /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0; + * Configures to select GPIO for ETM event channel. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * 29 ~ 63: Reserved */ - uint32_t etm_chn_event_sel: 6; - uint32_t reserved_6: 1; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + uint32_t etm_chn_event_sel:6; + uint32_t reserved_6:1; + /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ETM event send. + * 0: Not enable + * 1: Enable */ - uint32_t etm_chn_event_en: 1; - uint32_t reserved_8: 24; + uint32_t etm_chn_event_en:1; + uint32_t reserved_8:24; }; uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; @@ -207,126 +197,81 @@ typedef union { typedef union { struct { /** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO0. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ - uint32_t etm_task_gpio0_sel: 3; - uint32_t reserved_3: 2; + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_3:2; /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO0 to response ETM task. + * 0: Not enable + * 1: Enable */ - uint32_t etm_task_gpio0_en: 1; + uint32_t etm_task_gpio0_en:1; /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO1. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ - uint32_t etm_task_gpio1_sel: 3; - uint32_t reserved_9: 2; + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_9:2; /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO1 to response ETM task. + * 0: Not enable + * 1: Enable */ - uint32_t etm_task_gpio1_en: 1; + uint32_t etm_task_gpio1_en:1; /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO2. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ - uint32_t etm_task_gpio2_sel: 3; - uint32_t reserved_15: 2; + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_15:2; /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO2 to response ETM task. + * 0: Not enable + * 1: Enable */ - uint32_t etm_task_gpio2_en: 1; + uint32_t etm_task_gpio2_en:1; /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO3. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ - uint32_t etm_task_gpio3_sel: 3; - uint32_t reserved_21: 2; + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_21:2; /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO3 to response ETM task. + * 0: Not enable + * 1: Enable */ - uint32_t etm_task_gpio3_en: 1; + uint32_t etm_task_gpio3_en:1; /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. + * Configures to select an ETM task channel for GPIO4. + * 0: Select channel 0 + * 1: Select channel 1 + * ...... + * 7: Select channel 7 */ - uint32_t etm_task_gpio4_sel: 3; - uint32_t reserved_27: 2; + uint32_t etm_task_gpio4_sel:3; + uint32_t reserved_27:2; /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable GPIO4 to response ETM task. + * 0: Not enable + * 1: Enable */ - uint32_t etm_task_gpio4_en: 1; - uint32_t reserved_30: 2; + uint32_t etm_task_gpio4_en:1; + uint32_t reserved_30:2; }; uint32_t val; } gpio_ext_etm_task_pn_cfg_reg_t; @@ -426,7 +371,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774208; + /** date : R/W; bitpos: [27:0]; default: 37815040; * Version control register. */ uint32_t date: 28; @@ -436,7 +381,7 @@ typedef union { } gpio_ext_version_reg_t; typedef struct gpio_sd_dev_t { - volatile gpio_ext_clock_gate_reg_t clock_gate; + volatile uint32_t reserved; volatile gpio_ext_sigmadelta_misc_reg_t misc; volatile gpio_ext_sigmadeltan_reg_t channel[4]; } gpio_sd_dev_t; diff --git a/components/soc/esp32c5/register/soc/gpio_reg.h b/components/soc/esp32c5/register/soc/gpio_reg.h index c432c1f8e4..1c9c7f1991 100644 --- a/components/soc/esp32c5/register/soc/gpio_reg.h +++ b/components/soc/esp32c5/register/soc/gpio_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,8 @@ extern "C" { */ #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0) /** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. + * Represents the values of GPIO strapping pins. (need update the description, for + * example) * * - bit0: invalid * - bit1: MTMS @@ -36,9 +37,11 @@ extern "C" { */ #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) /** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; - * Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ + * Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 + * respectively. Bitxx ~ bitxx is invalid. */ #define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU #define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) @@ -50,11 +53,11 @@ extern "C" { */ #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) /** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO31.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ + * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ GPIO31. + * 0: Not set + * 1: The corresponding bit in GPIO_OUT_REG will be set to 1 + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_OUT_REG. */ #define GPIO_OUT_W1TS 0xFFFFFFFFU #define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) @@ -67,10 +70,11 @@ extern "C" { #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) /** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO31 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + * GPIO31 output. + * 0: Not clear + * 1: The corresponding bit in GPIO_OUT_REG will be cleared. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_OUT_REG. */ #define GPIO_OUT_W1TC 0xFFFFFFFFU #define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) @@ -78,13 +82,15 @@ extern "C" { #define GPIO_OUT_W1TC_S 0 /** GPIO_OUT1_REG register - * GPIO output register for GPIO32-32 + * GPIO output register */ #define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) /** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [0]; default: 0; - * Configures the output value of GPIO32 ~ 32 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ + * Configures the output value of GPIO32 ~ 32 output in simple GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit32 ~ bit32 correspond to the output value of GPIO32 ~ GPIO32 + * respectively. Bitxx ~ bitxx is invalid. */ #define GPIO_OUT1_DATA_ORIG (BIT(0)) #define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) @@ -92,15 +98,16 @@ extern "C" { #define GPIO_OUT1_DATA_ORIG_S 0 /** GPIO_OUT1_W1TS_REG register - * GPIO output set register for GPIO32-32 + * GPIO output set register */ #define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) /** GPIO_OUT1_W1TS : WT; bitpos: [0]; default: 0; * Configures whether or not to set the output register GPIO_OUT1_REG of GPIO32 ~ - * GPIO32.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_OUT1_REG. \\ + * GPIO32. + * 0: Not set + * 1: The corresponding bit in GPIO_OUT1_REG will be set to 1 + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_OUT1_REG. */ #define GPIO_OUT1_W1TS (BIT(0)) #define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) @@ -108,15 +115,16 @@ extern "C" { #define GPIO_OUT1_W1TS_S 0 /** GPIO_OUT1_W1TC_REG register - * GPIO output clear register for GPIO32-32 + * GPIO output clear register */ #define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) /** GPIO_OUT1_W1TC : WT; bitpos: [0]; default: 0; * Configures whether or not to clear the output register GPIO_OUT1_REG of GPIO32 ~ - * GPIO32 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Recommended operation: use this register to clear GPIO_OUT1_REG. \\ + * GPIO32 output. + * 0: Not clear + * 1: The corresponding bit in GPIO_OUT1_REG will be cleared. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_OUT1_REG. */ #define GPIO_OUT1_W1TC (BIT(0)) #define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) @@ -128,9 +136,10 @@ extern "C" { */ #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34) /** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO31.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable the output of GPIO0 ~ GPIO31. + * 0: Not enable + * 1: Enable + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. */ #define GPIO_ENABLE_DATA 0xFFFFFFFFU #define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) @@ -143,10 +152,11 @@ extern "C" { #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38) /** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO31.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ + * GPIO0 ~ GPIO31. + * 0: Not set + * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1 + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_ENABLE_REG. */ #define GPIO_ENABLE_W1TS 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) @@ -159,10 +169,11 @@ extern "C" { #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c) /** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO31. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ + * GPIO0 ~ GPIO31. + * 0: Not clear + * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_ENABLE_REG. */ #define GPIO_ENABLE_W1TC 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) @@ -170,13 +181,14 @@ extern "C" { #define GPIO_ENABLE_W1TC_S 0 /** GPIO_ENABLE1_REG register - * GPIO output enable register for GPIO32-32 + * GPIO output enable register */ #define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x40) /** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO32 ~ GPIO32.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable the output of GPIO32 ~ GPIO32. + * 0: Not enable + * 1: Enable + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. */ #define GPIO_ENABLE1_DATA (BIT(0)) #define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) @@ -184,15 +196,16 @@ extern "C" { #define GPIO_ENABLE1_DATA_S 0 /** GPIO_ENABLE1_W1TS_REG register - * GPIO output enable set register for GPIO32-32 + * GPIO output enable set register */ #define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x44) /** GPIO_ENABLE1_W1TS : WT; bitpos: [0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO32 ~ GPIO32.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_ENABLE1_REG.\\ + * Configures whether or not to set the output enable register GPIO_ENABLE1_REG of + * GPIO32 ~ GPIO32. + * 0: Not set + * 1: The corresponding bit in GPIO_ENABLE1_REG will be set to 1 + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_ENABLE1_REG. */ #define GPIO_ENABLE1_W1TS (BIT(0)) #define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) @@ -200,15 +213,16 @@ extern "C" { #define GPIO_ENABLE1_W1TS_S 0 /** GPIO_ENABLE1_W1TC_REG register - * GPIO output enable clear register for GPIO32-32 + * GPIO output enable clear register */ #define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x48) /** GPIO_ENABLE1_W1TC : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO32 ~ GPIO32. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Recommended operation: use this register to clear GPIO_ENABLE1_REG.\\ + * Configures whether or not to clear the output enable register GPIO_ENABLE1_REG of + * GPIO32 ~ GPIO32. + * 0: Not clear + * 1: The corresponding bit in GPIO_ENABLE1_REG will be cleared + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_ENABLE1_REG. */ #define GPIO_ENABLE1_W1TC (BIT(0)) #define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) @@ -220,10 +234,10 @@ extern "C" { */ #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64) /** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ + * Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input value: + * 0: Low level + * 1: High level + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. */ #define GPIO_IN_DATA_NEXT 0xFFFFFFFFU #define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) @@ -231,14 +245,15 @@ extern "C" { #define GPIO_IN_DATA_NEXT_S 0 /** GPIO_IN1_REG register - * GPIO input register for GPIO32-32 + * GPIO input register */ #define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x68) /** GPIO_IN1_DATA_NEXT : RO; bitpos: [0]; default: 0; * Represents the input value of GPIO32 ~ GPIO32. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ + * value: + * 0: Low level + * 1: High level + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. */ #define GPIO_IN1_DATA_NEXT (BIT(0)) #define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) @@ -252,6 +267,7 @@ extern "C" { /** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; * The interrupt status of GPIO0 ~ GPIO31, can be configured by the software. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - Each bit represents the status of its corresponding GPIO: * * - 0: Represents the GPIO does not generate the interrupt configured by @@ -273,6 +289,7 @@ extern "C" { * Configures whether or not to set the interrupt status register * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this * register to set GPIO_STATUS_INTERRUPT. @@ -290,6 +307,7 @@ extern "C" { * Configures whether or not to clear the interrupt status register * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this * register to clear GPIO_STATUS_INTERRUPT. @@ -300,12 +318,13 @@ extern "C" { #define GPIO_STATUS_W1TC_S 0 /** GPIO_STATUS1_REG register - * GPIO interrupt status register for GPIO32-32 + * GPIO interrupt status register */ #define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x80) /** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [0]; default: 0; * The interrupt status of GPIO32 ~ GPIO32, can be configured by the software. * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. * - Each bit represents the status of its corresponding GPIO: * * - 0: Represents the GPIO does not generate the interrupt configured by @@ -320,16 +339,17 @@ extern "C" { #define GPIO_STATUS1_INTERRUPT_S 0 /** GPIO_STATUS1_W1TS_REG register - * GPIO interrupt status set register for GPIO32-32 + * GPIO interrupt status set register */ #define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x84) /** GPIO_STATUS1_W1TS : WT; bitpos: [0]; default: 0; * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO32 ~ GPIO32. + * GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO32. * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. + * GPIO_STATUS1_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set GPIO_STATUS1_INTERRUPT. */ #define GPIO_STATUS1_W1TS (BIT(0)) #define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) @@ -337,16 +357,17 @@ extern "C" { #define GPIO_STATUS1_W1TS_S 0 /** GPIO_STATUS1_W1TC_REG register - * GPIO interrupt status clear register for GPIO32-32 + * GPIO interrupt status clear register */ #define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x88) /** GPIO_STATUS1_W1TC : WT; bitpos: [0]; default: 0; * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO32 ~ GPIO32. + * GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO32. * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. + * GPIO_STATUS1_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear GPIO_STATUS1_INTERRUPT. */ #define GPIO_STATUS1_W1TC (BIT(0)) #define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) @@ -354,52 +375,97 @@ extern "C" { #define GPIO_STATUS1_W1TC_S 0 /** GPIO_PROCPU_INT_REG register - * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + * GPIO_PROCPU_INT interrupt status register */ #define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4) /** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO31. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * Represents the GPIO_PROCPU_INT interrupt status of GPIO0 ~ GPIO31. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not + * generate the interrupt configured by GPIO_PIN$n_INT_TYPE. * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert - * (high) enable signal (bit13 of GPIO_PIN$n_REG). \\ + * after the GPIO_PROCPU_INT interrupt is enabled. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). */ #define GPIO_PROCPU_INT 0xFFFFFFFFU #define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) #define GPIO_PROCPU_INT_V 0xFFFFFFFFU #define GPIO_PROCPU_INT_S 0 -/** GPIO_PROCPU_INT1_REG register - * GPIO_PROCPU_INT interrupt status register for GPIO32-32 +/** GPIO_SDIO_INT_REG register + * GPIO_SDIO_INT interrupt status register */ -#define GPIO_PROCPU_INT1_REG (DR_REG_GPIO_BASE + 0xa8) -/** GPIO_PROCPU_INT1 : RO; bitpos: [0]; default: 0; - * Represents the CPU interrupt status of GPIO32 ~ GPIO32. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ +#define GPIO_SDIO_INT_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * Represents the GPIO_SDIO_INT interrupt status of GPIO0 ~ GPIO31. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_SDIO_INT interrupt is not enabled, or the GPIO does not generate + * the interrupt configured by GPIO_PIN$n_INT_TYPE. * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert - * (high) enable signal (bit13 of GPIO_PIN$n_REG). \\ + * after the GPIO_SDIO_INT interrupt is enabled. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PROCPU_INT1_REG register + * GPIO_PROCPU_INT interrupt status register + */ +#define GPIO_PROCPU_INT1_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PROCPU_INT1 : RO; bitpos: [0]; default: 0; + * Represents the GPIO_PROCPU_INT interrupt status of GPIO32 ~ GPIO32. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not + * generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_PROCPU_INT interrupt is enabled. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). */ #define GPIO_PROCPU_INT1 (BIT(0)) #define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) #define GPIO_PROCPU_INT1_V 0x00000001U #define GPIO_PROCPU_INT1_S 0 +/** GPIO_SDIO_INT1_REG register + * GPIO_SDIO_INT interrupt status register + */ +#define GPIO_SDIO_INT1_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_SDIO_INT1 : RO; bitpos: [0]; default: 0; + * Represents the GPIO_SDIO_INT interrupt status of GPIO32 ~ GPIO32. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_SDIO_INT interrupt is not enabled, or the GPIO does not generate + * the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_SDIO_INT interrupt is enabled. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ +#define GPIO_SDIO_INT1 (BIT(0)) +#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) +#define GPIO_SDIO_INT1_V 0x00000001U +#define GPIO_SDIO_INT1_S 0 + /** GPIO_STATUS_NEXT_REG register * GPIO interrupt source register */ -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4) +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xc4) /** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO31.\\ - * Each bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * Represents the interrupt source signal of GPIO0 ~ GPIO31. + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. Each + * bit represents: + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE. * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ + * sensitive interrupt and any edge interrupt. */ #define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) @@ -407,16 +473,17 @@ extern "C" { #define GPIO_STATUS_INTERRUPT_NEXT_S 0 /** GPIO_STATUS_NEXT1_REG register - * GPIO interrupt source register for GPIO32-32 + * GPIO interrupt source register */ -#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0xb8) +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0xc8) /** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [0]; default: 0; - * Represents the interrupt source signal of GPIO32 ~ GPIO32.\\ - * Each bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * Represents the interrupt source signal of GPIO32 ~ GPIO32. + * Bit0 ~ bit24 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. Each + * bit represents: + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE. * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ + * sensitive interrupt and any edge interrupt. */ #define GPIO_STATUS_INTERRUPT_NEXT1 (BIT(0)) #define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) @@ -424,25 +491,25 @@ extern "C" { #define GPIO_STATUS_INTERRUPT_NEXT1_S 0 /** GPIO_PIN0_REG register - * GPIO$N configuration register + * GPIO0 configuration register */ -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4) +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xd4) /** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN0_SYNC2_BYPASS 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) #define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_S 0 /** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN0_PAD_DRIVER (BIT(2)) #define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) @@ -450,46 +517,52 @@ extern "C" { #define GPIO_PIN0_PAD_DRIVER_S 2 /** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN0_SYNC1_BYPASS 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) #define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_S 3 /** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN0_INT_TYPE 0x00000007U #define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) #define GPIO_PIN0_INT_TYPE_V 0x00000007U #define GPIO_PIN0_INT_TYPE_S 7 /** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) #define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN0_WAKEUP_ENABLE_S 10 /** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN0_INT_ENA 0x0000001FU #define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) @@ -497,25 +570,25 @@ extern "C" { #define GPIO_PIN0_INT_ENA_S 13 /** GPIO_PIN1_REG register - * GPIO$N configuration register + * GPIO1 configuration register */ -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8) +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xd8) /** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN1_SYNC2_BYPASS 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) #define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_S 0 /** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN1_PAD_DRIVER (BIT(2)) #define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) @@ -523,46 +596,52 @@ extern "C" { #define GPIO_PIN1_PAD_DRIVER_S 2 /** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN1_SYNC1_BYPASS 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) #define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_S 3 /** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN1_INT_TYPE 0x00000007U #define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) #define GPIO_PIN1_INT_TYPE_V 0x00000007U #define GPIO_PIN1_INT_TYPE_S 7 /** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) #define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN1_WAKEUP_ENABLE_S 10 /** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN1_INT_ENA 0x0000001FU #define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) @@ -570,25 +649,25 @@ extern "C" { #define GPIO_PIN1_INT_ENA_S 13 /** GPIO_PIN2_REG register - * GPIO$N configuration register + * GPIO2 configuration register */ -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc) +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xdc) /** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN2_SYNC2_BYPASS 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) #define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_S 0 /** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN2_PAD_DRIVER (BIT(2)) #define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) @@ -596,46 +675,52 @@ extern "C" { #define GPIO_PIN2_PAD_DRIVER_S 2 /** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN2_SYNC1_BYPASS 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) #define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_S 3 /** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN2_INT_TYPE 0x00000007U #define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) #define GPIO_PIN2_INT_TYPE_V 0x00000007U #define GPIO_PIN2_INT_TYPE_S 7 /** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) #define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN2_WAKEUP_ENABLE_S 10 /** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN2_INT_ENA 0x0000001FU #define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) @@ -643,25 +728,25 @@ extern "C" { #define GPIO_PIN2_INT_ENA_S 13 /** GPIO_PIN3_REG register - * GPIO$N configuration register + * GPIO3 configuration register */ -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0) +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xe0) /** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN3_SYNC2_BYPASS 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) #define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_S 0 /** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN3_PAD_DRIVER (BIT(2)) #define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) @@ -669,46 +754,52 @@ extern "C" { #define GPIO_PIN3_PAD_DRIVER_S 2 /** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN3_SYNC1_BYPASS 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) #define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_S 3 /** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN3_INT_TYPE 0x00000007U #define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) #define GPIO_PIN3_INT_TYPE_V 0x00000007U #define GPIO_PIN3_INT_TYPE_S 7 /** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) #define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN3_WAKEUP_ENABLE_S 10 /** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN3_INT_ENA 0x0000001FU #define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) @@ -716,25 +807,25 @@ extern "C" { #define GPIO_PIN3_INT_ENA_S 13 /** GPIO_PIN4_REG register - * GPIO$N configuration register + * GPIO4 configuration register */ -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4) +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xe4) /** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN4_SYNC2_BYPASS 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) #define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_S 0 /** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN4_PAD_DRIVER (BIT(2)) #define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) @@ -742,46 +833,52 @@ extern "C" { #define GPIO_PIN4_PAD_DRIVER_S 2 /** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN4_SYNC1_BYPASS 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) #define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_S 3 /** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN4_INT_TYPE 0x00000007U #define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) #define GPIO_PIN4_INT_TYPE_V 0x00000007U #define GPIO_PIN4_INT_TYPE_S 7 /** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) #define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN4_WAKEUP_ENABLE_S 10 /** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN4_INT_ENA 0x0000001FU #define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) @@ -789,25 +886,25 @@ extern "C" { #define GPIO_PIN4_INT_ENA_S 13 /** GPIO_PIN5_REG register - * GPIO$N configuration register + * GPIO5 configuration register */ -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8) +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xe8) /** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN5_SYNC2_BYPASS 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) #define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_S 0 /** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN5_PAD_DRIVER (BIT(2)) #define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) @@ -815,46 +912,52 @@ extern "C" { #define GPIO_PIN5_PAD_DRIVER_S 2 /** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN5_SYNC1_BYPASS 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) #define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_S 3 /** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN5_INT_TYPE 0x00000007U #define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) #define GPIO_PIN5_INT_TYPE_V 0x00000007U #define GPIO_PIN5_INT_TYPE_S 7 /** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) #define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN5_WAKEUP_ENABLE_S 10 /** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN5_INT_ENA 0x0000001FU #define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) @@ -862,25 +965,25 @@ extern "C" { #define GPIO_PIN5_INT_ENA_S 13 /** GPIO_PIN6_REG register - * GPIO$N configuration register + * GPIO6 configuration register */ -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc) +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xec) /** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN6_SYNC2_BYPASS 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) #define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_S 0 /** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN6_PAD_DRIVER (BIT(2)) #define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) @@ -888,46 +991,52 @@ extern "C" { #define GPIO_PIN6_PAD_DRIVER_S 2 /** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN6_SYNC1_BYPASS 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) #define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_S 3 /** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN6_INT_TYPE 0x00000007U #define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) #define GPIO_PIN6_INT_TYPE_V 0x00000007U #define GPIO_PIN6_INT_TYPE_S 7 /** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) #define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN6_WAKEUP_ENABLE_S 10 /** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN6_INT_ENA 0x0000001FU #define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) @@ -935,25 +1044,25 @@ extern "C" { #define GPIO_PIN6_INT_ENA_S 13 /** GPIO_PIN7_REG register - * GPIO$N configuration register + * GPIO7 configuration register */ -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0) +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xf0) /** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN7_SYNC2_BYPASS 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) #define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_S 0 /** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN7_PAD_DRIVER (BIT(2)) #define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) @@ -961,46 +1070,52 @@ extern "C" { #define GPIO_PIN7_PAD_DRIVER_S 2 /** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN7_SYNC1_BYPASS 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) #define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_S 3 /** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN7_INT_TYPE 0x00000007U #define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) #define GPIO_PIN7_INT_TYPE_V 0x00000007U #define GPIO_PIN7_INT_TYPE_S 7 /** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) #define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN7_WAKEUP_ENABLE_S 10 /** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN7_INT_ENA 0x0000001FU #define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) @@ -1008,25 +1123,25 @@ extern "C" { #define GPIO_PIN7_INT_ENA_S 13 /** GPIO_PIN8_REG register - * GPIO$N configuration register + * GPIO8 configuration register */ -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4) +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xf4) /** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN8_SYNC2_BYPASS 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) #define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_S 0 /** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN8_PAD_DRIVER (BIT(2)) #define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) @@ -1034,46 +1149,52 @@ extern "C" { #define GPIO_PIN8_PAD_DRIVER_S 2 /** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN8_SYNC1_BYPASS 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) #define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_S 3 /** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN8_INT_TYPE 0x00000007U #define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) #define GPIO_PIN8_INT_TYPE_V 0x00000007U #define GPIO_PIN8_INT_TYPE_S 7 /** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) #define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN8_WAKEUP_ENABLE_S 10 /** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN8_INT_ENA 0x0000001FU #define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) @@ -1081,25 +1202,25 @@ extern "C" { #define GPIO_PIN8_INT_ENA_S 13 /** GPIO_PIN9_REG register - * GPIO$N configuration register + * GPIO9 configuration register */ -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8) +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xf8) /** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN9_SYNC2_BYPASS 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) #define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_S 0 /** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN9_PAD_DRIVER (BIT(2)) #define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) @@ -1107,46 +1228,52 @@ extern "C" { #define GPIO_PIN9_PAD_DRIVER_S 2 /** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN9_SYNC1_BYPASS 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) #define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_S 3 /** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN9_INT_TYPE 0x00000007U #define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) #define GPIO_PIN9_INT_TYPE_V 0x00000007U #define GPIO_PIN9_INT_TYPE_S 7 /** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) #define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN9_WAKEUP_ENABLE_S 10 /** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN9_INT_ENA 0x0000001FU #define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) @@ -1154,25 +1281,25 @@ extern "C" { #define GPIO_PIN9_INT_ENA_S 13 /** GPIO_PIN10_REG register - * GPIO$N configuration register + * GPIO10 configuration register */ -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec) +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xfc) /** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN10_SYNC2_BYPASS 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) #define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_S 0 /** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN10_PAD_DRIVER (BIT(2)) #define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) @@ -1180,46 +1307,52 @@ extern "C" { #define GPIO_PIN10_PAD_DRIVER_S 2 /** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN10_SYNC1_BYPASS 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) #define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_S 3 /** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN10_INT_TYPE 0x00000007U #define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) #define GPIO_PIN10_INT_TYPE_V 0x00000007U #define GPIO_PIN10_INT_TYPE_S 7 /** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) #define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN10_WAKEUP_ENABLE_S 10 /** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN10_INT_ENA 0x0000001FU #define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) @@ -1227,25 +1360,25 @@ extern "C" { #define GPIO_PIN10_INT_ENA_S 13 /** GPIO_PIN11_REG register - * GPIO$N configuration register + * GPIO11 configuration register */ -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0) +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x100) /** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN11_SYNC2_BYPASS 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) #define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_S 0 /** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN11_PAD_DRIVER (BIT(2)) #define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) @@ -1253,46 +1386,52 @@ extern "C" { #define GPIO_PIN11_PAD_DRIVER_S 2 /** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN11_SYNC1_BYPASS 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) #define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_S 3 /** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN11_INT_TYPE 0x00000007U #define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) #define GPIO_PIN11_INT_TYPE_V 0x00000007U #define GPIO_PIN11_INT_TYPE_S 7 /** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) #define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN11_WAKEUP_ENABLE_S 10 /** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN11_INT_ENA 0x0000001FU #define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) @@ -1300,25 +1439,25 @@ extern "C" { #define GPIO_PIN11_INT_ENA_S 13 /** GPIO_PIN12_REG register - * GPIO$N configuration register + * GPIO12 configuration register */ -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4) +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x104) /** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN12_SYNC2_BYPASS 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) #define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_S 0 /** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN12_PAD_DRIVER (BIT(2)) #define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) @@ -1326,46 +1465,52 @@ extern "C" { #define GPIO_PIN12_PAD_DRIVER_S 2 /** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN12_SYNC1_BYPASS 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) #define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_S 3 /** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN12_INT_TYPE 0x00000007U #define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) #define GPIO_PIN12_INT_TYPE_V 0x00000007U #define GPIO_PIN12_INT_TYPE_S 7 /** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) #define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN12_WAKEUP_ENABLE_S 10 /** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN12_INT_ENA 0x0000001FU #define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) @@ -1373,25 +1518,25 @@ extern "C" { #define GPIO_PIN12_INT_ENA_S 13 /** GPIO_PIN13_REG register - * GPIO$N configuration register + * GPIO13 configuration register */ -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8) +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x108) /** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN13_SYNC2_BYPASS 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) #define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_S 0 /** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN13_PAD_DRIVER (BIT(2)) #define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) @@ -1399,46 +1544,52 @@ extern "C" { #define GPIO_PIN13_PAD_DRIVER_S 2 /** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN13_SYNC1_BYPASS 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) #define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_S 3 /** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN13_INT_TYPE 0x00000007U #define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) #define GPIO_PIN13_INT_TYPE_V 0x00000007U #define GPIO_PIN13_INT_TYPE_S 7 /** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) #define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN13_WAKEUP_ENABLE_S 10 /** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN13_INT_ENA 0x0000001FU #define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) @@ -1446,25 +1597,25 @@ extern "C" { #define GPIO_PIN13_INT_ENA_S 13 /** GPIO_PIN14_REG register - * GPIO$N configuration register + * GPIO14 configuration register */ -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc) +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x10c) /** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN14_SYNC2_BYPASS 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) #define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_S 0 /** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN14_PAD_DRIVER (BIT(2)) #define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) @@ -1472,46 +1623,52 @@ extern "C" { #define GPIO_PIN14_PAD_DRIVER_S 2 /** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN14_SYNC1_BYPASS 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) #define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_S 3 /** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN14_INT_TYPE 0x00000007U #define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) #define GPIO_PIN14_INT_TYPE_V 0x00000007U #define GPIO_PIN14_INT_TYPE_S 7 /** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) #define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN14_WAKEUP_ENABLE_S 10 /** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN14_INT_ENA 0x0000001FU #define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) @@ -1519,25 +1676,25 @@ extern "C" { #define GPIO_PIN14_INT_ENA_S 13 /** GPIO_PIN15_REG register - * GPIO$N configuration register + * GPIO15 configuration register */ -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100) +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x110) /** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN15_SYNC2_BYPASS 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) #define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_S 0 /** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN15_PAD_DRIVER (BIT(2)) #define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) @@ -1545,46 +1702,52 @@ extern "C" { #define GPIO_PIN15_PAD_DRIVER_S 2 /** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN15_SYNC1_BYPASS 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) #define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_S 3 /** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN15_INT_TYPE 0x00000007U #define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) #define GPIO_PIN15_INT_TYPE_V 0x00000007U #define GPIO_PIN15_INT_TYPE_S 7 /** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) #define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN15_WAKEUP_ENABLE_S 10 /** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN15_INT_ENA 0x0000001FU #define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) @@ -1592,25 +1755,25 @@ extern "C" { #define GPIO_PIN15_INT_ENA_S 13 /** GPIO_PIN16_REG register - * GPIO$N configuration register + * GPIO16 configuration register */ -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104) +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x114) /** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN16_SYNC2_BYPASS 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) #define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_S 0 /** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN16_PAD_DRIVER (BIT(2)) #define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) @@ -1618,46 +1781,52 @@ extern "C" { #define GPIO_PIN16_PAD_DRIVER_S 2 /** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN16_SYNC1_BYPASS 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) #define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_S 3 /** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN16_INT_TYPE 0x00000007U #define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) #define GPIO_PIN16_INT_TYPE_V 0x00000007U #define GPIO_PIN16_INT_TYPE_S 7 /** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) #define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN16_WAKEUP_ENABLE_S 10 /** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN16_INT_ENA 0x0000001FU #define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) @@ -1665,25 +1834,25 @@ extern "C" { #define GPIO_PIN16_INT_ENA_S 13 /** GPIO_PIN17_REG register - * GPIO$N configuration register + * GPIO17 configuration register */ -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108) +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x118) /** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN17_SYNC2_BYPASS 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) #define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_S 0 /** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN17_PAD_DRIVER (BIT(2)) #define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) @@ -1691,46 +1860,52 @@ extern "C" { #define GPIO_PIN17_PAD_DRIVER_S 2 /** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN17_SYNC1_BYPASS 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) #define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_S 3 /** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN17_INT_TYPE 0x00000007U #define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) #define GPIO_PIN17_INT_TYPE_V 0x00000007U #define GPIO_PIN17_INT_TYPE_S 7 /** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) #define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN17_WAKEUP_ENABLE_S 10 /** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN17_INT_ENA 0x0000001FU #define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) @@ -1738,25 +1913,25 @@ extern "C" { #define GPIO_PIN17_INT_ENA_S 13 /** GPIO_PIN18_REG register - * GPIO$N configuration register + * GPIO18 configuration register */ -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c) +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x11c) /** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN18_SYNC2_BYPASS 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) #define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_S 0 /** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN18_PAD_DRIVER (BIT(2)) #define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) @@ -1764,46 +1939,52 @@ extern "C" { #define GPIO_PIN18_PAD_DRIVER_S 2 /** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN18_SYNC1_BYPASS 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) #define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_S 3 /** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN18_INT_TYPE 0x00000007U #define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) #define GPIO_PIN18_INT_TYPE_V 0x00000007U #define GPIO_PIN18_INT_TYPE_S 7 /** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) #define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN18_WAKEUP_ENABLE_S 10 /** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN18_INT_ENA 0x0000001FU #define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) @@ -1811,25 +1992,25 @@ extern "C" { #define GPIO_PIN18_INT_ENA_S 13 /** GPIO_PIN19_REG register - * GPIO$N configuration register + * GPIO19 configuration register */ -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110) +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x120) /** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN19_SYNC2_BYPASS 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) #define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_S 0 /** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN19_PAD_DRIVER (BIT(2)) #define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) @@ -1837,46 +2018,52 @@ extern "C" { #define GPIO_PIN19_PAD_DRIVER_S 2 /** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN19_SYNC1_BYPASS 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) #define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_S 3 /** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN19_INT_TYPE 0x00000007U #define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) #define GPIO_PIN19_INT_TYPE_V 0x00000007U #define GPIO_PIN19_INT_TYPE_S 7 /** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) #define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN19_WAKEUP_ENABLE_S 10 /** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN19_INT_ENA 0x0000001FU #define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) @@ -1884,25 +2071,25 @@ extern "C" { #define GPIO_PIN19_INT_ENA_S 13 /** GPIO_PIN20_REG register - * GPIO$N configuration register + * GPIO20 configuration register */ -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114) +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x124) /** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN20_SYNC2_BYPASS 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) #define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_S 0 /** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN20_PAD_DRIVER (BIT(2)) #define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) @@ -1910,46 +2097,52 @@ extern "C" { #define GPIO_PIN20_PAD_DRIVER_S 2 /** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN20_SYNC1_BYPASS 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) #define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_S 3 /** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN20_INT_TYPE 0x00000007U #define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) #define GPIO_PIN20_INT_TYPE_V 0x00000007U #define GPIO_PIN20_INT_TYPE_S 7 /** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) #define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN20_WAKEUP_ENABLE_S 10 /** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN20_INT_ENA 0x0000001FU #define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) @@ -1957,25 +2150,25 @@ extern "C" { #define GPIO_PIN20_INT_ENA_S 13 /** GPIO_PIN21_REG register - * GPIO$N configuration register + * GPIO21 configuration register */ -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118) +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x128) /** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN21_SYNC2_BYPASS 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) #define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_S 0 /** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN21_PAD_DRIVER (BIT(2)) #define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) @@ -1983,46 +2176,52 @@ extern "C" { #define GPIO_PIN21_PAD_DRIVER_S 2 /** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN21_SYNC1_BYPASS 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) #define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_S 3 /** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN21_INT_TYPE 0x00000007U #define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) #define GPIO_PIN21_INT_TYPE_V 0x00000007U #define GPIO_PIN21_INT_TYPE_S 7 /** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) #define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN21_WAKEUP_ENABLE_S 10 /** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN21_INT_ENA 0x0000001FU #define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) @@ -2030,25 +2229,25 @@ extern "C" { #define GPIO_PIN21_INT_ENA_S 13 /** GPIO_PIN22_REG register - * GPIO$N configuration register + * GPIO22 configuration register */ -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c) +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x12c) /** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN22_SYNC2_BYPASS 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) #define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_S 0 /** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN22_PAD_DRIVER (BIT(2)) #define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) @@ -2056,46 +2255,52 @@ extern "C" { #define GPIO_PIN22_PAD_DRIVER_S 2 /** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN22_SYNC1_BYPASS 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) #define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_S 3 /** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN22_INT_TYPE 0x00000007U #define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) #define GPIO_PIN22_INT_TYPE_V 0x00000007U #define GPIO_PIN22_INT_TYPE_S 7 /** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) #define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN22_WAKEUP_ENABLE_S 10 /** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN22_INT_ENA 0x0000001FU #define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) @@ -2103,25 +2308,25 @@ extern "C" { #define GPIO_PIN22_INT_ENA_S 13 /** GPIO_PIN23_REG register - * GPIO$N configuration register + * GPIO23 configuration register */ -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120) +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x130) /** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN23_SYNC2_BYPASS 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) #define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_S 0 /** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN23_PAD_DRIVER (BIT(2)) #define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) @@ -2129,46 +2334,52 @@ extern "C" { #define GPIO_PIN23_PAD_DRIVER_S 2 /** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN23_SYNC1_BYPASS 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) #define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_S 3 /** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN23_INT_TYPE 0x00000007U #define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) #define GPIO_PIN23_INT_TYPE_V 0x00000007U #define GPIO_PIN23_INT_TYPE_S 7 /** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) #define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN23_WAKEUP_ENABLE_S 10 /** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN23_INT_ENA 0x0000001FU #define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) @@ -2176,25 +2387,25 @@ extern "C" { #define GPIO_PIN23_INT_ENA_S 13 /** GPIO_PIN24_REG register - * GPIO$N configuration register + * GPIO24 configuration register */ -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124) +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x134) /** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN24_SYNC2_BYPASS 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) #define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_S 0 /** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN24_PAD_DRIVER (BIT(2)) #define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) @@ -2202,46 +2413,52 @@ extern "C" { #define GPIO_PIN24_PAD_DRIVER_S 2 /** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN24_SYNC1_BYPASS 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) #define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_S 3 /** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN24_INT_TYPE 0x00000007U #define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) #define GPIO_PIN24_INT_TYPE_V 0x00000007U #define GPIO_PIN24_INT_TYPE_S 7 /** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) #define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN24_WAKEUP_ENABLE_S 10 /** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN24_INT_ENA 0x0000001FU #define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) @@ -2249,25 +2466,25 @@ extern "C" { #define GPIO_PIN24_INT_ENA_S 13 /** GPIO_PIN25_REG register - * GPIO$N configuration register + * GPIO25 configuration register */ -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x128) +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x138) /** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN25_SYNC2_BYPASS 0x00000003U #define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) #define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN25_SYNC2_BYPASS_S 0 /** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN25_PAD_DRIVER (BIT(2)) #define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) @@ -2275,46 +2492,52 @@ extern "C" { #define GPIO_PIN25_PAD_DRIVER_S 2 /** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN25_SYNC1_BYPASS 0x00000003U #define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) #define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN25_SYNC1_BYPASS_S 3 /** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN25_INT_TYPE 0x00000007U #define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) #define GPIO_PIN25_INT_TYPE_V 0x00000007U #define GPIO_PIN25_INT_TYPE_S 7 /** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) #define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN25_WAKEUP_ENABLE_S 10 /** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN25_INT_ENA 0x0000001FU #define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) @@ -2322,25 +2545,25 @@ extern "C" { #define GPIO_PIN25_INT_ENA_S 13 /** GPIO_PIN26_REG register - * GPIO$N configuration register + * GPIO26 configuration register */ -#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x12c) +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x13c) /** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN26_SYNC2_BYPASS 0x00000003U #define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) #define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN26_SYNC2_BYPASS_S 0 /** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN26_PAD_DRIVER (BIT(2)) #define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) @@ -2348,46 +2571,52 @@ extern "C" { #define GPIO_PIN26_PAD_DRIVER_S 2 /** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN26_SYNC1_BYPASS 0x00000003U #define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) #define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN26_SYNC1_BYPASS_S 3 /** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN26_INT_TYPE 0x00000007U #define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) #define GPIO_PIN26_INT_TYPE_V 0x00000007U #define GPIO_PIN26_INT_TYPE_S 7 /** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) #define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN26_WAKEUP_ENABLE_S 10 /** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN26_INT_ENA 0x0000001FU #define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) @@ -2395,25 +2624,25 @@ extern "C" { #define GPIO_PIN26_INT_ENA_S 13 /** GPIO_PIN27_REG register - * GPIO$N configuration register + * GPIO27 configuration register */ -#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x130) +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x140) /** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN27_SYNC2_BYPASS 0x00000003U #define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) #define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN27_SYNC2_BYPASS_S 0 /** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN27_PAD_DRIVER (BIT(2)) #define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) @@ -2421,46 +2650,52 @@ extern "C" { #define GPIO_PIN27_PAD_DRIVER_S 2 /** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN27_SYNC1_BYPASS 0x00000003U #define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) #define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN27_SYNC1_BYPASS_S 3 /** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN27_INT_TYPE 0x00000007U #define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) #define GPIO_PIN27_INT_TYPE_V 0x00000007U #define GPIO_PIN27_INT_TYPE_S 7 /** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) #define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN27_WAKEUP_ENABLE_S 10 /** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN27_INT_ENA 0x0000001FU #define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) @@ -2468,25 +2703,25 @@ extern "C" { #define GPIO_PIN27_INT_ENA_S 13 /** GPIO_PIN28_REG register - * GPIO$N configuration register + * GPIO28 configuration register */ -#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x134) +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x144) /** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN28_SYNC2_BYPASS 0x00000003U #define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) #define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN28_SYNC2_BYPASS_S 0 /** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ #define GPIO_PIN28_PAD_DRIVER (BIT(2)) #define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) @@ -2494,377 +2729,91 @@ extern "C" { #define GPIO_PIN28_PAD_DRIVER_S 2 /** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ #define GPIO_PIN28_SYNC1_BYPASS 0x00000003U #define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) #define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN28_SYNC1_BYPASS_S 3 /** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ #define GPIO_PIN28_INT_TYPE 0x00000007U #define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) #define GPIO_PIN28_INT_TYPE_V 0x00000007U #define GPIO_PIN28_INT_TYPE_S 7 /** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ #define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) #define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN28_WAKEUP_ENABLE_S 10 /** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ #define GPIO_PIN28_INT_ENA 0x0000001FU #define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) #define GPIO_PIN28_INT_ENA_V 0x0000001FU #define GPIO_PIN28_INT_ENA_S 13 -/** GPIO_PIN29_REG register - * GPIO29 configuration register - */ -#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x138) -/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) -#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_S 0 -/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) -#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN29_PAD_DRIVER_S 2 -/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) -#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_S 3 -/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ -#define GPIO_PIN29_INT_TYPE 0x00000007U -#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) -#define GPIO_PIN29_INT_TYPE_V 0x00000007U -#define GPIO_PIN29_INT_TYPE_S 7 -/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) -#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN29_WAKEUP_ENABLE_S 10 -/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ -#define GPIO_PIN29_INT_ENA 0x0000001FU -#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) -#define GPIO_PIN29_INT_ENA_V 0x0000001FU -#define GPIO_PIN29_INT_ENA_S 13 - -/** GPIO_PIN30_REG register - * GPIO30 configuration register - */ -#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x13c) -/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) -#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN30_SYNC2_BYPASS_S 0 -/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ -#define GPIO_PIN30_PAD_DRIVER (BIT(2)) -#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) -#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN30_PAD_DRIVER_S 2 -/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) -#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN30_SYNC1_BYPASS_S 3 -/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ -#define GPIO_PIN30_INT_TYPE 0x00000007U -#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) -#define GPIO_PIN30_INT_TYPE_V 0x00000007U -#define GPIO_PIN30_INT_TYPE_S 7 -/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ -#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) -#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN30_WAKEUP_ENABLE_S 10 -/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ -#define GPIO_PIN30_INT_ENA 0x0000001FU -#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) -#define GPIO_PIN30_INT_ENA_V 0x0000001FU -#define GPIO_PIN30_INT_ENA_S 13 - -/** GPIO_PIN31_REG register - * GPIO31 configuration register - */ -#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x140) -/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) -#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN31_SYNC2_BYPASS_S 0 -/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ -#define GPIO_PIN31_PAD_DRIVER (BIT(2)) -#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) -#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN31_PAD_DRIVER_S 2 -/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) -#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN31_SYNC1_BYPASS_S 3 -/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ -#define GPIO_PIN31_INT_TYPE 0x00000007U -#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) -#define GPIO_PIN31_INT_TYPE_V 0x00000007U -#define GPIO_PIN31_INT_TYPE_S 7 -/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ -#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) -#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN31_WAKEUP_ENABLE_S 10 -/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ -#define GPIO_PIN31_INT_ENA 0x0000001FU -#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) -#define GPIO_PIN31_INT_ENA_V 0x0000001FU -#define GPIO_PIN31_INT_ENA_S 13 - -/** GPIO_PIN32_REG register - * GPIO32 configuration register - */ -#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x144) -/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) -#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN32_SYNC2_BYPASS_S 0 -/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ -#define GPIO_PIN32_PAD_DRIVER (BIT(2)) -#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) -#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN32_PAD_DRIVER_S 2 -/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) -#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN32_SYNC1_BYPASS_S 3 -/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ -#define GPIO_PIN32_INT_TYPE 0x00000007U -#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) -#define GPIO_PIN32_INT_TYPE_V 0x00000007U -#define GPIO_PIN32_INT_TYPE_S 7 -/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ -#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) -#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN32_WAKEUP_ENABLE_S 10 -/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ -#define GPIO_PIN32_INT_ENA 0x0000001FU -#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) -#define GPIO_PIN32_INT_ENA_V 0x0000001FU -#define GPIO_PIN32_INT_ENA_S 13 - /** GPIO_FUNC0_IN_SEL_CFG_REG register * Configuration register for input signal 0 */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) /** GPIO_FUNC0_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 0. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC0_IN_SEL 0x0000007FU #define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) #define GPIO_FUNC0_IN_SEL_V 0x0000007FU #define GPIO_FUNC0_IN_SEL_S 0 /** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC0_IN_INV_SEL (BIT(7)) #define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) #define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC0_IN_INV_SEL_S 7 /** GPIO_SIG0_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG0_IN_SEL (BIT(8)) #define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) @@ -2874,36 +2823,36 @@ extern "C" { /** GPIO_FUNC6_IN_SEL_CFG_REG register * Configuration register for input signal 6 */ -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) /** GPIO_FUNC6_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 6.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 6. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC6_IN_SEL 0x0000007FU #define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) #define GPIO_FUNC6_IN_SEL_V 0x0000007FU #define GPIO_FUNC6_IN_SEL_S 0 /** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC6_IN_INV_SEL (BIT(7)) #define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) #define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC6_IN_INV_SEL_S 7 /** GPIO_SIG6_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG6_IN_SEL (BIT(8)) #define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) @@ -2913,36 +2862,36 @@ extern "C" { /** GPIO_FUNC7_IN_SEL_CFG_REG register * Configuration register for input signal 7 */ -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) /** GPIO_FUNC7_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 7.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 7. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC7_IN_SEL 0x0000007FU #define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) #define GPIO_FUNC7_IN_SEL_V 0x0000007FU #define GPIO_FUNC7_IN_SEL_S 0 /** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC7_IN_INV_SEL (BIT(7)) #define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) #define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC7_IN_INV_SEL_S 7 /** GPIO_SIG7_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG7_IN_SEL (BIT(8)) #define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) @@ -2952,36 +2901,36 @@ extern "C" { /** GPIO_FUNC8_IN_SEL_CFG_REG register * Configuration register for input signal 8 */ -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) /** GPIO_FUNC8_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 8.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 8. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC8_IN_SEL 0x0000007FU #define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) #define GPIO_FUNC8_IN_SEL_V 0x0000007FU #define GPIO_FUNC8_IN_SEL_S 0 /** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC8_IN_INV_SEL (BIT(7)) #define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) #define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC8_IN_INV_SEL_S 7 /** GPIO_SIG8_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG8_IN_SEL (BIT(8)) #define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) @@ -2991,36 +2940,36 @@ extern "C" { /** GPIO_FUNC9_IN_SEL_CFG_REG register * Configuration register for input signal 9 */ -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) /** GPIO_FUNC9_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 9.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 9. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC9_IN_SEL 0x0000007FU #define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) #define GPIO_FUNC9_IN_SEL_V 0x0000007FU #define GPIO_FUNC9_IN_SEL_S 0 /** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC9_IN_INV_SEL (BIT(7)) #define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) #define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC9_IN_INV_SEL_S 7 /** GPIO_SIG9_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG9_IN_SEL (BIT(8)) #define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) @@ -3030,36 +2979,36 @@ extern "C" { /** GPIO_FUNC10_IN_SEL_CFG_REG register * Configuration register for input signal 10 */ -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) /** GPIO_FUNC10_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 10.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 10. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC10_IN_SEL 0x0000007FU #define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) #define GPIO_FUNC10_IN_SEL_V 0x0000007FU #define GPIO_FUNC10_IN_SEL_S 0 /** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC10_IN_INV_SEL (BIT(7)) #define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) #define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC10_IN_INV_SEL_S 7 /** GPIO_SIG10_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG10_IN_SEL (BIT(8)) #define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) @@ -3069,36 +3018,36 @@ extern "C" { /** GPIO_FUNC11_IN_SEL_CFG_REG register * Configuration register for input signal 11 */ -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) /** GPIO_FUNC11_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 11.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 11. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC11_IN_SEL 0x0000007FU #define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) #define GPIO_FUNC11_IN_SEL_V 0x0000007FU #define GPIO_FUNC11_IN_SEL_S 0 /** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC11_IN_INV_SEL (BIT(7)) #define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) #define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC11_IN_INV_SEL_S 7 /** GPIO_SIG11_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG11_IN_SEL (BIT(8)) #define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) @@ -3108,36 +3057,36 @@ extern "C" { /** GPIO_FUNC12_IN_SEL_CFG_REG register * Configuration register for input signal 12 */ -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) /** GPIO_FUNC12_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 12.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 12. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC12_IN_SEL 0x0000007FU #define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) #define GPIO_FUNC12_IN_SEL_V 0x0000007FU #define GPIO_FUNC12_IN_SEL_S 0 /** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC12_IN_INV_SEL (BIT(7)) #define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) #define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC12_IN_INV_SEL_S 7 /** GPIO_SIG12_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG12_IN_SEL (BIT(8)) #define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) @@ -3147,36 +3096,36 @@ extern "C" { /** GPIO_FUNC13_IN_SEL_CFG_REG register * Configuration register for input signal 13 */ -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) /** GPIO_FUNC13_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 13.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 13. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC13_IN_SEL 0x0000007FU #define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) #define GPIO_FUNC13_IN_SEL_V 0x0000007FU #define GPIO_FUNC13_IN_SEL_S 0 /** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC13_IN_INV_SEL (BIT(7)) #define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) #define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC13_IN_INV_SEL_S 7 /** GPIO_SIG13_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG13_IN_SEL (BIT(8)) #define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) @@ -3186,36 +3135,36 @@ extern "C" { /** GPIO_FUNC14_IN_SEL_CFG_REG register * Configuration register for input signal 14 */ -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) /** GPIO_FUNC14_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 14.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 14. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC14_IN_SEL 0x0000007FU #define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) #define GPIO_FUNC14_IN_SEL_V 0x0000007FU #define GPIO_FUNC14_IN_SEL_S 0 /** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC14_IN_INV_SEL (BIT(7)) #define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) #define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC14_IN_INV_SEL_S 7 /** GPIO_SIG14_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG14_IN_SEL (BIT(8)) #define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) @@ -3225,36 +3174,36 @@ extern "C" { /** GPIO_FUNC15_IN_SEL_CFG_REG register * Configuration register for input signal 15 */ -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) /** GPIO_FUNC15_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 15.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 15. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC15_IN_SEL 0x0000007FU #define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) #define GPIO_FUNC15_IN_SEL_V 0x0000007FU #define GPIO_FUNC15_IN_SEL_S 0 /** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC15_IN_INV_SEL (BIT(7)) #define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) #define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC15_IN_INV_SEL_S 7 /** GPIO_SIG15_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG15_IN_SEL (BIT(8)) #define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) @@ -3264,36 +3213,36 @@ extern "C" { /** GPIO_FUNC16_IN_SEL_CFG_REG register * Configuration register for input signal 16 */ -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) /** GPIO_FUNC16_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 16.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 16. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC16_IN_SEL 0x0000007FU #define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) #define GPIO_FUNC16_IN_SEL_V 0x0000007FU #define GPIO_FUNC16_IN_SEL_S 0 /** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC16_IN_INV_SEL (BIT(7)) #define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) #define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC16_IN_INV_SEL_S 7 /** GPIO_SIG16_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG16_IN_SEL (BIT(8)) #define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) @@ -3303,36 +3252,36 @@ extern "C" { /** GPIO_FUNC17_IN_SEL_CFG_REG register * Configuration register for input signal 17 */ -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) /** GPIO_FUNC17_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 17.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 17. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC17_IN_SEL 0x0000007FU #define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) #define GPIO_FUNC17_IN_SEL_V 0x0000007FU #define GPIO_FUNC17_IN_SEL_S 0 /** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC17_IN_INV_SEL (BIT(7)) #define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) #define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC17_IN_INV_SEL_S 7 /** GPIO_SIG17_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG17_IN_SEL (BIT(8)) #define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) @@ -3342,36 +3291,36 @@ extern "C" { /** GPIO_FUNC27_IN_SEL_CFG_REG register * Configuration register for input signal 27 */ -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) /** GPIO_FUNC27_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 27.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 27. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC27_IN_SEL 0x0000007FU #define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) #define GPIO_FUNC27_IN_SEL_V 0x0000007FU #define GPIO_FUNC27_IN_SEL_S 0 /** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC27_IN_INV_SEL (BIT(7)) #define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) #define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC27_IN_INV_SEL_S 7 /** GPIO_SIG27_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG27_IN_SEL (BIT(8)) #define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) @@ -3381,36 +3330,36 @@ extern "C" { /** GPIO_FUNC28_IN_SEL_CFG_REG register * Configuration register for input signal 28 */ -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) /** GPIO_FUNC28_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 28.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 28. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC28_IN_SEL 0x0000007FU #define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) #define GPIO_FUNC28_IN_SEL_V 0x0000007FU #define GPIO_FUNC28_IN_SEL_S 0 /** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC28_IN_INV_SEL (BIT(7)) #define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) #define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC28_IN_INV_SEL_S 7 /** GPIO_SIG28_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG28_IN_SEL (BIT(8)) #define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) @@ -3420,36 +3369,36 @@ extern "C" { /** GPIO_FUNC29_IN_SEL_CFG_REG register * Configuration register for input signal 29 */ -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) /** GPIO_FUNC29_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 29.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 29. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC29_IN_SEL 0x0000007FU #define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) #define GPIO_FUNC29_IN_SEL_V 0x0000007FU #define GPIO_FUNC29_IN_SEL_S 0 /** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC29_IN_INV_SEL (BIT(7)) #define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) #define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC29_IN_INV_SEL_S 7 /** GPIO_SIG29_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG29_IN_SEL (BIT(8)) #define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) @@ -3459,36 +3408,36 @@ extern "C" { /** GPIO_FUNC30_IN_SEL_CFG_REG register * Configuration register for input signal 30 */ -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) /** GPIO_FUNC30_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 30.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 30. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC30_IN_SEL 0x0000007FU #define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) #define GPIO_FUNC30_IN_SEL_V 0x0000007FU #define GPIO_FUNC30_IN_SEL_S 0 /** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC30_IN_INV_SEL (BIT(7)) #define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) #define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC30_IN_INV_SEL_S 7 /** GPIO_SIG30_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG30_IN_SEL (BIT(8)) #define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) @@ -3498,36 +3447,36 @@ extern "C" { /** GPIO_FUNC31_IN_SEL_CFG_REG register * Configuration register for input signal 31 */ -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) /** GPIO_FUNC31_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 31.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 31. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC31_IN_SEL 0x0000007FU #define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) #define GPIO_FUNC31_IN_SEL_V 0x0000007FU #define GPIO_FUNC31_IN_SEL_S 0 /** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC31_IN_INV_SEL (BIT(7)) #define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) #define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC31_IN_INV_SEL_S 7 /** GPIO_SIG31_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG31_IN_SEL (BIT(8)) #define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) @@ -3537,36 +3486,36 @@ extern "C" { /** GPIO_FUNC32_IN_SEL_CFG_REG register * Configuration register for input signal 32 */ -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) /** GPIO_FUNC32_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 32.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 32. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC32_IN_SEL 0x0000007FU #define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) #define GPIO_FUNC32_IN_SEL_V 0x0000007FU #define GPIO_FUNC32_IN_SEL_S 0 /** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC32_IN_INV_SEL (BIT(7)) #define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) #define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC32_IN_INV_SEL_S 7 /** GPIO_SIG32_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG32_IN_SEL (BIT(8)) #define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) @@ -3576,36 +3525,36 @@ extern "C" { /** GPIO_FUNC33_IN_SEL_CFG_REG register * Configuration register for input signal 33 */ -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) /** GPIO_FUNC33_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 33.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 33. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC33_IN_SEL 0x0000007FU #define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) #define GPIO_FUNC33_IN_SEL_V 0x0000007FU #define GPIO_FUNC33_IN_SEL_S 0 /** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC33_IN_INV_SEL (BIT(7)) #define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) #define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC33_IN_INV_SEL_S 7 /** GPIO_SIG33_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG33_IN_SEL (BIT(8)) #define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) @@ -3615,36 +3564,36 @@ extern "C" { /** GPIO_FUNC34_IN_SEL_CFG_REG register * Configuration register for input signal 34 */ -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c) /** GPIO_FUNC34_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 34.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 34. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC34_IN_SEL 0x0000007FU #define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) #define GPIO_FUNC34_IN_SEL_V 0x0000007FU #define GPIO_FUNC34_IN_SEL_S 0 /** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC34_IN_INV_SEL (BIT(7)) #define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) #define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC34_IN_INV_SEL_S 7 /** GPIO_SIG34_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG34_IN_SEL (BIT(8)) #define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) @@ -3654,36 +3603,36 @@ extern "C" { /** GPIO_FUNC35_IN_SEL_CFG_REG register * Configuration register for input signal 35 */ -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) /** GPIO_FUNC35_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 35.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 35. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC35_IN_SEL 0x0000007FU #define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) #define GPIO_FUNC35_IN_SEL_V 0x0000007FU #define GPIO_FUNC35_IN_SEL_S 0 /** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC35_IN_INV_SEL (BIT(7)) #define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) #define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC35_IN_INV_SEL_S 7 /** GPIO_SIG35_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG35_IN_SEL (BIT(8)) #define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) @@ -3693,36 +3642,36 @@ extern "C" { /** GPIO_FUNC41_IN_SEL_CFG_REG register * Configuration register for input signal 41 */ -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) /** GPIO_FUNC41_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 41.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 41. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC41_IN_SEL 0x0000007FU #define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) #define GPIO_FUNC41_IN_SEL_V 0x0000007FU #define GPIO_FUNC41_IN_SEL_S 0 /** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC41_IN_INV_SEL (BIT(7)) #define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) #define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC41_IN_INV_SEL_S 7 /** GPIO_SIG41_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG41_IN_SEL (BIT(8)) #define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) @@ -3732,36 +3681,36 @@ extern "C" { /** GPIO_FUNC42_IN_SEL_CFG_REG register * Configuration register for input signal 42 */ -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) /** GPIO_FUNC42_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 42.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 42. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC42_IN_SEL 0x0000007FU #define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) #define GPIO_FUNC42_IN_SEL_V 0x0000007FU #define GPIO_FUNC42_IN_SEL_S 0 /** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC42_IN_INV_SEL (BIT(7)) #define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) #define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC42_IN_INV_SEL_S 7 /** GPIO_SIG42_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG42_IN_SEL (BIT(8)) #define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) @@ -3771,36 +3720,36 @@ extern "C" { /** GPIO_FUNC43_IN_SEL_CFG_REG register * Configuration register for input signal 43 */ -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) /** GPIO_FUNC43_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 43.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 43. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC43_IN_SEL 0x0000007FU #define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) #define GPIO_FUNC43_IN_SEL_V 0x0000007FU #define GPIO_FUNC43_IN_SEL_S 0 /** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC43_IN_INV_SEL (BIT(7)) #define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) #define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC43_IN_INV_SEL_S 7 /** GPIO_SIG43_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG43_IN_SEL (BIT(8)) #define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) @@ -3810,36 +3759,36 @@ extern "C" { /** GPIO_FUNC46_IN_SEL_CFG_REG register * Configuration register for input signal 46 */ -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) /** GPIO_FUNC46_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 46.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 46. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC46_IN_SEL 0x0000007FU #define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) #define GPIO_FUNC46_IN_SEL_V 0x0000007FU #define GPIO_FUNC46_IN_SEL_S 0 /** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC46_IN_INV_SEL (BIT(7)) #define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) #define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC46_IN_INV_SEL_S 7 /** GPIO_SIG46_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG46_IN_SEL (BIT(8)) #define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) @@ -3849,36 +3798,36 @@ extern "C" { /** GPIO_FUNC47_IN_SEL_CFG_REG register * Configuration register for input signal 47 */ -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) /** GPIO_FUNC47_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 47.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 47. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC47_IN_SEL 0x0000007FU #define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) #define GPIO_FUNC47_IN_SEL_V 0x0000007FU #define GPIO_FUNC47_IN_SEL_S 0 /** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC47_IN_INV_SEL (BIT(7)) #define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) #define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC47_IN_INV_SEL_S 7 /** GPIO_SIG47_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG47_IN_SEL (BIT(8)) #define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) @@ -3888,36 +3837,36 @@ extern "C" { /** GPIO_FUNC48_IN_SEL_CFG_REG register * Configuration register for input signal 48 */ -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384) +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394) /** GPIO_FUNC48_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 48.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 48. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC48_IN_SEL 0x0000007FU #define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) #define GPIO_FUNC48_IN_SEL_V 0x0000007FU #define GPIO_FUNC48_IN_SEL_S 0 /** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC48_IN_INV_SEL (BIT(7)) #define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) #define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC48_IN_INV_SEL_S 7 /** GPIO_SIG48_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG48_IN_SEL (BIT(8)) #define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) @@ -3927,36 +3876,36 @@ extern "C" { /** GPIO_FUNC49_IN_SEL_CFG_REG register * Configuration register for input signal 49 */ -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388) +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398) /** GPIO_FUNC49_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 49.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 49. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC49_IN_SEL 0x0000007FU #define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) #define GPIO_FUNC49_IN_SEL_V 0x0000007FU #define GPIO_FUNC49_IN_SEL_S 0 /** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC49_IN_INV_SEL (BIT(7)) #define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) #define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC49_IN_INV_SEL_S 7 /** GPIO_SIG49_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG49_IN_SEL (BIT(8)) #define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) @@ -3966,36 +3915,36 @@ extern "C" { /** GPIO_FUNC50_IN_SEL_CFG_REG register * Configuration register for input signal 50 */ -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c) /** GPIO_FUNC50_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 50.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 50. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC50_IN_SEL 0x0000007FU #define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) #define GPIO_FUNC50_IN_SEL_V 0x0000007FU #define GPIO_FUNC50_IN_SEL_S 0 /** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC50_IN_INV_SEL (BIT(7)) #define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) #define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC50_IN_INV_SEL_S 7 /** GPIO_SIG50_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG50_IN_SEL (BIT(8)) #define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) @@ -4005,36 +3954,36 @@ extern "C" { /** GPIO_FUNC51_IN_SEL_CFG_REG register * Configuration register for input signal 51 */ -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0) /** GPIO_FUNC51_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 51.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 51. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC51_IN_SEL 0x0000007FU #define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) #define GPIO_FUNC51_IN_SEL_V 0x0000007FU #define GPIO_FUNC51_IN_SEL_S 0 /** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC51_IN_INV_SEL (BIT(7)) #define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) #define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC51_IN_INV_SEL_S 7 /** GPIO_SIG51_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG51_IN_SEL (BIT(8)) #define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) @@ -4044,36 +3993,36 @@ extern "C" { /** GPIO_FUNC52_IN_SEL_CFG_REG register * Configuration register for input signal 52 */ -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394) +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4) /** GPIO_FUNC52_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 52.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 52. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC52_IN_SEL 0x0000007FU #define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) #define GPIO_FUNC52_IN_SEL_V 0x0000007FU #define GPIO_FUNC52_IN_SEL_S 0 /** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC52_IN_INV_SEL (BIT(7)) #define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) #define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC52_IN_INV_SEL_S 7 /** GPIO_SIG52_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG52_IN_SEL (BIT(8)) #define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) @@ -4083,36 +4032,36 @@ extern "C" { /** GPIO_FUNC53_IN_SEL_CFG_REG register * Configuration register for input signal 53 */ -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398) +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8) /** GPIO_FUNC53_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 53.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 53. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC53_IN_SEL 0x0000007FU #define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) #define GPIO_FUNC53_IN_SEL_V 0x0000007FU #define GPIO_FUNC53_IN_SEL_S 0 /** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC53_IN_INV_SEL (BIT(7)) #define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) #define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC53_IN_INV_SEL_S 7 /** GPIO_SIG53_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG53_IN_SEL (BIT(8)) #define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) @@ -4122,36 +4071,36 @@ extern "C" { /** GPIO_FUNC54_IN_SEL_CFG_REG register * Configuration register for input signal 54 */ -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c) +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac) /** GPIO_FUNC54_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 54.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 54. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC54_IN_SEL 0x0000007FU #define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) #define GPIO_FUNC54_IN_SEL_V 0x0000007FU #define GPIO_FUNC54_IN_SEL_S 0 /** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC54_IN_INV_SEL (BIT(7)) #define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) #define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC54_IN_INV_SEL_S 7 /** GPIO_SIG54_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG54_IN_SEL (BIT(8)) #define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) @@ -4161,36 +4110,36 @@ extern "C" { /** GPIO_FUNC55_IN_SEL_CFG_REG register * Configuration register for input signal 55 */ -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0) +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0) /** GPIO_FUNC55_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 55.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 55. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC55_IN_SEL 0x0000007FU #define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) #define GPIO_FUNC55_IN_SEL_V 0x0000007FU #define GPIO_FUNC55_IN_SEL_S 0 /** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC55_IN_INV_SEL (BIT(7)) #define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) #define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC55_IN_INV_SEL_S 7 /** GPIO_SIG55_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG55_IN_SEL (BIT(8)) #define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) @@ -4200,36 +4149,36 @@ extern "C" { /** GPIO_FUNC56_IN_SEL_CFG_REG register * Configuration register for input signal 56 */ -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4) +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4) /** GPIO_FUNC56_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 56.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 56. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC56_IN_SEL 0x0000007FU #define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) #define GPIO_FUNC56_IN_SEL_V 0x0000007FU #define GPIO_FUNC56_IN_SEL_S 0 /** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC56_IN_INV_SEL (BIT(7)) #define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) #define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC56_IN_INV_SEL_S 7 /** GPIO_SIG56_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG56_IN_SEL (BIT(8)) #define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) @@ -4239,36 +4188,36 @@ extern "C" { /** GPIO_FUNC57_IN_SEL_CFG_REG register * Configuration register for input signal 57 */ -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8) +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8) /** GPIO_FUNC57_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 57.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 57. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC57_IN_SEL 0x0000007FU #define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) #define GPIO_FUNC57_IN_SEL_V 0x0000007FU #define GPIO_FUNC57_IN_SEL_S 0 /** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC57_IN_INV_SEL (BIT(7)) #define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) #define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC57_IN_INV_SEL_S 7 /** GPIO_SIG57_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG57_IN_SEL (BIT(8)) #define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) @@ -4278,36 +4227,36 @@ extern "C" { /** GPIO_FUNC58_IN_SEL_CFG_REG register * Configuration register for input signal 58 */ -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac) +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc) /** GPIO_FUNC58_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 58.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 58. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC58_IN_SEL 0x0000007FU #define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) #define GPIO_FUNC58_IN_SEL_V 0x0000007FU #define GPIO_FUNC58_IN_SEL_S 0 /** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC58_IN_INV_SEL (BIT(7)) #define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) #define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC58_IN_INV_SEL_S 7 /** GPIO_SIG58_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG58_IN_SEL (BIT(8)) #define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) @@ -4317,36 +4266,36 @@ extern "C" { /** GPIO_FUNC59_IN_SEL_CFG_REG register * Configuration register for input signal 59 */ -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0) +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0) /** GPIO_FUNC59_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 59.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 59. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC59_IN_SEL 0x0000007FU #define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) #define GPIO_FUNC59_IN_SEL_V 0x0000007FU #define GPIO_FUNC59_IN_SEL_S 0 /** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC59_IN_INV_SEL (BIT(7)) #define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) #define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC59_IN_INV_SEL_S 7 /** GPIO_SIG59_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG59_IN_SEL (BIT(8)) #define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) @@ -4356,36 +4305,36 @@ extern "C" { /** GPIO_FUNC60_IN_SEL_CFG_REG register * Configuration register for input signal 60 */ -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4) +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) /** GPIO_FUNC60_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 60.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 60. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC60_IN_SEL 0x0000007FU #define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) #define GPIO_FUNC60_IN_SEL_V 0x0000007FU #define GPIO_FUNC60_IN_SEL_S 0 /** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC60_IN_INV_SEL (BIT(7)) #define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) #define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC60_IN_INV_SEL_S 7 /** GPIO_SIG60_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG60_IN_SEL (BIT(8)) #define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) @@ -4395,36 +4344,36 @@ extern "C" { /** GPIO_FUNC61_IN_SEL_CFG_REG register * Configuration register for input signal 61 */ -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8) +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) /** GPIO_FUNC61_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 61.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 61. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC61_IN_SEL 0x0000007FU #define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) #define GPIO_FUNC61_IN_SEL_V 0x0000007FU #define GPIO_FUNC61_IN_SEL_S 0 /** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC61_IN_INV_SEL (BIT(7)) #define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) #define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC61_IN_INV_SEL_S 7 /** GPIO_SIG61_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG61_IN_SEL (BIT(8)) #define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) @@ -4434,36 +4383,36 @@ extern "C" { /** GPIO_FUNC62_IN_SEL_CFG_REG register * Configuration register for input signal 62 */ -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc) +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) /** GPIO_FUNC62_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 62.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 62. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC62_IN_SEL 0x0000007FU #define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) #define GPIO_FUNC62_IN_SEL_V 0x0000007FU #define GPIO_FUNC62_IN_SEL_S 0 /** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC62_IN_INV_SEL (BIT(7)) #define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) #define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC62_IN_INV_SEL_S 7 /** GPIO_SIG62_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG62_IN_SEL (BIT(8)) #define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) @@ -4473,36 +4422,36 @@ extern "C" { /** GPIO_FUNC63_IN_SEL_CFG_REG register * Configuration register for input signal 63 */ -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0) +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) /** GPIO_FUNC63_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 63.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 63. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC63_IN_SEL 0x0000007FU #define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) #define GPIO_FUNC63_IN_SEL_V 0x0000007FU #define GPIO_FUNC63_IN_SEL_S 0 /** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC63_IN_INV_SEL (BIT(7)) #define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) #define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC63_IN_INV_SEL_S 7 /** GPIO_SIG63_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG63_IN_SEL (BIT(8)) #define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) @@ -4512,36 +4461,36 @@ extern "C" { /** GPIO_FUNC64_IN_SEL_CFG_REG register * Configuration register for input signal 64 */ -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) /** GPIO_FUNC64_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 64.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 64. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC64_IN_SEL 0x0000007FU #define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) #define GPIO_FUNC64_IN_SEL_V 0x0000007FU #define GPIO_FUNC64_IN_SEL_S 0 /** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC64_IN_INV_SEL (BIT(7)) #define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) #define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC64_IN_INV_SEL_S 7 /** GPIO_SIG64_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG64_IN_SEL (BIT(8)) #define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) @@ -4551,36 +4500,36 @@ extern "C" { /** GPIO_FUNC65_IN_SEL_CFG_REG register * Configuration register for input signal 65 */ -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) /** GPIO_FUNC65_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 65.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 65. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC65_IN_SEL 0x0000007FU #define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) #define GPIO_FUNC65_IN_SEL_V 0x0000007FU #define GPIO_FUNC65_IN_SEL_S 0 /** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC65_IN_INV_SEL (BIT(7)) #define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) #define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC65_IN_INV_SEL_S 7 /** GPIO_SIG65_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG65_IN_SEL (BIT(8)) #define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) @@ -4590,36 +4539,36 @@ extern "C" { /** GPIO_FUNC66_IN_SEL_CFG_REG register * Configuration register for input signal 66 */ -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) /** GPIO_FUNC66_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 66.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 66. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC66_IN_SEL 0x0000007FU #define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) #define GPIO_FUNC66_IN_SEL_V 0x0000007FU #define GPIO_FUNC66_IN_SEL_S 0 /** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC66_IN_INV_SEL (BIT(7)) #define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) #define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC66_IN_INV_SEL_S 7 /** GPIO_SIG66_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG66_IN_SEL (BIT(8)) #define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) @@ -4629,36 +4578,36 @@ extern "C" { /** GPIO_FUNC70_IN_SEL_CFG_REG register * Configuration register for input signal 70 */ -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) /** GPIO_FUNC70_IN_SEL : R/W; bitpos: [6:0]; default: 64; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 70.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 70. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC70_IN_SEL 0x0000007FU #define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) #define GPIO_FUNC70_IN_SEL_V 0x0000007FU #define GPIO_FUNC70_IN_SEL_S 0 /** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC70_IN_INV_SEL (BIT(7)) #define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) #define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC70_IN_INV_SEL_S 7 /** GPIO_SIG70_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG70_IN_SEL (BIT(8)) #define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) @@ -4668,36 +4617,36 @@ extern "C" { /** GPIO_FUNC74_IN_SEL_CFG_REG register * Configuration register for input signal 74 */ -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) /** GPIO_FUNC74_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 74.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 74. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC74_IN_SEL 0x0000007FU #define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) #define GPIO_FUNC74_IN_SEL_V 0x0000007FU #define GPIO_FUNC74_IN_SEL_S 0 /** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC74_IN_INV_SEL (BIT(7)) #define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) #define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC74_IN_INV_SEL_S 7 /** GPIO_SIG74_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG74_IN_SEL (BIT(8)) #define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) @@ -4707,36 +4656,36 @@ extern "C" { /** GPIO_FUNC75_IN_SEL_CFG_REG register * Configuration register for input signal 75 */ -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0) +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400) /** GPIO_FUNC75_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 75.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 75. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC75_IN_SEL 0x0000007FU #define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) #define GPIO_FUNC75_IN_SEL_V 0x0000007FU #define GPIO_FUNC75_IN_SEL_S 0 /** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC75_IN_INV_SEL (BIT(7)) #define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) #define GPIO_FUNC75_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC75_IN_INV_SEL_S 7 /** GPIO_SIG75_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG75_IN_SEL (BIT(8)) #define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) @@ -4746,36 +4695,36 @@ extern "C" { /** GPIO_FUNC76_IN_SEL_CFG_REG register * Configuration register for input signal 76 */ -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4) +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404) /** GPIO_FUNC76_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 76.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 76. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC76_IN_SEL 0x0000007FU #define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) #define GPIO_FUNC76_IN_SEL_V 0x0000007FU #define GPIO_FUNC76_IN_SEL_S 0 /** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC76_IN_INV_SEL (BIT(7)) #define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) #define GPIO_FUNC76_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC76_IN_INV_SEL_S 7 /** GPIO_SIG76_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG76_IN_SEL (BIT(8)) #define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) @@ -4785,36 +4734,36 @@ extern "C" { /** GPIO_FUNC77_IN_SEL_CFG_REG register * Configuration register for input signal 77 */ -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8) +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408) /** GPIO_FUNC77_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 77.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 77. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC77_IN_SEL 0x0000007FU #define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) #define GPIO_FUNC77_IN_SEL_V 0x0000007FU #define GPIO_FUNC77_IN_SEL_S 0 /** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC77_IN_INV_SEL (BIT(7)) #define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) #define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC77_IN_INV_SEL_S 7 /** GPIO_SIG77_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG77_IN_SEL (BIT(8)) #define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) @@ -4824,36 +4773,36 @@ extern "C" { /** GPIO_FUNC78_IN_SEL_CFG_REG register * Configuration register for input signal 78 */ -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) /** GPIO_FUNC78_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 78.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 78. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC78_IN_SEL 0x0000007FU #define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) #define GPIO_FUNC78_IN_SEL_V 0x0000007FU #define GPIO_FUNC78_IN_SEL_S 0 /** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC78_IN_INV_SEL (BIT(7)) #define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) #define GPIO_FUNC78_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC78_IN_INV_SEL_S 7 /** GPIO_SIG78_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG78_IN_SEL (BIT(8)) #define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) @@ -4863,36 +4812,36 @@ extern "C" { /** GPIO_FUNC79_IN_SEL_CFG_REG register * Configuration register for input signal 79 */ -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400) +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) /** GPIO_FUNC79_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 79.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 79. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC79_IN_SEL 0x0000007FU #define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) #define GPIO_FUNC79_IN_SEL_V 0x0000007FU #define GPIO_FUNC79_IN_SEL_S 0 /** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC79_IN_INV_SEL (BIT(7)) #define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) #define GPIO_FUNC79_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC79_IN_INV_SEL_S 7 /** GPIO_SIG79_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG79_IN_SEL (BIT(8)) #define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) @@ -4902,36 +4851,36 @@ extern "C" { /** GPIO_FUNC80_IN_SEL_CFG_REG register * Configuration register for input signal 80 */ -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404) +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414) /** GPIO_FUNC80_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 80.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 80. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC80_IN_SEL 0x0000007FU #define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) #define GPIO_FUNC80_IN_SEL_V 0x0000007FU #define GPIO_FUNC80_IN_SEL_S 0 /** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC80_IN_INV_SEL (BIT(7)) #define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) #define GPIO_FUNC80_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC80_IN_INV_SEL_S 7 /** GPIO_SIG80_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG80_IN_SEL (BIT(8)) #define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) @@ -4941,36 +4890,36 @@ extern "C" { /** GPIO_FUNC81_IN_SEL_CFG_REG register * Configuration register for input signal 81 */ -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408) +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418) /** GPIO_FUNC81_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 81.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 81. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC81_IN_SEL 0x0000007FU #define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) #define GPIO_FUNC81_IN_SEL_V 0x0000007FU #define GPIO_FUNC81_IN_SEL_S 0 /** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC81_IN_INV_SEL (BIT(7)) #define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) #define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC81_IN_INV_SEL_S 7 /** GPIO_SIG81_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG81_IN_SEL (BIT(8)) #define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) @@ -4980,36 +4929,36 @@ extern "C" { /** GPIO_FUNC82_IN_SEL_CFG_REG register * Configuration register for input signal 82 */ -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) /** GPIO_FUNC82_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 82.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 82. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC82_IN_SEL 0x0000007FU #define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) #define GPIO_FUNC82_IN_SEL_V 0x0000007FU #define GPIO_FUNC82_IN_SEL_S 0 /** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC82_IN_INV_SEL (BIT(7)) #define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) #define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC82_IN_INV_SEL_S 7 /** GPIO_SIG82_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG82_IN_SEL (BIT(8)) #define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) @@ -5019,36 +4968,36 @@ extern "C" { /** GPIO_FUNC83_IN_SEL_CFG_REG register * Configuration register for input signal 83 */ -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) /** GPIO_FUNC83_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 83.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 83. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC83_IN_SEL 0x0000007FU #define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) #define GPIO_FUNC83_IN_SEL_V 0x0000007FU #define GPIO_FUNC83_IN_SEL_S 0 /** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC83_IN_INV_SEL (BIT(7)) #define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) #define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC83_IN_INV_SEL_S 7 /** GPIO_SIG83_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG83_IN_SEL (BIT(8)) #define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) @@ -5058,36 +5007,36 @@ extern "C" { /** GPIO_FUNC84_IN_SEL_CFG_REG register * Configuration register for input signal 84 */ -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414) +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424) /** GPIO_FUNC84_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 84.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 84. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC84_IN_SEL 0x0000007FU #define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) #define GPIO_FUNC84_IN_SEL_V 0x0000007FU #define GPIO_FUNC84_IN_SEL_S 0 /** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC84_IN_INV_SEL (BIT(7)) #define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) #define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC84_IN_INV_SEL_S 7 /** GPIO_SIG84_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG84_IN_SEL (BIT(8)) #define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) @@ -5097,36 +5046,36 @@ extern "C" { /** GPIO_FUNC85_IN_SEL_CFG_REG register * Configuration register for input signal 85 */ -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418) +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428) /** GPIO_FUNC85_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 85.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 85. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC85_IN_SEL 0x0000007FU #define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) #define GPIO_FUNC85_IN_SEL_V 0x0000007FU #define GPIO_FUNC85_IN_SEL_S 0 /** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC85_IN_INV_SEL (BIT(7)) #define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) #define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC85_IN_INV_SEL_S 7 /** GPIO_SIG85_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG85_IN_SEL (BIT(8)) #define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) @@ -5136,36 +5085,36 @@ extern "C" { /** GPIO_FUNC86_IN_SEL_CFG_REG register * Configuration register for input signal 86 */ -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c) /** GPIO_FUNC86_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 86.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 86. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC86_IN_SEL 0x0000007FU #define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) #define GPIO_FUNC86_IN_SEL_V 0x0000007FU #define GPIO_FUNC86_IN_SEL_S 0 /** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC86_IN_INV_SEL (BIT(7)) #define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) #define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC86_IN_INV_SEL_S 7 /** GPIO_SIG86_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG86_IN_SEL (BIT(8)) #define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) @@ -5175,36 +5124,36 @@ extern "C" { /** GPIO_FUNC87_IN_SEL_CFG_REG register * Configuration register for input signal 87 */ -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430) /** GPIO_FUNC87_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 87.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 87. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC87_IN_SEL 0x0000007FU #define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) #define GPIO_FUNC87_IN_SEL_V 0x0000007FU #define GPIO_FUNC87_IN_SEL_S 0 /** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC87_IN_INV_SEL (BIT(7)) #define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) #define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC87_IN_INV_SEL_S 7 /** GPIO_SIG87_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG87_IN_SEL (BIT(8)) #define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) @@ -5214,36 +5163,36 @@ extern "C" { /** GPIO_FUNC88_IN_SEL_CFG_REG register * Configuration register for input signal 88 */ -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424) +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434) /** GPIO_FUNC88_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 88.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 88. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC88_IN_SEL 0x0000007FU #define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) #define GPIO_FUNC88_IN_SEL_V 0x0000007FU #define GPIO_FUNC88_IN_SEL_S 0 /** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC88_IN_INV_SEL (BIT(7)) #define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) #define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC88_IN_INV_SEL_S 7 /** GPIO_SIG88_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG88_IN_SEL (BIT(8)) #define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) @@ -5253,36 +5202,36 @@ extern "C" { /** GPIO_FUNC89_IN_SEL_CFG_REG register * Configuration register for input signal 89 */ -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428) +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438) /** GPIO_FUNC89_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 89.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 89. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC89_IN_SEL 0x0000007FU #define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) #define GPIO_FUNC89_IN_SEL_V 0x0000007FU #define GPIO_FUNC89_IN_SEL_S 0 /** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC89_IN_INV_SEL (BIT(7)) #define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) #define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC89_IN_INV_SEL_S 7 /** GPIO_SIG89_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG89_IN_SEL (BIT(8)) #define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) @@ -5292,36 +5241,36 @@ extern "C" { /** GPIO_FUNC90_IN_SEL_CFG_REG register * Configuration register for input signal 90 */ -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c) +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c) /** GPIO_FUNC90_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 90.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 90. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC90_IN_SEL 0x0000007FU #define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) #define GPIO_FUNC90_IN_SEL_V 0x0000007FU #define GPIO_FUNC90_IN_SEL_S 0 /** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC90_IN_INV_SEL (BIT(7)) #define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) #define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC90_IN_INV_SEL_S 7 /** GPIO_SIG90_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG90_IN_SEL (BIT(8)) #define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) @@ -5331,36 +5280,36 @@ extern "C" { /** GPIO_FUNC91_IN_SEL_CFG_REG register * Configuration register for input signal 91 */ -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430) +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440) /** GPIO_FUNC91_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 91.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 91. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC91_IN_SEL 0x0000007FU #define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) #define GPIO_FUNC91_IN_SEL_V 0x0000007FU #define GPIO_FUNC91_IN_SEL_S 0 /** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC91_IN_INV_SEL (BIT(7)) #define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) #define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC91_IN_INV_SEL_S 7 /** GPIO_SIG91_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG91_IN_SEL (BIT(8)) #define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) @@ -5370,36 +5319,36 @@ extern "C" { /** GPIO_FUNC92_IN_SEL_CFG_REG register * Configuration register for input signal 92 */ -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434) +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444) /** GPIO_FUNC92_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 92.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 92. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC92_IN_SEL 0x0000007FU #define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) #define GPIO_FUNC92_IN_SEL_V 0x0000007FU #define GPIO_FUNC92_IN_SEL_S 0 /** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC92_IN_INV_SEL (BIT(7)) #define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) #define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC92_IN_INV_SEL_S 7 /** GPIO_SIG92_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG92_IN_SEL (BIT(8)) #define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) @@ -5409,36 +5358,36 @@ extern "C" { /** GPIO_FUNC97_IN_SEL_CFG_REG register * Configuration register for input signal 97 */ -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) /** GPIO_FUNC97_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 97.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 97. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC97_IN_SEL 0x0000007FU #define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) #define GPIO_FUNC97_IN_SEL_V 0x0000007FU #define GPIO_FUNC97_IN_SEL_S 0 /** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC97_IN_INV_SEL (BIT(7)) #define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) #define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC97_IN_INV_SEL_S 7 /** GPIO_SIG97_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG97_IN_SEL (BIT(8)) #define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) @@ -5448,36 +5397,36 @@ extern "C" { /** GPIO_FUNC98_IN_SEL_CFG_REG register * Configuration register for input signal 98 */ -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) /** GPIO_FUNC98_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 98.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 98. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC98_IN_SEL 0x0000007FU #define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) #define GPIO_FUNC98_IN_SEL_V 0x0000007FU #define GPIO_FUNC98_IN_SEL_S 0 /** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC98_IN_INV_SEL (BIT(7)) #define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) #define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC98_IN_INV_SEL_S 7 /** GPIO_SIG98_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG98_IN_SEL (BIT(8)) #define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) @@ -5487,36 +5436,36 @@ extern "C" { /** GPIO_FUNC99_IN_SEL_CFG_REG register * Configuration register for input signal 99 */ -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) /** GPIO_FUNC99_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 99.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 99. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC99_IN_SEL 0x0000007FU #define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) #define GPIO_FUNC99_IN_SEL_V 0x0000007FU #define GPIO_FUNC99_IN_SEL_S 0 /** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC99_IN_INV_SEL (BIT(7)) #define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) #define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC99_IN_INV_SEL_S 7 /** GPIO_SIG99_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG99_IN_SEL (BIT(8)) #define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) @@ -5526,36 +5475,36 @@ extern "C" { /** GPIO_FUNC100_IN_SEL_CFG_REG register * Configuration register for input signal 100 */ -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) /** GPIO_FUNC100_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 100.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 100. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC100_IN_SEL 0x0000007FU #define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) #define GPIO_FUNC100_IN_SEL_V 0x0000007FU #define GPIO_FUNC100_IN_SEL_S 0 /** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC100_IN_INV_SEL (BIT(7)) #define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) #define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC100_IN_INV_SEL_S 7 /** GPIO_SIG100_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG100_IN_SEL (BIT(8)) #define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) @@ -5565,36 +5514,36 @@ extern "C" { /** GPIO_FUNC101_IN_SEL_CFG_REG register * Configuration register for input signal 101 */ -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468) /** GPIO_FUNC101_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 101.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 101. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC101_IN_SEL 0x0000007FU #define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) #define GPIO_FUNC101_IN_SEL_V 0x0000007FU #define GPIO_FUNC101_IN_SEL_S 0 /** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC101_IN_INV_SEL (BIT(7)) #define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) #define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC101_IN_INV_SEL_S 7 /** GPIO_SIG101_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG101_IN_SEL (BIT(8)) #define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) @@ -5604,36 +5553,36 @@ extern "C" { /** GPIO_FUNC102_IN_SEL_CFG_REG register * Configuration register for input signal 102 */ -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c) /** GPIO_FUNC102_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 102.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 102. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC102_IN_SEL 0x0000007FU #define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) #define GPIO_FUNC102_IN_SEL_V 0x0000007FU #define GPIO_FUNC102_IN_SEL_S 0 /** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC102_IN_INV_SEL (BIT(7)) #define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) #define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC102_IN_INV_SEL_S 7 /** GPIO_SIG102_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG102_IN_SEL (BIT(8)) #define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) @@ -5643,36 +5592,36 @@ extern "C" { /** GPIO_FUNC103_IN_SEL_CFG_REG register * Configuration register for input signal 103 */ -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470) /** GPIO_FUNC103_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 103.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 103. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC103_IN_SEL 0x0000007FU #define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) #define GPIO_FUNC103_IN_SEL_V 0x0000007FU #define GPIO_FUNC103_IN_SEL_S 0 /** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC103_IN_INV_SEL (BIT(7)) #define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) #define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC103_IN_INV_SEL_S 7 /** GPIO_SIG103_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG103_IN_SEL (BIT(8)) #define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) @@ -5682,36 +5631,36 @@ extern "C" { /** GPIO_FUNC104_IN_SEL_CFG_REG register * Configuration register for input signal 104 */ -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474) /** GPIO_FUNC104_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 104.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 104. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC104_IN_SEL 0x0000007FU #define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) #define GPIO_FUNC104_IN_SEL_V 0x0000007FU #define GPIO_FUNC104_IN_SEL_S 0 /** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC104_IN_INV_SEL (BIT(7)) #define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) #define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC104_IN_INV_SEL_S 7 /** GPIO_SIG104_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG104_IN_SEL (BIT(8)) #define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) @@ -5721,36 +5670,36 @@ extern "C" { /** GPIO_FUNC105_IN_SEL_CFG_REG register * Configuration register for input signal 105 */ -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468) +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478) /** GPIO_FUNC105_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 105.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 105. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC105_IN_SEL 0x0000007FU #define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) #define GPIO_FUNC105_IN_SEL_V 0x0000007FU #define GPIO_FUNC105_IN_SEL_S 0 /** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC105_IN_INV_SEL (BIT(7)) #define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) #define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC105_IN_INV_SEL_S 7 /** GPIO_SIG105_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG105_IN_SEL (BIT(8)) #define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) @@ -5760,36 +5709,36 @@ extern "C" { /** GPIO_FUNC106_IN_SEL_CFG_REG register * Configuration register for input signal 106 */ -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c) +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c) /** GPIO_FUNC106_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 106.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 106. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC106_IN_SEL 0x0000007FU #define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) #define GPIO_FUNC106_IN_SEL_V 0x0000007FU #define GPIO_FUNC106_IN_SEL_S 0 /** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC106_IN_INV_SEL (BIT(7)) #define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) #define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC106_IN_INV_SEL_S 7 /** GPIO_SIG106_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG106_IN_SEL (BIT(8)) #define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) @@ -5799,36 +5748,36 @@ extern "C" { /** GPIO_FUNC107_IN_SEL_CFG_REG register * Configuration register for input signal 107 */ -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470) +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480) /** GPIO_FUNC107_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 107.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 107. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC107_IN_SEL 0x0000007FU #define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) #define GPIO_FUNC107_IN_SEL_V 0x0000007FU #define GPIO_FUNC107_IN_SEL_S 0 /** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC107_IN_INV_SEL (BIT(7)) #define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) #define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC107_IN_INV_SEL_S 7 /** GPIO_SIG107_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG107_IN_SEL (BIT(8)) #define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) @@ -5838,36 +5787,36 @@ extern "C" { /** GPIO_FUNC108_IN_SEL_CFG_REG register * Configuration register for input signal 108 */ -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474) +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484) /** GPIO_FUNC108_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 108.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 108. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC108_IN_SEL 0x0000007FU #define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) #define GPIO_FUNC108_IN_SEL_V 0x0000007FU #define GPIO_FUNC108_IN_SEL_S 0 /** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC108_IN_INV_SEL (BIT(7)) #define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) #define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC108_IN_INV_SEL_S 7 /** GPIO_SIG108_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG108_IN_SEL (BIT(8)) #define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) @@ -5877,36 +5826,36 @@ extern "C" { /** GPIO_FUNC109_IN_SEL_CFG_REG register * Configuration register for input signal 109 */ -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478) +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488) /** GPIO_FUNC109_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 109.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 109. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC109_IN_SEL 0x0000007FU #define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) #define GPIO_FUNC109_IN_SEL_V 0x0000007FU #define GPIO_FUNC109_IN_SEL_S 0 /** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC109_IN_INV_SEL (BIT(7)) #define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) #define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC109_IN_INV_SEL_S 7 /** GPIO_SIG109_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG109_IN_SEL (BIT(8)) #define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) @@ -5916,36 +5865,36 @@ extern "C" { /** GPIO_FUNC110_IN_SEL_CFG_REG register * Configuration register for input signal 110 */ -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c) +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48c) /** GPIO_FUNC110_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 110.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 110. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC110_IN_SEL 0x0000007FU #define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) #define GPIO_FUNC110_IN_SEL_V 0x0000007FU #define GPIO_FUNC110_IN_SEL_S 0 /** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC110_IN_INV_SEL (BIT(7)) #define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) #define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC110_IN_INV_SEL_S 7 /** GPIO_SIG110_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG110_IN_SEL (BIT(8)) #define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) @@ -5955,36 +5904,36 @@ extern "C" { /** GPIO_FUNC111_IN_SEL_CFG_REG register * Configuration register for input signal 111 */ -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480) +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490) /** GPIO_FUNC111_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 111.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 111. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC111_IN_SEL 0x0000007FU #define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) #define GPIO_FUNC111_IN_SEL_V 0x0000007FU #define GPIO_FUNC111_IN_SEL_S 0 /** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC111_IN_INV_SEL (BIT(7)) #define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) #define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC111_IN_INV_SEL_S 7 /** GPIO_SIG111_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG111_IN_SEL (BIT(8)) #define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) @@ -5994,36 +5943,36 @@ extern "C" { /** GPIO_FUNC112_IN_SEL_CFG_REG register * Configuration register for input signal 112 */ -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484) +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494) /** GPIO_FUNC112_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 112.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 112. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC112_IN_SEL 0x0000007FU #define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) #define GPIO_FUNC112_IN_SEL_V 0x0000007FU #define GPIO_FUNC112_IN_SEL_S 0 /** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC112_IN_INV_SEL (BIT(7)) #define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) #define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC112_IN_INV_SEL_S 7 /** GPIO_SIG112_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG112_IN_SEL (BIT(8)) #define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) @@ -6033,36 +5982,36 @@ extern "C" { /** GPIO_FUNC113_IN_SEL_CFG_REG register * Configuration register for input signal 113 */ -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488) +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x498) /** GPIO_FUNC113_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 113.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 113. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC113_IN_SEL 0x0000007FU #define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) #define GPIO_FUNC113_IN_SEL_V 0x0000007FU #define GPIO_FUNC113_IN_SEL_S 0 /** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC113_IN_INV_SEL (BIT(7)) #define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) #define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC113_IN_INV_SEL_S 7 /** GPIO_SIG113_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG113_IN_SEL (BIT(8)) #define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) @@ -6072,36 +6021,36 @@ extern "C" { /** GPIO_FUNC114_IN_SEL_CFG_REG register * Configuration register for input signal 114 */ -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48c) +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) /** GPIO_FUNC114_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 114.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 114. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC114_IN_SEL 0x0000007FU #define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) #define GPIO_FUNC114_IN_SEL_V 0x0000007FU #define GPIO_FUNC114_IN_SEL_S 0 /** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC114_IN_INV_SEL (BIT(7)) #define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) #define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC114_IN_INV_SEL_S 7 /** GPIO_SIG114_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG114_IN_SEL (BIT(8)) #define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) @@ -6111,36 +6060,36 @@ extern "C" { /** GPIO_FUNC115_IN_SEL_CFG_REG register * Configuration register for input signal 115 */ -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490) +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) /** GPIO_FUNC115_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 115.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 115. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC115_IN_SEL 0x0000007FU #define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) #define GPIO_FUNC115_IN_SEL_V 0x0000007FU #define GPIO_FUNC115_IN_SEL_S 0 /** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC115_IN_INV_SEL (BIT(7)) #define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) #define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC115_IN_INV_SEL_S 7 /** GPIO_SIG115_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG115_IN_SEL (BIT(8)) #define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) @@ -6150,36 +6099,36 @@ extern "C" { /** GPIO_FUNC116_IN_SEL_CFG_REG register * Configuration register for input signal 116 */ -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494) +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) /** GPIO_FUNC116_IN_SEL : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 116.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal 116. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ #define GPIO_FUNC116_IN_SEL 0x0000007FU #define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) #define GPIO_FUNC116_IN_SEL_V 0x0000007FU #define GPIO_FUNC116_IN_SEL_S 0 /** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC116_IN_INV_SEL (BIT(7)) #define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) #define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U #define GPIO_FUNC116_IN_INV_SEL_S 7 /** GPIO_SIG116_IN_SEL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ #define GPIO_SIG116_IN_SEL (BIT(8)) #define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) @@ -6189,21 +6138,20 @@ extern "C" { /** GPIO_FUNC0_OUT_SEL_CFG_REG register * Configuration register for GPIO0 output */ -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4) +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) /** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO0.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO0. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC0_OUT_SEL 0x000001FFU @@ -6211,27 +6159,27 @@ extern "C" { #define GPIO_FUNC0_OUT_SEL_V 0x000001FFU #define GPIO_FUNC0_OUT_SEL_S 0 /** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) #define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC0_OUT_INV_SEL_S 9 /** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. */ #define GPIO_FUNC0_OE_SEL (BIT(10)) #define GPIO_FUNC0_OE_SEL_M (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S) #define GPIO_FUNC0_OE_SEL_V 0x00000001U #define GPIO_FUNC0_OE_SEL_S 10 /** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC0_OE_INV_SEL (BIT(11)) #define GPIO_FUNC0_OE_INV_SEL_M (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S) @@ -6241,21 +6189,20 @@ extern "C" { /** GPIO_FUNC1_OUT_SEL_CFG_REG register * Configuration register for GPIO1 output */ -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8) +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) /** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO1.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO1. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC1_OUT_SEL 0x000001FFU @@ -6263,27 +6210,27 @@ extern "C" { #define GPIO_FUNC1_OUT_SEL_V 0x000001FFU #define GPIO_FUNC1_OUT_SEL_S 0 /** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) #define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC1_OUT_INV_SEL_S 9 /** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. */ #define GPIO_FUNC1_OE_SEL (BIT(10)) #define GPIO_FUNC1_OE_SEL_M (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S) #define GPIO_FUNC1_OE_SEL_V 0x00000001U #define GPIO_FUNC1_OE_SEL_S 10 /** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC1_OE_INV_SEL (BIT(11)) #define GPIO_FUNC1_OE_INV_SEL_M (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S) @@ -6293,21 +6240,20 @@ extern "C" { /** GPIO_FUNC2_OUT_SEL_CFG_REG register * Configuration register for GPIO2 output */ -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc) +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) /** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO2.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO2. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC2_OUT_SEL 0x000001FFU @@ -6315,27 +6261,27 @@ extern "C" { #define GPIO_FUNC2_OUT_SEL_V 0x000001FFU #define GPIO_FUNC2_OUT_SEL_S 0 /** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) #define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC2_OUT_INV_SEL_S 9 /** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. */ #define GPIO_FUNC2_OE_SEL (BIT(10)) #define GPIO_FUNC2_OE_SEL_M (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S) #define GPIO_FUNC2_OE_SEL_V 0x00000001U #define GPIO_FUNC2_OE_SEL_S 10 /** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC2_OE_INV_SEL (BIT(11)) #define GPIO_FUNC2_OE_INV_SEL_M (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S) @@ -6345,21 +6291,20 @@ extern "C" { /** GPIO_FUNC3_OUT_SEL_CFG_REG register * Configuration register for GPIO3 output */ -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0) +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) /** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO3.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO3. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC3_OUT_SEL 0x000001FFU @@ -6367,27 +6312,27 @@ extern "C" { #define GPIO_FUNC3_OUT_SEL_V 0x000001FFU #define GPIO_FUNC3_OUT_SEL_S 0 /** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) #define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC3_OUT_INV_SEL_S 9 /** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. */ #define GPIO_FUNC3_OE_SEL (BIT(10)) #define GPIO_FUNC3_OE_SEL_M (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S) #define GPIO_FUNC3_OE_SEL_V 0x00000001U #define GPIO_FUNC3_OE_SEL_S 10 /** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC3_OE_INV_SEL (BIT(11)) #define GPIO_FUNC3_OE_INV_SEL_M (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S) @@ -6397,21 +6342,20 @@ extern "C" { /** GPIO_FUNC4_OUT_SEL_CFG_REG register * Configuration register for GPIO4 output */ -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) /** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO4.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO4. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC4_OUT_SEL 0x000001FFU @@ -6419,27 +6363,27 @@ extern "C" { #define GPIO_FUNC4_OUT_SEL_V 0x000001FFU #define GPIO_FUNC4_OUT_SEL_S 0 /** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) #define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC4_OUT_INV_SEL_S 9 /** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. */ #define GPIO_FUNC4_OE_SEL (BIT(10)) #define GPIO_FUNC4_OE_SEL_M (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S) #define GPIO_FUNC4_OE_SEL_V 0x00000001U #define GPIO_FUNC4_OE_SEL_S 10 /** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC4_OE_INV_SEL (BIT(11)) #define GPIO_FUNC4_OE_INV_SEL_M (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S) @@ -6449,21 +6393,20 @@ extern "C" { /** GPIO_FUNC5_OUT_SEL_CFG_REG register * Configuration register for GPIO5 output */ -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) /** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO5.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO5. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC5_OUT_SEL 0x000001FFU @@ -6471,27 +6414,27 @@ extern "C" { #define GPIO_FUNC5_OUT_SEL_V 0x000001FFU #define GPIO_FUNC5_OUT_SEL_S 0 /** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) #define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC5_OUT_INV_SEL_S 9 /** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. */ #define GPIO_FUNC5_OE_SEL (BIT(10)) #define GPIO_FUNC5_OE_SEL_M (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S) #define GPIO_FUNC5_OE_SEL_V 0x00000001U #define GPIO_FUNC5_OE_SEL_S 10 /** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC5_OE_INV_SEL (BIT(11)) #define GPIO_FUNC5_OE_INV_SEL_M (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S) @@ -6501,21 +6444,20 @@ extern "C" { /** GPIO_FUNC6_OUT_SEL_CFG_REG register * Configuration register for GPIO6 output */ -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) /** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO6.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO6. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC6_OUT_SEL 0x000001FFU @@ -6523,27 +6465,27 @@ extern "C" { #define GPIO_FUNC6_OUT_SEL_V 0x000001FFU #define GPIO_FUNC6_OUT_SEL_S 0 /** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) #define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC6_OUT_INV_SEL_S 9 /** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. */ #define GPIO_FUNC6_OE_SEL (BIT(10)) #define GPIO_FUNC6_OE_SEL_M (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S) #define GPIO_FUNC6_OE_SEL_V 0x00000001U #define GPIO_FUNC6_OE_SEL_S 10 /** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC6_OE_INV_SEL (BIT(11)) #define GPIO_FUNC6_OE_INV_SEL_M (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S) @@ -6553,21 +6495,20 @@ extern "C" { /** GPIO_FUNC7_OUT_SEL_CFG_REG register * Configuration register for GPIO7 output */ -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) /** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO7.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO7. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC7_OUT_SEL 0x000001FFU @@ -6575,27 +6516,27 @@ extern "C" { #define GPIO_FUNC7_OUT_SEL_V 0x000001FFU #define GPIO_FUNC7_OUT_SEL_S 0 /** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) #define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC7_OUT_INV_SEL_S 9 /** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. */ #define GPIO_FUNC7_OE_SEL (BIT(10)) #define GPIO_FUNC7_OE_SEL_M (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S) #define GPIO_FUNC7_OE_SEL_V 0x00000001U #define GPIO_FUNC7_OE_SEL_S 10 /** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC7_OE_INV_SEL (BIT(11)) #define GPIO_FUNC7_OE_INV_SEL_M (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S) @@ -6605,21 +6546,20 @@ extern "C" { /** GPIO_FUNC8_OUT_SEL_CFG_REG register * Configuration register for GPIO8 output */ -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) /** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO8.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO8. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC8_OUT_SEL 0x000001FFU @@ -6627,27 +6567,27 @@ extern "C" { #define GPIO_FUNC8_OUT_SEL_V 0x000001FFU #define GPIO_FUNC8_OUT_SEL_S 0 /** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) #define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC8_OUT_INV_SEL_S 9 /** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. */ #define GPIO_FUNC8_OE_SEL (BIT(10)) #define GPIO_FUNC8_OE_SEL_M (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S) #define GPIO_FUNC8_OE_SEL_V 0x00000001U #define GPIO_FUNC8_OE_SEL_S 10 /** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC8_OE_INV_SEL (BIT(11)) #define GPIO_FUNC8_OE_INV_SEL_M (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S) @@ -6657,21 +6597,20 @@ extern "C" { /** GPIO_FUNC9_OUT_SEL_CFG_REG register * Configuration register for GPIO9 output */ -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) /** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO9.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO9. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC9_OUT_SEL 0x000001FFU @@ -6679,27 +6618,27 @@ extern "C" { #define GPIO_FUNC9_OUT_SEL_V 0x000001FFU #define GPIO_FUNC9_OUT_SEL_S 0 /** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) #define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC9_OUT_INV_SEL_S 9 /** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. */ #define GPIO_FUNC9_OE_SEL (BIT(10)) #define GPIO_FUNC9_OE_SEL_M (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S) #define GPIO_FUNC9_OE_SEL_V 0x00000001U #define GPIO_FUNC9_OE_SEL_S 10 /** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC9_OE_INV_SEL (BIT(11)) #define GPIO_FUNC9_OE_INV_SEL_M (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S) @@ -6709,21 +6648,20 @@ extern "C" { /** GPIO_FUNC10_OUT_SEL_CFG_REG register * Configuration register for GPIO10 output */ -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) /** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO10.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO10. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC10_OUT_SEL 0x000001FFU @@ -6731,27 +6669,27 @@ extern "C" { #define GPIO_FUNC10_OUT_SEL_V 0x000001FFU #define GPIO_FUNC10_OUT_SEL_S 0 /** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) #define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC10_OUT_INV_SEL_S 9 /** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. */ #define GPIO_FUNC10_OE_SEL (BIT(10)) #define GPIO_FUNC10_OE_SEL_M (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S) #define GPIO_FUNC10_OE_SEL_V 0x00000001U #define GPIO_FUNC10_OE_SEL_S 10 /** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC10_OE_INV_SEL (BIT(11)) #define GPIO_FUNC10_OE_INV_SEL_M (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S) @@ -6761,21 +6699,20 @@ extern "C" { /** GPIO_FUNC11_OUT_SEL_CFG_REG register * Configuration register for GPIO11 output */ -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) /** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO11.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO11. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC11_OUT_SEL 0x000001FFU @@ -6783,27 +6720,27 @@ extern "C" { #define GPIO_FUNC11_OUT_SEL_V 0x000001FFU #define GPIO_FUNC11_OUT_SEL_S 0 /** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) #define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC11_OUT_INV_SEL_S 9 /** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. */ #define GPIO_FUNC11_OE_SEL (BIT(10)) #define GPIO_FUNC11_OE_SEL_M (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S) #define GPIO_FUNC11_OE_SEL_V 0x00000001U #define GPIO_FUNC11_OE_SEL_S 10 /** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC11_OE_INV_SEL (BIT(11)) #define GPIO_FUNC11_OE_INV_SEL_M (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S) @@ -6813,21 +6750,20 @@ extern "C" { /** GPIO_FUNC12_OUT_SEL_CFG_REG register * Configuration register for GPIO12 output */ -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) /** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO12.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO12. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC12_OUT_SEL 0x000001FFU @@ -6835,27 +6771,27 @@ extern "C" { #define GPIO_FUNC12_OUT_SEL_V 0x000001FFU #define GPIO_FUNC12_OUT_SEL_S 0 /** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) #define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC12_OUT_INV_SEL_S 9 /** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. */ #define GPIO_FUNC12_OE_SEL (BIT(10)) #define GPIO_FUNC12_OE_SEL_M (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S) #define GPIO_FUNC12_OE_SEL_V 0x00000001U #define GPIO_FUNC12_OE_SEL_S 10 /** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC12_OE_INV_SEL (BIT(11)) #define GPIO_FUNC12_OE_INV_SEL_M (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S) @@ -6865,21 +6801,20 @@ extern "C" { /** GPIO_FUNC13_OUT_SEL_CFG_REG register * Configuration register for GPIO13 output */ -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) /** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO13.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO13. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC13_OUT_SEL 0x000001FFU @@ -6887,27 +6822,27 @@ extern "C" { #define GPIO_FUNC13_OUT_SEL_V 0x000001FFU #define GPIO_FUNC13_OUT_SEL_S 0 /** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) #define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC13_OUT_INV_SEL_S 9 /** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. */ #define GPIO_FUNC13_OE_SEL (BIT(10)) #define GPIO_FUNC13_OE_SEL_M (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S) #define GPIO_FUNC13_OE_SEL_V 0x00000001U #define GPIO_FUNC13_OE_SEL_S 10 /** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC13_OE_INV_SEL (BIT(11)) #define GPIO_FUNC13_OE_INV_SEL_M (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S) @@ -6917,21 +6852,20 @@ extern "C" { /** GPIO_FUNC14_OUT_SEL_CFG_REG register * Configuration register for GPIO14 output */ -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) /** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO14.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO14. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC14_OUT_SEL 0x000001FFU @@ -6939,27 +6873,27 @@ extern "C" { #define GPIO_FUNC14_OUT_SEL_V 0x000001FFU #define GPIO_FUNC14_OUT_SEL_S 0 /** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) #define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC14_OUT_INV_SEL_S 9 /** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. */ #define GPIO_FUNC14_OE_SEL (BIT(10)) #define GPIO_FUNC14_OE_SEL_M (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S) #define GPIO_FUNC14_OE_SEL_V 0x00000001U #define GPIO_FUNC14_OE_SEL_S 10 /** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC14_OE_INV_SEL (BIT(11)) #define GPIO_FUNC14_OE_INV_SEL_M (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S) @@ -6969,21 +6903,20 @@ extern "C" { /** GPIO_FUNC15_OUT_SEL_CFG_REG register * Configuration register for GPIO15 output */ -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) /** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO15.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO15. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC15_OUT_SEL 0x000001FFU @@ -6991,27 +6924,27 @@ extern "C" { #define GPIO_FUNC15_OUT_SEL_V 0x000001FFU #define GPIO_FUNC15_OUT_SEL_S 0 /** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) #define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC15_OUT_INV_SEL_S 9 /** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. */ #define GPIO_FUNC15_OE_SEL (BIT(10)) #define GPIO_FUNC15_OE_SEL_M (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S) #define GPIO_FUNC15_OE_SEL_V 0x00000001U #define GPIO_FUNC15_OE_SEL_S 10 /** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC15_OE_INV_SEL (BIT(11)) #define GPIO_FUNC15_OE_INV_SEL_M (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S) @@ -7021,21 +6954,20 @@ extern "C" { /** GPIO_FUNC16_OUT_SEL_CFG_REG register * Configuration register for GPIO16 output */ -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) /** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO16.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO16. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC16_OUT_SEL 0x000001FFU @@ -7043,27 +6975,27 @@ extern "C" { #define GPIO_FUNC16_OUT_SEL_V 0x000001FFU #define GPIO_FUNC16_OUT_SEL_S 0 /** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) #define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC16_OUT_INV_SEL_S 9 /** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. */ #define GPIO_FUNC16_OE_SEL (BIT(10)) #define GPIO_FUNC16_OE_SEL_M (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S) #define GPIO_FUNC16_OE_SEL_V 0x00000001U #define GPIO_FUNC16_OE_SEL_S 10 /** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC16_OE_INV_SEL (BIT(11)) #define GPIO_FUNC16_OE_INV_SEL_M (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S) @@ -7073,21 +7005,20 @@ extern "C" { /** GPIO_FUNC17_OUT_SEL_CFG_REG register * Configuration register for GPIO17 output */ -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) /** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO17.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO17. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC17_OUT_SEL 0x000001FFU @@ -7095,27 +7026,27 @@ extern "C" { #define GPIO_FUNC17_OUT_SEL_V 0x000001FFU #define GPIO_FUNC17_OUT_SEL_S 0 /** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) #define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC17_OUT_INV_SEL_S 9 /** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. */ #define GPIO_FUNC17_OE_SEL (BIT(10)) #define GPIO_FUNC17_OE_SEL_M (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S) #define GPIO_FUNC17_OE_SEL_V 0x00000001U #define GPIO_FUNC17_OE_SEL_S 10 /** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC17_OE_INV_SEL (BIT(11)) #define GPIO_FUNC17_OE_INV_SEL_M (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S) @@ -7125,21 +7056,20 @@ extern "C" { /** GPIO_FUNC18_OUT_SEL_CFG_REG register * Configuration register for GPIO18 output */ -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) /** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO18.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO18. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC18_OUT_SEL 0x000001FFU @@ -7147,27 +7077,27 @@ extern "C" { #define GPIO_FUNC18_OUT_SEL_V 0x000001FFU #define GPIO_FUNC18_OUT_SEL_S 0 /** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) #define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC18_OUT_INV_SEL_S 9 /** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. */ #define GPIO_FUNC18_OE_SEL (BIT(10)) #define GPIO_FUNC18_OE_SEL_M (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S) #define GPIO_FUNC18_OE_SEL_V 0x00000001U #define GPIO_FUNC18_OE_SEL_S 10 /** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC18_OE_INV_SEL (BIT(11)) #define GPIO_FUNC18_OE_INV_SEL_M (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S) @@ -7177,21 +7107,20 @@ extern "C" { /** GPIO_FUNC19_OUT_SEL_CFG_REG register * Configuration register for GPIO19 output */ -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) /** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO19.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO19. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC19_OUT_SEL 0x000001FFU @@ -7199,27 +7128,27 @@ extern "C" { #define GPIO_FUNC19_OUT_SEL_V 0x000001FFU #define GPIO_FUNC19_OUT_SEL_S 0 /** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) #define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC19_OUT_INV_SEL_S 9 /** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. */ #define GPIO_FUNC19_OE_SEL (BIT(10)) #define GPIO_FUNC19_OE_SEL_M (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S) #define GPIO_FUNC19_OE_SEL_V 0x00000001U #define GPIO_FUNC19_OE_SEL_S 10 /** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC19_OE_INV_SEL (BIT(11)) #define GPIO_FUNC19_OE_INV_SEL_M (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S) @@ -7229,21 +7158,20 @@ extern "C" { /** GPIO_FUNC20_OUT_SEL_CFG_REG register * Configuration register for GPIO20 output */ -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) /** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO20.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO20. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC20_OUT_SEL 0x000001FFU @@ -7251,27 +7179,27 @@ extern "C" { #define GPIO_FUNC20_OUT_SEL_V 0x000001FFU #define GPIO_FUNC20_OUT_SEL_S 0 /** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) #define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC20_OUT_INV_SEL_S 9 /** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. */ #define GPIO_FUNC20_OE_SEL (BIT(10)) #define GPIO_FUNC20_OE_SEL_M (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S) #define GPIO_FUNC20_OE_SEL_V 0x00000001U #define GPIO_FUNC20_OE_SEL_S 10 /** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC20_OE_INV_SEL (BIT(11)) #define GPIO_FUNC20_OE_INV_SEL_M (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S) @@ -7281,21 +7209,20 @@ extern "C" { /** GPIO_FUNC21_OUT_SEL_CFG_REG register * Configuration register for GPIO21 output */ -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28) /** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO21.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO21. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC21_OUT_SEL 0x000001FFU @@ -7303,27 +7230,27 @@ extern "C" { #define GPIO_FUNC21_OUT_SEL_V 0x000001FFU #define GPIO_FUNC21_OUT_SEL_S 0 /** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) #define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC21_OUT_INV_SEL_S 9 /** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. */ #define GPIO_FUNC21_OE_SEL (BIT(10)) #define GPIO_FUNC21_OE_SEL_M (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S) #define GPIO_FUNC21_OE_SEL_V 0x00000001U #define GPIO_FUNC21_OE_SEL_S 10 /** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC21_OE_INV_SEL (BIT(11)) #define GPIO_FUNC21_OE_INV_SEL_M (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S) @@ -7333,21 +7260,20 @@ extern "C" { /** GPIO_FUNC22_OUT_SEL_CFG_REG register * Configuration register for GPIO22 output */ -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c) /** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO22.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO22. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC22_OUT_SEL 0x000001FFU @@ -7355,27 +7281,27 @@ extern "C" { #define GPIO_FUNC22_OUT_SEL_V 0x000001FFU #define GPIO_FUNC22_OUT_SEL_S 0 /** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) #define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC22_OUT_INV_SEL_S 9 /** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. */ #define GPIO_FUNC22_OE_SEL (BIT(10)) #define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S) #define GPIO_FUNC22_OE_SEL_V 0x00000001U #define GPIO_FUNC22_OE_SEL_S 10 /** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC22_OE_INV_SEL (BIT(11)) #define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S) @@ -7385,21 +7311,20 @@ extern "C" { /** GPIO_FUNC23_OUT_SEL_CFG_REG register * Configuration register for GPIO23 output */ -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30) /** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO23.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO23. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC23_OUT_SEL 0x000001FFU @@ -7407,27 +7332,27 @@ extern "C" { #define GPIO_FUNC23_OUT_SEL_V 0x000001FFU #define GPIO_FUNC23_OUT_SEL_S 0 /** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) #define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC23_OUT_INV_SEL_S 9 /** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. */ #define GPIO_FUNC23_OE_SEL (BIT(10)) #define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S) #define GPIO_FUNC23_OE_SEL_V 0x00000001U #define GPIO_FUNC23_OE_SEL_S 10 /** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC23_OE_INV_SEL (BIT(11)) #define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S) @@ -7437,21 +7362,20 @@ extern "C" { /** GPIO_FUNC24_OUT_SEL_CFG_REG register * Configuration register for GPIO24 output */ -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34) /** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO24.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO24. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC24_OUT_SEL 0x000001FFU @@ -7459,27 +7383,27 @@ extern "C" { #define GPIO_FUNC24_OUT_SEL_V 0x000001FFU #define GPIO_FUNC24_OUT_SEL_S 0 /** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) #define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC24_OUT_INV_SEL_S 9 /** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. */ #define GPIO_FUNC24_OE_SEL (BIT(10)) #define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S) #define GPIO_FUNC24_OE_SEL_V 0x00000001U #define GPIO_FUNC24_OE_SEL_S 10 /** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC24_OE_INV_SEL (BIT(11)) #define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S) @@ -7489,21 +7413,20 @@ extern "C" { /** GPIO_FUNC25_OUT_SEL_CFG_REG register * Configuration register for GPIO25 output */ -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28) +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb38) /** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO25.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO25. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 25 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC25_OUT_SEL 0x000001FFU @@ -7511,27 +7434,27 @@ extern "C" { #define GPIO_FUNC25_OUT_SEL_V 0x000001FFU #define GPIO_FUNC25_OUT_SEL_S 0 /** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) #define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC25_OUT_INV_SEL_S 9 /** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 25 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 25 of GPIO_ENABLE_REG. */ #define GPIO_FUNC25_OE_SEL (BIT(10)) #define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S) #define GPIO_FUNC25_OE_SEL_V 0x00000001U #define GPIO_FUNC25_OE_SEL_S 10 /** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC25_OE_INV_SEL (BIT(11)) #define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S) @@ -7541,21 +7464,20 @@ extern "C" { /** GPIO_FUNC26_OUT_SEL_CFG_REG register * Configuration register for GPIO26 output */ -#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c) +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb3c) /** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO26.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO26. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 26 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC26_OUT_SEL 0x000001FFU @@ -7563,27 +7485,27 @@ extern "C" { #define GPIO_FUNC26_OUT_SEL_V 0x000001FFU #define GPIO_FUNC26_OUT_SEL_S 0 /** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) #define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC26_OUT_INV_SEL_S 9 /** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 26 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 26 of GPIO_ENABLE_REG. */ #define GPIO_FUNC26_OE_SEL (BIT(10)) #define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S) #define GPIO_FUNC26_OE_SEL_V 0x00000001U #define GPIO_FUNC26_OE_SEL_S 10 /** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC26_OE_INV_SEL (BIT(11)) #define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S) @@ -7593,21 +7515,20 @@ extern "C" { /** GPIO_FUNC27_OUT_SEL_CFG_REG register * Configuration register for GPIO27 output */ -#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30) +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb40) /** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO27.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO27. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 27 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC27_OUT_SEL 0x000001FFU @@ -7615,27 +7536,27 @@ extern "C" { #define GPIO_FUNC27_OUT_SEL_V 0x000001FFU #define GPIO_FUNC27_OUT_SEL_S 0 /** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) #define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC27_OUT_INV_SEL_S 9 /** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 27 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 27 of GPIO_ENABLE_REG. */ #define GPIO_FUNC27_OE_SEL (BIT(10)) #define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S) #define GPIO_FUNC27_OE_SEL_V 0x00000001U #define GPIO_FUNC27_OE_SEL_S 10 /** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC27_OE_INV_SEL (BIT(11)) #define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S) @@ -7645,21 +7566,20 @@ extern "C" { /** GPIO_FUNC28_OUT_SEL_CFG_REG register * Configuration register for GPIO28 output */ -#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34) +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb44) /** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO28.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIO28. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit 28 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value * and output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ #define GPIO_FUNC28_OUT_SEL 0x000001FFU @@ -7667,249 +7587,41 @@ extern "C" { #define GPIO_FUNC28_OUT_SEL_V 0x000001FFU #define GPIO_FUNC28_OUT_SEL_S 0 /** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) #define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC28_OUT_INV_SEL_S 9 /** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 28 of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit 28 of GPIO_ENABLE_REG. */ #define GPIO_FUNC28_OE_SEL (BIT(10)) #define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S) #define GPIO_FUNC28_OE_SEL_V 0x00000001U #define GPIO_FUNC28_OE_SEL_S 10 /** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ #define GPIO_FUNC28_OE_INV_SEL (BIT(11)) #define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S) #define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U #define GPIO_FUNC28_OE_INV_SEL_S 11 -/** GPIO_FUNC29_OUT_SEL_CFG_REG register - * Configuration register for GPIO$n output - */ -#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb38) -/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ -#define GPIO_FUNC29_OUT_SEL 0x000001FFU -#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) -#define GPIO_FUNC29_OUT_SEL_V 0x000001FFU -#define GPIO_FUNC29_OUT_SEL_S 0 -/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) -#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) -#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OUT_INV_SEL_S 9 -/** GPIO_FUNC29_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ -#define GPIO_FUNC29_OE_SEL (BIT(10)) -#define GPIO_FUNC29_OE_SEL_M (GPIO_FUNC29_OE_SEL_V << GPIO_FUNC29_OE_SEL_S) -#define GPIO_FUNC29_OE_SEL_V 0x00000001U -#define GPIO_FUNC29_OE_SEL_S 10 -/** GPIO_FUNC29_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC29_OE_INV_SEL (BIT(11)) -#define GPIO_FUNC29_OE_INV_SEL_M (GPIO_FUNC29_OE_INV_SEL_V << GPIO_FUNC29_OE_INV_SEL_S) -#define GPIO_FUNC29_OE_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OE_INV_SEL_S 11 - -/** GPIO_FUNC30_OUT_SEL_CFG_REG register - * Configuration register for GPIO$n output - */ -#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb3c) -/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ -#define GPIO_FUNC30_OUT_SEL 0x000001FFU -#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) -#define GPIO_FUNC30_OUT_SEL_V 0x000001FFU -#define GPIO_FUNC30_OUT_SEL_S 0 -/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) -#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) -#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_OUT_INV_SEL_S 9 -/** GPIO_FUNC30_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ -#define GPIO_FUNC30_OE_SEL (BIT(10)) -#define GPIO_FUNC30_OE_SEL_M (GPIO_FUNC30_OE_SEL_V << GPIO_FUNC30_OE_SEL_S) -#define GPIO_FUNC30_OE_SEL_V 0x00000001U -#define GPIO_FUNC30_OE_SEL_S 10 -/** GPIO_FUNC30_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC30_OE_INV_SEL (BIT(11)) -#define GPIO_FUNC30_OE_INV_SEL_M (GPIO_FUNC30_OE_INV_SEL_V << GPIO_FUNC30_OE_INV_SEL_S) -#define GPIO_FUNC30_OE_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_OE_INV_SEL_S 11 - -/** GPIO_FUNC31_OUT_SEL_CFG_REG register - * Configuration register for GPIO$n output - */ -#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb40) -/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ -#define GPIO_FUNC31_OUT_SEL 0x000001FFU -#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) -#define GPIO_FUNC31_OUT_SEL_V 0x000001FFU -#define GPIO_FUNC31_OUT_SEL_S 0 -/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) -#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) -#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_OUT_INV_SEL_S 9 -/** GPIO_FUNC31_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ -#define GPIO_FUNC31_OE_SEL (BIT(10)) -#define GPIO_FUNC31_OE_SEL_M (GPIO_FUNC31_OE_SEL_V << GPIO_FUNC31_OE_SEL_S) -#define GPIO_FUNC31_OE_SEL_V 0x00000001U -#define GPIO_FUNC31_OE_SEL_S 10 -/** GPIO_FUNC31_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC31_OE_INV_SEL (BIT(11)) -#define GPIO_FUNC31_OE_INV_SEL_M (GPIO_FUNC31_OE_INV_SEL_V << GPIO_FUNC31_OE_INV_SEL_S) -#define GPIO_FUNC31_OE_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_OE_INV_SEL_S 11 - -/** GPIO_FUNC32_OUT_SEL_CFG_REG register - * Configuration register for GPIO$n output - */ -#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb44) -/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ -#define GPIO_FUNC32_OUT_SEL 0x000001FFU -#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) -#define GPIO_FUNC32_OUT_SEL_V 0x000001FFU -#define GPIO_FUNC32_OUT_SEL_S 0 -/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) -#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) -#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_OUT_INV_SEL_S 9 -/** GPIO_FUNC32_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ -#define GPIO_FUNC32_OE_SEL (BIT(10)) -#define GPIO_FUNC32_OE_SEL_M (GPIO_FUNC32_OE_SEL_V << GPIO_FUNC32_OE_SEL_S) -#define GPIO_FUNC32_OE_SEL_V 0x00000001U -#define GPIO_FUNC32_OE_SEL_S 10 -/** GPIO_FUNC32_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define GPIO_FUNC32_OE_INV_SEL (BIT(11)) -#define GPIO_FUNC32_OE_INV_SEL_M (GPIO_FUNC32_OE_INV_SEL_V << GPIO_FUNC32_OE_INV_SEL_S) -#define GPIO_FUNC32_OE_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_OE_INV_SEL_S 11 - /** GPIO_CLOCK_GATE_REG register * GPIO clock gate register */ #define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8) /** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * Configures whether or not to enable clock gate. + * 0: Not enable + * 1: Enable, the clock is free running. */ #define GPIO_CLK_EN (BIT(0)) #define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) @@ -7920,8 +7632,8 @@ extern "C" { * GPIO version register */ #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc) -/** GPIO_DATE : R/W; bitpos: [27:0]; default: 36774208; - * Version control register. \\ +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37815040; + * Version control register. */ #define GPIO_DATE 0x0FFFFFFFU #define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) diff --git a/components/soc/esp32c5/register/soc/gpio_struct.h b/components/soc/esp32c5/register/soc/gpio_struct.h index 87e5a170a9..1d8ac31ee6 100644 --- a/components/soc/esp32c5/register/soc/gpio_struct.h +++ b/components/soc/esp32c5/register/soc/gpio_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +17,8 @@ extern "C" { typedef union { struct { /** strapping : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. + * Represents the values of GPIO strapping pins. (need update the description, for + * example) * * - bit0: invalid * - bit1: MTMS @@ -39,9 +40,11 @@ typedef union { typedef union { struct { /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0; - * Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ + * Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 + * respectively. Bitxx ~ bitxx is invalid. */ uint32_t out_data_orig:32; }; @@ -54,11 +57,11 @@ typedef union { typedef union { struct { /** out_w1ts : WT; bitpos: [31:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO31.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ + * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ GPIO31. + * 0: Not set + * 1: The corresponding bit in GPIO_OUT_REG will be set to 1 + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_OUT_REG. */ uint32_t out_w1ts:32; }; @@ -72,82 +75,17 @@ typedef union { struct { /** out_w1tc : WT; bitpos: [31:0]; default: 0; * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO31 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + * GPIO31 output. + * 0: Not clear + * 1: The corresponding bit in GPIO_OUT_REG will be cleared. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_OUT_REG. */ uint32_t out_w1tc:32; }; uint32_t val; } gpio_out_w1tc_reg_t; -/** Type of enable register - * GPIO output enable register - */ -typedef union { - struct { - /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO31.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t enable_data:32; - }; - uint32_t val; -} gpio_enable_reg_t; - -/** Type of enable_w1ts register - * GPIO output enable set register - */ -typedef union { - struct { - /** enable_w1ts : WT; bitpos: [31:0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO31.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ - */ - uint32_t enable_w1ts:32; - }; - uint32_t val; -} gpio_enable_w1ts_reg_t; - -/** Type of enable_w1tc register - * GPIO output enable clear register - */ -typedef union { - struct { - /** enable_w1tc : WT; bitpos: [31:0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO31. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ - */ - uint32_t enable_w1tc:32; - }; - uint32_t val; -} gpio_enable_w1tc_reg_t; - -/** Type of in register - * GPIO input register - */ -typedef union { - struct { - /** in_data_next : RO; bitpos: [31:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ - */ - uint32_t in_data_next:32; - }; - uint32_t val; -} gpio_in_reg_t; - - /** Group: configuration register */ /** Type of out1 register * GPIO output register for GPIO32-32 @@ -155,9 +93,11 @@ typedef union { typedef union { struct { /** out1_data_orig : R/W/SC/WTC; bitpos: [0]; default: 0; - * Configures the output value of GPIO32 ~ 32 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ + * Configures the output value of GPIO32 ~ 32 output in simple GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit32 ~ bit32 correspond to the output value of GPIO32 ~ GPIO32 + * respectively. Bitxx ~ bitxx is invalid. */ uint32_t out1_data_orig:1; uint32_t reserved_1:31; @@ -172,10 +112,11 @@ typedef union { struct { /** out1_w1ts : WT; bitpos: [0]; default: 0; * Configures whether or not to set the output register GPIO_OUT1_REG of GPIO32 ~ - * GPIO32.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_OUT1_REG. \\ + * GPIO32. + * 0: Not set + * 1: The corresponding bit in GPIO_OUT1_REG will be set to 1 + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_OUT1_REG. */ uint32_t out1_w1ts:1; uint32_t reserved_1:31; @@ -190,10 +131,11 @@ typedef union { struct { /** out1_w1tc : WT; bitpos: [0]; default: 0; * Configures whether or not to clear the output register GPIO_OUT1_REG of GPIO32 ~ - * GPIO32 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Recommended operation: use this register to clear GPIO_OUT1_REG. \\ + * GPIO32 output. + * 0: Not clear + * 1: The corresponding bit in GPIO_OUT1_REG will be cleared. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_OUT1_REG. */ uint32_t out1_w1tc:1; uint32_t reserved_1:31; @@ -201,15 +143,68 @@ typedef union { uint32_t val; } gpio_out1_w1tc_reg_t; +/** Type of enable register + * GPIO output enable register + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; + * Configures whether or not to enable the output of GPIO0 ~ GPIO31. + * 0: Not enable + * 1: Enable + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + */ + uint32_t enable_data:32; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * Configures whether or not to set the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO31. + * 0: Not set + * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1 + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_ENABLE_REG. + */ + uint32_t enable_w1ts:32; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of + * GPIO0 ~ GPIO31. + * 0: Not clear + * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_ENABLE_REG. + */ + uint32_t enable_w1tc:32; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + /** Type of enable1 register * GPIO output enable register for GPIO32-32 */ typedef union { struct { /** enable1_data : R/W/WTC; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO32 ~ GPIO32.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Configures whether or not to enable the output of GPIO32 ~ GPIO32. + * 0: Not enable + * 1: Enable + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. */ uint32_t enable1_data:1; uint32_t reserved_1:31; @@ -223,11 +218,12 @@ typedef union { typedef union { struct { /** enable1_w1ts : WT; bitpos: [0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO32 ~ GPIO32.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Recommended operation: use this register to set GPIO_ENABLE1_REG.\\ + * Configures whether or not to set the output enable register GPIO_ENABLE1_REG of + * GPIO32 ~ GPIO32. + * 0: Not set + * 1: The corresponding bit in GPIO_ENABLE1_REG will be set to 1 + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set GPIO_ENABLE1_REG. */ uint32_t enable1_w1ts:1; uint32_t reserved_1:31; @@ -241,11 +237,12 @@ typedef union { typedef union { struct { /** enable1_w1tc : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO32 ~ GPIO32. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Recommended operation: use this register to clear GPIO_ENABLE1_REG.\\ + * Configures whether or not to clear the output enable register GPIO_ENABLE1_REG of + * GPIO32 ~ GPIO32. + * 0: Not clear + * 1: The corresponding bit in GPIO_ENABLE1_REG will be cleared + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear GPIO_ENABLE1_REG. */ uint32_t enable1_w1tc:1; uint32_t reserved_1:31; @@ -253,6 +250,22 @@ typedef union { uint32_t val; } gpio_enable1_w1tc_reg_t; +/** Type of in register + * GPIO input register + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input value: + * 0: Low level + * 1: High level + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. + */ + uint32_t in_data_next:32; + }; + uint32_t val; +} gpio_in_reg_t; + /** Type of in1 register * GPIO input register for GPIO32-32 */ @@ -260,9 +273,10 @@ typedef union { struct { /** in1_data_next : RO; bitpos: [0]; default: 0; * Represents the input value of GPIO32 ~ GPIO32. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ + * value: + * 0: Low level + * 1: High level + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. */ uint32_t in1_data_next:1; uint32_t reserved_1:31; @@ -270,125 +284,6 @@ typedef union { uint32_t val; } gpio_in1_reg_t; -/** Type of status1 register - * GPIO interrupt status register for GPIO32-32 - */ -typedef union { - struct { - /** status1_interrupt : R/W/WTC; bitpos: [0]; default: 0; - * The interrupt status of GPIO32 ~ GPIO32, can be configured by the software. - * - * - Each bit represents the status of its corresponding GPIO: - * - * - 0: Represents the GPIO does not generate the interrupt configured by - * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. - * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, - * or this bit is configured to 1 by the software. - * - */ - uint32_t status1_interrupt:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_status1_reg_t; - -/** Type of status1_w1ts register - * GPIO interrupt status set register for GPIO32-32 - */ -typedef union { - struct { - /** status1_w1ts : WT; bitpos: [0]; default: 0; - * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO32 ~ GPIO32. - * - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. - */ - uint32_t status1_w1ts:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_status1_w1ts_reg_t; - -/** Type of status1_w1tc register - * GPIO interrupt status clear register for GPIO32-32 - */ -typedef union { - struct { - /** status1_w1tc : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO32 ~ GPIO32. - * - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. - */ - uint32_t status1_w1tc:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_status1_w1tc_reg_t; - -/** Type of procpu_int register - * GPIO_PROCPU_INT interrupt status register for GPIO0-31 - */ -typedef union { - struct { - /** procpu_int : RO; bitpos: [31:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO31. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert - * (high) enable signal (bit13 of GPIO_PIN$n_REG). \\ - */ - uint32_t procpu_int:32; - }; - uint32_t val; -} gpio_procpu_int_reg_t; - -/** Type of procpu_int1 register - * GPIO_PROCPU_INT interrupt status register for GPIO32-32 - */ -typedef union { - struct { - /** procpu_int1 : RO; bitpos: [0]; default: 0; - * Represents the CPU interrupt status of GPIO32 ~ GPIO32. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert - * (high) enable signal (bit13 of GPIO_PIN$n_REG). \\ - */ - uint32_t procpu_int1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_procpu_int1_reg_t; - -/** Type of status_next1 register - * GPIO interrupt source register for GPIO32-32 - */ -typedef union { - struct { - /** status_interrupt_next1 : RO; bitpos: [0]; default: 0; - * Represents the interrupt source signal of GPIO32 ~ GPIO32.\\ - * Each bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ - */ - uint32_t status_interrupt_next1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_status_next1_reg_t; - - /** Group: Interrupt Status Registers */ /** Type of status register * GPIO interrupt status register @@ -398,6 +293,7 @@ typedef union { /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0; * The interrupt status of GPIO0 ~ GPIO31, can be configured by the software. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - Each bit represents the status of its corresponding GPIO: * * - 0: Represents the GPIO does not generate the interrupt configured by @@ -420,6 +316,7 @@ typedef union { * Configures whether or not to set the interrupt status register * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this * register to set GPIO_STATUS_INTERRUPT. @@ -438,6 +335,7 @@ typedef union { * Configures whether or not to clear the interrupt status register * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31. * + * - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. * - If the value 1 is written to a bit here, the corresponding bit in * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this * register to clear GPIO_STATUS_INTERRUPT. @@ -447,24 +345,193 @@ typedef union { uint32_t val; } gpio_status_w1tc_reg_t; +/** Type of status1 register + * GPIO interrupt status register for GPIO32-32 + */ +typedef union { + struct { + /** status1_interrupt : R/W/WTC; bitpos: [0]; default: 0; + * The interrupt status of GPIO32 ~ GPIO32, can be configured by the software. + * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * - Each bit represents the status of its corresponding GPIO: + * + * - 0: Represents the GPIO does not generate the interrupt configured by + * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, + * or this bit is configured to 1 by the software. + * + */ + uint32_t status1_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_status1_reg_t; + +/** Type of status1_w1ts register + * GPIO interrupt status set register for GPIO32-32 + */ +typedef union { + struct { + /** status1_w1ts : WT; bitpos: [0]; default: 0; + * Configures whether or not to set the interrupt status register + * GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO32. + * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS1_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set GPIO_STATUS1_INTERRUPT. + */ + uint32_t status1_w1ts:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_status1_w1ts_reg_t; + +/** Type of status1_w1tc register + * GPIO interrupt status clear register for GPIO32-32 + */ +typedef union { + struct { + /** status1_w1tc : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear the interrupt status register + * GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO32. + * + * - Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * GPIO_STATUS1_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear GPIO_STATUS1_INTERRUPT. + */ + uint32_t status1_w1tc:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_status1_w1tc_reg_t; + +/** Type of procpu_int register + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * Represents the GPIO_PROCPU_INT interrupt status of GPIO0 ~ GPIO31. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not + * generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_PROCPU_INT interrupt is enabled. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ + uint32_t procpu_int:32; + }; + uint32_t val; +} gpio_procpu_int_reg_t; + +/** Type of sdio_int register + * GPIO_SDIO_INT interrupt status register + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * Represents the GPIO_SDIO_INT interrupt status of GPIO0 ~ GPIO31. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_SDIO_INT interrupt is not enabled, or the GPIO does not generate + * the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_SDIO_INT interrupt is enabled. + * Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_sdio_int_reg_t; + +/** Type of procpu_int1 register + * GPIO_PROCPU_INT interrupt status register for GPIO32-32 + */ +typedef union { + struct { + /** procpu_int1 : RO; bitpos: [0]; default: 0; + * Represents the GPIO_PROCPU_INT interrupt status of GPIO32 ~ GPIO32. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_PROCPU_INT interrupt is not enabled, or the GPIO does not + * generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_PROCPU_INT interrupt is enabled. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ + uint32_t procpu_int1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_procpu_int1_reg_t; + +/** Type of sdio_int1 register + * GPIO_SDIO_INT interrupt status register + */ +typedef union { + struct { + /** sdio_int1 : RO; bitpos: [0]; default: 0; + * Represents the GPIO_SDIO_INT interrupt status of GPIO32 ~ GPIO32. Each bit + * represents:(need update in different project) + * 0: Represents GPIO_SDIO_INT interrupt is not enabled, or the GPIO does not generate + * the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE + * after the GPIO_SDIO_INT interrupt is enabled. + * Bit32 ~ bit32 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. This + * interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) + * enable signal (bit13 of GPIO_PIN$n_REG). + */ + uint32_t sdio_int1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_sdio_int1_reg_t; + /** Type of status_next register * GPIO interrupt source register */ typedef union { struct { /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO31.\\ - * Each bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ + * Represents the interrupt source signal of GPIO0 ~ GPIO31. + * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. Each + * bit represents: + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE. * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ + * sensitive interrupt and any edge interrupt. */ uint32_t status_interrupt_next:32; }; uint32_t val; } gpio_status_next_reg_t; +/** Type of status_next1 register + * GPIO interrupt source register for GPIO32-32 + */ +typedef union { + struct { + /** status_interrupt_next1 : RO; bitpos: [0]; default: 0; + * Represents the interrupt source signal of GPIO32 ~ GPIO32. + * Bit0 ~ bit24 are corresponding to GPIO32 ~ GPIO32. Bitxx ~ bitxx is invalid. Each + * bit represents: + * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE. + * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE. + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt. + */ + uint32_t status_interrupt_next1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_status_next1_reg_t; /** Group: Pin Configuration Registers */ /** Type of pinn register @@ -474,54 +541,60 @@ typedef union { struct { /** sync2_bypass : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ uint32_t sync2_bypass:2; /** pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output */ uint32_t pad_driver:1; /** sync1_bypass : R/W; bitpos: [4:3]; default: 0; * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge */ uint32_t sync1_bypass:2; uint32_t reserved_5:2; /** int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * Configures GPIO interrupt type. + * 0: GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger */ uint32_t int_type:3; /** wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * Configures whether or not to enable GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. */ uint32_t wakeup_enable:1; uint32_t reserved_11:2; /** int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. + * Configures whether or not to enable gpio_procpu_int or gpio_sdio_int(need update in + * different project). * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * - bit13: Configures whether or not to enable gpio_procpu_int(need update in + * different project): + * 0: Disable + * 1: Enable + * - bit15: Configures whether or not to enable gpio_sdio_int(need update in different + * project): + * 0: Disable + * 1: Enable + * - bit16 ~ bit17: invalid */ uint32_t int_ena:5; uint32_t reserved_18:14; @@ -529,254 +602,6 @@ typedef union { uint32_t val; } gpio_pinn_reg_t; -/** Type of pin29 register - * GPIO29 configuration register - */ -typedef union { - struct { - /** pin29_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin29_sync2_bypass:2; - /** pin29_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ - uint32_t pin29_pad_driver:1; - /** pin29_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin29_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin29_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ - uint32_t pin29_int_type:3; - /** pin29_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ - uint32_t pin29_wakeup_enable:1; - uint32_t reserved_11:2; - /** pin29_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ - uint32_t pin29_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin29_reg_t; - -/** Type of pin30 register - * GPIO30 configuration register - */ -typedef union { - struct { - /** pin30_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin30_sync2_bypass:2; - /** pin30_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ - uint32_t pin30_pad_driver:1; - /** pin30_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin30_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin30_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ - uint32_t pin30_int_type:3; - /** pin30_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ - uint32_t pin30_wakeup_enable:1; - uint32_t reserved_11:2; - /** pin30_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ - uint32_t pin30_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin30_reg_t; - -/** Type of pin31 register - * GPIO31 configuration register - */ -typedef union { - struct { - /** pin31_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin31_sync2_bypass:2; - /** pin31_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ - uint32_t pin31_pad_driver:1; - /** pin31_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin31_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin31_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ - uint32_t pin31_int_type:3; - /** pin31_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ - uint32_t pin31_wakeup_enable:1; - uint32_t reserved_11:2; - /** pin31_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ - uint32_t pin31_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin31_reg_t; - -/** Type of pin32 register - * GPIO32 configuration register - */ -typedef union { - struct { - /** pin32_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin32_sync2_bypass:2; - /** pin32_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ - */ - uint32_t pin32_pad_driver:1; - /** pin32_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ - uint32_t pin32_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin32_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ - */ - uint32_t pin32_int_type:3; - /** pin32_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ - */ - uint32_t pin32_wakeup_enable:1; - uint32_t reserved_11:2; - /** pin32_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt or CPU non-maskable interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid - */ - uint32_t pin32_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin32_reg_t; - /** Group: Input Configuration Registers */ /** Type of funcn_in_sel_cfg register @@ -785,28 +610,28 @@ typedef union { typedef union { struct { /** in_sel : R/W; bitpos: [6:0]; default: 96; - * Configures to select a pin from the 29 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 27: Select GPIO27\\ - * 28: Select GPIO28\\ - * Or\\ - * 0x40: A constantly high input\\ - * 0x60: A constantly low input\\ + * Configures to select a pin from the 29 GPIO pins to connect the input signal f. + * 0: Select GPIO0 + * 1: Select GPIO1 + * ...... + * 27: Select GPIO27 + * 28: Select GPIO28 + * Or + * 0x40: A constantly high input + * 0x60: A constantly low input */ uint32_t in_sel:7; /** in_inv_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the input value. + * 0: Not invert + * 1: Invert */ uint32_t in_inv_sel:1; /** sig_in_sel : R/W; bitpos: [8]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ + * Configures whether or not to route signals via GPIO matrix. * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + * IO MUX. + * 1: Route signals via GPIO matrix. */ uint32_t sig_in_sel:1; uint32_t reserved_9:23; @@ -824,37 +649,36 @@ typedef union { struct { /** out_sel : R/W/SC; bitpos: [8:0]; default: 256; * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIOn.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ + * output from GPIOn. + * 0: Select signal 0 + * 1: Select signal 1 + * ...... + * 254: Select signal 254 + * 255: Select signal 255 + * Or * 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and * output enable. * - * For the detailed signal list, see Table link. + * For the detailed signal list, see Table . * " */ uint32_t out_sel:9; /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert */ uint32_t out_inv_sel:1; /** oen_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\ + * Configures to select the source of output enable signal. + * 0: Use output enable signal from peripheral. + * 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. */ uint32_t oen_sel:1; - /** oen_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + /** oe_inv_sel : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert */ uint32_t oen_inv_sel:1; uint32_t reserved_12:20; @@ -862,186 +686,6 @@ typedef union { uint32_t val; } gpio_func_out_sel_cfg_reg_t; -/** Type of func29_out_sel_cfg register - * Configuration register for GPIO$n output - */ -typedef union { - struct { - /** func29_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ - uint32_t func29_out_sel:9; - /** func29_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func29_out_inv_sel:1; - /** func29_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ - uint32_t func29_oe_sel:1; - /** func29_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func29_oe_inv_sel:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} gpio_func29_out_sel_cfg_reg_t; - -/** Type of func30_out_sel_cfg register - * Configuration register for GPIO$n output - */ -typedef union { - struct { - /** func30_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ - uint32_t func30_out_sel:9; - /** func30_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func30_out_inv_sel:1; - /** func30_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ - uint32_t func30_oe_sel:1; - /** func30_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func30_oe_inv_sel:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} gpio_func30_out_sel_cfg_reg_t; - -/** Type of func31_out_sel_cfg register - * Configuration register for GPIO$n output - */ -typedef union { - struct { - /** func31_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ - uint32_t func31_out_sel:9; - /** func31_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func31_out_inv_sel:1; - /** func31_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ - uint32_t func31_oe_sel:1; - /** func31_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func31_oe_inv_sel:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} gpio_func31_out_sel_cfg_reg_t; - -/** Type of func32_out_sel_cfg register - * Configuration register for GPIO$n output - */ -typedef union { - struct { - /** func32_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO$n.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " - */ - uint32_t func32_out_sel:9; - /** func32_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func32_out_inv_sel:1; - /** func32_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\ - */ - uint32_t func32_oe_sel:1; - /** func32_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t func32_oe_inv_sel:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} gpio_func32_out_sel_cfg_reg_t; - /** Group: Clock Gate Register */ /** Type of clock_gate register @@ -1050,9 +694,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * Configures whether or not to enable clock gate. + * 0: Not enable + * 1: Enable, the clock is free running. */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -1067,8 +711,8 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774208; - * Version control register. \\ + /** date : R/W; bitpos: [27:0]; default: 37815040; + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -1104,27 +748,29 @@ typedef struct { volatile gpio_status1_w1tc_reg_t status1_w1tc; uint32_t reserved_08c[6]; volatile gpio_procpu_int_reg_t pcpu_int; + volatile gpio_sdio_int_reg_t sdio_int; volatile gpio_procpu_int1_reg_t pcpu_int1; - uint32_t reserved_0ac[2]; + volatile gpio_sdio_int1_reg_t sdio_int1; + uint32_t reserved_0b4[4]; volatile gpio_status_next_reg_t status_next; volatile gpio_status_next1_reg_t status_next1; - uint32_t reserved_0bc[2]; + uint32_t reserved_0cc[2]; volatile gpio_pinn_reg_t pin[29]; - volatile gpio_pin29_reg_t pin29; - volatile gpio_pin30_reg_t pin30; - volatile gpio_pin31_reg_t pin31; - volatile gpio_pin32_reg_t pin32; - uint32_t reserved_148[95]; + volatile gpio_pinn_reg_t pin29; + volatile gpio_pinn_reg_t pin30; + volatile gpio_pinn_reg_t pin31; + volatile gpio_pinn_reg_t pin32; + uint32_t reserved_158[95]; volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* 1-5, 18-26, 36-40, 44-45, 67-69, 71-73, 93-96, 117-255 are reserved * The length ought to match the SIG_GPIO_OUT_IDX that defined in `gpio_sig_map.h` */ - uint32_t reserved_48d[256]; + uint32_t reserved_49d[256]; volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[29]; - volatile gpio_func29_out_sel_cfg_reg_t func29_out_sel_cfg; - volatile gpio_func30_out_sel_cfg_reg_t func30_out_sel_cfg; - volatile gpio_func31_out_sel_cfg_reg_t func31_out_sel_cfg; - volatile gpio_func32_out_sel_cfg_reg_t func32_out_sel_cfg; - uint32_t reserved_b48[172]; + volatile gpio_func_out_sel_cfg_reg_t func29_out_sel_cfg; + volatile gpio_func_out_sel_cfg_reg_t func30_out_sel_cfg; + volatile gpio_func_out_sel_cfg_reg_t func31_out_sel_cfg; + volatile gpio_func_out_sel_cfg_reg_t func32_out_sel_cfg; + uint32_t reserved_b58[168]; volatile gpio_clock_gate_reg_t clock_gate; volatile gpio_date_reg_t date; } gpio_dev_t; diff --git a/components/soc/esp32c5/register/soc/io_mux_reg.h b/components/soc/esp32c5/register/soc/io_mux_reg.h index 150fddf5d5..0576291a35 100644 --- a/components/soc/esp32c5/register/soc/io_mux_reg.h +++ b/components/soc/esp32c5/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -143,7 +143,7 @@ extern "C" { #define EXT_OSC_SLOW_GPIO_NUM 0 -#define MAX_RTC_GPIO_NUM 7 +#define MAX_RTC_GPIO_NUM 6 #define MAX_PAD_GPIO_NUM 28 #define MAX_GPIO_NUM 32 #define DIG_IO_HOLD_BIT_SHIFT 32 @@ -160,11 +160,13 @@ extern "C" { #define FUNC_XTAL_32K_N_GPIO1 1 #define FUNC_XTAL_32K_N_GPIO1_0 0 +// Strapping: Boot Mode select #define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x8) #define FUNC_MTMS_FSPIQ 2 #define FUNC_MTMS_GPIO2 1 #define FUNC_MTMS_MTMS 0 +// Strapping: Boot Mode select/sdio_out_strap #define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0xC) #define FUNC_MTDI_GPIO3 1 #define FUNC_MTDI_MTDI 0 @@ -187,7 +189,7 @@ extern "C" { #define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) #define FUNC_GPIO7_FSPID 2 #define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_GPIO7_0 0 +#define FUNC_GPIO7_SDIO_DATA1 0 #define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) #define FUNC_GPIO8_GPIO8 1 @@ -200,7 +202,7 @@ extern "C" { #define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x28) #define FUNC_GPIO10_FSPICS0 2 #define FUNC_GPIO10_GPIO10 1 -#define FUNC_GPIO10_GPIO10_0 0 +#define FUNC_GPIO10_SDIO_CMD 0 #define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C) #define FUNC_U0TXD_GPIO11 1 @@ -212,11 +214,11 @@ extern "C" { #define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) #define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_GPIO13_0 0 +#define FUNC_GPIO13_SDIO_DATA3 0 #define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38) #define FUNC_GPIO14_GPIO14 1 -#define FUNC_GPIO14_GPIO14_0 0 +#define FUNC_GPIO14_SDIO_DATA2 0 #define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x3C) #define FUNC_SPICS1_GPIO15 1 @@ -258,22 +260,39 @@ extern "C" { #define FUNC_GPIO24_GPIO24 1 #define FUNC_GPIO24_GPIO24_0 0 +// Strapping: sdio_in_strap #define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x64) #define FUNC_GPIO25_GPIO25 1 #define FUNC_GPIO25_GPIO25_0 0 +// Strapping: Boot Mode select (analog mode) #define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x68) #define FUNC_GPIO26_GPIO26 1 #define FUNC_GPIO26_GPIO26_0 0 +// Strapping: Boot Mode select #define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x6C) #define FUNC_GPIO27_GPIO27 1 #define FUNC_GPIO27_GPIO27_0 0 +// Strapping: Boot Mode select #define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x70) #define FUNC_GPIO28_GPIO28 1 #define FUNC_GPIO28_GPIO28_0 0 +/** + * Strapping Info: + * + * GPIO28,GPIO27,GPIO3,GPIO2,GPIO26: + * 1XXXX: SPI Boot mode + * 01XXX: Download mode by UART0/USB + * 00XX0: Download mode by UART0/SDIO + * 00101: Diag mode0 + * 00111: Test mode (GPIO25,should be 1 in mbist mode) + * 00001: analog mode + * 00011: Diag mode1 + */ + /** IO_MUX_DATE_REG register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_gpio_reg.h b/components/soc/esp32c5/register/soc/lp_gpio_reg.h index c12e4b8871..94be70b34f 100644 --- a/components/soc/esp32c5/register/soc/lp_gpio_reg.h +++ b/components/soc/esp32c5/register/soc/lp_gpio_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,257 +12,182 @@ extern "C" { #endif /** LP_GPIO_OUT_REG register - * LP GPIO output register + * GPIO output register for GPIO0-6 */ #define LP_GPIO_OUT_REG (DR_REG_LP_GPIO_BASE + 0x4) -/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures the output of GPIO0 ~ GPIO7.\\ - * 0: Low level\\ - * 1: High level\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ +/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO output register for GPIO0-6 */ -#define LP_GPIO_OUT_DATA_ORIG 0x000000FFU +#define LP_GPIO_OUT_DATA_ORIG 0x0000007FU #define LP_GPIO_OUT_DATA_ORIG_M (LP_GPIO_OUT_DATA_ORIG_V << LP_GPIO_OUT_DATA_ORIG_S) -#define LP_GPIO_OUT_DATA_ORIG_V 0x000000FFU +#define LP_GPIO_OUT_DATA_ORIG_V 0x0000007FU #define LP_GPIO_OUT_DATA_ORIG_S 0 /** LP_GPIO_OUT_W1TS_REG register - * LP GPIO output set register + * GPIO output set register for GPIO0-6 */ #define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x8) -/** LP_GPIO_OUT_W1TS : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~ - * GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG - * will be set to 1. - * - Recommended operation: use this register to set LP_IO_OUT_REG. +/** LP_GPIO_OUT_W1TS : WT; bitpos: [6:0]; default: 0; + * GPIO output set register for GPIO0-6 */ -#define LP_GPIO_OUT_W1TS 0x000000FFU +#define LP_GPIO_OUT_W1TS 0x0000007FU #define LP_GPIO_OUT_W1TS_M (LP_GPIO_OUT_W1TS_V << LP_GPIO_OUT_W1TS_S) -#define LP_GPIO_OUT_W1TS_V 0x000000FFU +#define LP_GPIO_OUT_W1TS_V 0x0000007FU #define LP_GPIO_OUT_W1TS_S 0 /** LP_GPIO_OUT_W1TC_REG register - * LP GPIO output clear register + * GPIO output clear register for GPIO0-6 */ #define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_GPIO_BASE + 0xc) -/** LP_GPIO_OUT_W1TC : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~ - * GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG - * will be cleared. - * - Recommended operation: use this register to clear LP_IO_OUT_REG. +/** LP_GPIO_OUT_W1TC : WT; bitpos: [6:0]; default: 0; + * GPIO output clear register for GPIO0-6 */ -#define LP_GPIO_OUT_W1TC 0x000000FFU +#define LP_GPIO_OUT_W1TC 0x0000007FU #define LP_GPIO_OUT_W1TC_M (LP_GPIO_OUT_W1TC_V << LP_GPIO_OUT_W1TC_S) -#define LP_GPIO_OUT_W1TC_V 0x000000FFU +#define LP_GPIO_OUT_W1TC_V 0x0000007FU #define LP_GPIO_OUT_W1TC_S 0 /** LP_GPIO_ENABLE_REG register - * LP GPIO output enable register + * GPIO output enable register for GPIO0-6 */ #define LP_GPIO_ENABLE_REG (DR_REG_LP_GPIO_BASE + 0x10) -/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\ - * 0: Not enable\\ - * 1: Enable\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ +/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO output enable register for GPIO0-6 */ -#define LP_GPIO_ENABLE_DATA 0x000000FFU +#define LP_GPIO_ENABLE_DATA 0x0000007FU #define LP_GPIO_ENABLE_DATA_M (LP_GPIO_ENABLE_DATA_V << LP_GPIO_ENABLE_DATA_S) -#define LP_GPIO_ENABLE_DATA_V 0x000000FFU +#define LP_GPIO_ENABLE_DATA_V 0x0000007FU #define LP_GPIO_ENABLE_DATA_S 0 /** LP_GPIO_ENABLE_W1TS_REG register - * LP GPIO output enable set register + * GPIO output enable set register for GPIO0-6 */ #define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x14) -/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to set the output enable register LP_IO_ENABLE_REG of - * GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_ENABLE_REG will be set to 1. - * - Recommended operation: use this register to set LP_IO_ENABLE_REG. +/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [6:0]; default: 0; + * GPIO output enable set register for GPIO0-6 */ -#define LP_GPIO_ENABLE_W1TS 0x000000FFU +#define LP_GPIO_ENABLE_W1TS 0x0000007FU #define LP_GPIO_ENABLE_W1TS_M (LP_GPIO_ENABLE_W1TS_V << LP_GPIO_ENABLE_W1TS_S) -#define LP_GPIO_ENABLE_W1TS_V 0x000000FFU +#define LP_GPIO_ENABLE_W1TS_V 0x0000007FU #define LP_GPIO_ENABLE_W1TS_S 0 /** LP_GPIO_ENABLE_W1TC_REG register - * LP GPIO output enable clear register + * GPIO output enable clear register for GPIO0-6 */ #define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x18) -/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of - * GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_ENABLE_REG will be cleared. - * - Recommended operation: use this register to clear LP_IO_ENABLE_REG. +/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [6:0]; default: 0; + * GPIO output enable clear register for GPIO0-6 */ -#define LP_GPIO_ENABLE_W1TC 0x000000FFU +#define LP_GPIO_ENABLE_W1TC 0x0000007FU #define LP_GPIO_ENABLE_W1TC_M (LP_GPIO_ENABLE_W1TC_V << LP_GPIO_ENABLE_W1TC_S) -#define LP_GPIO_ENABLE_W1TC_V 0x000000FFU +#define LP_GPIO_ENABLE_W1TC_V 0x0000007FU #define LP_GPIO_ENABLE_W1TC_S 0 /** LP_GPIO_IN_REG register - * LP GPIO input register + * GPIO input register for GPIO0-6 */ #define LP_GPIO_IN_REG (DR_REG_LP_GPIO_BASE + 0x1c) -/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO7.\\ - * 0: Low level input\\ - * 1: High level input\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ +/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [6:0]; default: 0; + * GPIO input register for GPIO0-6 */ -#define LP_GPIO_IN_DATA_NEXT 0x000000FFU +#define LP_GPIO_IN_DATA_NEXT 0x0000007FU #define LP_GPIO_IN_DATA_NEXT_M (LP_GPIO_IN_DATA_NEXT_V << LP_GPIO_IN_DATA_NEXT_S) -#define LP_GPIO_IN_DATA_NEXT_V 0x000000FFU +#define LP_GPIO_IN_DATA_NEXT_V 0x0000007FU #define LP_GPIO_IN_DATA_NEXT_S 0 /** LP_GPIO_STATUS_REG register - * LP GPIO interrupt status register + * GPIO interrupt status register for GPIO0-6 */ #define LP_GPIO_STATUS_REG (DR_REG_LP_GPIO_BASE + 0x20) -/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures the interrupt status of GPIO0 ~ GPIO7.\\ - * 0: No interrupt\\ - * 1: Interrupt is triggered\\ - * Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This - * register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\ +/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO interrupt status register for GPIO0-6 */ -#define LP_GPIO_STATUS_INTERRUPT 0x000000FFU +#define LP_GPIO_STATUS_INTERRUPT 0x0000007FU #define LP_GPIO_STATUS_INTERRUPT_M (LP_GPIO_STATUS_INTERRUPT_V << LP_GPIO_STATUS_INTERRUPT_S) -#define LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU +#define LP_GPIO_STATUS_INTERRUPT_V 0x0000007FU #define LP_GPIO_STATUS_INTERRUPT_S 0 /** LP_GPIO_STATUS_W1TS_REG register - * LP GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-6 */ #define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x24) -/** LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of - * GPIO0 ~ GPIO7.\\ - * - * - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_STATUS_INT will be set to 1. - * - Recommended operation: use this register to set LP_IO_STATUS_INT. +/** LP_GPIO_STATUS_W1TS : WT; bitpos: [6:0]; default: 0; + * GPIO interrupt status set register for GPIO0-6 */ -#define LP_GPIO_STATUS_W1TS 0x000000FFU +#define LP_GPIO_STATUS_W1TS 0x0000007FU #define LP_GPIO_STATUS_W1TS_M (LP_GPIO_STATUS_W1TS_V << LP_GPIO_STATUS_W1TS_S) -#define LP_GPIO_STATUS_W1TS_V 0x000000FFU +#define LP_GPIO_STATUS_W1TS_V 0x0000007FU #define LP_GPIO_STATUS_W1TS_S 0 /** LP_GPIO_STATUS_W1TC_REG register - * LP GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-6 */ #define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x28) -/** LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT - * of GPIO0 ~ GPIO7. \\ - * - * - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_STATUS_INT will be cleared - * - ecommended operation: use this register to clear LP_IO_STATUS_INT. +/** LP_GPIO_STATUS_W1TC : WT; bitpos: [6:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-6 */ -#define LP_GPIO_STATUS_W1TC 0x000000FFU +#define LP_GPIO_STATUS_W1TC 0x0000007FU #define LP_GPIO_STATUS_W1TC_M (LP_GPIO_STATUS_W1TC_V << LP_GPIO_STATUS_W1TC_S) -#define LP_GPIO_STATUS_W1TC_V 0x000000FFU +#define LP_GPIO_STATUS_W1TC_V 0x0000007FU #define LP_GPIO_STATUS_W1TC_S 0 /** LP_GPIO_STATUS_NEXT_REG register - * LP GPIO interrupt source register + * GPIO interrupt source register for GPIO0-6 */ #define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_GPIO_BASE + 0x2c) -/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0; - * Represents the interrupt source status of GPIO0 ~ GPIO7.\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\ - * 0: Interrupt source status is invalid.\\ - * 1: Interrupt source status is valid.\\ - * The interrupt here can be rising-edge triggered, falling-edge triggered, any edge - * triggered, or level triggered.\\ +/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [6:0]; default: 0; + * GPIO interrupt source register for GPIO0-6 */ -#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x000000FFU +#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x0000007FU #define LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_STATUS_INTERRUPT_NEXT_S) -#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x000000FFU +#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x0000007FU #define LP_GPIO_STATUS_INTERRUPT_NEXT_S 0 /** LP_GPIO_PIN0_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN0_REG (DR_REG_LP_GPIO_BASE + 0x30) /** LP_GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN0_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN0_SYNC2_BYPASS_M (LP_GPIO_PIN0_SYNC2_BYPASS_V << LP_GPIO_PIN0_SYNC2_BYPASS_S) #define LP_GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN0_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO0.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN0_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_PIN0_PAD_DRIVER_S) #define LP_GPIO_PIN0_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN0_PAD_DRIVER_S 2 /** LP_GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN0_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN0_SYNC1_BYPASS_M (LP_GPIO_PIN0_SYNC1_BYPASS_V << LP_GPIO_PIN0_SYNC1_BYPASS_S) #define LP_GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN0_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO0 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN0_INT_TYPE 0x00000007U #define LP_GPIO_PIN0_INT_TYPE_M (LP_GPIO_PIN0_INT_TYPE_V << LP_GPIO_PIN0_INT_TYPE_S) #define LP_GPIO_PIN0_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN0_INT_TYPE_S 7 /** LP_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO0 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_PIN0_WAKEUP_ENABLE_S) @@ -270,71 +195,50 @@ extern "C" { #define LP_GPIO_PIN0_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN1_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN1_REG (DR_REG_LP_GPIO_BASE + 0x34) /** LP_GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN1_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN1_SYNC2_BYPASS_M (LP_GPIO_PIN1_SYNC2_BYPASS_V << LP_GPIO_PIN1_SYNC2_BYPASS_S) #define LP_GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN1_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO1.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN1_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_PIN1_PAD_DRIVER_S) #define LP_GPIO_PIN1_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN1_PAD_DRIVER_S 2 /** LP_GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN1_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN1_SYNC1_BYPASS_M (LP_GPIO_PIN1_SYNC1_BYPASS_V << LP_GPIO_PIN1_SYNC1_BYPASS_S) #define LP_GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN1_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN1_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN1_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO1 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN1_INT_TYPE 0x00000007U #define LP_GPIO_PIN1_INT_TYPE_M (LP_GPIO_PIN1_INT_TYPE_V << LP_GPIO_PIN1_INT_TYPE_S) #define LP_GPIO_PIN1_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN1_INT_TYPE_S 7 /** LP_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO1 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_PIN1_WAKEUP_ENABLE_S) @@ -342,71 +246,50 @@ extern "C" { #define LP_GPIO_PIN1_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN2_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN2_REG (DR_REG_LP_GPIO_BASE + 0x38) /** LP_GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN2_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN2_SYNC2_BYPASS_M (LP_GPIO_PIN2_SYNC2_BYPASS_V << LP_GPIO_PIN2_SYNC2_BYPASS_S) #define LP_GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN2_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO2.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN2_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_PIN2_PAD_DRIVER_S) #define LP_GPIO_PIN2_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN2_PAD_DRIVER_S 2 /** LP_GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN2_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN2_SYNC1_BYPASS_M (LP_GPIO_PIN2_SYNC1_BYPASS_V << LP_GPIO_PIN2_SYNC1_BYPASS_S) #define LP_GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN2_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN2_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN2_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO2 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN2_INT_TYPE 0x00000007U #define LP_GPIO_PIN2_INT_TYPE_M (LP_GPIO_PIN2_INT_TYPE_V << LP_GPIO_PIN2_INT_TYPE_S) #define LP_GPIO_PIN2_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN2_INT_TYPE_S 7 /** LP_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO2 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_PIN2_WAKEUP_ENABLE_S) @@ -414,71 +297,50 @@ extern "C" { #define LP_GPIO_PIN2_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN3_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN3_REG (DR_REG_LP_GPIO_BASE + 0x3c) /** LP_GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN3_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN3_SYNC2_BYPASS_M (LP_GPIO_PIN3_SYNC2_BYPASS_V << LP_GPIO_PIN3_SYNC2_BYPASS_S) #define LP_GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN3_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO3.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN3_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_PIN3_PAD_DRIVER_S) #define LP_GPIO_PIN3_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN3_PAD_DRIVER_S 2 /** LP_GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN3_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN3_SYNC1_BYPASS_M (LP_GPIO_PIN3_SYNC1_BYPASS_V << LP_GPIO_PIN3_SYNC1_BYPASS_S) #define LP_GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN3_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN3_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN3_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO3 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN3_INT_TYPE 0x00000007U #define LP_GPIO_PIN3_INT_TYPE_M (LP_GPIO_PIN3_INT_TYPE_V << LP_GPIO_PIN3_INT_TYPE_S) #define LP_GPIO_PIN3_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN3_INT_TYPE_S 7 /** LP_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO3 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_PIN3_WAKEUP_ENABLE_S) @@ -486,71 +348,50 @@ extern "C" { #define LP_GPIO_PIN3_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN4_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN4_REG (DR_REG_LP_GPIO_BASE + 0x40) /** LP_GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN4_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN4_SYNC2_BYPASS_M (LP_GPIO_PIN4_SYNC2_BYPASS_V << LP_GPIO_PIN4_SYNC2_BYPASS_S) #define LP_GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN4_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO4.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN4_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_PIN4_PAD_DRIVER_S) #define LP_GPIO_PIN4_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN4_PAD_DRIVER_S 2 /** LP_GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN4_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN4_SYNC1_BYPASS_M (LP_GPIO_PIN4_SYNC1_BYPASS_V << LP_GPIO_PIN4_SYNC1_BYPASS_S) #define LP_GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN4_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN4_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN4_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO4 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN4_INT_TYPE 0x00000007U #define LP_GPIO_PIN4_INT_TYPE_M (LP_GPIO_PIN4_INT_TYPE_V << LP_GPIO_PIN4_INT_TYPE_S) #define LP_GPIO_PIN4_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN4_INT_TYPE_S 7 /** LP_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO4 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_PIN4_WAKEUP_ENABLE_S) @@ -558,71 +399,50 @@ extern "C" { #define LP_GPIO_PIN4_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN5_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN5_REG (DR_REG_LP_GPIO_BASE + 0x44) /** LP_GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN5_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN5_SYNC2_BYPASS_M (LP_GPIO_PIN5_SYNC2_BYPASS_V << LP_GPIO_PIN5_SYNC2_BYPASS_S) #define LP_GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN5_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO5.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN5_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_PIN5_PAD_DRIVER_S) #define LP_GPIO_PIN5_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN5_PAD_DRIVER_S 2 /** LP_GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN5_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN5_SYNC1_BYPASS_M (LP_GPIO_PIN5_SYNC1_BYPASS_V << LP_GPIO_PIN5_SYNC1_BYPASS_S) #define LP_GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN5_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN5_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN5_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO5 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN5_INT_TYPE 0x00000007U #define LP_GPIO_PIN5_INT_TYPE_M (LP_GPIO_PIN5_INT_TYPE_V << LP_GPIO_PIN5_INT_TYPE_S) #define LP_GPIO_PIN5_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN5_INT_TYPE_S 7 /** LP_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO5 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_PIN5_WAKEUP_ENABLE_S) @@ -630,166 +450,69 @@ extern "C" { #define LP_GPIO_PIN5_WAKEUP_ENABLE_S 10 /** LP_GPIO_PIN6_REG register - * LP GPIO0 configuration register + * GPIO pin configuration register */ #define LP_GPIO_PIN6_REG (DR_REG_LP_GPIO_BASE + 0x48) /** LP_GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN6_SYNC2_BYPASS 0x00000003U #define LP_GPIO_PIN6_SYNC2_BYPASS_M (LP_GPIO_PIN6_SYNC2_BYPASS_V << LP_GPIO_PIN6_SYNC2_BYPASS_S) #define LP_GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define LP_GPIO_PIN6_SYNC2_BYPASS_S 0 /** LP_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO6.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define LP_GPIO_PIN6_PAD_DRIVER (BIT(2)) #define LP_GPIO_PIN6_PAD_DRIVER_M (LP_GPIO_PIN6_PAD_DRIVER_V << LP_GPIO_PIN6_PAD_DRIVER_S) #define LP_GPIO_PIN6_PAD_DRIVER_V 0x00000001U #define LP_GPIO_PIN6_PAD_DRIVER_S 2 /** LP_GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define LP_GPIO_PIN6_SYNC1_BYPASS 0x00000003U #define LP_GPIO_PIN6_SYNC1_BYPASS_M (LP_GPIO_PIN6_SYNC1_BYPASS_V << LP_GPIO_PIN6_SYNC1_BYPASS_S) #define LP_GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U #define LP_GPIO_PIN6_SYNC1_BYPASS_S 3 /** LP_GPIO_PIN6_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ #define LP_GPIO_PIN6_EDGE_WAKEUP_CLR (BIT(5)) #define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S) #define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V 0x00000001U #define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S 5 /** LP_GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO6 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define LP_GPIO_PIN6_INT_TYPE 0x00000007U #define LP_GPIO_PIN6_INT_TYPE_M (LP_GPIO_PIN6_INT_TYPE_V << LP_GPIO_PIN6_INT_TYPE_S) #define LP_GPIO_PIN6_INT_TYPE_V 0x00000007U #define LP_GPIO_PIN6_INT_TYPE_S 7 /** LP_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO6 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define LP_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) #define LP_GPIO_PIN6_WAKEUP_ENABLE_M (LP_GPIO_PIN6_WAKEUP_ENABLE_V << LP_GPIO_PIN6_WAKEUP_ENABLE_S) #define LP_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U #define LP_GPIO_PIN6_WAKEUP_ENABLE_S 10 -/** LP_GPIO_PIN7_REG register - * LP GPIO0 configuration register - */ -#define LP_GPIO_PIN7_REG (DR_REG_LP_GPIO_BASE + 0x4c) -/** LP_GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define LP_GPIO_PIN7_SYNC2_BYPASS 0x00000003U -#define LP_GPIO_PIN7_SYNC2_BYPASS_M (LP_GPIO_PIN7_SYNC2_BYPASS_V << LP_GPIO_PIN7_SYNC2_BYPASS_S) -#define LP_GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U -#define LP_GPIO_PIN7_SYNC2_BYPASS_S 0 -/** LP_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIO7.\\ - * 0: Normal output\\ - * 1: Open drain output\\ - */ -#define LP_GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define LP_GPIO_PIN7_PAD_DRIVER_M (LP_GPIO_PIN7_PAD_DRIVER_V << LP_GPIO_PIN7_PAD_DRIVER_S) -#define LP_GPIO_PIN7_PAD_DRIVER_V 0x00000001U -#define LP_GPIO_PIN7_PAD_DRIVER_S 2 -/** LP_GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ - */ -#define LP_GPIO_PIN7_SYNC1_BYPASS 0x00000003U -#define LP_GPIO_PIN7_SYNC1_BYPASS_M (LP_GPIO_PIN7_SYNC1_BYPASS_V << LP_GPIO_PIN7_SYNC1_BYPASS_S) -#define LP_GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U -#define LP_GPIO_PIN7_SYNC1_BYPASS_S 3 -/** LP_GPIO_PIN7_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. - */ -#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR (BIT(5)) -#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN7_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN7_EDGE_WAKEUP_CLR_S) -#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_V 0x00000001U -#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_S 5 -/** LP_GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO7 interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ - */ -#define LP_GPIO_PIN7_INT_TYPE 0x00000007U -#define LP_GPIO_PIN7_INT_TYPE_M (LP_GPIO_PIN7_INT_TYPE_V << LP_GPIO_PIN7_INT_TYPE_S) -#define LP_GPIO_PIN7_INT_TYPE_V 0x00000007U -#define LP_GPIO_PIN7_INT_TYPE_S 7 -/** LP_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO7 wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ - */ -#define LP_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define LP_GPIO_PIN7_WAKEUP_ENABLE_M (LP_GPIO_PIN7_WAKEUP_ENABLE_V << LP_GPIO_PIN7_WAKEUP_ENABLE_S) -#define LP_GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U -#define LP_GPIO_PIN7_WAKEUP_ENABLE_S 10 - /** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b0) /** LP_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC0_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_FUNC0_OUT_INV_SEL_S) #define LP_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC0_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC0_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_FUNC0_OE_INV_SEL_S) @@ -797,22 +520,18 @@ extern "C" { #define LP_GPIO_FUNC0_OE_INV_SEL_S 2 /** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b4) /** LP_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC1_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_FUNC1_OUT_INV_SEL_S) #define LP_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC1_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC1_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_FUNC1_OE_INV_SEL_S) @@ -820,22 +539,18 @@ extern "C" { #define LP_GPIO_FUNC1_OE_INV_SEL_S 2 /** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b8) /** LP_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC2_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_FUNC2_OUT_INV_SEL_S) #define LP_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC2_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC2_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_FUNC2_OE_INV_SEL_S) @@ -843,22 +558,18 @@ extern "C" { #define LP_GPIO_FUNC2_OE_INV_SEL_S 2 /** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2bc) /** LP_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC3_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_FUNC3_OUT_INV_SEL_S) #define LP_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC3_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC3_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_FUNC3_OE_INV_SEL_S) @@ -866,22 +577,18 @@ extern "C" { #define LP_GPIO_FUNC3_OE_INV_SEL_S 2 /** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c0) /** LP_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC4_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_FUNC4_OUT_INV_SEL_S) #define LP_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC4_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC4_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_FUNC4_OE_INV_SEL_S) @@ -889,22 +596,18 @@ extern "C" { #define LP_GPIO_FUNC4_OE_INV_SEL_S 2 /** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c4) /** LP_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC5_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_FUNC5_OUT_INV_SEL_S) #define LP_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC5_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC5_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_FUNC5_OE_INV_SEL_S) @@ -912,57 +615,30 @@ extern "C" { #define LP_GPIO_FUNC5_OE_INV_SEL_S 2 /** LP_GPIO_FUNC6_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ #define LP_GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c8) /** LP_GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC6_OUT_INV_SEL (BIT(0)) #define LP_GPIO_FUNC6_OUT_INV_SEL_M (LP_GPIO_FUNC6_OUT_INV_SEL_V << LP_GPIO_FUNC6_OUT_INV_SEL_S) #define LP_GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC6_OUT_INV_SEL_S 0 /** LP_GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define LP_GPIO_FUNC6_OE_INV_SEL (BIT(2)) #define LP_GPIO_FUNC6_OE_INV_SEL_M (LP_GPIO_FUNC6_OE_INV_SEL_V << LP_GPIO_FUNC6_OE_INV_SEL_S) #define LP_GPIO_FUNC6_OE_INV_SEL_V 0x00000001U #define LP_GPIO_FUNC6_OE_INV_SEL_S 2 -/** LP_GPIO_FUNC7_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output - */ -#define LP_GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2cc) -/** LP_GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define LP_GPIO_FUNC7_OUT_INV_SEL (BIT(0)) -#define LP_GPIO_FUNC7_OUT_INV_SEL_M (LP_GPIO_FUNC7_OUT_INV_SEL_V << LP_GPIO_FUNC7_OUT_INV_SEL_S) -#define LP_GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U -#define LP_GPIO_FUNC7_OUT_INV_SEL_S 0 -/** LP_GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ -#define LP_GPIO_FUNC7_OE_INV_SEL (BIT(2)) -#define LP_GPIO_FUNC7_OE_INV_SEL_M (LP_GPIO_FUNC7_OE_INV_SEL_V << LP_GPIO_FUNC7_OE_INV_SEL_S) -#define LP_GPIO_FUNC7_OE_INV_SEL_V 0x00000001U -#define LP_GPIO_FUNC7_OE_INV_SEL_S 2 - /** LP_GPIO_CLOCK_GATE_REG register * GPIO clock gate register */ #define LP_GPIO_CLOCK_GATE_REG (DR_REG_LP_GPIO_BASE + 0x3f8) /** LP_GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate.\\ + * set this bit to enable GPIO clock gate */ #define LP_GPIO_CLK_EN (BIT(0)) #define LP_GPIO_CLK_EN_M (LP_GPIO_CLK_EN_V << LP_GPIO_CLK_EN_S) @@ -973,8 +649,8 @@ extern "C" { * GPIO version register */ #define LP_GPIO_DATE_REG (DR_REG_LP_GPIO_BASE + 0x3fc) -/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 36773904; - * version register.\\ +/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 37814832; + * version register */ #define LP_GPIO_DATE 0x0FFFFFFFU #define LP_GPIO_DATE_M (LP_GPIO_DATE_V << LP_GPIO_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_gpio_struct.h b/components/soc/esp32c5/register/soc/lp_gpio_struct.h index 826a29ef18..5a178a32cc 100644 --- a/components/soc/esp32c5/register/soc/lp_gpio_struct.h +++ b/components/soc/esp32c5/register/soc/lp_gpio_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,266 +12,191 @@ extern "C" { /** Group: configuration register */ /** Type of out register - * LP GPIO output register + * GPIO output register for GPIO0-6 */ typedef union { struct { - /** out_data_orig : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures the output of GPIO0 ~ GPIO7.\\ - * 0: Low level\\ - * 1: High level\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ + /** out_data_orig : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO output register for GPIO0-6 */ - uint32_t out_data_orig:8; - uint32_t reserved_8:24; + uint32_t out_data_orig:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_out_reg_t; /** Type of out_w1ts register - * LP GPIO output set register + * GPIO output set register for GPIO0-6 */ typedef union { struct { - /** out_data_w1ts : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~ - * GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG - * will be set to 1. - * - Recommended operation: use this register to set LP_IO_OUT_REG. + /** out_w1ts : WT; bitpos: [6:0]; default: 0; + * GPIO output set register for GPIO0-6 */ - uint32_t out_data_w1ts:8; - uint32_t reserved_8:24; + uint32_t out_w1ts:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_out_w1ts_reg_t; /** Type of out_w1tc register - * LP GPIO output clear register + * GPIO output clear register for GPIO0-6 */ typedef union { struct { - /** out_data_w1tc : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~ - * GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG - * will be cleared. - * - Recommended operation: use this register to clear LP_IO_OUT_REG. + /** out_w1tc : WT; bitpos: [6:0]; default: 0; + * GPIO output clear register for GPIO0-6 */ - uint32_t out_data_w1tc:8; - uint32_t reserved_8:24; + uint32_t out_w1tc:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_out_w1tc_reg_t; /** Type of enable register - * LP GPIO output enable register + * GPIO output enable register for GPIO0-6 */ typedef union { struct { - /** enable_data : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\ - * 0: Not enable\\ - * 1: Enable\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ + /** enable_data : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO output enable register for GPIO0-6 */ - uint32_t enable_data:8; - uint32_t reserved_8:24; + uint32_t enable_data:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_enable_reg_t; /** Type of enable_w1ts register - * LP GPIO output enable set register + * GPIO output enable set register for GPIO0-6 */ typedef union { struct { - /** out_enable_w1ts : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to set the output enable register LP_IO_ENABLE_REG of - * GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_ENABLE_REG will be set to 1. - * - Recommended operation: use this register to set LP_IO_ENABLE_REG. + /** enable_w1ts : WT; bitpos: [6:0]; default: 0; + * GPIO output enable set register for GPIO0-6 */ - uint32_t out_enable_w1ts:8; - uint32_t reserved_8:24; + uint32_t enable_w1ts:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_enable_w1ts_reg_t; /** Type of enable_w1tc register - * LP GPIO output enable clear register + * GPIO output enable clear register for GPIO0-6 */ typedef union { struct { - /** out_enable_w1tc : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of - * GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_ENABLE_REG will be cleared. - * - Recommended operation: use this register to clear LP_IO_ENABLE_REG. + /** enable_w1tc : WT; bitpos: [6:0]; default: 0; + * GPIO output enable clear register for GPIO0-6 */ - uint32_t out_enable_w1tc:8; - uint32_t reserved_8:24; + uint32_t enable_w1tc:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_enable_w1tc_reg_t; /** Type of in register - * LP GPIO input register + * GPIO input register for GPIO0-6 */ typedef union { struct { - /** in_data_next : RO; bitpos: [7:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO7.\\ - * 0: Low level input\\ - * 1: High level input\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\ + /** in_data_next : RO; bitpos: [6:0]; default: 0; + * GPIO input register for GPIO0-6 */ - uint32_t in_data_next:8; - uint32_t reserved_8:24; + uint32_t in_data_next:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_in_reg_t; /** Type of status register - * LP GPIO interrupt status register + * GPIO interrupt status register for GPIO0-6 */ typedef union { struct { - /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; - * Configures the interrupt status of GPIO0 ~ GPIO7.\\ - * 0: No interrupt\\ - * 1: Interrupt is triggered\\ - * Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This - * register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\ + /** status_interrupt : R/W/WTC; bitpos: [6:0]; default: 0; + * GPIO interrupt status register for GPIO0-6 */ - uint32_t status_interrupt:8; - uint32_t reserved_8:24; + uint32_t status_interrupt:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_status_reg_t; /** Type of status_w1ts register - * LP GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-6 */ typedef union { struct { - /** status_intr_w1ts : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of - * GPIO0 ~ GPIO7.\\ - * - * - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_STATUS_INT will be set to 1. - * - Recommended operation: use this register to set LP_IO_STATUS_INT. + /** status_w1ts : WT; bitpos: [6:0]; default: 0; + * GPIO interrupt status set register for GPIO0-6 */ - uint32_t status_intr_w1ts:8; - uint32_t reserved_8:24; + uint32_t status_w1ts:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_status_w1ts_reg_t; /** Type of status_w1tc register - * LP GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-6 */ typedef union { struct { - /** status_intr_w1tc : WT; bitpos: [7:0]; default: 0; - * Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT - * of GPIO0 ~ GPIO7. \\ - * - * - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. - * - If the value 1 is written to a bit here, the corresponding bit in - * LP_IO_STATUS_INT will be cleared - * - ecommended operation: use this register to clear LP_IO_STATUS_INT. + /** status_w1tc : WT; bitpos: [6:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-6 */ - uint32_t status_intr_w1tc:8; - uint32_t reserved_8:24; + uint32_t status_w1tc:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_status_w1tc_reg_t; /** Type of status_next register - * LP GPIO interrupt source register + * GPIO interrupt source register for GPIO0-6 */ typedef union { struct { - /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; - * Represents the interrupt source status of GPIO0 ~ GPIO7.\\ - * bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\ - * 0: Interrupt source status is invalid.\\ - * 1: Interrupt source status is valid.\\ - * The interrupt here can be rising-edge triggered, falling-edge triggered, any edge - * triggered, or level triggered.\\ + /** status_interrupt_next : RO; bitpos: [6:0]; default: 0; + * GPIO interrupt source register for GPIO0-6 */ - uint32_t status_interrupt_next:8; - uint32_t reserved_8:24; + uint32_t status_interrupt_next:7; + uint32_t reserved_7:25; }; uint32_t val; } lp_gpio_status_next_reg_t; /** Type of pinn register - * LP GPIO0 configuration register + * GPIO pin configuration register */ typedef union { struct { /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync2_bypass:2; /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select the pin dirve mode of GPIOn.\\ - * 0: Normal output\\ - * 1: Open drain output\\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ uint32_t pinn_pad_driver:1; /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of LP IO - * MUX operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync1_bypass:2; /** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\ - * - * - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7. - * - If the value 1 is written to a bit here, the edge wake-up status of corresponding - * GPIO will be cleared. + * GPIO wakeup clear register. */ uint32_t pinn_edge_wakeup_clr:1; uint32_t reserved_6:1; /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIOn interrupt type.\\ - * 0: GPIO interrupt disabled \\ - * 1: Rising edge trigger \\ - * 2: Falling edge trigger \\ - * 3: Any edge trigger \\ - * 4: Low level trigger \\ - * 5: High level trigger \\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ uint32_t pinn_int_type:3; /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIOn wake-up function.\\ - * 0: Not enable\\ - * 1: Enable\\ - * This function is disabled when PD_LP_PERI is powered off.\\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ uint32_t pinn_wakeup_enable:1; uint32_t reserved_11:21; @@ -280,21 +205,17 @@ typedef union { } lp_gpio_pinn_reg_t; /** Type of funcn_out_sel_cfg register - * Configuration register for GPIO0 output + * GPIO output function select register */ typedef union { struct { /** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ uint32_t funcn_out_inv_sel:1; uint32_t reserved_1:1; /** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ uint32_t funcn_oe_inv_sel:1; uint32_t reserved_3:29; @@ -308,7 +229,7 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate.\\ + * set this bit to enable GPIO clock gate */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -321,8 +242,8 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36773904; - * version register.\\ + /** date : R/W; bitpos: [27:0]; default: 37814832; + * version register */ uint32_t date:28; uint32_t reserved_28:4; @@ -344,10 +265,10 @@ typedef struct { volatile lp_gpio_status_w1ts_reg_t status_w1ts; volatile lp_gpio_status_w1tc_reg_t status_w1tc; volatile lp_gpio_status_next_reg_t status_next; - volatile lp_gpio_pinn_reg_t pinn[8]; - uint32_t reserved_050[152]; - volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[8]; - uint32_t reserved_2d0[74]; + volatile lp_gpio_pinn_reg_t pinn[7]; + uint32_t reserved_04c[153]; + volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[7]; + uint32_t reserved_2cc[75]; volatile lp_gpio_clock_gate_reg_t clock_gate; volatile lp_gpio_date_reg_t date; } lp_gpio_dev_t; diff --git a/components/soc/esp32c5/register/soc/lp_iomux_reg.h b/components/soc/esp32c5/register/soc/lp_iomux_reg.h index 6efb6f2c0b..8ca1234433 100644 --- a/components/soc/esp32c5/register/soc/lp_iomux_reg.h +++ b/components/soc/esp32c5/register/soc/lp_iomux_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,136 +16,105 @@ extern "C" { */ #define LP_IO_MUX_GPIO0_REG (DR_REG_LP_IO_MUX_BASE + 0x0) /** LP_IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO0 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO0_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO0_MCU_OE_M (LP_IO_MUX_GPIO0_MCU_OE_V << LP_IO_MUX_GPIO0_MCU_OE_S) #define LP_IO_MUX_GPIO0_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO0_MCU_OE_S 0 /** LP_IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO0.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO0_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO0_SLP_SEL_M (LP_IO_MUX_GPIO0_SLP_SEL_V << LP_IO_MUX_GPIO0_SLP_SEL_S) #define LP_IO_MUX_GPIO0_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO0_SLP_SEL_S 1 /** LP_IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO0 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO0_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO0_MCU_WPD_M (LP_IO_MUX_GPIO0_MCU_WPD_V << LP_IO_MUX_GPIO0_MCU_WPD_S) #define LP_IO_MUX_GPIO0_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO0_MCU_WPD_S 2 /** LP_IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO0 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO0_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO0_MCU_WPU_M (LP_IO_MUX_GPIO0_MCU_WPU_V << LP_IO_MUX_GPIO0_MCU_WPU_S) #define LP_IO_MUX_GPIO0_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO0_MCU_WPU_S 3 /** LP_IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO0 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO0_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO0_MCU_IE_M (LP_IO_MUX_GPIO0_MCU_IE_V << LP_IO_MUX_GPIO0_MCU_IE_S) #define LP_IO_MUX_GPIO0_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO0_MCU_IE_S 4 /** LP_IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO0 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO0_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO0_MCU_DRV_M (LP_IO_MUX_GPIO0_MCU_DRV_V << LP_IO_MUX_GPIO0_MCU_DRV_S) #define LP_IO_MUX_GPIO0_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO0_MCU_DRV_S 5 /** LP_IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO0 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO0_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO0_FUN_WPD_M (LP_IO_MUX_GPIO0_FUN_WPD_V << LP_IO_MUX_GPIO0_FUN_WPD_S) #define LP_IO_MUX_GPIO0_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO0_FUN_WPD_S 7 /** LP_IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO0 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO0_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO0_FUN_WPU_M (LP_IO_MUX_GPIO0_FUN_WPU_V << LP_IO_MUX_GPIO0_FUN_WPU_S) #define LP_IO_MUX_GPIO0_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO0_FUN_WPU_S 8 /** LP_IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO0 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO0_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO0_FUN_IE_M (LP_IO_MUX_GPIO0_FUN_IE_V << LP_IO_MUX_GPIO0_FUN_IE_S) #define LP_IO_MUX_GPIO0_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO0_FUN_IE_S 9 /** LP_IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO0 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO0_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO0_FUN_DRV_M (LP_IO_MUX_GPIO0_FUN_DRV_V << LP_IO_MUX_GPIO0_FUN_DRV_S) #define LP_IO_MUX_GPIO0_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO0_FUN_DRV_S 10 /** LP_IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO0 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO0_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO0_MCU_SEL_M (LP_IO_MUX_GPIO0_MCU_SEL_V << LP_IO_MUX_GPIO0_MCU_SEL_S) #define LP_IO_MUX_GPIO0_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO0_MCU_SEL_S 12 /** LP_IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO0_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO0_FILTER_EN_M (LP_IO_MUX_GPIO0_FILTER_EN_V << LP_IO_MUX_GPIO0_FILTER_EN_S) #define LP_IO_MUX_GPIO0_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO0_FILTER_EN_S 15 /** LP_IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO0_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO0_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO0_HYS_EN_M (LP_IO_MUX_GPIO0_HYS_EN_V << LP_IO_MUX_GPIO0_HYS_EN_S) #define LP_IO_MUX_GPIO0_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO0_HYS_EN_S 16 /** LP_IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO0. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO0_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO0_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO0_HYS_SEL_M (LP_IO_MUX_GPIO0_HYS_SEL_V << LP_IO_MUX_GPIO0_HYS_SEL_S) @@ -153,140 +122,109 @@ extern "C" { #define LP_IO_MUX_GPIO0_HYS_SEL_S 17 /** LP_IO_MUX_GPIO1_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO1 */ #define LP_IO_MUX_GPIO1_REG (DR_REG_LP_IO_MUX_BASE + 0x4) /** LP_IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO1 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO1_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO1_MCU_OE_M (LP_IO_MUX_GPIO1_MCU_OE_V << LP_IO_MUX_GPIO1_MCU_OE_S) #define LP_IO_MUX_GPIO1_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO1_MCU_OE_S 0 /** LP_IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO1.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO1_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO1_SLP_SEL_M (LP_IO_MUX_GPIO1_SLP_SEL_V << LP_IO_MUX_GPIO1_SLP_SEL_S) #define LP_IO_MUX_GPIO1_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO1_SLP_SEL_S 1 /** LP_IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO1 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO1_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO1_MCU_WPD_M (LP_IO_MUX_GPIO1_MCU_WPD_V << LP_IO_MUX_GPIO1_MCU_WPD_S) #define LP_IO_MUX_GPIO1_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO1_MCU_WPD_S 2 /** LP_IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO1 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO1_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO1_MCU_WPU_M (LP_IO_MUX_GPIO1_MCU_WPU_V << LP_IO_MUX_GPIO1_MCU_WPU_S) #define LP_IO_MUX_GPIO1_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO1_MCU_WPU_S 3 /** LP_IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO1 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO1_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO1_MCU_IE_M (LP_IO_MUX_GPIO1_MCU_IE_V << LP_IO_MUX_GPIO1_MCU_IE_S) #define LP_IO_MUX_GPIO1_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO1_MCU_IE_S 4 /** LP_IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO1 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO1_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO1_MCU_DRV_M (LP_IO_MUX_GPIO1_MCU_DRV_V << LP_IO_MUX_GPIO1_MCU_DRV_S) #define LP_IO_MUX_GPIO1_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO1_MCU_DRV_S 5 /** LP_IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO1 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO1_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO1_FUN_WPD_M (LP_IO_MUX_GPIO1_FUN_WPD_V << LP_IO_MUX_GPIO1_FUN_WPD_S) #define LP_IO_MUX_GPIO1_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO1_FUN_WPD_S 7 /** LP_IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO1 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO1_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO1_FUN_WPU_M (LP_IO_MUX_GPIO1_FUN_WPU_V << LP_IO_MUX_GPIO1_FUN_WPU_S) #define LP_IO_MUX_GPIO1_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO1_FUN_WPU_S 8 /** LP_IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO1 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO1_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO1_FUN_IE_M (LP_IO_MUX_GPIO1_FUN_IE_V << LP_IO_MUX_GPIO1_FUN_IE_S) #define LP_IO_MUX_GPIO1_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO1_FUN_IE_S 9 /** LP_IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO1 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO1_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO1_FUN_DRV_M (LP_IO_MUX_GPIO1_FUN_DRV_V << LP_IO_MUX_GPIO1_FUN_DRV_S) #define LP_IO_MUX_GPIO1_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO1_FUN_DRV_S 10 /** LP_IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO1 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO1_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO1_MCU_SEL_M (LP_IO_MUX_GPIO1_MCU_SEL_V << LP_IO_MUX_GPIO1_MCU_SEL_S) #define LP_IO_MUX_GPIO1_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO1_MCU_SEL_S 12 /** LP_IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO1_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO1_FILTER_EN_M (LP_IO_MUX_GPIO1_FILTER_EN_V << LP_IO_MUX_GPIO1_FILTER_EN_S) #define LP_IO_MUX_GPIO1_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO1_FILTER_EN_S 15 /** LP_IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO1_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO1_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO1_HYS_EN_M (LP_IO_MUX_GPIO1_HYS_EN_V << LP_IO_MUX_GPIO1_HYS_EN_S) #define LP_IO_MUX_GPIO1_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO1_HYS_EN_S 16 /** LP_IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO1. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO1_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO1_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO1_HYS_SEL_M (LP_IO_MUX_GPIO1_HYS_SEL_V << LP_IO_MUX_GPIO1_HYS_SEL_S) @@ -294,140 +232,109 @@ extern "C" { #define LP_IO_MUX_GPIO1_HYS_SEL_S 17 /** LP_IO_MUX_GPIO2_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO2 */ #define LP_IO_MUX_GPIO2_REG (DR_REG_LP_IO_MUX_BASE + 0x8) /** LP_IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO2 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO2_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO2_MCU_OE_M (LP_IO_MUX_GPIO2_MCU_OE_V << LP_IO_MUX_GPIO2_MCU_OE_S) #define LP_IO_MUX_GPIO2_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO2_MCU_OE_S 0 /** LP_IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO2.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO2_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO2_SLP_SEL_M (LP_IO_MUX_GPIO2_SLP_SEL_V << LP_IO_MUX_GPIO2_SLP_SEL_S) #define LP_IO_MUX_GPIO2_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO2_SLP_SEL_S 1 /** LP_IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO2 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO2_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO2_MCU_WPD_M (LP_IO_MUX_GPIO2_MCU_WPD_V << LP_IO_MUX_GPIO2_MCU_WPD_S) #define LP_IO_MUX_GPIO2_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO2_MCU_WPD_S 2 /** LP_IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO2 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO2_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO2_MCU_WPU_M (LP_IO_MUX_GPIO2_MCU_WPU_V << LP_IO_MUX_GPIO2_MCU_WPU_S) #define LP_IO_MUX_GPIO2_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO2_MCU_WPU_S 3 /** LP_IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO2 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO2_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO2_MCU_IE_M (LP_IO_MUX_GPIO2_MCU_IE_V << LP_IO_MUX_GPIO2_MCU_IE_S) #define LP_IO_MUX_GPIO2_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO2_MCU_IE_S 4 /** LP_IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO2 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO2_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO2_MCU_DRV_M (LP_IO_MUX_GPIO2_MCU_DRV_V << LP_IO_MUX_GPIO2_MCU_DRV_S) #define LP_IO_MUX_GPIO2_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO2_MCU_DRV_S 5 /** LP_IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO2 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO2_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO2_FUN_WPD_M (LP_IO_MUX_GPIO2_FUN_WPD_V << LP_IO_MUX_GPIO2_FUN_WPD_S) #define LP_IO_MUX_GPIO2_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO2_FUN_WPD_S 7 /** LP_IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO2 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO2_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO2_FUN_WPU_M (LP_IO_MUX_GPIO2_FUN_WPU_V << LP_IO_MUX_GPIO2_FUN_WPU_S) #define LP_IO_MUX_GPIO2_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO2_FUN_WPU_S 8 /** LP_IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO2 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO2_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO2_FUN_IE_M (LP_IO_MUX_GPIO2_FUN_IE_V << LP_IO_MUX_GPIO2_FUN_IE_S) #define LP_IO_MUX_GPIO2_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO2_FUN_IE_S 9 /** LP_IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO2 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO2_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO2_FUN_DRV_M (LP_IO_MUX_GPIO2_FUN_DRV_V << LP_IO_MUX_GPIO2_FUN_DRV_S) #define LP_IO_MUX_GPIO2_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO2_FUN_DRV_S 10 /** LP_IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO2 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO2_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO2_MCU_SEL_M (LP_IO_MUX_GPIO2_MCU_SEL_V << LP_IO_MUX_GPIO2_MCU_SEL_S) #define LP_IO_MUX_GPIO2_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO2_MCU_SEL_S 12 /** LP_IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO2_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO2_FILTER_EN_M (LP_IO_MUX_GPIO2_FILTER_EN_V << LP_IO_MUX_GPIO2_FILTER_EN_S) #define LP_IO_MUX_GPIO2_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO2_FILTER_EN_S 15 /** LP_IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO2_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO2_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO2_HYS_EN_M (LP_IO_MUX_GPIO2_HYS_EN_V << LP_IO_MUX_GPIO2_HYS_EN_S) #define LP_IO_MUX_GPIO2_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO2_HYS_EN_S 16 /** LP_IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO2. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO2_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO2_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO2_HYS_SEL_M (LP_IO_MUX_GPIO2_HYS_SEL_V << LP_IO_MUX_GPIO2_HYS_SEL_S) @@ -435,140 +342,109 @@ extern "C" { #define LP_IO_MUX_GPIO2_HYS_SEL_S 17 /** LP_IO_MUX_GPIO3_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO3 */ #define LP_IO_MUX_GPIO3_REG (DR_REG_LP_IO_MUX_BASE + 0xc) /** LP_IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO3 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO3_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO3_MCU_OE_M (LP_IO_MUX_GPIO3_MCU_OE_V << LP_IO_MUX_GPIO3_MCU_OE_S) #define LP_IO_MUX_GPIO3_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO3_MCU_OE_S 0 /** LP_IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO3.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO3_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO3_SLP_SEL_M (LP_IO_MUX_GPIO3_SLP_SEL_V << LP_IO_MUX_GPIO3_SLP_SEL_S) #define LP_IO_MUX_GPIO3_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO3_SLP_SEL_S 1 /** LP_IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO3 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO3_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO3_MCU_WPD_M (LP_IO_MUX_GPIO3_MCU_WPD_V << LP_IO_MUX_GPIO3_MCU_WPD_S) #define LP_IO_MUX_GPIO3_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO3_MCU_WPD_S 2 /** LP_IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO3 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO3_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO3_MCU_WPU_M (LP_IO_MUX_GPIO3_MCU_WPU_V << LP_IO_MUX_GPIO3_MCU_WPU_S) #define LP_IO_MUX_GPIO3_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO3_MCU_WPU_S 3 /** LP_IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO3 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO3_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO3_MCU_IE_M (LP_IO_MUX_GPIO3_MCU_IE_V << LP_IO_MUX_GPIO3_MCU_IE_S) #define LP_IO_MUX_GPIO3_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO3_MCU_IE_S 4 /** LP_IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO3 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO3_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO3_MCU_DRV_M (LP_IO_MUX_GPIO3_MCU_DRV_V << LP_IO_MUX_GPIO3_MCU_DRV_S) #define LP_IO_MUX_GPIO3_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO3_MCU_DRV_S 5 /** LP_IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO3 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO3_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO3_FUN_WPD_M (LP_IO_MUX_GPIO3_FUN_WPD_V << LP_IO_MUX_GPIO3_FUN_WPD_S) #define LP_IO_MUX_GPIO3_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO3_FUN_WPD_S 7 /** LP_IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO3 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO3_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO3_FUN_WPU_M (LP_IO_MUX_GPIO3_FUN_WPU_V << LP_IO_MUX_GPIO3_FUN_WPU_S) #define LP_IO_MUX_GPIO3_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO3_FUN_WPU_S 8 /** LP_IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO3 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO3_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO3_FUN_IE_M (LP_IO_MUX_GPIO3_FUN_IE_V << LP_IO_MUX_GPIO3_FUN_IE_S) #define LP_IO_MUX_GPIO3_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO3_FUN_IE_S 9 /** LP_IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO3 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO3_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO3_FUN_DRV_M (LP_IO_MUX_GPIO3_FUN_DRV_V << LP_IO_MUX_GPIO3_FUN_DRV_S) #define LP_IO_MUX_GPIO3_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO3_FUN_DRV_S 10 /** LP_IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO3 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO3_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO3_MCU_SEL_M (LP_IO_MUX_GPIO3_MCU_SEL_V << LP_IO_MUX_GPIO3_MCU_SEL_S) #define LP_IO_MUX_GPIO3_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO3_MCU_SEL_S 12 /** LP_IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO3_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO3_FILTER_EN_M (LP_IO_MUX_GPIO3_FILTER_EN_V << LP_IO_MUX_GPIO3_FILTER_EN_S) #define LP_IO_MUX_GPIO3_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO3_FILTER_EN_S 15 /** LP_IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO3_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO3_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO3_HYS_EN_M (LP_IO_MUX_GPIO3_HYS_EN_V << LP_IO_MUX_GPIO3_HYS_EN_S) #define LP_IO_MUX_GPIO3_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO3_HYS_EN_S 16 /** LP_IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO3. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO3_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO3_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO3_HYS_SEL_M (LP_IO_MUX_GPIO3_HYS_SEL_V << LP_IO_MUX_GPIO3_HYS_SEL_S) @@ -576,140 +452,109 @@ extern "C" { #define LP_IO_MUX_GPIO3_HYS_SEL_S 17 /** LP_IO_MUX_GPIO4_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO4 */ #define LP_IO_MUX_GPIO4_REG (DR_REG_LP_IO_MUX_BASE + 0x10) /** LP_IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO4 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO4_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO4_MCU_OE_M (LP_IO_MUX_GPIO4_MCU_OE_V << LP_IO_MUX_GPIO4_MCU_OE_S) #define LP_IO_MUX_GPIO4_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO4_MCU_OE_S 0 /** LP_IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO4.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO4_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO4_SLP_SEL_M (LP_IO_MUX_GPIO4_SLP_SEL_V << LP_IO_MUX_GPIO4_SLP_SEL_S) #define LP_IO_MUX_GPIO4_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO4_SLP_SEL_S 1 /** LP_IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO4 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO4_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO4_MCU_WPD_M (LP_IO_MUX_GPIO4_MCU_WPD_V << LP_IO_MUX_GPIO4_MCU_WPD_S) #define LP_IO_MUX_GPIO4_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO4_MCU_WPD_S 2 /** LP_IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO4 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO4_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO4_MCU_WPU_M (LP_IO_MUX_GPIO4_MCU_WPU_V << LP_IO_MUX_GPIO4_MCU_WPU_S) #define LP_IO_MUX_GPIO4_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO4_MCU_WPU_S 3 /** LP_IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO4 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO4_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO4_MCU_IE_M (LP_IO_MUX_GPIO4_MCU_IE_V << LP_IO_MUX_GPIO4_MCU_IE_S) #define LP_IO_MUX_GPIO4_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO4_MCU_IE_S 4 /** LP_IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO4 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO4_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO4_MCU_DRV_M (LP_IO_MUX_GPIO4_MCU_DRV_V << LP_IO_MUX_GPIO4_MCU_DRV_S) #define LP_IO_MUX_GPIO4_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO4_MCU_DRV_S 5 /** LP_IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO4 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO4_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO4_FUN_WPD_M (LP_IO_MUX_GPIO4_FUN_WPD_V << LP_IO_MUX_GPIO4_FUN_WPD_S) #define LP_IO_MUX_GPIO4_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO4_FUN_WPD_S 7 /** LP_IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO4 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO4_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO4_FUN_WPU_M (LP_IO_MUX_GPIO4_FUN_WPU_V << LP_IO_MUX_GPIO4_FUN_WPU_S) #define LP_IO_MUX_GPIO4_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO4_FUN_WPU_S 8 /** LP_IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO4 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO4_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO4_FUN_IE_M (LP_IO_MUX_GPIO4_FUN_IE_V << LP_IO_MUX_GPIO4_FUN_IE_S) #define LP_IO_MUX_GPIO4_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO4_FUN_IE_S 9 /** LP_IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO4 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO4_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO4_FUN_DRV_M (LP_IO_MUX_GPIO4_FUN_DRV_V << LP_IO_MUX_GPIO4_FUN_DRV_S) #define LP_IO_MUX_GPIO4_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO4_FUN_DRV_S 10 /** LP_IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO4 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO4_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO4_MCU_SEL_M (LP_IO_MUX_GPIO4_MCU_SEL_V << LP_IO_MUX_GPIO4_MCU_SEL_S) #define LP_IO_MUX_GPIO4_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO4_MCU_SEL_S 12 /** LP_IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO4_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO4_FILTER_EN_M (LP_IO_MUX_GPIO4_FILTER_EN_V << LP_IO_MUX_GPIO4_FILTER_EN_S) #define LP_IO_MUX_GPIO4_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO4_FILTER_EN_S 15 /** LP_IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO4_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO4_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO4_HYS_EN_M (LP_IO_MUX_GPIO4_HYS_EN_V << LP_IO_MUX_GPIO4_HYS_EN_S) #define LP_IO_MUX_GPIO4_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO4_HYS_EN_S 16 /** LP_IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO4. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO4_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO4_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO4_HYS_SEL_M (LP_IO_MUX_GPIO4_HYS_SEL_V << LP_IO_MUX_GPIO4_HYS_SEL_S) @@ -717,140 +562,109 @@ extern "C" { #define LP_IO_MUX_GPIO4_HYS_SEL_S 17 /** LP_IO_MUX_GPIO5_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO5 */ #define LP_IO_MUX_GPIO5_REG (DR_REG_LP_IO_MUX_BASE + 0x14) /** LP_IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO5 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO5_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO5_MCU_OE_M (LP_IO_MUX_GPIO5_MCU_OE_V << LP_IO_MUX_GPIO5_MCU_OE_S) #define LP_IO_MUX_GPIO5_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO5_MCU_OE_S 0 /** LP_IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO5.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO5_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO5_SLP_SEL_M (LP_IO_MUX_GPIO5_SLP_SEL_V << LP_IO_MUX_GPIO5_SLP_SEL_S) #define LP_IO_MUX_GPIO5_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO5_SLP_SEL_S 1 /** LP_IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO5 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO5_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO5_MCU_WPD_M (LP_IO_MUX_GPIO5_MCU_WPD_V << LP_IO_MUX_GPIO5_MCU_WPD_S) #define LP_IO_MUX_GPIO5_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO5_MCU_WPD_S 2 /** LP_IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO5 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO5_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO5_MCU_WPU_M (LP_IO_MUX_GPIO5_MCU_WPU_V << LP_IO_MUX_GPIO5_MCU_WPU_S) #define LP_IO_MUX_GPIO5_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO5_MCU_WPU_S 3 /** LP_IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO5 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO5_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO5_MCU_IE_M (LP_IO_MUX_GPIO5_MCU_IE_V << LP_IO_MUX_GPIO5_MCU_IE_S) #define LP_IO_MUX_GPIO5_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO5_MCU_IE_S 4 /** LP_IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO5 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO5_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO5_MCU_DRV_M (LP_IO_MUX_GPIO5_MCU_DRV_V << LP_IO_MUX_GPIO5_MCU_DRV_S) #define LP_IO_MUX_GPIO5_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO5_MCU_DRV_S 5 /** LP_IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO5 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO5_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO5_FUN_WPD_M (LP_IO_MUX_GPIO5_FUN_WPD_V << LP_IO_MUX_GPIO5_FUN_WPD_S) #define LP_IO_MUX_GPIO5_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO5_FUN_WPD_S 7 /** LP_IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO5 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO5_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO5_FUN_WPU_M (LP_IO_MUX_GPIO5_FUN_WPU_V << LP_IO_MUX_GPIO5_FUN_WPU_S) #define LP_IO_MUX_GPIO5_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO5_FUN_WPU_S 8 /** LP_IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO5 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO5_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO5_FUN_IE_M (LP_IO_MUX_GPIO5_FUN_IE_V << LP_IO_MUX_GPIO5_FUN_IE_S) #define LP_IO_MUX_GPIO5_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO5_FUN_IE_S 9 /** LP_IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO5 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO5_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO5_FUN_DRV_M (LP_IO_MUX_GPIO5_FUN_DRV_V << LP_IO_MUX_GPIO5_FUN_DRV_S) #define LP_IO_MUX_GPIO5_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO5_FUN_DRV_S 10 /** LP_IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO5 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO5_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO5_MCU_SEL_M (LP_IO_MUX_GPIO5_MCU_SEL_V << LP_IO_MUX_GPIO5_MCU_SEL_S) #define LP_IO_MUX_GPIO5_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO5_MCU_SEL_S 12 /** LP_IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO5_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO5_FILTER_EN_M (LP_IO_MUX_GPIO5_FILTER_EN_V << LP_IO_MUX_GPIO5_FILTER_EN_S) #define LP_IO_MUX_GPIO5_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO5_FILTER_EN_S 15 /** LP_IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO5_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO5_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO5_HYS_EN_M (LP_IO_MUX_GPIO5_HYS_EN_V << LP_IO_MUX_GPIO5_HYS_EN_S) #define LP_IO_MUX_GPIO5_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO5_HYS_EN_S 16 /** LP_IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO5. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO5_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO5_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO5_HYS_SEL_M (LP_IO_MUX_GPIO5_HYS_SEL_V << LP_IO_MUX_GPIO5_HYS_SEL_S) @@ -858,293 +672,121 @@ extern "C" { #define LP_IO_MUX_GPIO5_HYS_SEL_S 17 /** LP_IO_MUX_GPIO6_REG register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIO6 */ #define LP_IO_MUX_GPIO6_REG (DR_REG_LP_IO_MUX_BASE + 0x18) /** LP_IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO6 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ #define LP_IO_MUX_GPIO6_MCU_OE (BIT(0)) #define LP_IO_MUX_GPIO6_MCU_OE_M (LP_IO_MUX_GPIO6_MCU_OE_V << LP_IO_MUX_GPIO6_MCU_OE_S) #define LP_IO_MUX_GPIO6_MCU_OE_V 0x00000001U #define LP_IO_MUX_GPIO6_MCU_OE_S 0 /** LP_IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO6.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ #define LP_IO_MUX_GPIO6_SLP_SEL (BIT(1)) #define LP_IO_MUX_GPIO6_SLP_SEL_M (LP_IO_MUX_GPIO6_SLP_SEL_V << LP_IO_MUX_GPIO6_SLP_SEL_S) #define LP_IO_MUX_GPIO6_SLP_SEL_V 0x00000001U #define LP_IO_MUX_GPIO6_SLP_SEL_S 1 /** LP_IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO6 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ #define LP_IO_MUX_GPIO6_MCU_WPD (BIT(2)) #define LP_IO_MUX_GPIO6_MCU_WPD_M (LP_IO_MUX_GPIO6_MCU_WPD_V << LP_IO_MUX_GPIO6_MCU_WPD_S) #define LP_IO_MUX_GPIO6_MCU_WPD_V 0x00000001U #define LP_IO_MUX_GPIO6_MCU_WPD_S 2 /** LP_IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO6 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ #define LP_IO_MUX_GPIO6_MCU_WPU (BIT(3)) #define LP_IO_MUX_GPIO6_MCU_WPU_M (LP_IO_MUX_GPIO6_MCU_WPU_V << LP_IO_MUX_GPIO6_MCU_WPU_S) #define LP_IO_MUX_GPIO6_MCU_WPU_V 0x00000001U #define LP_IO_MUX_GPIO6_MCU_WPU_S 3 /** LP_IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO6 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO6_MCU_IE (BIT(4)) #define LP_IO_MUX_GPIO6_MCU_IE_M (LP_IO_MUX_GPIO6_MCU_IE_V << LP_IO_MUX_GPIO6_MCU_IE_S) #define LP_IO_MUX_GPIO6_MCU_IE_V 0x00000001U #define LP_IO_MUX_GPIO6_MCU_IE_S 4 /** LP_IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO6 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ #define LP_IO_MUX_GPIO6_MCU_DRV 0x00000003U #define LP_IO_MUX_GPIO6_MCU_DRV_M (LP_IO_MUX_GPIO6_MCU_DRV_V << LP_IO_MUX_GPIO6_MCU_DRV_S) #define LP_IO_MUX_GPIO6_MCU_DRV_V 0x00000003U #define LP_IO_MUX_GPIO6_MCU_DRV_S 5 /** LP_IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO6 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ #define LP_IO_MUX_GPIO6_FUN_WPD (BIT(7)) #define LP_IO_MUX_GPIO6_FUN_WPD_M (LP_IO_MUX_GPIO6_FUN_WPD_V << LP_IO_MUX_GPIO6_FUN_WPD_S) #define LP_IO_MUX_GPIO6_FUN_WPD_V 0x00000001U #define LP_IO_MUX_GPIO6_FUN_WPD_S 7 /** LP_IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO6 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ #define LP_IO_MUX_GPIO6_FUN_WPU (BIT(8)) #define LP_IO_MUX_GPIO6_FUN_WPU_M (LP_IO_MUX_GPIO6_FUN_WPU_V << LP_IO_MUX_GPIO6_FUN_WPU_S) #define LP_IO_MUX_GPIO6_FUN_WPU_V 0x00000001U #define LP_IO_MUX_GPIO6_FUN_WPU_S 8 /** LP_IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO6 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ #define LP_IO_MUX_GPIO6_FUN_IE (BIT(9)) #define LP_IO_MUX_GPIO6_FUN_IE_M (LP_IO_MUX_GPIO6_FUN_IE_V << LP_IO_MUX_GPIO6_FUN_IE_S) #define LP_IO_MUX_GPIO6_FUN_IE_V 0x00000001U #define LP_IO_MUX_GPIO6_FUN_IE_S 9 /** LP_IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO6 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ #define LP_IO_MUX_GPIO6_FUN_DRV 0x00000003U #define LP_IO_MUX_GPIO6_FUN_DRV_M (LP_IO_MUX_GPIO6_FUN_DRV_V << LP_IO_MUX_GPIO6_FUN_DRV_S) #define LP_IO_MUX_GPIO6_FUN_DRV_V 0x00000003U #define LP_IO_MUX_GPIO6_FUN_DRV_S 10 /** LP_IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO6 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ #define LP_IO_MUX_GPIO6_MCU_SEL 0x00000007U #define LP_IO_MUX_GPIO6_MCU_SEL_M (LP_IO_MUX_GPIO6_MCU_SEL_V << LP_IO_MUX_GPIO6_MCU_SEL_S) #define LP_IO_MUX_GPIO6_MCU_SEL_V 0x00000007U #define LP_IO_MUX_GPIO6_MCU_SEL_S 12 /** LP_IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ #define LP_IO_MUX_GPIO6_FILTER_EN (BIT(15)) #define LP_IO_MUX_GPIO6_FILTER_EN_M (LP_IO_MUX_GPIO6_FILTER_EN_V << LP_IO_MUX_GPIO6_FILTER_EN_S) #define LP_IO_MUX_GPIO6_FILTER_EN_V 0x00000001U #define LP_IO_MUX_GPIO6_FILTER_EN_S 15 /** LP_IO_MUX_GPIO6_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO6_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ #define LP_IO_MUX_GPIO6_HYS_EN (BIT(16)) #define LP_IO_MUX_GPIO6_HYS_EN_M (LP_IO_MUX_GPIO6_HYS_EN_V << LP_IO_MUX_GPIO6_HYS_EN_S) #define LP_IO_MUX_GPIO6_HYS_EN_V 0x00000001U #define LP_IO_MUX_GPIO6_HYS_EN_S 16 /** LP_IO_MUX_GPIO6_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO6. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO6_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ #define LP_IO_MUX_GPIO6_HYS_SEL (BIT(17)) #define LP_IO_MUX_GPIO6_HYS_SEL_M (LP_IO_MUX_GPIO6_HYS_SEL_V << LP_IO_MUX_GPIO6_HYS_SEL_S) #define LP_IO_MUX_GPIO6_HYS_SEL_V 0x00000001U #define LP_IO_MUX_GPIO6_HYS_SEL_S 17 -/** LP_IO_MUX_GPIO7_REG register - * LP_IO_MUX Configure Register for pad GPIO0 - */ -#define LP_IO_MUX_GPIO7_REG (DR_REG_LP_IO_MUX_BASE + 0x1c) -/** LP_IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIO7 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_MCU_OE (BIT(0)) -#define LP_IO_MUX_GPIO7_MCU_OE_M (LP_IO_MUX_GPIO7_MCU_OE_V << LP_IO_MUX_GPIO7_MCU_OE_S) -#define LP_IO_MUX_GPIO7_MCU_OE_V 0x00000001U -#define LP_IO_MUX_GPIO7_MCU_OE_S 0 -/** LP_IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIO7.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_SLP_SEL (BIT(1)) -#define LP_IO_MUX_GPIO7_SLP_SEL_M (LP_IO_MUX_GPIO7_SLP_SEL_V << LP_IO_MUX_GPIO7_SLP_SEL_S) -#define LP_IO_MUX_GPIO7_SLP_SEL_V 0x00000001U -#define LP_IO_MUX_GPIO7_SLP_SEL_S 1 -/** LP_IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO7 during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_MCU_WPD (BIT(2)) -#define LP_IO_MUX_GPIO7_MCU_WPD_M (LP_IO_MUX_GPIO7_MCU_WPD_V << LP_IO_MUX_GPIO7_MCU_WPD_S) -#define LP_IO_MUX_GPIO7_MCU_WPD_V 0x00000001U -#define LP_IO_MUX_GPIO7_MCU_WPD_S 2 -/** LP_IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO7 during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_MCU_WPU (BIT(3)) -#define LP_IO_MUX_GPIO7_MCU_WPU_M (LP_IO_MUX_GPIO7_MCU_WPU_V << LP_IO_MUX_GPIO7_MCU_WPU_S) -#define LP_IO_MUX_GPIO7_MCU_WPU_V 0x00000001U -#define LP_IO_MUX_GPIO7_MCU_WPU_S 3 -/** LP_IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIO7 during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_MCU_IE (BIT(4)) -#define LP_IO_MUX_GPIO7_MCU_IE_M (LP_IO_MUX_GPIO7_MCU_IE_V << LP_IO_MUX_GPIO7_MCU_IE_S) -#define LP_IO_MUX_GPIO7_MCU_IE_V 0x00000001U -#define LP_IO_MUX_GPIO7_MCU_IE_S 4 -/** LP_IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIO7 during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ - */ -#define LP_IO_MUX_GPIO7_MCU_DRV 0x00000003U -#define LP_IO_MUX_GPIO7_MCU_DRV_M (LP_IO_MUX_GPIO7_MCU_DRV_V << LP_IO_MUX_GPIO7_MCU_DRV_S) -#define LP_IO_MUX_GPIO7_MCU_DRV_V 0x00000003U -#define LP_IO_MUX_GPIO7_MCU_DRV_S 5 -/** LP_IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIO7 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_FUN_WPD (BIT(7)) -#define LP_IO_MUX_GPIO7_FUN_WPD_M (LP_IO_MUX_GPIO7_FUN_WPD_V << LP_IO_MUX_GPIO7_FUN_WPD_S) -#define LP_IO_MUX_GPIO7_FUN_WPD_V 0x00000001U -#define LP_IO_MUX_GPIO7_FUN_WPD_S 7 -/** LP_IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIO7 in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_FUN_WPU (BIT(8)) -#define LP_IO_MUX_GPIO7_FUN_WPU_M (LP_IO_MUX_GPIO7_FUN_WPU_V << LP_IO_MUX_GPIO7_FUN_WPU_S) -#define LP_IO_MUX_GPIO7_FUN_WPU_V 0x00000001U -#define LP_IO_MUX_GPIO7_FUN_WPU_S 8 -/** LP_IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIO7 in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_FUN_IE (BIT(9)) -#define LP_IO_MUX_GPIO7_FUN_IE_M (LP_IO_MUX_GPIO7_FUN_IE_V << LP_IO_MUX_GPIO7_FUN_IE_S) -#define LP_IO_MUX_GPIO7_FUN_IE_V 0x00000001U -#define LP_IO_MUX_GPIO7_FUN_IE_S 9 -/** LP_IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIO7 in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ - */ -#define LP_IO_MUX_GPIO7_FUN_DRV 0x00000003U -#define LP_IO_MUX_GPIO7_FUN_DRV_M (LP_IO_MUX_GPIO7_FUN_DRV_V << LP_IO_MUX_GPIO7_FUN_DRV_S) -#define LP_IO_MUX_GPIO7_FUN_DRV_V 0x00000003U -#define LP_IO_MUX_GPIO7_FUN_DRV_S 10 -/** LP_IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIO7 in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ - */ -#define LP_IO_MUX_GPIO7_MCU_SEL 0x00000007U -#define LP_IO_MUX_GPIO7_MCU_SEL_M (LP_IO_MUX_GPIO7_MCU_SEL_V << LP_IO_MUX_GPIO7_MCU_SEL_S) -#define LP_IO_MUX_GPIO7_MCU_SEL_V 0x00000007U -#define LP_IO_MUX_GPIO7_MCU_SEL_S 12 -/** LP_IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_FILTER_EN (BIT(15)) -#define LP_IO_MUX_GPIO7_FILTER_EN_M (LP_IO_MUX_GPIO7_FILTER_EN_V << LP_IO_MUX_GPIO7_FILTER_EN_S) -#define LP_IO_MUX_GPIO7_FILTER_EN_V 0x00000001U -#define LP_IO_MUX_GPIO7_FILTER_EN_S 15 -/** LP_IO_MUX_GPIO7_HYS_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIO7_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ - */ -#define LP_IO_MUX_GPIO7_HYS_EN (BIT(16)) -#define LP_IO_MUX_GPIO7_HYS_EN_M (LP_IO_MUX_GPIO7_HYS_EN_V << LP_IO_MUX_GPIO7_HYS_EN_S) -#define LP_IO_MUX_GPIO7_HYS_EN_V 0x00000001U -#define LP_IO_MUX_GPIO7_HYS_EN_S 16 -/** LP_IO_MUX_GPIO7_HYS_SEL : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIO7. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIO7_HYS_EN\\ - */ -#define LP_IO_MUX_GPIO7_HYS_SEL (BIT(17)) -#define LP_IO_MUX_GPIO7_HYS_SEL_M (LP_IO_MUX_GPIO7_HYS_SEL_V << LP_IO_MUX_GPIO7_HYS_SEL_S) -#define LP_IO_MUX_GPIO7_HYS_SEL_V 0x00000001U -#define LP_IO_MUX_GPIO7_HYS_SEL_S 17 - /** LP_IO_MUX_DATE_REG register * LP_IO_MUX Version Control Register */ #define LP_IO_MUX_DATE_REG (DR_REG_LP_IO_MUX_BASE + 0x1fc) /** LP_IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35721840; - * Version control register. \\ + * Version control register */ #define LP_IO_MUX_REG_DATE 0x0FFFFFFFU #define LP_IO_MUX_REG_DATE_M (LP_IO_MUX_REG_DATE_V << LP_IO_MUX_REG_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_iomux_struct.h b/components/soc/esp32c5/register/soc/lp_iomux_struct.h index c44af7d068..a9279f4ee2 100644 --- a/components/soc/esp32c5/register/soc/lp_iomux_struct.h +++ b/components/soc/esp32c5/register/soc/lp_iomux_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,102 +12,71 @@ extern "C" { /** Group: Configure Registers */ /** Type of gpion register - * LP_IO_MUX Configure Register for pad GPIO0 + * LP_IO_MUX Configure Register for pad GPIOn */ typedef union { struct { /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIOn during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ uint32_t gpion_mcu_oe:1; /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the sleep mode for GPIOn.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ uint32_t gpion_slp_sel:1; /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIOn during sleep - * mode. \\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ uint32_t gpion_mcu_wpd:1; /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIOn during sleep - * mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ uint32_t gpion_mcu_wpu:1; /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIOn during sleep mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ uint32_t gpion_mcu_ie:1; /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIOn during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ uint32_t gpion_mcu_drv:2; /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the pull-down resistor of GPIOn in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ uint32_t gpion_fun_wpd:1; /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the pull-up resistor of GPIOn in normal - * execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ uint32_t gpion_fun_wpu:1; /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the input of GPIOn in normal execution mode.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ uint32_t gpion_fun_ie:1; /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIOn in normal execution mode.\\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ uint32_t gpion_fun_drv:2; /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * Configures to select the LP IO MUX function for GPIOn in normal execution mode.\\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ uint32_t gpion_mcu_sel:3; /** gpion_filter_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ uint32_t gpion_filter_en:1; /** gpion_hys_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIOn_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ uint32_t gpion_hys_en:1; /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIOn. \\ - * 0: Choose the output enable signal of eFuse\\ - * 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ uint32_t gpion_hys_sel:1; uint32_t reserved_18:14; @@ -121,7 +90,7 @@ typedef union { typedef union { struct { /** reg_date : R/W; bitpos: [27:0]; default: 35721840; - * Version control register. \\ + * Version control register */ uint32_t reg_date:28; uint32_t reserved_28:4; @@ -131,8 +100,8 @@ typedef union { typedef struct { - volatile lp_io_mux_gpion_reg_t gpion[8]; - uint32_t reserved_020[119]; + volatile lp_io_mux_gpion_reg_t gpion[7]; + uint32_t reserved_01c[120]; volatile lp_io_mux_date_reg_t date; } lp_io_mux_dev_t; diff --git a/components/soc/esp32c5/rtc_io_periph.c b/components/soc/esp32c5/rtc_io_periph.c index a71b07c127..7a9cd8d407 100644 --- a/components/soc/esp32c5/rtc_io_periph.c +++ b/components/soc/esp32c5/rtc_io_periph.c @@ -14,7 +14,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO4_CHANNEL, //GPIO4 RTCIO_GPIO5_CHANNEL, //GPIO5 RTCIO_GPIO6_CHANNEL, //GPIO6 - RTCIO_GPIO7_CHANNEL, //GPIO7 + -1,//GPIO7 -1,//GPIO8 -1,//GPIO9 -1,//GPIO10 diff --git a/components/ulp/lp_core/lp_core_i2c.c b/components/ulp/lp_core/lp_core_i2c.c index 154af3e38b..7761d8f28b 100644 --- a/components/ulp/lp_core/lp_core_i2c.c +++ b/components/ulp/lp_core/lp_core_i2c.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,8 +7,8 @@ #include "lp_core_i2c.h" #include "esp_check.h" #include "hal/i2c_hal.h" +#include "hal/i2c_ll.h" #include "driver/rtc_io.h" -#include "soc/rtc_io_channel.h" #include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" @@ -32,13 +32,13 @@ static esp_err_t lp_i2c_gpio_is_cfg_valid(gpio_num_t sda_io_num, gpio_num_t scl_ #if !SOC_LP_GPIO_MATRIX_SUPPORTED /* Verify that the SDA and SCL line belong to the LP IO Mux I2C function group */ - if (sda_io_num != RTCIO_GPIO6_CHANNEL) { - ESP_LOGE(LPI2C_TAG, "SDA pin can only be configured as GPIO#6"); + if (sda_io_num != LP_I2C_SDA_IOMUX_PAD) { + ESP_LOGE(LPI2C_TAG, LP_I2C_SDA_PIN_ERR_LOG); return ESP_ERR_INVALID_ARG; } - if (scl_io_num != RTCIO_GPIO7_CHANNEL) { - ESP_LOGE(LPI2C_TAG, "SCL pin can only be configured as GPIO#7"); + if (scl_io_num != LP_I2C_SCL_IOMUX_PAD) { + ESP_LOGE(LPI2C_TAG, LP_I2C_SCL_PIN_ERR_LOG); return ESP_ERR_INVALID_ARG; } #endif /* !SOC_LP_GPIO_MATRIX_SUPPORTED */ diff --git a/docs/en/api-reference/peripherals/gpio/esp32c5.inc b/docs/en/api-reference/peripherals/gpio/esp32c5.inc index fe9a1c554e..bf8de7ff4c 100644 --- a/docs/en/api-reference/peripherals/gpio/esp32c5.inc +++ b/docs/en/api-reference/peripherals/gpio/esp32c5.inc @@ -59,7 +59,7 @@ The table below provides more information on pin usage, and please note the comm * - GPIO7 - - - LP_GPIO7 + - - Strapping pin * - GPIO8 @@ -150,7 +150,7 @@ The table below provides more information on pin usage, and please note the comm * - GPIO25 - - - - + - Strapping pin * - GPIO26 - @@ -169,7 +169,7 @@ The table below provides more information on pin usage, and please note the comm .. note:: - - Strapping pin: GPIO2, GPIO7, GPIO27, and GPIO28 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__. + - Strapping pin: GPIO2, GPIO7, GPIO25, GPIO27, and GPIO28 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__. - SPI0/1: GPIO16 ~ GPIO22 are usually used for SPI flash and PSRAM, they're not recommended for other uses. - USB-JTAG: GPIO13 and GPIO14 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled. diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc index 1676f35b27..433eb247c0 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc @@ -59,7 +59,7 @@ * - GPIO7 - - - LP_GPIO7 + - - Strapping 管脚 * - GPIO8 @@ -150,7 +150,7 @@ * - GPIO25 - - - - + - Strapping 管脚 * - GPIO26 - @@ -169,7 +169,7 @@ .. note:: - - Strapping 管脚：GPIO2、GPIO7、GPIO27 和 GPIO28 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。 + - Strapping 管脚：GPIO2、GPIO7、GPIO25、GPIO27 和 GPIO28 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。 - SPI0/1：GPIO16 ~ GPIO22 通常用于 SPI flash 和 PSRAM，不推荐用于其他用途。 - USB-JTAG：GPIO13 和 GPIO14 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。 diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 347dd2adf4..750feb74fd 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -41,8 +41,8 @@ menu "Example Configuration" depends on !IDF_TARGET_ESP32 default 2 if !IDF_TARGET_ESP32H2 default 10 if IDF_TARGET_ESP32H2 - range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 - range 0 6 if IDF_TARGET_ESP32C61 + range 0 7 if IDF_TARGET_ESP32C6 + range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 7 14 if IDF_TARGET_ESP32H2 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 @@ -117,8 +117,8 @@ menu "Example Configuration" depends on !IDF_TARGET_ESP32 default 4 if !IDF_TARGET_ESP32H2 default 11 if IDF_TARGET_ESP32H2 - range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 - range 0 6 if IDF_TARGET_ESP32C61 + range 0 7 if IDF_TARGET_ESP32C6 + range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 7 14 if IDF_TARGET_ESP32H2 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 @@ -272,10 +272,10 @@ menu "Example Configuration" config EXAMPLE_GPIO_WAKEUP_PIN int "Enable wakeup from GPIO" default 0 - range 0 7 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 - range 0 6 if IDF_TARGET_ESP32C61 + range 0 7 if IDF_TARGET_ESP32C6 + range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 0 15 if IDF_TARGET_ESP32P4 - range 0 5 if !IDF_TARGET_ESP32C6 && !IDF_TARGET_ESP32C5 + range 0 5 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL bool "Enable GPIO high-level wakeup" From 40cc70c325114024c1a464fefe66d261c4b25e45 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 10 Apr 2025 18:33:25 +0800 Subject: [PATCH 2/3] fix(gpio): fix IO22-24 GPIO/IOMUX registers not restored after TOP PD for C61 --- components/soc/esp32c5/system_retention_periph.c | 10 +++++----- components/soc/esp32c61/system_retention_periph.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/components/soc/esp32c5/system_retention_periph.c b/components/soc/esp32c5/system_retention_periph.c index b8c4e1c675..a1b78a03cb 100644 --- a/components/soc/esp32c5/system_retention_periph.c +++ b/components/soc/esp32c5/system_retention_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,17 +49,17 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = { _Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions"); /* IO MUX Registers Context */ -#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_GPIO28 - REG_IO_MUX_BASE) / 4) + 1) -#define N_REGS_IOMUX_1() (((GPIO_FUNC32_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1) +#define N_REGS_IOMUX_0() (SOC_GPIO_PIN_COUNT) +#define N_REGS_IOMUX_1() (SOC_GPIO_PIN_COUNT) #define N_REGS_IOMUX_2() (((GPIO_FUNC116_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1) -#define N_REGS_IOMUX_3() (((GPIO_PIN32_REG - GPIO_PIN0_REG) / 4) + 1) +#define N_REGS_IOMUX_3() (SOC_GPIO_PIN_COUNT) #define GPIO_RETENTION_REGS_CNT 6 #define GPIO_RETENTION_MAP_BASE GPIO_OUT_REG static const uint32_t gpio_regs_map[4] = {0x90009009, 0, 0, 0}; const regdma_entries_config_t iomux_regs_retention[] = { - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), IO_MUX_GPIO0_REG, IO_MUX_GPIO0_REG, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */ [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, diff --git a/components/soc/esp32c61/system_retention_periph.c b/components/soc/esp32c61/system_retention_periph.c index f695bec2ba..d0237b4493 100644 --- a/components/soc/esp32c61/system_retention_periph.c +++ b/components/soc/esp32c61/system_retention_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -45,16 +45,16 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = { _Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions"); /* IO MUX Registers Context */ -#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_SPID - REG_IO_MUX_BASE) / 4) + 1) -#define N_REGS_IOMUX_1() (((GPIO_FUNC21_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1) +#define N_REGS_IOMUX_0() (SOC_GPIO_PIN_COUNT) +#define N_REGS_IOMUX_1() (SOC_GPIO_PIN_COUNT) #define N_REGS_IOMUX_2() (((GPIO_FUNC121_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1) -#define N_REGS_IOMUX_3() (((GPIO_PIN21_REG - GPIO_PIN0_REG) / 4) + 1) +#define N_REGS_IOMUX_3() (SOC_GPIO_PIN_COUNT) #define N_REGS_IOMUX_4() (1) #define N_REGS_IOMUX_5() (1) #define N_REGS_IOMUX_6() (1) const regdma_entries_config_t iomux_regs_retention[] = { - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), IO_MUX_GPIO0_REG, IO_MUX_GPIO0_REG, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */ [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, From 6994be3acdc524bf4112c36a23607eea275f71bb Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 15 Apr 2025 15:10:17 +0800 Subject: [PATCH 3/3] fix(gpio): add some detailed error log for gpio_pullup_en and gpio_pulldown_en --- components/esp_driver_gpio/src/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 6def528987..56a09aad33 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -75,7 +75,7 @@ static gpio_context_t gpio_context = { esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PU)", ESP_ERR_INVALID_ARG); if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -113,7 +113,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error (input-only pad has no internal PD)", ESP_ERR_INVALID_ARG); if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock);