diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 38f5aa2ec9..761f187033 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -94,6 +94,7 @@ menu "Bootloader config" choice BOOTLOADER_VDDSDIO_BOOST bool "VDDSDIO LDO voltage" default BOOTLOADER_VDDSDIO_BOOST_1_9V + depends on SOC_CONFIGURABLE_VDDSDIO_SUPPORTED help If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse or MTDI bootstrapping pin), bootloader will change LDO settings to diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 7f093b2e06..dde67db6a4 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -13,8 +13,9 @@ entries: cpu: esp_cpu_compare_and_set (noflash) esp_memory_utils (noflash) rtc_clk (noflash) - if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645 + if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED: rtc_init:rtc_vddsdio_set_config (noflash) + if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645 rtc_pm (noflash_text) rtc_sleep (noflash_text) rtc_time (noflash_text) diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c index 277b2a0acd..abb5370c67 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_init.c @@ -129,16 +129,6 @@ void rtc_init(rtc_config_t cfg) #endif } -rtc_vddsdio_config_t rtc_vddsdio_get_config(void) -{ - rtc_vddsdio_config_t result = {0}; - return result; -} - -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) -{ -} - static void set_ocode_by_efuse(int ocode_scheme_ver) { assert(ocode_scheme_ver == 1); diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 4692562138..e3f75bb0ff 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -159,43 +159,6 @@ void rtc_init(rtc_config_t cfg) #endif } -rtc_vddsdio_config_t rtc_vddsdio_get_config(void) -{ - rtc_vddsdio_config_t result; - uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG); - result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S; - result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S; - result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S; - if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) { - // Get configuration from RTC - result.force = 1; - result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S; - result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S; - return result; - } else { - result.force = 0; - } - - // Otherwise, VDD_SDIO is controlled by bootstrapping pin - uint32_t strap_reg = REG_READ(GPIO_STRAP_REG); - result.force = 0; - result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V; - result.enable = 1; - return result; -} - -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) -{ - uint32_t val = 0; - val |= (config.force << RTC_CNTL_SDIO_FORCE_S); - val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S); - val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S); - val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S); - val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S); - val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S); - val |= RTC_CNTL_SDIO_PD_EN; - REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); -} static void set_ocode_by_efuse(int calib_version) { diff --git a/components/esp_hw_support/port/esp32h4/rtc_init.c b/components/esp_hw_support/port/esp32h4/rtc_init.c index 04867ab772..40174e3682 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_init.c +++ b/components/esp_hw_support/port/esp32h4/rtc_init.c @@ -174,40 +174,3 @@ void dslp_osc_pd(void){ REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG,RTC_CNTL_RC32K_XPD, 0); REG_SET_FIELD(RTC_CNTL_PLL8M_REG, RTC_CNTL_XPD_PLL8M, 0); } -rtc_vddsdio_config_t rtc_vddsdio_get_config(void) -{ - rtc_vddsdio_config_t result; - uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG); - result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S; - result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S; - result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S; - if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) { - // Get configuration from RTC - result.force = 1; - result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S; - result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S; - return result; - } else { - result.force = 0; - } - - // Otherwise, VDD_SDIO is controlled by bootstrapping pin - uint32_t strap_reg = REG_READ(GPIO_STRAP_REG); - result.force = 0; - result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V; - result.enable = 1; - return result; -} - -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) -{ - uint32_t val = 0; - val |= (config.force << RTC_CNTL_SDIO_FORCE_S); - val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S); - val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S); - val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S); - val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S); - val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S); - val |= RTC_CNTL_SDIO_PD_EN; - REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); -} diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 51b79a8480..b0deb421d2 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -649,12 +649,10 @@ void IRAM_ATTR esp_deep_sleep_start(void) */ #if !CONFIG_IDF_TARGET_ESP32C6 // TODO: WIFI-5150 static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, - uint32_t flash_enable_time_us, - rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline)); + uint32_t flash_enable_time_us) IRAM_ATTR __attribute__((noinline)); static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, - uint32_t flash_enable_time_us, - rtc_vddsdio_config_t vddsdio_config) + uint32_t flash_enable_time_us) { #if CONFIG_IDF_TARGET_ESP32C6 return ESP_ERR_NOT_SUPPORTED; // TODO: WIFI-5150 @@ -662,11 +660,14 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags, // Enter sleep uint32_t reject = esp_sleep_start(pd_flags); +#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED + rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config(); // If VDDSDIO regulator was controlled by RTC registers before sleep, // restore the configuration. if (vddsdio_config.force) { rtc_vddsdio_set_config(vddsdio_config); } +#endif // If SPI flash was powered down, wait for it to become ready if (pd_flags & RTC_SLEEP_PD_VDDSDIO) { @@ -828,8 +829,6 @@ esp_err_t esp_light_sleep_start(void) periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in); - rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config(); - // Safety net: enable WDT in case exit from light sleep fails #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5653 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; @@ -858,7 +857,7 @@ esp_err_t esp_light_sleep_start(void) err = ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION; } else { // Enter sleep, then wait for flash to be ready on wakeup - err = esp_light_sleep_inner(pd_flags, flash_enable_time_us, vddsdio_config); + err = esp_light_sleep_inner(pd_flags, flash_enable_time_us); } // light sleep wakeup flag only makes sense after a successful light sleep diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index eacfc0cc2b..cad3fb2397 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -15,7 +15,8 @@ entries: sleep_modes:esp_sleep_enable_timer_wakeup (noflash) sleep_modes:timer_wakeup_prepare (noflash) sleep_modes:get_power_down_flags (noflash) - rtc_init:rtc_vddsdio_get_config (noflash) + if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED: + rtc_init:rtc_vddsdio_get_config (noflash) esp_clk:esp_clk_slowclk_cal_set (noflash) esp_clk:esp_clk_slowclk_cal_get (noflash) esp_clk:esp_rtc_get_time_us (noflash) diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 2f0f687b25..7d015b5064 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -747,6 +747,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y +config SOC_CONFIGURABLE_VDDSDIO_SUPPORTED + bool + default y + config SOC_CLK_APLL_SUPPORTED bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index cded5d102d..ccabb3b234 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -375,6 +375,8 @@ #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_CONFIGURABLE_VDDSDIO_SUPPORTED (1) + /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_APLL_SUPPORTED (1) // apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h index 2331a29758..b922a3b2eb 100644 --- a/components/soc/esp32c2/include/soc/rtc.h +++ b/components/soc/esp32c2/include/soc/rtc.h @@ -722,37 +722,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -/** - * Structure describing vddsdio configuration - */ -typedef struct { - uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. - uint32_t enable : 1; //!< Enable VDDSDIO regulator - uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V - uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator -} rtc_vddsdio_config_t; - -/** - * Get current VDDSDIO configuration - * If VDDSDIO configuration is overridden by RTC, get values from RTC - * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE - * Otherwise, use default values and the level of MTDI bootstrapping pin. - * @return currently used VDDSDIO configuration - */ -rtc_vddsdio_config_t rtc_vddsdio_get_config(void); - -/** - * Set new VDDSDIO configuration using RTC registers. - * If config.force == 1, this overrides configuration done using bootstrapping - * pins and EFUSE. - * - * @param config new VDDSDIO configuration - */ -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); - - // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- // **WARNING**: The following are only for backwards compatibility. // Please use the declarations in soc/clk_tree_defs.h instead. diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 0e10a3181e..8b56920082 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -764,37 +764,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -/** - * Structure describing vddsdio configuration - */ -typedef struct { - uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. - uint32_t enable : 1; //!< Enable VDDSDIO regulator - uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V - uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator -} rtc_vddsdio_config_t; - -/** - * Get current VDDSDIO configuration - * If VDDSDIO configuration is overridden by RTC, get values from RTC - * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE - * Otherwise, use default values and the level of MTDI bootstrapping pin. - * @return currently used VDDSDIO configuration - */ -rtc_vddsdio_config_t rtc_vddsdio_get_config(void); - -/** - * Set new VDDSDIO configuration using RTC registers. - * If config.force == 1, this overrides configuration done using bootstrapping - * pins and EFUSE. - * - * @param config new VDDSDIO configuration - */ -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); - - // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- // **WARNING**: The following are only for backwards compatibility. // Please use the declarations in soc/clk_tree_defs.h instead. diff --git a/components/soc/esp32c6/include/soc/rtc.h b/components/soc/esp32c6/include/soc/rtc.h index a2bd881c3b..000f15b1e8 100644 --- a/components/soc/esp32c6/include/soc/rtc.h +++ b/components/soc/esp32c6/include/soc/rtc.h @@ -714,37 +714,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -/** - * Structure describing vddsdio configuration - */ -typedef struct { - uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. - uint32_t enable : 1; //!< Enable VDDSDIO regulator - uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V - uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator -} rtc_vddsdio_config_t; - -/** - * Get current VDDSDIO configuration - * If VDDSDIO configuration is overridden by RTC, get values from RTC - * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE - * Otherwise, use default values and the level of MTDI bootstrapping pin. - * @return currently used VDDSDIO configuration - */ -rtc_vddsdio_config_t rtc_vddsdio_get_config(void); - -/** - * Set new VDDSDIO configuration using RTC registers. - * If config.force == 1, this overrides configuration done using bootstrapping - * pins and EFUSE. - * - * @param config new VDDSDIO configuration - */ -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); - - // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- // **WARNING**: The following are only for backwards compatibility. // Please use the declarations in soc/clk_tree_defs.h instead. diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index ebccc6c12a..2c15f6fc14 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -769,37 +769,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -/** - * Structure describing vddsdio configuration - */ -typedef struct { - uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. - uint32_t enable : 1; //!< Enable VDDSDIO regulator - uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V - uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator -} rtc_vddsdio_config_t; - -/** - * Get current VDDSDIO configuration - * If VDDSDIO configuration is overridden by RTC, get values from RTC - * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE - * Otherwise, use default values and the level of MTDI bootstrapping pin. - * @return currently used VDDSDIO configuration - */ -rtc_vddsdio_config_t rtc_vddsdio_get_config(void); - -/** - * Set new VDDSDIO configuration using RTC registers. - * If config.force == 1, this overrides configuration done using bootstrapping - * pins and EFUSE. - * - * @param config new VDDSDIO configuration - */ -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); - - // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- // **WARNING**: The following are only for backwards compatibility. // Please use the declarations in soc/clk_tree_defs.h instead. diff --git a/components/soc/esp32h4/include/soc/rtc.h b/components/soc/esp32h4/include/soc/rtc.h index b21a9931e3..bbdd6397b8 100644 --- a/components/soc/esp32h4/include/soc/rtc.h +++ b/components/soc/esp32h4/include/soc/rtc.h @@ -854,36 +854,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -/** - * Structure describing vddsdio configuration - */ -typedef struct { - uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. - uint32_t enable : 1; //!< Enable VDDSDIO regulator - uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V - uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator - uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator -} rtc_vddsdio_config_t; - -/** - * Get current VDDSDIO configuration - * If VDDSDIO configuration is overridden by RTC, get values from RTC - * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE - * Otherwise, use default values and the level of MTDI bootstrapping pin. - * @return currently used VDDSDIO configuration - */ -rtc_vddsdio_config_t rtc_vddsdio_get_config(void); - -/** - * Set new VDDSDIO configuration using RTC registers. - * If config.force == 1, this overrides configuration done using bootstrapping - * pins and EFUSE. - * - * @param config new VDDSDIO configuration - */ -void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); - /** * Regulator config */ diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 6625c4b502..fc7d0175c0 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -959,6 +959,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y +config SOC_CONFIGURABLE_VDDSDIO_SUPPORTED + bool + default y + config SOC_CLK_APLL_SUPPORTED bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index e3b41a8211..2f89ba8101 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -417,6 +417,8 @@ #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_CONFIGURABLE_VDDSDIO_SUPPORTED (1) + /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_APLL_SUPPORTED (1) // apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index f7efbec865..f145a7e9ec 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -1007,6 +1007,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y +config SOC_CONFIGURABLE_VDDSDIO_SUPPORTED + bool + default y + config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 1bda95f405..a0af8c3e9d 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -413,6 +413,7 @@ #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_CONFIGURABLE_VDDSDIO_SUPPORTED (1) #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!