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feat(gptimer): support timer group driver on c5 mp

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there's no change between mpw and mp as far as I can tell from the
register
This commit is contained in:
morris
2024-03-26 16:13:17 +08:00
parent 19700a57e6
commit a615180bc0
9 changed files with 215 additions and 473 deletions
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components/esp_hw_support/port/esp32c5/rtc_time.c
+2 -1
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@@ -126,7 +126,8 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
}
/* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
// calibration clock source is set by PCR register: PCR_32K_SEL
// REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */