From 6c35ee3fc59a8ea7539be53e411f70fda4cc00b4 Mon Sep 17 00:00:00 2001 From: cje Date: Mon, 15 Aug 2022 19:50:55 +0800 Subject: [PATCH] fix chip broken bug when run in monitor mode of S2 and modify voltage param to fit all sleep mode of S2/C2/C3 --- .../esp_hw_support/port/esp32c2/rtc_sleep.c | 106 ++++++++++---- .../esp_hw_support/port/esp32c3/rtc_sleep.c | 119 +++++++++++----- .../esp_hw_support/port/esp32s2/rtc_sleep.c | 129 ++++++++++++++---- .../esp_hw_support/port/esp32s3/rtc_sleep.c | 56 +++++--- components/soc/esp32c2/include/soc/rtc.h | 30 ++-- components/soc/esp32c3/include/soc/rtc.h | 30 ++-- components/soc/esp32s2/include/soc/rtc.h | 32 +++-- components/soc/esp32s3/include/soc/rtc.h | 17 ++- 8 files changed, 370 insertions(+), 149 deletions(-) diff --git a/components/esp_hw_support/port/esp32c2/rtc_sleep.c b/components/esp_hw_support/port/esp32c2/rtc_sleep.c index 1cb648cf37..325a22699f 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c2/rtc_sleep.c @@ -62,31 +62,81 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .deep_slp_reject = 1, .light_slp_reject = 1, }; - if (sleep_flags & RTC_SLEEP_PD_DIG) { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP : RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + assert(sleep_flags & RTC_SLEEP_PD_XTAL); + if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * dbg_att_slp need to set to 0: rtc voltage is about 0.98v + * support all features: + * - 8MD256 as RTC slow clock src + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + out_config->rtc_dbias_slp = 0; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + /* + * Default mode + * rtc voltage in sleep need stable and not less than 0.7v + * support features: + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7; + } else { + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power): + * not support features: + * - 8MD256 as RTC slow clock src + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = 0; + } } else { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + out_config->rtc_regulator_fpu = 1; + // rtc & digital voltage from high to low + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { + /* + * digital voltage need to be >= 1.1v + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0) + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){ + /* + * dbg_att_slp need to set to 0: digital voltage is about 0.64v & rtc voltage is 0.98v + * Support features: + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = 0; + out_config->rtc_dbias_slp = 0; + } else { + /* + * digital voltage not less than 0.6v. + * not support features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6; + } + } + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } else { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; } } @@ -97,19 +147,19 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) rtc_sleep_pu(pu_cfg); } + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); if (cfg.deep_slp) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -118,9 +168,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index 4cc3465659..97d7c866e3 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -79,36 +79,89 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ }; if (sleep_flags & RTC_SLEEP_PD_DIG) { - unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; -#if CONFIG_ESP32C3_REV_MIN_FULL < 3 + assert(sleep_flags & RTC_SLEEP_PD_XTAL); + bool eco2_workaround = false; + #if CONFIG_ESP32C3_REV_MIN_FULL < 3 if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) { - atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ + eco2_workaround = true; /* workaround for deep sleep issue in high temp on ECO2 and below */ + } + #endif + if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * dbg_att_slp need to set to 0: rtc voltage is about 0.83v + * support all features: + * - 8MD256 as RTC slow clock src + * - RTC memory under high temperature + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + out_config->rtc_dbias_slp = 0; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + /* + * Default mode + * rtc voltage in sleep need stable and not less than 0.7v + * support features: + * - RTC memory under high temperature + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7; + } else { + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power): + * not support features: + * - RTC IO as input + * - RTC memory under high temperature + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = 0; /* not used */ } -#endif - - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = atten_deep_sleep; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; } else { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + out_config->rtc_regulator_fpu = 1; + // rtc & digital voltage from high to low + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { + /* + * digital voltage need to be >= 1.1v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){ + /* + * dbg_att_slp need to set to 0: digital voltage is about 0.67v & rtc vol is about 0.83v + * Support features: + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = 0; + out_config->rtc_dbias_slp = 0; + } else { + /* + * digital voltage not less than 0.6v. + * not support features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6; + } + } + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } else { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; } } @@ -142,20 +195,19 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); } + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); if (cfg.deep_slp) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -164,12 +216,11 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } /* mem force pu */ SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); - + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index 334efd8c3c..eae28a95d8 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -61,33 +61,102 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ }; if (sleep_flags & RTC_SLEEP_PD_DIG) { - out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10; - out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V00; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + assert(sleep_flags & RTC_SLEEP_PD_XTAL); + out_config->dig_dbias_slp = 0; //not used + //rtc voltage from high to low + if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * rtc voltage in sleep mode >= 0.9v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * Support all features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - 8MD256 as RTC slow clock src + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + /* + * rtc voltage in sleep mode >= 0.7v (default mode) + * Support features: + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7; + } else { + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power) + * Support features: + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = 0; + } + } else { + out_config->rtc_regulator_fpu = 1; + // rtc & digital voltage from high to low + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * digital voltage need to be >= 1.1v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * rtc voltage need to near digital voltage to keep system stable + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0) + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { + /* + * rtc voltage need to be >= 0.9v + * digital voltage need to near rtc voltage to make system stable and low current + * Support features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9; + } else { + /* + * digital voltage not less than 0.75v. + * rtc voltage need to near digital voltage to keep system stable + * Support features: + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75; + } + } + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; } else { - out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10; - out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DIG_DBIAS_1V10 - : !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DIG_DBIAS_1V10 - : RTC_CNTL_DIG_DBIAS_0V90; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 - : !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 - : RTC_CNTL_DBIAS_1V00; - - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)? + RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; } } @@ -138,12 +207,13 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } + assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); @@ -151,17 +221,16 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); if (cfg.deep_slp) { - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } else { - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index 41f4c71232..836a484602 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -69,7 +69,6 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, .deep_slp_reject = 1, .light_slp_reject = 1, - .dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT, .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10 }; @@ -77,30 +76,37 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ assert(sleep_flags & RTC_SLEEP_PD_XTAL); out_config->dig_dbias_slp = 0; //not used //rtc voltage from high to low - if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { + if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || (!(sleep_flags & RTC_SLEEP_PD_INT_8M))) { /* - * rtc voltage in sleep mode >= 1.1v + * rtc voltage in sleep mode >= 0.9v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 * Support all features: - * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monotor = 0) + * - 8MD256 as RTC slow clock src + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) * - RTC IO as input * - RTC Memory at high temperature * - ULP * - Touch sensor - * - 8MD256 as RTC slow clock src */ out_config->rtc_regulator_fpu = 1; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { /* - * rtc voltage in sleep need stable and not less than 0.7v (default mode): - * can't use ADC/Temperature sensor in monitor mode + * rtc voltage in sleep mode >= 0.7v (default mode): + * Support follow features: + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor */ out_config->rtc_regulator_fpu = 1; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; } else { /* * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power): - also can't use RTC IO as input, RTC memory can't work under high temperature + * Support follow features: + * - ULP + * - Touch sensor */ out_config->rtc_regulator_fpu = 0; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW; @@ -110,23 +116,36 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ //voltage from high to low if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { /* - * digital voltage not less than 1.1v, rtc voltage not less than 1.1v to keep system stable + * digital voltage not less than 1.1v, rtc voltage is about 1.1v * Support all features: * - XTAL * - RC 8M used by digital system - * - ADC/Temperature sensor in monitor mode (ULP) + * - 8MD256 as RTC slow clock src (only need dbg_atten_slp to 0) + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) * - ULP * - Touch sensor - * - 8MD256 as RTC slow clock src */ out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){ + /* + * dbg_atten_slp need to set to 0. + * digital voltage is about 0.67v, rtc voltage is about 1.1v + * Support features: + * - 8MD256 as RTC slow clock src + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = 0; } else { /* - * digital voltage not less than 0.6v - * if use RTC_SLEEP_USE_ADC_TESEN_MONITOR, rtc voltage need to be >= 0.9v(default voltage), others just use default rtc voltage. - * - not support XTAL - * - not support RC 8M in digital system + * digital voltage not less than 0.6v, rtc voltage is about 0.95v + * Support features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor */ out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; @@ -192,13 +211,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + if (cfg.deep_slp) { SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h index 4f86b86943..78a975a04c 100644 --- a/components/soc/esp32c2/include/soc/rtc.h +++ b/components/soc/esp32c2/include/soc/rtc.h @@ -104,15 +104,27 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 30 + +/* +use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5 /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value @@ -535,18 +547,14 @@ typedef struct { uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode - uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode - uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode - uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; //!< enable deep sleep reject uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 0fa0a59482..bf102a9380 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -56,7 +56,6 @@ extern "C" { /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. */ -#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias #define RTC_CNTL_DBIAS_0V90 13 //digital voltage #define RTC_CNTL_DBIAS_0V95 16 #define RTC_CNTL_DBIAS_1V00 18 @@ -107,14 +106,27 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 25 + +/* +use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5 /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value @@ -572,18 +584,14 @@ typedef struct { uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode - uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode - uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode - uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; //!< enable deep sleep reject uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 71d038e267..e703c4c0bc 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -111,13 +111,31 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 + +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 +#define RTC_CNTL_BIASSLP_MONITOR_ON 0 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_ON 0 + +/* +use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 RTC_CNTL_DBIAS_1V25 + +/* +use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9 5 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9 4 +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75 0 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75 1 + /** * @brief Possible main XTAL frequency values. @@ -589,11 +607,8 @@ typedef struct { uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode - uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode @@ -601,6 +616,7 @@ typedef struct { uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; //!< enable deep sleep reject uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 0a8fc97d0a..44861c15b5 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -112,20 +112,20 @@ set sleep_init default param */ #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 14 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_ON 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_ON 0 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 +#define RTC_CNTL_BIASSLP_MONITOR_ON 0 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_ON 0 /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value @@ -598,7 +598,6 @@ typedef struct { uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode - uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode