fix(wdt): changed register dump on non panic task WDT to be more descriptive

Closes https://github.com/espressif/esp-idf/issues/14400

components/esp_hw_support/include/esp_private/esp_cpu_internal.h

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#pragma once
+
+#include "sdkconfig.h"
+
+#if CONFIG_IDF_TARGET_ARCH_XTENSA
+#include "xtensa_context.h"
+#elif CONFIG_IDF_TARGET_ARCH_RISCV
+#include "riscv/rvruntime-frames.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_IDF_TARGET_ARCH_XTENSA
+typedef XtExcFrame esp_cpu_frame_t;
+#elif CONFIG_IDF_TARGET_ARCH_RISCV
+typedef RvExcFrame esp_cpu_frame_t;
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_system/include/esp_private/panic_internal.h

@@ -85,6 +85,8 @@ void panic_set_address(void *frame, uint32_t addr);
 
 uint32_t panic_get_cause(const void* frame);
 
+void panic_prepare_frame_from_ctx(void* frame);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_system/port/arch/riscv/debug_helpers.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,9 @@
 #include "esp_private/freertos_debug.h"
 #include "esp_err.h"
 #include "esp_attr.h"
-#include "riscv/rvruntime-frames.h"
+#include "esp_private/esp_cpu_internal.h"
+#include "esp_private/panic_internal.h"
+#include <string.h>
 
 #if CONFIG_ESP_SYSTEM_USE_EH_FRAME
 #include "esp_private/eh_frame_parser.h"
@@ -47,13 +49,18 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
 
     void *frame = snapshot.pxTopOfStack;
 
+    esp_cpu_frame_t backtrace_frame = {};
+    memcpy(&backtrace_frame, frame, sizeof(esp_cpu_frame_t));
+
 #if CONFIG_ESP_SYSTEM_USE_EH_FRAME
-        esp_rom_printf("Print CPU %d (current core) backtrace\n", current_core);
+    esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) backtrace\n", current_core);
-        esp_eh_frame_print_backtrace(frame);
+    esp_eh_frame_print_backtrace(frame);
 #else // CONFIG_ESP_SYSTEM_USE_EH_FRAME
-        esp_rom_printf("Print CPU %d (current core) registers\n", current_core);
+    esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) registers\n", current_core);
-        panic_print_registers(frame, current_core);
+    panic_prepare_frame_from_ctx(&backtrace_frame);
-        esp_rom_printf("\r\n");
+
+    panic_print_registers(&backtrace_frame, current_core);
+    esp_rom_printf("\r\n");
 #endif // CONFIG_ESP_SYSTEM_USE_EH_FRAME
 
     return ESP_OK;

components/esp_system/port/arch/riscv/panic_arch.c

@@ -432,3 +432,17 @@ void panic_set_address(void *f, uint32_t addr)
 {
     ((RvExcFrame *)f)->mepc = addr;
 }
+
+void panic_prepare_frame_from_ctx(void* frame)
+{
+    /* Cleanup the frame, status registers are not saved during context switches, so these will contain garbage
+       values from the stack.
+    */
+    ((RvExcFrame *)frame)->mstatus = RV_READ_CSR(mstatus);
+    ((RvExcFrame *)frame)->mtvec = RV_READ_CSR(mtvec);
+
+    ((RvExcFrame *)frame)->mcause = MCAUSE_INVALID_VALUE;
+    ((RvExcFrame *)frame)->mtval = MCAUSE_INVALID_VALUE;
+
+    ((RvExcFrame *)frame)->mhartid = RV_READ_CSR(mhartid);
+}

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -470,3 +470,9 @@ void panic_print_backtrace(const void *f, int core)
     esp_backtrace_frame_t frame = {.pc = xt_frame->pc, .sp = xt_frame->a1, .next_pc = xt_frame->a0, .exc_frame = xt_frame};
     esp_backtrace_print_from_frame(100, &frame, true);
 }
+
+void panic_prepare_frame_from_ctx(void* frame)
+{
+    /* Nothing to cleanup on xtensa */
+    (void)frame;
+}

components/riscv/include/esp_private/panic_reason.h

@@ -18,3 +18,6 @@
 #endif
 
 #define PANIC_RSN_CACHEERR    3
+
+#define MCAUSE_INVALID_VALUE                 0xDEADC0DE // Frame mcause value was written by SW to indicate no useful info, e.g. during a register dump without a crash
+