mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feature/move_memory_layout_to_heap' into 'master'
G0: Memory layouts are now part of heap components Closes IDF-1264 See merge request espressif/esp-idf!14028
This commit is contained in:
Omar Chebib
@@ -19,6 +19,11 @@ if(CONFIG_HEAP_TRACING_STANDALONE)
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-Wno-frame-address)
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endif()
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# Add SoC memory layout to the sources
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list(APPEND srcs "port/memory_layout_utils.c")
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list(APPEND srcs "port/${target}/memory_layout.c")
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idf_component_register(SRCS "${srcs}"
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INCLUDE_DIRS include
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LDFRAGMENTS linker.lf
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@@ -2,7 +2,9 @@
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# Component Makefile
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#
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COMPONENT_OBJS := heap_caps_init.o heap_caps.o multi_heap.o heap_tlsf.o
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COMPONENT_SRCDIRS := . port port/$(IDF_TARGET)
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COMPONENT_ADD_INCLUDEDIRS := include
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COMPONENT_OBJS := heap_caps_init.o heap_caps.o multi_heap.o heap_tlsf.o port/memory_layout_utils.o port/$(IDF_TARGET)/memory_layout.o
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ifndef CONFIG_HEAP_POISONING_DISABLED
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COMPONENT_OBJS += multi_heap_poisoning.o
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@@ -20,7 +20,7 @@
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#include "multi_heap.h"
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#include "multi_heap_platform.h"
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#include "esp_heap_caps_init.h"
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#include "soc/soc_memory_layout.h"
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#include "heap_memory_layout.h"
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static const char *TAG = "heap_init";
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@@ -0,0 +1,113 @@
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
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//
|
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// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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// See the License for the specific language governing permissions and
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||||
// limitations under the License.
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||||
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#pragma once
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#define SOC_MEMORY_TYPE_NO_PRIOS 3
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Type descriptor holds a description for a particular type of memory on a particular SoC.
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*/
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typedef struct {
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const char *name; ///< Name of this memory type
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uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
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bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
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bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
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} soc_memory_type_desc_t;
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/* Constant table of tag descriptors for all this SoC's tags */
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extern const soc_memory_type_desc_t soc_memory_types[];
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extern const size_t soc_memory_type_count;
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/* Region descriptor holds a description for a particular region of memory on a particular SoC.
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*/
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typedef struct {
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intptr_t start; ///< Start address of the region
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size_t size; ///< Size of the region in bytes
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size_t type; ///< Type of the region (index into soc_memory_types array)
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intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
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} soc_memory_region_t;
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extern const soc_memory_region_t soc_memory_regions[];
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extern const size_t soc_memory_region_count;
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/* Region descriptor holds a description for a particular region of
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memory reserved on this SoC for a particular use (ie not available
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for stack/heap usage.) */
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typedef struct {
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intptr_t start;
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intptr_t end;
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} soc_reserved_region_t;
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/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
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* for a particular purpose.
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*
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* Usually used to mark out memory addresses needed for hardware or ROM code
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* purposes.
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*
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* Don't call this macro from user code which can use normal C static allocation
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* instead.
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*
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* @param START Start address to be reserved.
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* @param END One after the address of the last byte to be reserved. (ie length of
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* the reserved region is (END - START) in bytes.
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* @param NAME Name for the reserved region. Must be a valid variable name,
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* unique to this source file.
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*/
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#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
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__attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
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static soc_reserved_region_t reserved_region_##NAME = { START, END };
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/* Return available memory regions for this SoC. Each available memory
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* region is a contiguous piece of memory which is not being used by
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* static data, used by ROM code, or reserved by a component using
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* the SOC_RESERVE_MEMORY_REGION() macro.
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*
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* This result is soc_memory_regions[] minus all regions reserved
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* via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
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* some regions up.)
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*
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* At startup, all available memory returned by this function is
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* registered as heap space.
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*
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* @note OS-level startup function only, not recommended to call from
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* app code.
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*
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* @param regions Pointer to an array for reading available regions into.
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* Size of the array should be at least the result of
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* soc_get_available_memory_region_max_count(). Entries in the array
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* will be ordered by memory address.
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*
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* @return Number of entries copied to 'regions'. Will be no greater than
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* the result of soc_get_available_memory_region_max_count().
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*/
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size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
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/* Return the maximum number of available memory regions which could be
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* returned by soc_get_available_memory_regions(). Used to size the
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* array passed to that function.
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*/
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size_t soc_get_available_memory_region_max_count(void);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,21 @@
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
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||||
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||||
/**
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||||
* Compatibility header file.
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||||
*/
|
||||
#pragma once
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||||
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#include "heap_memory_layout.h"
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#include "soc/soc_memory_types.h"
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@@ -0,0 +1,201 @@
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
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||||
// limitations under the License.
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||||
#ifndef BOOTLOADER_BUILD
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#include <stdlib.h>
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#include <stdint.h>
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#include "soc/soc.h"
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#include "heap_memory_layout.h"
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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#define MALLOC_IRAM_CAP MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_IRAM_8BIT
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#else
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#define MALLOC_IRAM_CAP MALLOC_CAP_EXEC|MALLOC_CAP_32BIT
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#endif
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/* Memory layout for ESP32 SoC */
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/*
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Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
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map consist of one or more regions in the address space.
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Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
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ones can't fulfill the memory request.
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The prioritised capabilities work roughly like this:
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- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
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finally eat into the application memory.
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- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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- Most other malloc caps only fit in one region anyway.
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*/
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const soc_memory_type_desc_t soc_memory_types[] = {
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//Type 0: Plain ole D-port RAM
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{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
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//Type 1: Plain ole D-port RAM which has an alias on the I-port
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//(This DRAM is also the region used by ROM during startup)
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
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//Type 2: IRAM
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{ "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }, false, false},
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//Type 3-8: PID 2-7 IRAM
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{ "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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{ "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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{ "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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{ "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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{ "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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{ "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
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//Type 9-14: PID 2-7 DRAM
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{ "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID4DRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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//Type 15: SPI SRAM data
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||||
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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//Type 16: RTC Fast RAM
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||||
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
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||||
};
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||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/*
|
||||
Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
|
||||
Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
|
||||
from low to high start address.
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory
|
||||
#endif
|
||||
#ifdef CONFIG_SPIRAM
|
||||
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 15, 0}, //SPI SRAM, if available
|
||||
#endif
|
||||
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
|
||||
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
|
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{ 0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
|
||||
{ 0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
|
||||
{ 0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
|
||||
{ 0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
|
||||
{ 0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
|
||||
{ 0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
|
||||
{ 0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
|
||||
{ 0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
|
||||
{ 0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
|
||||
{ 0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
|
||||
{ 0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
|
||||
{ 0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
|
||||
{ 0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
|
||||
{ 0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
|
||||
{ 0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
|
||||
{ 0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
|
||||
{ 0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
|
||||
{ 0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
|
||||
{ 0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
|
||||
{ 0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
|
||||
{ 0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
|
||||
{ 0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
|
||||
{ 0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
|
||||
{ 0x40070000, 0x8000, 2, 0}, //pool 0
|
||||
{ 0x40078000, 0x8000, 2, 0}, //pool 1
|
||||
{ 0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
|
||||
{ 0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
|
||||
{ 0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
|
||||
{ 0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
|
||||
{ 0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
|
||||
{ 0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
|
||||
{ 0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
|
||||
{ 0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
|
||||
{ 0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
|
||||
{ 0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
|
||||
{ 0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
|
||||
{ 0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
|
||||
{ 0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
|
||||
{ 0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
|
||||
{ 0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
|
||||
{ 0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
/* Reserved memory regions
|
||||
|
||||
These are removed from the soc_memory_regions array when heaps are created.
|
||||
*/
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache);
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache);
|
||||
#endif
|
||||
|
||||
/* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because
|
||||
after the scheduler has started, the ROM stack is not used anymore by anything. We handle it instead by not allowing
|
||||
any mallocs memory regions with the startup_stack flag set (these are the IRAM/DRAM region) until the
|
||||
scheduler has started.
|
||||
|
||||
The 0x3ffe0000 region also contains static RAM for various ROM functions. The following lines
|
||||
reserve the regions for UART and ETSC, so these functions are usable. Libraries like xtos, which are
|
||||
not usable in FreeRTOS anyway, are commented out in the linker script so they cannot be used; we
|
||||
do not disable their memory regions here and they will be used as general purpose heap memory.
|
||||
|
||||
Enabling the heap allocator for this region but disabling allocation here until FreeRTOS is started up
|
||||
is a somewhat risky action in theory, because on initializing the allocator, the multi_heap implementation
|
||||
will go and write metadata at the start and end of all regions. For the ESP32, these linked
|
||||
list entries happen to end up in a region that is not touched by the stack; they can be placed safely there.
|
||||
*/
|
||||
|
||||
SOC_RESERVE_MEMORY_REGION(0x3ffe0000, 0x3ffe0440, rom_pro_data); //Reserve ROM PRO data region
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM APP data region
|
||||
#endif
|
||||
|
||||
SOC_RESERVE_MEMORY_REGION(0x3ffae000, 0x3ffae6e0, rom_data);
|
||||
|
||||
#if CONFIG_ESP32_MEMMAP_TRACEMEM
|
||||
#if CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
|
||||
SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region, 32K for both cpu
|
||||
#else
|
||||
SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace mem region, 16K (upper-half) for pro cpu
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPIRAM
|
||||
/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
|
||||
* memory to heap depending on the actual SPIRAM chip size. */
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, spi_ram);
|
||||
#endif
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// IRAM code region
|
||||
// ESP32 has an IRAM-only region 0x4008_0000 - 0x4009_FFFF, reserve the used part
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
|
||||
|
||||
// RTC Fast RAM region
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
#ifdef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
|
||||
#else
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* BOOTLOADER_BUILD */
|
||||
@@ -0,0 +1,99 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/**
|
||||
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
|
||||
* Each type of memory map consists of one or more regions in the address space.
|
||||
* Each type contains an array of prioritized capabilities.
|
||||
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
|
||||
*
|
||||
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
|
||||
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: RTCRAM
|
||||
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/**
|
||||
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
*
|
||||
* @note Because of requirements in the coalescing code which merges adjacent regions,
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
|
||||
|
||||
/**
|
||||
* Reserved memory regions.
|
||||
* These are removed from the soc_memory_regions array when heaps are created.
|
||||
*
|
||||
*/
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// Target has a big D/IRAM region, the part used by code is reserved
|
||||
// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
|
||||
#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW
|
||||
region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
|
||||
*/
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
|
||||
#endif
|
||||
|
||||
#endif // BOOTLOADER_BUILD
|
||||
@@ -0,0 +1,99 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/**
|
||||
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
|
||||
* Each type of memory map consists of one or more regions in the address space.
|
||||
* Each type contains an array of prioritized capabilities.
|
||||
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
|
||||
*
|
||||
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
|
||||
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: RTCRAM
|
||||
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/**
|
||||
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
*
|
||||
* @note Because of requirements in the coalescing code which merges adjacent regions,
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
|
||||
|
||||
/**
|
||||
* Reserved memory regions.
|
||||
* These are removed from the soc_memory_regions array when heaps are created.
|
||||
*
|
||||
*/
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// Target has a big D/IRAM region, the part used by code is reserved
|
||||
// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
|
||||
#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW
|
||||
region on H2, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
|
||||
*/
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
|
||||
#endif
|
||||
|
||||
#endif // BOOTLOADER_BUILD
|
||||
@@ -0,0 +1,160 @@
|
||||
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/* Memory layout for ESP32 SoC */
|
||||
|
||||
/*
|
||||
Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
|
||||
map consist of one or more regions in the address space.
|
||||
|
||||
Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
|
||||
ones can't fulfill the memory request.
|
||||
|
||||
The prioritised capabilities work roughly like this:
|
||||
- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
|
||||
finally eat into the application memory.
|
||||
- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
|
||||
- Most other malloc caps only fit in one region anyway.
|
||||
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
//Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
|
||||
//Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, false},
|
||||
//Type 3: IRAM
|
||||
//In ESP32S2, All IRAM region are available by D-port (D/IRAM).
|
||||
{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
//Type 4: SPI SRAM data
|
||||
//TODO, in fact, part of them support EDMA, to be supported.
|
||||
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
|
||||
//Type 5: RTC Fast RAM
|
||||
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/*
|
||||
Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
|
||||
Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
|
||||
from low to high start address.
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ SOC_RTC_DRAM_LOW, 0x2000, 5, 0}, //RTC Fast Memory
|
||||
#endif
|
||||
#ifdef CONFIG_SPIRAM
|
||||
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available
|
||||
#endif
|
||||
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
|
||||
#if CONFIG_ESP32S2_DATA_CACHE_0KB
|
||||
{ 0x3FFB2000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40022000}, //Block 1, can be use as I/D cache memory
|
||||
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block 2, can be use as D cache memory
|
||||
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
|
||||
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
|
||||
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block 2, can be use as D cache memory
|
||||
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
|
||||
#else
|
||||
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_ESP32S2_DATA_CACHE_0KB
|
||||
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block SOC_MEMORY_TYPE_DEFAULT, can be use as D cache memory
|
||||
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
|
||||
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
|
||||
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
|
||||
#endif
|
||||
#endif
|
||||
{ 0x3FFB8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FFBC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FFC0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40030000}, //Block 6, can be used as trace memory
|
||||
{ 0x3FFC4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40034000}, //Block 7, can be used as trace memory
|
||||
{ 0x3FFC8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40038000}, //Block 8, can be used as trace memory
|
||||
{ 0x3FFCC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4003C000}, //Block 9, can be used as trace memory
|
||||
|
||||
{ 0x3FFD0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40040000}, //Block 10, can be used as trace memory
|
||||
{ 0x3FFD4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40044000}, //Block 11, can be used as trace memory
|
||||
{ 0x3FFD8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40048000}, //Block 12, can be used as trace memory
|
||||
{ 0x3FFDC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4004C000}, //Block 13, can be used as trace memory
|
||||
{ 0x3FFE0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40050000}, //Block 14, can be used as trace memory
|
||||
{ 0x3FFE4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40054000}, //Block 15, can be used as trace memory
|
||||
{ 0x3FFE8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40058000}, //Block 16, can be used as trace memory
|
||||
{ 0x3FFEC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4005C000}, //Block 17, can be used as trace memory
|
||||
{ 0x3FFF0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
|
||||
{ 0x3FFF4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
|
||||
{ 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
|
||||
{ 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
extern int _dram0_rtos_reserved_start;
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;
|
||||
|
||||
/* Reserved memory regions
|
||||
|
||||
These are removed from the soc_memory_regions array when heaps are created.
|
||||
*/
|
||||
//ROM data region
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_dram0_rtos_reserved_start, SOC_BYTE_ACCESSIBLE_HIGH, rom_data_region);
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// ESP32S2 has a big D/IRAM region, the part used by code is reserved
|
||||
// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
|
||||
#define I_D_OFFSET (SOC_IRAM_LOW - SOC_DRAM_LOW)
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
|
||||
|
||||
#ifdef CONFIG_SPIRAM
|
||||
/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
|
||||
* memory to heap depending on the actual SPIRAM chip size. */
|
||||
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region);
|
||||
#endif
|
||||
|
||||
// Blocks 19 and 20 may be reserved for the trace memory
|
||||
#if CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM > 0
|
||||
SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
|
||||
#endif
|
||||
|
||||
// RTC Fast RAM region
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
#ifdef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
|
||||
#else
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif // BOOTLOADER_BUILD
|
||||
@@ -0,0 +1,113 @@
|
||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/**
|
||||
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
|
||||
* Each type of memory map consists of one or more regions in the address space.
|
||||
* Each type contains an array of prioritized capabilities.
|
||||
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
|
||||
*
|
||||
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
|
||||
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: SPI SRAM data
|
||||
{ "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
|
||||
};
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/**
|
||||
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
*
|
||||
* @note Because of requirements in the coalescing code which merges adjacent regions,
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
#ifdef CONFIG_SPIRAM
|
||||
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available
|
||||
#endif
|
||||
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
{ 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM
|
||||
#endif
|
||||
{ 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy
|
||||
{ 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy
|
||||
{ 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task
|
||||
#if CONFIG_ESP32S3_DATA_CACHE_32KB
|
||||
{ 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM
|
||||
#endif
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end; // defined in sections.ld.in
|
||||
|
||||
/**
|
||||
* Reserved memory regions.
|
||||
* These are removed from the soc_memory_regions array when heaps are created.
|
||||
*
|
||||
*/
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// ESP32S3 has a big D/IRAM region, the part used by code is reserved
|
||||
// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
|
||||
#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
|
||||
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_start + 0x4000, iram_code_1);
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start + 0x4000 - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code_2);
|
||||
#else
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPIRAM
|
||||
/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
|
||||
* memory to heap depending on the actual SPIRAM chip size. */
|
||||
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region);
|
||||
#endif
|
||||
|
||||
#if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0
|
||||
SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
|
||||
#endif
|
||||
|
||||
#endif // BOOTLOADER_BUILD
|
||||
@@ -0,0 +1,200 @@
|
||||
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/soc_memory_layout.h"
|
||||
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32C3
|
||||
#include "esp32c3/rom/rom_layout.h"
|
||||
#define ROM_HAS_LAYOUT_TABLE 1
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/rom_layout.h"
|
||||
#define ROM_HAS_LAYOUT_TABLE 1
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rom_layout.h"
|
||||
#define ROM_HAS_LAYOUT_TABLE 1
|
||||
#else
|
||||
#define ROM_HAS_LAYOUT_TABLE 0
|
||||
#endif
|
||||
|
||||
static const char *TAG = "memory_layout";
|
||||
|
||||
/* These variables come from the linker script,
|
||||
delimit the start and end of entries created via
|
||||
SOC_RESERVE_MEMORY_REGION() macro.
|
||||
*/
|
||||
extern soc_reserved_region_t soc_reserved_memory_region_start;
|
||||
extern soc_reserved_region_t soc_reserved_memory_region_end;
|
||||
|
||||
static size_t s_get_num_reserved_regions(void)
|
||||
{
|
||||
size_t result = ( &soc_reserved_memory_region_end
|
||||
- &soc_reserved_memory_region_start );
|
||||
#if ROM_HAS_LAYOUT_TABLE
|
||||
return result + 1; // ROM table means one entry needs to be added at runtime
|
||||
#else
|
||||
return result;
|
||||
#endif
|
||||
}
|
||||
|
||||
size_t soc_get_available_memory_region_max_count(void)
|
||||
{
|
||||
/* Worst-case: each reserved memory region splits an available
|
||||
region in two, so the maximum possible number of regions
|
||||
is the number of regions of memory plus the number of reservations */
|
||||
return soc_memory_region_count + s_get_num_reserved_regions();
|
||||
}
|
||||
|
||||
static int s_compare_reserved_regions(const void *a, const void *b)
|
||||
{
|
||||
const soc_reserved_region_t *r_a = (soc_reserved_region_t *)a;
|
||||
const soc_reserved_region_t *r_b = (soc_reserved_region_t *)b;
|
||||
return (int)r_a->start - (int)r_b->start;
|
||||
}
|
||||
|
||||
/* Initialize a mutable array of reserved regions in 'reserved',
|
||||
then sort it by start address and check for overlapping
|
||||
reserved regions (illegal).
|
||||
*/
|
||||
static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t count)
|
||||
{
|
||||
#if ROM_HAS_LAYOUT_TABLE
|
||||
/* Get the ROM layout to find which part of DRAM is reserved */
|
||||
const ets_rom_layout_t *layout = ets_rom_layout_p;
|
||||
reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
|
||||
reserved[0].end = SOC_DIRAM_DRAM_HIGH;
|
||||
|
||||
memcpy(reserved + 1, &soc_reserved_memory_region_start, (count - 1) * sizeof(soc_reserved_region_t));
|
||||
#else
|
||||
memcpy(reserved, &soc_reserved_memory_region_start, count * sizeof(soc_reserved_region_t));
|
||||
#endif
|
||||
|
||||
/* Sort by starting address */
|
||||
qsort(reserved, count, sizeof(soc_reserved_region_t), s_compare_reserved_regions);
|
||||
|
||||
/* Validity checks */
|
||||
ESP_EARLY_LOGV(TAG, "reserved range is %p - %p",
|
||||
&soc_reserved_memory_region_start,
|
||||
&soc_reserved_memory_region_end);
|
||||
ESP_EARLY_LOGD(TAG, "Checking %d reserved memory ranges:", count);
|
||||
for (size_t i = 0; i < count; i++) {
|
||||
ESP_EARLY_LOGD(TAG, "Reserved memory range 0x%08x - 0x%08x",
|
||||
reserved[i].start, reserved[i].end);
|
||||
reserved[i].start = reserved[i].start & ~3; /* expand all reserved areas to word boundaries */
|
||||
reserved[i].end = (reserved[i].end + 3) & ~3;
|
||||
assert(reserved[i].start <= reserved[i].end);
|
||||
if (i < count - 1) {
|
||||
assert(reserved[i + 1].start > reserved[i].start);
|
||||
if (reserved[i].end > reserved[i + 1].start) {
|
||||
ESP_EARLY_LOGE(TAG, "SOC_RESERVE_MEMORY_REGION region range " \
|
||||
"0x%08x - 0x%08x overlaps with 0x%08x - 0x%08x",
|
||||
reserved[i].start, reserved[i].end, reserved[i + 1].start,
|
||||
reserved[i + 1].end);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
size_t soc_get_available_memory_regions(soc_memory_region_t *regions)
|
||||
{
|
||||
soc_memory_region_t *out_region = regions;
|
||||
/* make a local copy of the "input" regions so we can modify them */
|
||||
soc_memory_region_t in_regions[soc_memory_region_count];
|
||||
memcpy(in_regions, soc_memory_regions, sizeof(in_regions));
|
||||
soc_memory_region_t *in_region = in_regions;
|
||||
|
||||
size_t num_reserved = s_get_num_reserved_regions();
|
||||
soc_reserved_region_t reserved[num_reserved];
|
||||
|
||||
s_prepare_reserved_regions(reserved, num_reserved);
|
||||
|
||||
/* Go through the "in" regions (full regions, with no reserved
|
||||
sections removed from them) one at a time, trim off each reserved
|
||||
region, and then copy them to an out_region once trimmed
|
||||
*/
|
||||
ESP_EARLY_LOGD(TAG, "Building list of available memory regions:");
|
||||
while (in_region != in_regions + soc_memory_region_count) {
|
||||
soc_memory_region_t in = *in_region;
|
||||
ESP_EARLY_LOGV(TAG, "Examining memory region 0x%08x - 0x%08x", in.start, in.start + in.size);
|
||||
intptr_t in_start = in.start;
|
||||
intptr_t in_end = in_start + in.size;
|
||||
bool copy_in_to_out = true;
|
||||
bool move_to_next = true;
|
||||
|
||||
for (size_t i = 0; i < num_reserved; i++) {
|
||||
if (reserved[i].end <= in_start) {
|
||||
/* reserved region ends before 'in' starts */
|
||||
continue;
|
||||
} else if (reserved[i].start >= in_end) {
|
||||
/* reserved region starts after 'in' ends */
|
||||
break;
|
||||
} else if (reserved[i].start <= in_start &&
|
||||
reserved[i].end >= in_end) { /* reserved covers all of 'in' */
|
||||
ESP_EARLY_LOGV(TAG, "Region 0x%08x - 0x%08x inside of reserved 0x%08x - 0x%08x",
|
||||
in_start, in_end, reserved[i].start, reserved[i].end);
|
||||
/* skip 'in' entirely */
|
||||
copy_in_to_out = false;
|
||||
break;
|
||||
} else if (in_start < reserved[i].start &&
|
||||
in_end > reserved[i].end) { /* reserved contained inside 'in', need to "hole punch" */
|
||||
ESP_EARLY_LOGV(TAG, "Region 0x%08x - 0x%08x contains reserved 0x%08x - 0x%08x",
|
||||
in_start, in_end, reserved[i].start, reserved[i].end);
|
||||
assert(in_start < reserved[i].start);
|
||||
assert(in_end > reserved[i].end);
|
||||
|
||||
/* shrink this region to end where the reserved section starts */
|
||||
in_end = reserved[i].start;
|
||||
in.size = in_end - in_start;
|
||||
|
||||
/* update in_region so the 'next' iteration uses the region
|
||||
after the reserved section */
|
||||
in_region->size -= (reserved[i].end - in_region->start);
|
||||
in_region->start = reserved[i].end;
|
||||
|
||||
/* add first region, then re-run while loop with the updated in_region */
|
||||
move_to_next = false;
|
||||
break;
|
||||
} else if (reserved[i].start <= in_start) { /* reserved overlaps start of 'in' */
|
||||
ESP_EARLY_LOGV(TAG, "Start of region 0x%08x - 0x%08x overlaps reserved 0x%08x - 0x%08x",
|
||||
in_start, in_end, reserved[i].start, reserved[i].end);
|
||||
in.start = reserved[i].end;
|
||||
in_start = in.start;
|
||||
in.size = in_end - in_start;
|
||||
} else { /* reserved overlaps end of 'in' */
|
||||
ESP_EARLY_LOGV(TAG, "End of region 0x%08x - 0x%08x overlaps reserved 0x%08x - 0x%08x",
|
||||
in_start, in_end, reserved[i].start, reserved[i].end);
|
||||
in_end = reserved[i].start;
|
||||
in.size = in_end - in_start;
|
||||
}
|
||||
}
|
||||
|
||||
/* ignore regions smaller than 16B */
|
||||
if (in.size <= 16) {
|
||||
copy_in_to_out = false;
|
||||
}
|
||||
|
||||
if (copy_in_to_out) {
|
||||
ESP_EARLY_LOGD(TAG, "Available memory region 0x%08x - 0x%08x", in.start, in.start + in.size);
|
||||
*out_region++ = in;
|
||||
}
|
||||
if (move_to_next) {
|
||||
in_region++;
|
||||
}
|
||||
}
|
||||
|
||||
return (out_region - regions); /* return number of regions */
|
||||
}
|
||||
Reference in New Issue
Block a user