From a7c5c7134b4930da6e86605d517f1ceca5b51948 Mon Sep 17 00:00:00 2001
From: Chen Yudong <chenyudong@espressif.com>
Date: Tue, 12 Oct 2021 20:35:39 +0800
Subject: [PATCH] ci: increase parallel count for UT_S3

---
 .gitlab/ci/target-test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml
index 932e6ee798..73c449e3d2 100644
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
@@ -727,7 +727,7 @@ UT_C3_SDSPI:
 
 UT_S3:
   extends: .unit_test_esp32s3_template
-  parallel: 29
+  parallel: 30
   tags:
     - ESP32S3_IDF
     - UT_T1_1