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	Merge branch 'feature/mcpwm_support_c5' into 'master'
feat(mcpwm): add driver support on esp32c5 Closes IDF-8709 and IDF-9101 See merge request espressif/esp-idf!29876
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		@@ -112,7 +112,7 @@ static inline void mcpwm_ll_reset_register(int group_id)
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#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
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/**
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 * @brief Enable MCPWM module clock
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 * @brief Enable MCPWM function clock
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 *
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 * @note Not support to enable/disable the peripheral clock
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 *
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@@ -128,25 +128,26 @@ static inline void mcpwm_ll_group_enable_clock(int group_id, bool en)
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/**
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 * @brief Set the clock source for MCPWM
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 *
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 * @param mcpwm Peripheral instance address
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 * @param group_id Group ID
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 * @param clk_src Clock source for the MCPWM peripheral
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 */
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static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, mcpwm_timer_clock_source_t clk_src)
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static inline void mcpwm_ll_group_set_clock_source(int group_id, mcpwm_timer_clock_source_t clk_src)
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{
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    (void)mcpwm;
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    (void)group_id;
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    (void)clk_src;
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}
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/**
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 * @brief Set the MCPWM group clock prescale
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 *
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 * @param mcpwm Peripheral instance address
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 * @param group_id Group ID
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 * @param pre_scale Prescale value
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 */
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static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
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static inline void mcpwm_ll_group_set_clock_prescale(int group_id, int prescale)
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{
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    // group clock: PWM_clk = CLK_160M / (prescale)
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    HAL_ASSERT(prescale <= 256 && prescale > 0);
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    mcpwm_dev_t *mcpwm = MCPWM_LL_GET_HW(group_id);
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    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale, prescale - 1);
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}
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@@ -220,7 +221,7 @@ static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm)
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 * @brief Clear MCPWM interrupt status by mask
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 *
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 * @param mcpwm Peripheral instance address
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 * @param mask Interupt status mask
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 * @param mask Interrupt status mask
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 */
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__attribute__((always_inline))
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static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask)
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@@ -1620,18 +1621,6 @@ static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel
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/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
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{
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    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale) + 1;
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}
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static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
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{
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    mcpwm_timer_cfg0_reg_t cfg0;
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    cfg0.val = mcpwm->timer[timer_id].timer_cfg0.val;
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    return cfg0.timer_prescale + 1;
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}
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static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric)
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{
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    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1);
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