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Merge branch 'fix/fix_c3_c2_cache_freeze_soc_caps_issue_v5.3' into 'release/v5.3'

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cache: fixed SOC_CACHE_FREEZE_SUPPORTED not defined on C3 / C2 issue (v5.3)

See merge request espressif/esp-idf!39884
This commit is contained in:
Michael (XIAO Xufeng)
2025-06-24 23:14:11 +08:00
parent 2bfcab5047 2784693977
commit a81456e0d0
6 changed files with 64 additions and 2 deletions
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28
components/hal/esp32c2/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -149,6 +149,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
Cache_Invalidate_Addr(vaddr, size); Cache_Invalidate_Addr(vaddr, size);
} }
/**
* @brief Freeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
* @brief Unfreeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Disable();
}
/** /**
* @brief Get Cache line size, in bytes * @brief Get Cache line size, in bytes
* *

28
components/hal/esp32c3/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -152,6 +152,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
Cache_Invalidate_Addr(vaddr, size); Cache_Invalidate_Addr(vaddr, size);
} }
/**
* @brief Freeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
* @brief Unfreeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
Cache_Freeze_ICache_Disable();
}
/** /**
* @brief Get Cache line size, in bytes * @brief Get Cache line size, in bytes
* *

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@@ -227,6 +227,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
bool bool
default y default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM config SOC_CPU_CORES_NUM
int int
default 1 default 1

1
components/soc/esp32c2/include/soc/soc_caps.h
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@@ -93,6 +93,7 @@
/*-------------------------- CACHE CAPS --------------------------------------*/ /*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_FREEZE_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/ /*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_CORES_NUM (1U)

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@@ -311,6 +311,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
bool bool
default y default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CACHE_MEMORY_IBANK_SIZE config SOC_CACHE_MEMORY_IBANK_SIZE
hex hex
default 0x4000 default 0x4000

1
components/soc/esp32c3/include/soc/soc_caps.h
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@@ -124,6 +124,7 @@
/*-------------------------- CACHE CAPS --------------------------------------*/ /*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
#define SOC_CACHE_FREEZE_SUPPORTED 1
#define SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 // has to be same as the definition in ROM component #define SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 // has to be same as the definition in ROM component
/*-------------------------- CPU CAPS ----------------------------------------*/ /*-------------------------- CPU CAPS ----------------------------------------*/