From a90dcfba1aac68deff9f74447592d5d2e6ab363c Mon Sep 17 00:00:00 2001 From: Omar Chebib Date: Tue, 8 Dec 2020 17:25:46 +0800 Subject: [PATCH] panic: Add support for SoC-level panic Activate "invalid access to cache raises panic (PRO CPU)" CI unit test in order to test SoC-level panics. --- components/esp32c3/cache_err_int.c | 2 +- components/esp_common/src/int_wdt.c | 4 ++-- components/riscv/vectors.S | 4 ++-- .../spi_flash/test/test_cache_disabled.c | 21 ++++++++++++++++--- 4 files changed, 23 insertions(+), 8 deletions(-) diff --git a/components/esp32c3/cache_err_int.c b/components/esp32c3/cache_err_int.c index 20edd475bf..d4efe24d2c 100644 --- a/components/esp32c3/cache_err_int.c +++ b/components/esp32c3/cache_err_int.c @@ -59,7 +59,7 @@ void esp_cache_err_int_init(void) /* Set the type and priority to cache error interrupts. */ esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); - esprv_intc_int_set_priority(ETS_CACHEERR_INUM, 4); + esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); /* On the hardware side, stat by clearing all the bits reponsible for * enabling cache access error interrupts. */ diff --git a/components/esp_common/src/int_wdt.c b/components/esp_common/src/int_wdt.c index edd70e9448..a2de13404d 100644 --- a/components/esp_common/src/int_wdt.c +++ b/components/esp_common/src/int_wdt.c @@ -126,11 +126,11 @@ void esp_int_wdt_cpu_init(void) /* Set the type and priority to cache error interrupts, if supported. */ #if SOC_INTERRUPT_TYPE_CAN_SET - interrupt_controller_hal_set_type(BIT(WDT_INT_NUM), INTR_TYPE_LEVEL); + interrupt_controller_hal_set_type(WDT_INT_NUM, INTR_TYPE_LEVEL); #endif #if SOC_INTERRUPT_LEVEL_CAN_SET - interrupt_controller_hal_set_level(WDT_INT_NUM, 4); + interrupt_controller_hal_set_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM); #endif #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S index 04c6bd63ad..74e1482ce0 100644 --- a/components/riscv/vectors.S +++ b/components/riscv/vectors.S @@ -122,12 +122,12 @@ _vector_table: .option push .option norvc j _panic_handler /* exception handler, entry 0 */ - .rept 23 + .rept (ETS_T1_WDT_INUM - 1) j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */ .endr j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/ j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/ - .rept 6 + .rept (ETS_MAX_INUM - ETS_CACHEERR_INUM) j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */ .endr diff --git a/components/spi_flash/test/test_cache_disabled.c b/components/spi_flash/test/test_cache_disabled.c index aae44bd431..40f5bb0d4c 100644 --- a/components/spi_flash/test/test_cache_disabled.c +++ b/components/spi_flash/test/test_cache_disabled.c @@ -51,10 +51,19 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash vQueueDelete(result_queue); } -static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98 }; +/** + * On ESP32-C3 boards, constant data with a size less or equal to 8 bytes + * (64 bits) are placed in the DRAM. + * Let's add a third unused element to this array to force it to the DROM. + */ +static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98, 0x42 }; static void IRAM_ATTR cache_access_test_func(void* arg) { + /* Assert that the array s_in_rodata is in DROM. If not, this test is + * invalid as disabling the cache wouldn't have any effect. */ + TEST_ASSERT(esp_ptr_in_drom(s_in_rodata)); + spi_flash_disable_interrupts_caches_and_other_cpu(); volatile uint32_t* src = (volatile uint32_t*) s_in_rodata; uint32_t v1 = src[0]; @@ -65,9 +74,15 @@ static void IRAM_ATTR cache_access_test_func(void* arg) vTaskDelete(NULL); } +#ifdef CONFIG_IDF_TARGET_ESP32C3 +#define CACHE_ERROR_REASON "Cache exception,RTC_SW_CPU_RST" +#else +#define CACHE_ERROR_REASON "Cache disabled,SW_RESET" +#endif + // These tests works properly if they resets the chip with the // "Cache disabled but cached memory region accessed" reason and the correct CPU is logged. -TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]") +TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]") { xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0); vTaskDelay(1000/portTICK_PERIOD_MS); @@ -75,7 +90,7 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore] #ifndef CONFIG_FREERTOS_UNICORE -TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][ignore]") +TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset=TG1WDT_SYS_RESET]") { xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1); vTaskDelay(1000/portTICK_PERIOD_MS);