diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
index 13607bcf3d..b017f76624 100644
--- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
+++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
@@ -233,8 +233,9 @@ static void wdt_reset_cpu0_info_enable(void)
 
 static void wdt_reset_info_dump(int cpu)
 {
-    // TODO ESP32-C3 IDF-2118
-    ESP_LOGE(TAG, "WDT reset info dump is not supported yet");
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
 }
 
 static void bootloader_check_wdt_reset(void)
diff --git a/components/esp32c3/crosscore_int.c b/components/esp32c3/crosscore_int.c
index e704b33914..2eaccec255 100644
--- a/components/esp32c3/crosscore_int.c
+++ b/components/esp32c3/crosscore_int.c
@@ -58,6 +58,10 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg)
          * to allow DFS features without the extra latency of the ISR hook.
          */
     }
+    // TODO: ESP32-C3 IDF-2986
+    // if (my_reason_val & REASON_PRINT_BACKTRACE) {
+    //     esp_backtrace_print(100);
+    // }
 }
 
 // Initialize the crosscore interrupt on this core.
diff --git a/components/esp_system/task_wdt.c b/components/esp_system/task_wdt.c
index 27a68a5b15..26d716b452 100644
--- a/components/esp_system/task_wdt.c
+++ b/components/esp_system/task_wdt.c
@@ -184,7 +184,7 @@ static void task_wdt_isr(void *arg)
         abort();
     } else {
 
-#if !CONFIG_IDF_TARGET_ESP32C3 // TODO ESP32-C3 add backtrace printing support IDF-2285
+#if !CONFIG_IDF_TARGET_ESP32C3 // TODO: ESP32-C3 IDF-2986
         int current_core = xPortGetCoreID();
         //Print backtrace of current core
         ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core);