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ci: fixed flakey light sleep example test

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A wake-up from timer would trigger before the gpio wakeup in certain cases,
failing the test.

Change the regex to only expect the GPIO wakeup, so that even if there is an extra
timer wakeup it wont fail the test.
This commit is contained in:
Marius Vikhammer
2022-07-19 11:03:16 +08:00
parent 45ba00544a
commit a9ed589501
1 changed files with 6 additions and 4 deletions
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10
examples/system/light_sleep/pytest_light_sleep.py
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@@ -18,6 +18,8 @@ def test_light_sleep(dut: Dut) -> None:
ENTERING_SLEEP_STR = 'Entering light sleep' ENTERING_SLEEP_STR = 'Entering light sleep'
EXIT_SLEEP_REGEX = r'Returned from light sleep, reason: (\w+), t=(\d+) ms, slept for (\d+) ms' EXIT_SLEEP_REGEX = r'Returned from light sleep, reason: (\w+), t=(\d+) ms, slept for (\d+) ms'
EXIT_SLEEP_PIN_REGEX = r'Returned from light sleep, reason: (pin), t=(\d+) ms, slept for (\d+) ms'
EXIT_SLEEP_UART_REGEX = r'Returned from light sleep, reason: (uart), t=(\d+) ms, slept for (\d+) ms'
WAITING_FOR_GPIO_STR = r'Waiting for GPIO\d to go high...' WAITING_FOR_GPIO_STR = r'Waiting for GPIO\d to go high...'
WAKEUP_INTERVAL_MS = 2000 WAKEUP_INTERVAL_MS = 2000
@@ -44,9 +46,9 @@ def test_light_sleep(dut: Dut) -> None:
logging.info('Pulling GPIO0 low using DTR') logging.info('Pulling GPIO0 low using DTR')
dut.serial.proc.setDTR(True) dut.serial.proc.setDTR(True)
time.sleep(1) time.sleep(1)
match = dut.expect(EXIT_SLEEP_REGEX) match = dut.expect(EXIT_SLEEP_PIN_REGEX)
logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3))) logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3)))
assert(match.group(1).decode('utf8') == 'pin' and int(match.group(3)) < WAKEUP_INTERVAL_MS) assert(int(match.group(3)) < WAKEUP_INTERVAL_MS)
dut.expect(WAITING_FOR_GPIO_STR) dut.expect(WAITING_FOR_GPIO_STR)
logging.info('Is waiting for GPIO...') logging.info('Is waiting for GPIO...')
@@ -58,9 +60,9 @@ def test_light_sleep(dut: Dut) -> None:
# Write 'U' to uart, 'U' in ascii is 0x55 which contains 8 edges in total # Write 'U' to uart, 'U' in ascii is 0x55 which contains 8 edges in total
dut.write('U') dut.write('U')
time.sleep(1) time.sleep(1)
match = dut.expect(EXIT_SLEEP_REGEX) match = dut.expect(EXIT_SLEEP_UART_REGEX)
logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3))) logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3)))
assert(match.group(1).decode('utf8') == 'uart' and int(match.group(3)) < WAKEUP_INTERVAL_MS) assert(int(match.group(3)) < WAKEUP_INTERVAL_MS)
logging.info('Went to sleep again') logging.info('Went to sleep again')
match = dut.expect(EXIT_SLEEP_REGEX) match = dut.expect(EXIT_SLEEP_REGEX)