diff --git a/components/esp_system/port/esp32s2/clk.c b/components/esp_system/port/esp32s2/clk.c
index 852d143292..6f032f46f9 100644
--- a/components/esp_system/port/esp32s2/clk.c
+++ b/components/esp_system/port/esp32s2/clk.c
@@ -242,7 +242,6 @@ void esp_perip_clk_init(void)
                            DPORT_LEDC_CLK_EN |
                            DPORT_TIMERGROUP1_CLK_EN |
                            DPORT_SPI3_CLK_EN |
-                           DPORT_SPI4_CLK_EN |
                            DPORT_PWM0_CLK_EN |
                            DPORT_TWAI_CLK_EN |
                            DPORT_PWM1_CLK_EN |
@@ -281,7 +280,6 @@ void esp_perip_clk_init(void)
                         DPORT_RMT_CLK_EN |
                         DPORT_UHCI1_CLK_EN |
                         DPORT_SPI3_CLK_EN |
-                        DPORT_SPI4_CLK_EN |
                         DPORT_I2C_EXT1_CLK_EN |
                         DPORT_I2S1_CLK_EN |
                         DPORT_SPI2_DMA_CLK_EN |
diff --git a/components/soc/soc/esp32s2/include/soc/system_reg.h b/components/soc/soc/esp32s2/include/soc/system_reg.h
index cc7183c84b..4e335cc7ab 100644
--- a/components/soc/soc/esp32s2/include/soc/system_reg.h
+++ b/components/soc/soc/esp32s2/include/soc/system_reg.h
@@ -190,12 +190,6 @@ extern "C" {
 
 #define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG
 #define DPORT_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x040)
-/* DPORT_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
-/*description: */
-#define DPORT_SPI4_CLK_EN  (BIT(31))
-#define DPORT_SPI4_CLK_EN_M  (BIT(31))
-#define DPORT_SPI4_CLK_EN_V  0x1
-#define DPORT_SPI4_CLK_EN_S  31
 /* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
 /*description: */
 #define DPORT_ADC2_ARB_CLK_EN  (BIT(30))
@@ -424,12 +418,6 @@ extern "C" {
 
 #define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG
 #define DPORT_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x048)
-/* DPORT_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define DPORT_SPI4_RST  (BIT(31))
-#define DPORT_SPI4_RST_M  (BIT(31))
-#define DPORT_SPI4_RST_V  0x1
-#define DPORT_SPI4_RST_S  31
 /* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
 /*description: */
 #define DPORT_ADC2_ARB_RST  (BIT(30))