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https://github.com/espressif/esp-idf.git
synced 2025-11-03 08:31:44 +01:00
feat(lp-core): bringup lp-core for C5 MP
LP-Core is now able to boot and run on C5 MP chip.
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@@ -120,6 +120,16 @@ static inline void lp_core_ll_request_sleep(void)
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PMU.lp_ext.pwr1.sleep_req = 1;
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}
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/**
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* @brief Get which interrupts have triggered on the LP core
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*
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* @return uint8_t bit mask of triggered LP interrupt sources
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*/
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static inline uint8_t lp_core_ll_get_triggered_interrupt_srcs(void)
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{
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return LPPERI.interrupt_source.lp_interrupt_source;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -683,6 +683,16 @@ FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
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hw->lp_ext.int_clr.val = mask;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
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{
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hw->lp_ext.int_clr.sw_trigger = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable)
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{
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hw->lp_ext.int_ena.sw_trigger = enable;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -44,6 +44,15 @@ typedef enum {
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RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
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} rtcio_ll_out_mode_t;
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typedef enum {
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RTCIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */
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RTCIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */
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RTCIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */
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RTCIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */
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RTCIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */
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RTCIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */
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} rtcio_ll_intr_type_t;
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/**
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* @brief Select a RTC IOMUX function for the RTC IO
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*
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@@ -451,6 +460,18 @@ static inline void rtcio_ll_clear_interrupt_status(void)
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abort();
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}
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/**
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* Enable interrupt function and set interrupt type
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*
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* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
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* @param type Interrupt type on high level or low level.
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*/
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static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type)
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{
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// TODO: [ESP32C5] IDF-8719
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//LP_GPIO.pin[rtcio_num].int_type = type;
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}
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#ifdef __cplusplus
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}
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#endif
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