From dd414b930587973ae1a1734eaecb74ac20b975ae Mon Sep 17 00:00:00 2001 From: jingli Date: Mon, 2 May 2022 12:31:25 +0800 Subject: [PATCH 1/4] =?UTF-8?q?esp=5Fhw=5F=E2=80=8Esupport/sleep:=20?= =?UTF-8?q?=E2=80=8Efix=20cannot=20lightsleep=20again=20after=20a=20wakeup?= =?UTF-8?q?=20from=20ULP?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since ulp wakeup signal are connected to ulp int raw(except esp32), we need to clear ulp int raw before sleep when ulp wakeup enabled. Otherwise, if the ulp int raw is already set, chip will not sleep properly. Closes https://github.com/espressif/esp-idf/issues/6229 --- components/esp_hw_support/sleep_modes.c | 6 ++++- .../hal/esp32/include/hal/rtc_cntl_ll.h | 23 ++++++++--------- .../hal/esp32s2/include/hal/rtc_cntl_ll.h | 25 +++++++++---------- .../hal/esp32s3/include/hal/rtc_cntl_ll.h | 25 +++++++++---------- components/hal/include/hal/rtc_hal.h | 2 ++ tools/ci/check_copyright_ignore.txt | 3 --- 6 files changed, 41 insertions(+), 43 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 0f3f659f38..dbd589a169 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -397,10 +397,14 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) } #endif -#ifdef CONFIG_IDF_TARGET_ESP32 +#if CONFIG_ULP_COPROC_ENABLED // Enable ULP wakeup if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) { +#ifdef CONFIG_IDF_TARGET_ESP32 rtc_hal_ulp_wakeup_enable(); +#else + rtc_hal_ulp_int_clear(); +#endif } #endif diff --git a/components/hal/esp32/include/hal/rtc_cntl_ll.h b/components/hal/esp32/include/hal/rtc_cntl_ll.h index f026da853b..31caf551bf 100644 --- a/components/hal/esp32/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -50,6 +42,11 @@ static inline void rtc_cntl_ll_ulp_wakeup_enable(void) SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); } +static inline void rtc_cntl_ll_ulp_int_clear(void) +{ + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index e1ad1d52cd..eb7a0f7e23 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -53,6 +45,13 @@ static inline void rtc_cntl_ll_ulp_wakeup_enable(void) SET_PERI_REG_BITS(RTC_CNTL_STATE0_REG, RTC_CNTL_WAKEUP_ENA_V, 0x800, RTC_CNTL_WAKEUP_ENA_S); } +static inline void rtc_cntl_ll_ulp_int_clear(void) +{ + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index 075b961aa2..f55cf7a7f0 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -133,6 +125,13 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +static inline void rtc_cntl_ll_ulp_int_clear(void) +{ + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); + REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/rtc_hal.h b/components/hal/include/hal/rtc_hal.h index c547677922..ae399f3fe3 100644 --- a/components/hal/include/hal/rtc_hal.h +++ b/components/hal/include/hal/rtc_hal.h @@ -83,3 +83,5 @@ void rtc_cntl_hal_disable_tagmem_retention(void *addr); * Enable wakeup from ULP coprocessor. */ #define rtc_hal_ulp_wakeup_enable() rtc_cntl_ll_ulp_wakeup_enable() + +#define rtc_hal_ulp_int_clear() rtc_cntl_ll_ulp_int_clear() diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index d8a4ae1131..7254950af0 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -793,7 +793,6 @@ components/hal/esp32/include/hal/dac_ll.h components/hal/esp32/include/hal/i2c_ll.h components/hal/esp32/include/hal/interrupt_controller_ll.h components/hal/esp32/include/hal/mpu_ll.h -components/hal/esp32/include/hal/rtc_cntl_ll.h components/hal/esp32/include/hal/rtc_io_ll.h components/hal/esp32/include/hal/rwdt_ll.h components/hal/esp32/include/hal/sha_ll.h @@ -850,7 +849,6 @@ components/hal/esp32s2/include/hal/interrupt_controller_ll.h components/hal/esp32s2/include/hal/memprot_ll.h components/hal/esp32s2/include/hal/memprot_peri_ll.h components/hal/esp32s2/include/hal/mpu_ll.h -components/hal/esp32s2/include/hal/rtc_cntl_ll.h components/hal/esp32s2/include/hal/rtc_io_ll.h components/hal/esp32s2/include/hal/sha_ll.h components/hal/esp32s2/include/hal/sigmadelta_ll.h @@ -868,7 +866,6 @@ components/hal/esp32s3/include/hal/i2c_ll.h components/hal/esp32s3/include/hal/interrupt_controller_ll.h components/hal/esp32s3/include/hal/memprot_ll.h components/hal/esp32s3/include/hal/mpu_ll.h -components/hal/esp32s3/include/hal/rtc_cntl_ll.h components/hal/esp32s3/include/hal/rwdt_ll.h components/hal/esp32s3/include/hal/sha_ll.h components/hal/esp32s3/include/hal/sigmadelta_ll.h From ddcc5bfe38591656e93199968cc2eae1a3dc343d Mon Sep 17 00:00:00 2001 From: jingli Date: Sat, 7 May 2022 22:58:04 +0800 Subject: [PATCH 2/4] improve ulp riscv test case Add second sleep and wakeup test in test case `ULP-RISC-V is able to wakeup main CPU from light sleep` --- .../ulp/test/ulp_riscv/test_ulp_riscv_main.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/components/ulp/test/ulp_riscv/test_ulp_riscv_main.c b/components/ulp/test/ulp_riscv/test_ulp_riscv_main.c index 15d2304c0e..b4d1963d6e 100644 --- a/components/ulp/test/ulp_riscv/test_ulp_riscv_main.c +++ b/components/ulp/test/ulp_riscv/test_ulp_riscv_main.c @@ -113,7 +113,24 @@ TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp]") while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST) ; gettimeofday(&end, NULL); - printf("Response time %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000); + printf("Response time 1st: %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000); + + /* Verify test data */ + TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST); + TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK); + + /* Enter Light Sleep again */ + TEST_ASSERT(esp_light_sleep_start() == ESP_OK); + + /* Wait for wakeup from ULP RISC-V Coprocessor */ + TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP); + + /* Wait till we receive the correct command response */ + gettimeofday(&start, NULL); + while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST) + ; + gettimeofday(&end, NULL); + printf("Response time 2nd: %jd ms\n", ((intmax_t)end.tv_sec - (intmax_t)start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000); /* Verify test data */ TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST); From abb6bb11813080fd3d62641a811c9c635dc561da Mon Sep 17 00:00:00 2001 From: jingli Date: Sat, 7 May 2022 21:52:56 +0800 Subject: [PATCH 3/4] esp_hw_support/sleep: fix cannot enable sleep reject in some cases When enable sleep reject before this fix, we have two limitations: 1. it must be light sleep 2. RTC GPIO wakeup source must be set We require light sleep because `esp_deep_sleep_start` function has been declared with "noreturn" attribute, So developers don't expect that this function may return (due to an error or a sleep reject). But the requirement for RTC GPIO wakeup source is not reasonable for all chips. This requirement exists because ESP32 only supports RTC GPIO and SDIO sleep reject sources. But later chips support all sleep reject sources. This fix brings the following changes: for ESP32: RTC GPIO and SDIO sleep reject sources can be enabled when corresponding wakeup source is set. for later chips: all sleep reject sources can be enabled when corresponding wakeup source is set. --- .../esp_hw_support/port/esp32/rtc_sleep.c | 3 +++ components/esp_hw_support/sleep_modes.c | 13 ++++++----- components/soc/esp32/include/soc/rtc.h | 12 +++++++++- components/soc/esp32c2/include/soc/rtc.h | 17 ++++++++++++-- components/soc/esp32c3/include/soc/rtc.h | 17 ++++++++++++-- components/soc/esp32h2/include/soc/rtc.h | 17 ++++++++++++-- components/soc/esp32s2/include/soc/rtc.h | 23 +++++++++++++++++-- components/soc/esp32s3/include/soc/rtc.h | 23 +++++++++++++++++-- 8 files changed, 108 insertions(+), 17 deletions(-) diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index dff1b49acd..cbac7d74e0 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -201,6 +201,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); } void rtc_sleep_low_init(uint32_t slowclk_period) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index dbd589a169..2ac1905760 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -357,6 +357,11 @@ inline static uint32_t call_rtc_sleep_start(uint32_t reject_triggers, uint32_t l //TODO: IDF-4813 bool esp_no_sleep = false; +inline static bool is_light_sleep(uint32_t pd_flags) +{ + return (pd_flags & RTC_SLEEP_PD_DIG) == 0; +} + static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) { #if CONFIG_IDF_TARGET_ESP32S3 @@ -433,15 +438,11 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) } #endif uint32_t reject_triggers = 0; - if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) { + if (is_light_sleep(pd_flags)) { /* Light sleep, enable sleep reject for faster return from this function, * in case the wakeup is already triggerred. */ -#if CONFIG_IDF_TARGET_ESP32 - reject_triggers = RTC_CNTL_LIGHT_SLP_REJECT_EN_M | RTC_CNTL_GPIO_REJECT_EN_M; -#else - reject_triggers = s_config.wakeup_triggers; -#endif + reject_triggers = s_config.wakeup_triggers & RTC_SLEEP_REJECT_MASK; } // Enter sleep diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 1ca2c4707d..e768f8c8e9 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -515,6 +515,8 @@ typedef struct rtc_sleep_config_s { uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -548,7 +550,9 @@ typedef struct rtc_sleep_config_s { : RTC_CNTL_DBIAS_0V90, \ .lslp_meminf_pd = 1, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1 \ }; #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) @@ -615,6 +619,12 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup #define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + * esp32 only supports GPIO and SDIO sleep reject sources + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | RTC_SDIO_TRIG_EN) + /** * @brief Enter deep or light sleep mode * diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h index 35616e179e..72df334bcd 100644 --- a/components/soc/esp32c2/include/soc/rtc.h +++ b/components/soc/esp32c2/include/soc/rtc.h @@ -610,8 +610,8 @@ typedef struct { uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -707,6 +707,19 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_USB_TRIG_EN BIT(14) #define RTC_BROWNOUT_DET_TRIG_EN BIT(16) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_USB_TRIG_EN | \ + RTC_BROWNOUT_DET_TRIG_EN) + /** * @brief Enter deep or light sleep mode * diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 2fbf1431d0..5acd321588 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -626,8 +626,8 @@ typedef struct { uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -723,6 +723,19 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_USB_TRIG_EN BIT(14) #define RTC_BROWNOUT_DET_TRIG_EN BIT(16) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_USB_TRIG_EN | \ + RTC_BROWNOUT_DET_TRIG_EN) + /** * @brief Enter deep or light sleep mode * diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 5bfaf03e37..ae64da5df1 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -642,8 +642,8 @@ typedef struct { uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -739,6 +739,19 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_USB_TRIG_EN BIT(14) #define RTC_BROWNOUT_DET_TRIG_EN BIT(16) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_USB_TRIG_EN | \ + RTC_BROWNOUT_DET_TRIG_EN) + /** * @brief Enter deep or light sleep mode * diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 91cad6f860..b33be653cb 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -683,8 +683,8 @@ typedef struct { uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -775,6 +775,25 @@ void rtc_sleep_low_init(uint32_t slowclk_period); #define RTC_COCPU_TRAP_TRIG_EN BIT(13) #define RTC_USB_TRIG_EN BIT(14) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_EXT0_TRIG_EN | \ + RTC_EXT1_TRIG_EN | \ + RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_SDIO_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_TOUCH_TRIG_EN | \ + RTC_ULP_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_COCPU_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_COCPU_TRAP_TRIG_EN | \ + RTC_USB_TRIG_EN) + /** * @brief Enter deep or light sleep mode * diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index c5e5b764cb..52ccfe77b4 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -633,8 +633,8 @@ typedef struct { uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject } rtc_sleep_config_t; /** @@ -737,6 +737,25 @@ void rtc_sleep_set_wakeup_time(uint64_t t); #define RTC_COCPU_TRAP_TRIG_EN BIT(13) #define RTC_USB_TRIG_EN BIT(14) +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_EXT0_TRIG_EN | \ + RTC_EXT1_TRIG_EN | \ + RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_SDIO_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_TOUCH_TRIG_EN | \ + RTC_ULP_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_COCPU_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_COCPU_TRAP_TRIG_EN | \ + RTC_USB_TRIG_EN) + /** * @brief Enter deep or light sleep mode * From a85e187ea79eafee035421074060942ae31125d7 Mon Sep 17 00:00:00 2001 From: jingli Date: Thu, 12 May 2022 21:51:21 +0800 Subject: [PATCH 4/4] remove wrong function rtc_cntl_ll_ulp_wakeup_enable for esp32s2 and esp32s3 --- components/hal/esp32s2/include/hal/rtc_cntl_ll.h | 5 ----- components/hal/esp32s3/include/hal/rtc_cntl_ll.h | 5 ----- 2 files changed, 10 deletions(-) diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index eb7a0f7e23..ffba472c47 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -40,11 +40,6 @@ static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline void rtc_cntl_ll_ulp_wakeup_enable(void) -{ - SET_PERI_REG_BITS(RTC_CNTL_STATE0_REG, RTC_CNTL_WAKEUP_ENA_V, 0x800, RTC_CNTL_WAKEUP_ENA_S); -} - static inline void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index f55cf7a7f0..3dfa5e3e71 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -44,11 +44,6 @@ static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline void rtc_cntl_ll_ulp_wakeup_enable(void) -{ - SET_PERI_REG_BITS(RTC_CNTL_STATE0_REG, RTC_CNTL_WAKEUP_ENA_V, 0x800, RTC_CNTL_WAKEUP_ENA_S); -} - static inline void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL1_REG, APB_CTRL_RETENTION_TAG_LINK_ADDR, link_addr);