From 5869850af27ce2dd376cc8212f43668a965b88fe Mon Sep 17 00:00:00 2001 From: Sachin Billore Date: Tue, 21 May 2024 15:31:09 +0530 Subject: [PATCH 1/2] feat: add esp32p4 APM HAL/LL API --- .../bootloader_support/src/bootloader_mem.c | 2 + .../esp_hw_support/sleep_system_peripheral.c | 3 + components/hal/apm_hal.c | 48 +- components/hal/esp32p4/include/hal/apm_ll.h | 433 ++++++++++++++++++ components/hal/include/hal/apm_hal.h | 93 +++- .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c6/include/soc/soc_caps.h | 1 + .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32h2/include/soc/soc_caps.h | 1 + .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32p4/include/soc/reg_base.h | 9 +- components/soc/esp32p4/include/soc/soc_caps.h | 2 +- .../soc/esp32p4/ld/esp32p4.peripherals.ld | 3 - 13 files changed, 592 insertions(+), 15 deletions(-) create mode 100644 components/hal/esp32p4/include/hal/apm_ll.h diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index 2af61961e1..d9f8466a1c 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -33,8 +33,10 @@ void bootloader_init_mem(void) * So, at boot disabling these filters. They will enable as per the * use case by TEE initialization code. */ +#ifdef SOC_APM_CTRL_FILTER_SUPPORTED apm_hal_apm_ctrl_filter_enable_all(false); #endif +#endif #if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5! // disable apm filter diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c index cd36fe7f52..2f37fb1542 100644 --- a/components/esp_hw_support/sleep_system_peripheral.c +++ b/components/esp_hw_support/sleep_system_peripheral.c @@ -39,12 +39,15 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_hp_system_retention_in #if SOC_APM_SUPPORTED static __attribute__((unused)) esp_err_t sleep_sys_periph_tee_apm_retention_init(void *arg) { +/* TBD for ESP32P4 IDF-10020. */ +#ifndef CONFIG_IDF_TARGET_ESP32P4 esp_err_t err = sleep_retention_entries_create(tee_apm_regs_retention, ARRAY_SIZE(tee_apm_regs_retention), REGDMA_LINK_PRI_NON_CRITICAL_TEE_APM, SLEEP_RETENTION_MODULE_SYS_PERIPH); if (err == ESP_OK) { err = sleep_retention_entries_create(tee_apm_highpri_regs_retention, ARRAY_SIZE(tee_apm_highpri_regs_retention), REGDMA_LINK_PRI_CRITICAL_TEE_APM, SLEEP_RETENTION_MODULE_SYS_PERIPH); } ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (%s) retention", "TEE/APM"); ESP_LOGD(TAG, "TEE/APM sleep retention initialization"); +#endif return ESP_OK; } #endif diff --git a/components/hal/apm_hal.c b/components/hal/apm_hal.c index c57c7486a2..cb08dbde48 100644 --- a/components/hal/apm_hal.c +++ b/components/hal/apm_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,50 @@ #include "hal/apm_ll.h" #include "hal/log.h" +#if CONFIG_IDF_TARGET_ESP32P4 +void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, + apm_ll_secure_mode_t sec_mode, bool enable) +{ + apm_ll_hp_peri_access_enable(master_id, hp_peri, sec_mode, enable); +} + + +void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable) +{ + apm_ll_lp_peri_access_enable(lp_peri, enable); +} + +void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr) +{ + apm_ll_peri_region_config(regn_num, regn_low_addr, regn_high_addr); +} + +int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, + uint32_t regn_num, uint32_t regn_pms) +{ + return apm_ll_peri_region_pms(master_id, sec_mode, regn_num, regn_pms); +} + +int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +{ + return apm_ll_apm_ctrl_clk_gating_enable(apm_ctrl, enable); +} + +void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr) +{ + apm_ll_dma_region_set_low_address(regn_num, regn_low_addr); + apm_ll_dma_region_set_high_address(regn_num, regn_high_addr); +} + +void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data) +{ + HAL_ASSERT(pms_data); + + apm_ll_dma_region_r_pms(pms_data->dma_master, pms_data->pms_r_mask); + apm_ll_dma_region_w_pms(pms_data->dma_master, pms_data->pms_w_mask); +} +#else + void apm_tee_hal_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode) { apm_tee_ll_set_master_secure_mode(apm_ctrl, master_id, sec_mode); @@ -129,3 +173,5 @@ esp_err_t apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path) { return apm_ll_apm_ctrl_get_int_src_num(apm_path->apm_ctrl, apm_path->apm_m_path); } + +#endif //CONFIG_IDF_TARGET_ESP32P4 diff --git a/components/hal/esp32p4/include/hal/apm_ll.h b/components/hal/esp32p4/include/hal/apm_ll.h new file mode 100644 index 0000000000..9757e44b7c --- /dev/null +++ b/components/hal/esp32p4/include/hal/apm_ll.h @@ -0,0 +1,433 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/dma_pms_reg.h" +#include "soc/hp2lp_peri_pms_reg.h" +#include "soc/hp_peri_pms_reg.h" +#include "soc/lp2hp_peri_pms_reg.h" +#include "soc/lp_peri_pms_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Master Secure Mode + */ +typedef enum { + APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode (Machine mode). */ + APM_LL_SECURE_MODE_REE = 1, /* Rich execution environment mode (User mode). */ + APM_LL_SECURE_MODE_INV = 2, /* Invalid mode. */ +} apm_ll_secure_mode_t; + +/** + * @brief Bus Masters. + */ +typedef enum { + APM_LL_MASTER_LPCPU = 0, + APM_LL_MASTER_HPCPU0, + APM_LL_MASTER_HPCPU1, + APM_LL_MASTER_DMA, +} apm_ll_master_id_t; + + +/** + * @brief APM Controller + */ +typedef enum { + LP_APM_CTRL = 0, + HP2LP_APM_CTRL, + HP_APM_CTRL, + LP2HP_APM_CTRL, + DMA_APM_CTRL, + MAX_APM_CTRL, +} apm_ll_apm_ctrl_t; + +/** + * @brief HP CPU Peripherals. + */ +typedef enum { + PMS_COREn_XM_PSRAM_ALLOW = 0, + PMS_COREn_XM_FLASH_ALLOW, + PMS_COREn_XM_L2MEM_ALLOW, + PMS_COREn_XM_L2ROM_ALLOW, + PMS_COREn_XM_TRACE0_ALLOW = 6, + PMS_COREn_XM_TRACE1_ALLOW, + PMS_COREn_XM_CPU_BUS_MON_ALLOW, + PMS_COREn_XM_L2MEM_MON_ALLOW, + PMS_COREn_XM_TCM_MON_ALLOW, + PMS_COREn_XM_CACHE_ALLOW, + + PMS_COREn_XM_HP_USBOTG_ALLOW = 32, + PMS_COREn_XM_HP_USBOTG11_ALLOW, + PMS_COREn_XM_HP_USBOTG11_WRAP_ALLOW, + PMS_COREn_XM_HP_GDMA_ALLOW, + PMS_COREn_XM_HP_SDMMC_ALLOW = 37, + PMS_COREn_XM_HP_AHB_PDMA_ALLOW, + PMS_COREn_XM_HP_JPEG_ALLOW, + PMS_COREn_XM_HP_PPA_ALLOW, + PMS_COREn_XM_HP_DMA2D_ALLOW, + PMS_COREn_XM_HP_KEY_MANAGER_ALLOW, + PMS_COREn_XM_HP_AXI_PDMA_ALLOW, + PMS_COREn_XM_HP_FLASH_ALLOW, + PMS_COREn_XM_HP_PSRAM_ALLOW, + PMS_COREn_XM_HP_CRYPTO_ALLOW, + PMS_COREn_XM_HP_GMAC_ALLOW, + PMS_COREn_XM_HP_USB_PHY_ALLOW, + PMS_COREn_XM_HP_CSI_HOST_ALLOW = 50, + PMS_COREn_XM_HP_DSI_HOST_ALLOW, + PMS_COREn_XM_HP_ISP_ALLOW, + PMS_COREn_XM_HP_H264_CORE_ALLOW, + PMS_COREn_XM_HP_RMT_ALLOW, + PMS_COREn_XM_HP_BITSRAMBLER_ALLOW, + PMS_COREn_XM_HP_AXI_ICM_ALLOW, + PMS_COREn_XM_HP_PERI_PMS_ALLOW, + PMS_COREn_XM_LP2HP_PERI_PMS_ALLOW, + PMS_COREn_XM_DMA_PMS_ALLOW, + PMS_COREn_XM_HP_H264_DMA2D_ALLOW = 60, + + PMS_COREn_XM_HP_MCPWM0_ALLOW = 64, + PMS_COREn_XM_HP_MCPWM1_ALLOW, + PMS_COREn_XM_HP_TIMER_GROUP0_ALLOW, + PMS_COREn_XM_HP_TIMER_GROUP1_ALLOW, + PMS_COREn_XM_HP_I2C0_ALLOW, + PMS_COREn_XM_HP_I2C1_ALLOW, + PMS_COREn_XM_HP_I2S0_ALLOW, + PMS_COREn_XM_HP_I2S1_ALLOW, + PMS_COREn_XM_HP_I2S2_ALLOW, + PMS_COREn_XM_HP_PCNT_ALLOW, + PMS_COREn_XM_HP_UART0_ALLOW, + PMS_COREn_XM_HP_UART1_ALLOW, + PMS_COREn_XM_HP_UART2_ALLOW, + PMS_COREn_XM_HP_UART3_ALLOW, + PMS_COREn_XM_HP_UART4_ALLOW, + PMS_COREn_XM_HP_PARLIO_ALLOW269 , + PMS_COREn_XM_HP_GPSPI2_ALLOW270 , + PMS_COREn_XM_HP_GPSPI3_ALLOW271 , + PMS_COREn_XM_HP_USBDEVICE_ALLOW, + PMS_COREn_XM_HP_LEDC_ALLOW, + PMS_COREn_XM_HP_ETM_ALLOW = 85, + PMS_COREn_XM_HP_INTRMTX_ALLOW, + PMS_COREn_XM_HP_TWAI0_ALLOW, + PMS_COREn_XM_HP_TWAI1_ALLOW, + PMS_COREn_XM_HP_TWAI2_ALLOW, + PMS_COREn_XM_HP_I3C_MST_ALLOW, + PMS_COREn_XM_HP_I3C_SLV_ALLOW, + PMS_COREn_XM_HP_LCDCAM_ALLOW, + PMS_COREn_XM_HP_ADC_ALLOW = 94, + PMS_COREn_XM_HP_UHCI_ALLOW, + + PMS_COREn_XM_HP_GPIO_ALLOW = 96, + PMS_COREn_XM_HP_IOMUX_ALLOW, + PMS_COREn_XM_HP_SYSTIMER_ALLOW, + PMS_COREn_XM_HP_SYS_REG_ALLOW, + PMS_COREn_XM_HP_CLKRST_ALLOW, + PMS_COREn_XM_HP_PERI_MAX, +} apm_ll_hp_peri_t; + + +/** + * @brief LP CPU Peripherals. + */ +typedef enum { + PMS_MM_LP_SYSREG_ALLOW = 0, + PMS_MM_LP_AONCLKRST_ALLOW, + PMS_MM_LP_TIMER_ALLOW, + PMS_MM_LP_ANAPERI_ALLOW, + PMS_MM_LP_PMU_ALLOW, + PMS_MM_LP_WDT_ALLOW, + PMS_MM_LP_MAILBOX_ALLOW, + PMS_MM_LP_PERICLKRST_ALLOW = 8, + PMS_MM_LP_UART_ALLOW, + PMS_MM_LP_I2C_ALLOW, + PMS_MM_LP_SPI_ALLOW, + PMS_MM_LP_I2CMST_ALLOW, + PMS_MM_LP_I2S_ALLOW, + PMS_MM_LP_ADC_ALLOW, + PMS_MM_LP_TOUCH_ALLOW, + PMS_MM_LP_IOMUX_ALLOW, + PMS_MM_LP_INTR_ALLOW, + PMS_MM_LP_EFUSE_ALLOW, + PMS_MM_LP_PMS_ALLOW, + PMS_MM_HP2LP_PMS_ALLOW, + PMS_MM_LP_TSENS_ALLOW, + PMS_MM_LP_HUK_ALLOW, + PMS_HP_COREn_MM_LP_SRAM_ALLOW, + PMS_LP_MM_PERI_MAX, +} apm_ll_lp_peri_t; + + +/** + * @brief LP CPU Peripherals. + */ +typedef enum { + PMS_DMA_GDMA_CH0 = 0, + PMS_DMA_GDMA_CH1, + PMS_DMA_GDMA_CH2, + PMS_DMA_GDMA_CH3, + PMS_DMA_AHB_PDMA_ADC, + PMS_DMA_AHB_PDMA_I2S0, + PMS_DMA_AHB_PDMA_I2S1, + PMS_DMA_AHB_PDMA_I2S2, + PMS_DMA_AHB_PDMA_I3C_MST, + PMS_DMA_AHB_PDMA_UHCI0, + PMS_DMA_AHB_PDMA_RMT, + PMS_DMA_AXI_PDMA_LCDCAM, + PMS_DMA_AXI_PDMA_GPSPI2, + PMS_DMA_AXI_PDMA_GPSPI3, + PMS_DMA_AXI_PDMA_PARLIO, + PMS_DMA_AXI_PDMA_AES, + PMS_DMA_AXI_PDMA_SHA, + PMS_DMA_DMA2D_JPEG, + PMS_DMA_USB, + PMS_DMA_GMAC, + PMS_DMA_SDMMC, + PMS_DMA_USBOTG11, + PMS_DMA_TRACE0, + PMS_DMA_TRACE1, + PMS_DMA_L2MEM_MON, + PMS_DMA_TCM_MON, + PMS_DMA_H264, + PMS_DMA_DMA2D_PPA, + PMS_DMA_DMA2D_DUMMY, + PMS_DMA_AHB_PDMA_DUMMY, + PMS_DMA_AXI_PDMA_DUMMY, + PMS_DMA_MAX, +} apm_ll_dma_master_t; + +#define PMS_PERI_MAX_REGION_NUM 2 +#define PMS_DMA_MAX_REGION_NUM 32 + +#define PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri) \ + ({\ + (PMS_CORE0_MM_HP_PERI_PMS_REG0_REG + (master_id * 0x20) \ + + (sec_mode * 0x10) + ((hp_peri/32) * 0x4) ); \ + }) + +#define PMS_PERI_REGION_LOW_REG(regn_num) \ + ({\ + (PMS_PERI_REGION0_LOW_REG + (regn_num * 8)); \ + }) + + +#define PMS_PERI_REGION_HIGH_REG(regn_num) \ + ({\ + (PMS_PERI_REGION0_HIGH_REG + (regn_num * 8)); \ + }) + +#define PMS_DMA_PMS_R_REG(dma_master) \ + ({\ + (PMS_DMA_GDMA_CH0_R_PMS_REG + (dma_master * 8)); \ + }) + +#define PMS_DMA_PMS_W_REG(dma_master) \ + ({\ + (PMS_DMA_GDMA_CH0_W_PMS_REG + (dma_master * 8)); \ + }) + + +/** + * @brief Configure HP peripherals access permission for the HP CPU0/1. + * + * @param master_id HP CPU0/1 + * @param hp_peri HP peripheral whose access permission to be configured. + * @param enable Permission enable/disable + */ +static inline void apm_ll_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, + apm_ll_secure_mode_t sec_mode, bool enable) +{ + HAL_ASSERT((master_id > APM_LL_MASTER_LPCPU) && (master_id < APM_LL_MASTER_DMA) + && (hp_peri < PMS_COREn_XM_HP_PERI_MAX) && (sec_mode < APM_LL_SECURE_MODE_INV)); + + if (enable) { + REG_SET_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri%32)); + } else { + REG_CLR_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri%32)); + } +} + +/** + * @brief Configure LP peripherals access permission for the LP CPU. + * + * @param lp_peri LP peripheral whose access permission to be configured. + * @param enable Permission enable/disable + */ +static inline void apm_ll_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable) +{ + HAL_ASSERT(lp_peri < PMS_LP_MM_PERI_MAX); + + if (enable) { + REG_SET_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(lp_peri)); + } else { + REG_CLR_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(lp_peri)); + } +} + +/** + * @brief Configure peripherals configurable address ranges. + * + * @param regn_num Configurable address range number. + * @param regn_low_addr Configurable address range start address. + * @param regn_high_addr Configurable address range end address. + */ +static inline void apm_ll_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, + uint32_t regn_high_addr) +{ + HAL_ASSERT(regn_num < PMS_PERI_MAX_REGION_NUM); + + REG_WRITE(PMS_PERI_REGION_LOW_REG(regn_num), regn_low_addr); + REG_WRITE(PMS_PERI_REGION_HIGH_REG(regn_num), regn_high_addr); +} + +/** + * @brief Configure peripherals configurable address ranges. + * + * @param master_id LP CPU and HP CPU0/1 + * @param sec_mode CPU privilege mode (Machine/User) which corresponds to (TEE/REE). + * @param regn_num Configurable address range number. + * @param regn_pms Configurable address range permission setting(2-bits field). + * Bit 0: Region 0 permission enable/disable. + * Bit 1: Region 1 permission enable/disable. + * @return Configuration performed successfully? + */ +static inline int apm_ll_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, + uint32_t regn_num, uint32_t regn_pms) +{ + HAL_ASSERT((master_id < APM_LL_MASTER_DMA) && (sec_mode < APM_LL_SECURE_MODE_INV)); + + regn_pms &= 0x3; + + switch(master_id) { + case APM_LL_MASTER_LPCPU: + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_pms); + break; + case APM_LL_MASTER_HPCPU0: + if (sec_mode) { + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn_pms); + } else { + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn_pms); + } + break; + case APM_LL_MASTER_HPCPU1: + if (sec_mode) { + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn_pms); + } else { + REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn_pms); + } + break; + default: + return -1; + } + + return 0; +} + +/** + * @brief Configure APM controller clock gating. + * + * @param apm_ctrl APM controller (LP_PERI/HP_PERI/HP_DMA/LP2HP_PERI/HP2LP_PERI). + * @param enable Permission enable/disable. + * enable: Enable automatic clock gating. + * disable: Keep the clock always on. + */ +static inline int apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +{ + uint32_t reg = 0; + + HAL_ASSERT(apm_ctrl < MAX_APM_CTRL); + + switch(apm_ctrl) { + case LP_APM_CTRL: + reg = PMS_LP_PERI_PMS_CLK_EN_REG; + break; + case HP2LP_APM_CTRL: + reg = PMS_HP2LP_PERI_PMS_CLK_EN_REG; + break; + case HP_APM_CTRL: + reg = PMS_HP_PERI_PMS_CLK_EN_REG; + break; + case LP2HP_APM_CTRL: + reg = PMS_LP2HP_PERI_PMS_CLK_EN_REG; + break; + case DMA_APM_CTRL: + reg = PMS_DMA_CLK_EN_REG; + break; + default: + return -1; + } + + if (enable) { + REG_CLR_BIT(reg, BIT(0)); + } else { + REG_SET_BIT(reg, BIT(0)); + } + + return 0; +} + +/** + * @brief Configure DMA configurable address range low address. + * + * @param regn_num Configurable DMA address range number. + * @param regn_low_addr Configurable DMA address range start address. + */ +static inline void apm_ll_dma_region_set_low_address(uint32_t regn_num, uint32_t regn_low_addr) +{ + HAL_ASSERT(regn_num < PMS_DMA_MAX_REGION_NUM); + + REG_WRITE((PMS_DMA_REGION0_LOW_REG + (regn_num * 8)), regn_low_addr); +} + +/** + * @brief Configure DMA configurable address range high address. + * + * @param regn_num Configurable DMA address range number. + * @param regn_high_addr Configurable DMA address range end address. + */ +static inline void apm_ll_dma_region_set_high_address(uint32_t regn_num, uint32_t regn_high_addr) +{ + HAL_ASSERT(regn_num < PMS_DMA_MAX_REGION_NUM); + + REG_WRITE((PMS_DMA_REGION0_HIGH_REG + (regn_num * 8)), regn_high_addr); +} + +/** + * @brief Configure DMA configurable address range read permission. + * + * @param dma_master DMA master whose access permission to be configured. + * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. + * 0: Disable read permission. + * 1: Enable read permission. + */ +static inline void apm_ll_dma_region_r_pms(apm_ll_dma_master_t dma_master, uint32_t regn_mask) +{ + HAL_ASSERT(dma_master < PMS_DMA_MAX); + + REG_WRITE(PMS_DMA_PMS_R_REG(dma_master), regn_mask); +} + +/** + * @brief Configure DMA configurable address range write permission. + * + * @param dma_master DMA master whose access permission to be configured. + * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. + * 0: Disable write permission. + * 1: Enable write permission. + */ +static inline void apm_ll_dma_region_w_pms(apm_ll_dma_master_t dma_master, uint32_t regn_mask) +{ + HAL_ASSERT(dma_master < PMS_DMA_MAX); + + REG_WRITE(PMS_DMA_PMS_W_REG(dma_master), regn_mask); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/apm_hal.h b/components/hal/include/hal/apm_hal.h index 16d32d534f..6f8b6eb5e9 100644 --- a/components/hal/include/hal/apm_hal.h +++ b/components/hal/include/hal/apm_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,93 @@ extern "C" { #if SOC_APM_SUPPORTED #include "hal/apm_ll.h" +#if CONFIG_IDF_TARGET_ESP32P4 + +/** + * @brief DMA configurable region configuration data. + */ +typedef struct { + apm_ll_dma_master_t dma_master; /* DMA master whose access permission to be configured.*/ + uint32_t pms_r_mask; /* Read permission mask. */ + uint32_t pms_w_mask; /* Write permission mask. */ +} apm_hal_dma_region_config_data_t; + +/** + * @brief Configure HP peripherals access permission for the HP CPU0/1. + * + * @param master_id HP CPU0/1 + * @param hp_peri HP peripheral whose access permission to be configured. + * @param enable Permission enable/disable + */ +void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri, + apm_ll_secure_mode_t sec_mode, bool enable); + +/** + * @brief Configure LP peripherals access permission for the LP CPU. + * + * @param lp_peri LP peripheral whose access permission to be configured. + * @param enable Permission enable/disable + */ +void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable); + +/** + * @brief Configure peripherals configurable address ranges. + * + * @param regn_num Configurable address range number. + * @param regn_low_addr Configurable address range start address. + * @param regn_high_addr Configurable address range end address. + */ +void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, + uint32_t regn_high_addr); + +/** + * @brief Configure peripherals configurable address ranges. + * + * @param master_id LP CPU and HP CPU0/1 + * @param sec_mode CPU privilege mode (Machine/User) which corresponds to (TEE/REE). + * @param regn_num Configurable address range number. + * @param regn_pms Configurable address range permission setting(2-bits field). + * Bit 0: Region 0 permission enable/disable. + * Bit 1: Region 1 permission enable/disable. + * @return Configuration performed successfully? + */ +int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode, + uint32_t regn_num, uint32_t regn_pms); + +/** + * @brief Configure APM controller clock gating. + * + * @param apm_ctrl APM controller (LP_PERI/HP_PERI/HP_DMA/LP2HP_PERI/HP2LP_PERI). + * @param enable Permission enable/disable. + * enable: Enable automatic clock gating. + * disable: Keep the clock always on. + * @return Clock gating set successfully? + */ +int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable); + +/** + * @brief Configure DMA configurable address range low address. + * + * @param regn_num Configurable DMA address range number. + * @param regn_low_addr Configurable DMA address range start address. + * @param regn_high_addr Configurable DMA address range end address. + */ +void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr); + +/** + * @brief Configure DMA configurable address range read permission. + * + * @param pms_data DMA configurable region configuration data. + * @param dma_master DMA master whose access permission to be configured. + * @param regn_mask 32-bits field, each bit for corresponding DMA configurable address range permission. + * 0: Disable read permission. + * 1: Enable read permission. + */ +void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data); + + +#else + /** * @brief Region configuration data. */ @@ -157,7 +244,9 @@ void apm_hal_apm_ctrl_reset_event_enable(bool enable); */ esp_err_t apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); -#endif +#endif //CONFIG_IDF_TARGET_ESP32P4 + +#endif //SOC_APM_SUPPORTED #ifdef __cplusplus } diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index f3f3df1034..044e3b9018 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -179,6 +179,10 @@ config SOC_APM_SUPPORTED bool default y +config SOC_APM_CTRL_FILTER_SUPPORTED + bool + default y + config SOC_PMU_SUPPORTED bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index c16ebceee4..7ecbc89d4c 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -61,6 +61,7 @@ #define SOC_SDIO_SLAVE_SUPPORTED 1 #define SOC_BOD_SUPPORTED 1 #define SOC_APM_SUPPORTED 1 +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 9ebdecb32c..e7175ce72d 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -179,6 +179,10 @@ config SOC_APM_SUPPORTED bool default y +config SOC_APM_CTRL_FILTER_SUPPORTED + bool + default y + config SOC_PMU_SUPPORTED bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 8728e3f730..ea7c186088 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -61,6 +61,7 @@ #define SOC_SECURE_BOOT_SUPPORTED 1 #define SOC_BOD_SUPPORTED 1 #define SOC_APM_SUPPORTED 1 +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 #define SOC_LP_AON_SUPPORTED 1 diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 7c9036b62b..de14345481 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -207,6 +207,10 @@ config SOC_BOD_SUPPORTED bool default y +config SOC_APM_SUPPORTED + bool + default y + config SOC_PMU_SUPPORTED bool default y diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h index f851cb5c74..4c2bbc2c7e 100644 --- a/components/soc/esp32p4/include/soc/reg_base.h +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -195,13 +195,6 @@ #define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE #define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE -//TODO: IDF-7542 -// #define DR_REG_TEE_BASE 0x60098000 -// #define DR_REG_HP_APM_BASE 0x60099000 -// #define DR_REG_LP_APM0_BASE 0x60099800 -// #define DR_REG_LP_TEE_BASE 0x600B3400 -// #define DR_REG_LP_APM_BASE 0x600B3800 - #define DR_REG_PAU_BASE DR_REG_REGDMA_BASE //TODO: IDF-7688 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 60f0faa36f..8adbc6b698 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -69,7 +69,7 @@ #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 #define SOC_BOD_SUPPORTED 1 -// #define SOC_APM_SUPPORTED 1 //TODO: IDF-7542 +#define SOC_APM_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_DCDC_SUPPORTED 1 #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531 diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 0b293ba89e..f8aaaf3fef 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -68,8 +68,6 @@ PROVIDE ( MSPI_IOMUX = 0x500E1200 ); PROVIDE ( HP_SYSTEM = 0x500E5000 ); PROVIDE ( HP_SYS_CLKRST = 0x500E6000 ); -PROVIDE ( TEE = 0x60098000 ); /* TODO: IDF-7542 */ -PROVIDE ( HP_APM = 0x60099000 ); /* TODO: IDF-7542 */ PROVIDE ( PMU = 0x50115000 ); PROVIDE ( LP_SYS = 0x50110000 ); @@ -89,7 +87,6 @@ PROVIDE ( LP_PERI_PMS = 0x5012E000 ); PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 ); PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); PROVIDE ( LP_ANA_PERI = 0x50113000 ); -PROVIDE ( LP_APM = 0x600B3800 ); /* TODO: IDF-7542 */ PROVIDE ( AHB_DMA = 0x50085000 ); PROVIDE ( AXI_DMA = 0x5008a000 ); PROVIDE ( LCD_CAM = 0x500dc000 ); From f7faae7c2d59e8a381f201fa05e537c0a953b746 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 20 May 2024 22:41:32 +0800 Subject: [PATCH 2/2] fix(soc): fix the pms reg headers base addr --- .../soc/esp32p4/include/soc/dma_pms_reg.h | 260 +++++++++--------- .../esp32p4/include/soc/hp2lp_peri_pms_reg.h | 14 +- .../soc/esp32p4/include/soc/hp_peri_pms_reg.h | 38 +-- .../esp32p4/include/soc/lp2hp_peri_pms_reg.h | 12 +- .../soc/esp32p4/include/soc/lp_peri_pms_reg.h | 16 +- 5 files changed, 170 insertions(+), 170 deletions(-) diff --git a/components/soc/esp32p4/include/soc/dma_pms_reg.h b/components/soc/esp32p4/include/soc/dma_pms_reg.h index 273935329d..d985c15a13 100644 --- a/components/soc/esp32p4/include/soc/dma_pms_reg.h +++ b/components/soc/esp32p4/include/soc/dma_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { /** PMS_DMA_DATE_REG register * Version control register */ -#define PMS_DMA_DATE_REG (DR_REG_PMS_DMA_BASE + 0x0) +#define PMS_DMA_DATE_REG (DR_REG_DMA_PMS_BASE + 0x0) /** PMS_DMA_DATE : R/W; bitpos: [31:0]; default: 539165460; * Version control register. */ @@ -26,7 +26,7 @@ extern "C" { /** PMS_DMA_CLK_EN_REG register * Clock gating register */ -#define PMS_DMA_CLK_EN_REG (DR_REG_PMS_DMA_BASE + 0x4) +#define PMS_DMA_CLK_EN_REG (DR_REG_DMA_PMS_BASE + 0x4) /** PMS_DMA_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: Enable automatic clock gating. @@ -40,7 +40,7 @@ extern "C" { /** PMS_DMA_REGION0_LOW_REG register * Region0 start address configuration register */ -#define PMS_DMA_REGION0_LOW_REG (DR_REG_PMS_DMA_BASE + 0x8) +#define PMS_DMA_REGION0_LOW_REG (DR_REG_DMA_PMS_BASE + 0x8) /** PMS_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region0. */ @@ -52,7 +52,7 @@ extern "C" { /** PMS_DMA_REGION0_HIGH_REG register * Region0 end address configuration register */ -#define PMS_DMA_REGION0_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xc) +#define PMS_DMA_REGION0_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc) /** PMS_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region0. */ @@ -64,7 +64,7 @@ extern "C" { /** PMS_DMA_REGION1_LOW_REG register * Region1 start address configuration register */ -#define PMS_DMA_REGION1_LOW_REG (DR_REG_PMS_DMA_BASE + 0x10) +#define PMS_DMA_REGION1_LOW_REG (DR_REG_DMA_PMS_BASE + 0x10) /** PMS_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region1. */ @@ -76,7 +76,7 @@ extern "C" { /** PMS_DMA_REGION1_HIGH_REG register * Region1 end address configuration register */ -#define PMS_DMA_REGION1_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x14) +#define PMS_DMA_REGION1_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x14) /** PMS_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region1. */ @@ -88,7 +88,7 @@ extern "C" { /** PMS_DMA_REGION2_LOW_REG register * Region2 start address configuration register */ -#define PMS_DMA_REGION2_LOW_REG (DR_REG_PMS_DMA_BASE + 0x18) +#define PMS_DMA_REGION2_LOW_REG (DR_REG_DMA_PMS_BASE + 0x18) /** PMS_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region2. */ @@ -100,7 +100,7 @@ extern "C" { /** PMS_DMA_REGION2_HIGH_REG register * Region2 end address configuration register */ -#define PMS_DMA_REGION2_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x1c) +#define PMS_DMA_REGION2_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x1c) /** PMS_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region2. */ @@ -112,7 +112,7 @@ extern "C" { /** PMS_DMA_REGION3_LOW_REG register * Region3 start address configuration register */ -#define PMS_DMA_REGION3_LOW_REG (DR_REG_PMS_DMA_BASE + 0x20) +#define PMS_DMA_REGION3_LOW_REG (DR_REG_DMA_PMS_BASE + 0x20) /** PMS_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region3. */ @@ -124,7 +124,7 @@ extern "C" { /** PMS_DMA_REGION3_HIGH_REG register * Region3 end address configuration register */ -#define PMS_DMA_REGION3_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x24) +#define PMS_DMA_REGION3_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x24) /** PMS_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region3. */ @@ -136,7 +136,7 @@ extern "C" { /** PMS_DMA_REGION4_LOW_REG register * Region4 start address configuration register */ -#define PMS_DMA_REGION4_LOW_REG (DR_REG_PMS_DMA_BASE + 0x28) +#define PMS_DMA_REGION4_LOW_REG (DR_REG_DMA_PMS_BASE + 0x28) /** PMS_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region4. */ @@ -148,7 +148,7 @@ extern "C" { /** PMS_DMA_REGION4_HIGH_REG register * Region4 end address configuration register */ -#define PMS_DMA_REGION4_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x2c) +#define PMS_DMA_REGION4_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x2c) /** PMS_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region4. */ @@ -160,7 +160,7 @@ extern "C" { /** PMS_DMA_REGION5_LOW_REG register * Region5 start address configuration register */ -#define PMS_DMA_REGION5_LOW_REG (DR_REG_PMS_DMA_BASE + 0x30) +#define PMS_DMA_REGION5_LOW_REG (DR_REG_DMA_PMS_BASE + 0x30) /** PMS_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region5. */ @@ -172,7 +172,7 @@ extern "C" { /** PMS_DMA_REGION5_HIGH_REG register * Region5 end address configuration register */ -#define PMS_DMA_REGION5_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x34) +#define PMS_DMA_REGION5_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x34) /** PMS_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region5. */ @@ -184,7 +184,7 @@ extern "C" { /** PMS_DMA_REGION6_LOW_REG register * Region6 start address configuration register */ -#define PMS_DMA_REGION6_LOW_REG (DR_REG_PMS_DMA_BASE + 0x38) +#define PMS_DMA_REGION6_LOW_REG (DR_REG_DMA_PMS_BASE + 0x38) /** PMS_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region6. */ @@ -196,7 +196,7 @@ extern "C" { /** PMS_DMA_REGION6_HIGH_REG register * Region6 end address configuration register */ -#define PMS_DMA_REGION6_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x3c) +#define PMS_DMA_REGION6_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x3c) /** PMS_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region6. */ @@ -208,7 +208,7 @@ extern "C" { /** PMS_DMA_REGION7_LOW_REG register * Region7 start address configuration register */ -#define PMS_DMA_REGION7_LOW_REG (DR_REG_PMS_DMA_BASE + 0x40) +#define PMS_DMA_REGION7_LOW_REG (DR_REG_DMA_PMS_BASE + 0x40) /** PMS_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region7. */ @@ -220,7 +220,7 @@ extern "C" { /** PMS_DMA_REGION7_HIGH_REG register * Region7 end address configuration register */ -#define PMS_DMA_REGION7_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x44) +#define PMS_DMA_REGION7_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x44) /** PMS_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region7. */ @@ -232,7 +232,7 @@ extern "C" { /** PMS_DMA_REGION8_LOW_REG register * Region8 start address configuration register */ -#define PMS_DMA_REGION8_LOW_REG (DR_REG_PMS_DMA_BASE + 0x48) +#define PMS_DMA_REGION8_LOW_REG (DR_REG_DMA_PMS_BASE + 0x48) /** PMS_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region8. */ @@ -244,7 +244,7 @@ extern "C" { /** PMS_DMA_REGION8_HIGH_REG register * Region8 end address configuration register */ -#define PMS_DMA_REGION8_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x4c) +#define PMS_DMA_REGION8_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x4c) /** PMS_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region8. */ @@ -256,7 +256,7 @@ extern "C" { /** PMS_DMA_REGION9_LOW_REG register * Region9 start address configuration register */ -#define PMS_DMA_REGION9_LOW_REG (DR_REG_PMS_DMA_BASE + 0x50) +#define PMS_DMA_REGION9_LOW_REG (DR_REG_DMA_PMS_BASE + 0x50) /** PMS_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region9. */ @@ -268,7 +268,7 @@ extern "C" { /** PMS_DMA_REGION9_HIGH_REG register * Region9 end address configuration register */ -#define PMS_DMA_REGION9_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x54) +#define PMS_DMA_REGION9_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x54) /** PMS_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region9. */ @@ -280,7 +280,7 @@ extern "C" { /** PMS_DMA_REGION10_LOW_REG register * Region10 start address configuration register */ -#define PMS_DMA_REGION10_LOW_REG (DR_REG_PMS_DMA_BASE + 0x58) +#define PMS_DMA_REGION10_LOW_REG (DR_REG_DMA_PMS_BASE + 0x58) /** PMS_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region10. */ @@ -292,7 +292,7 @@ extern "C" { /** PMS_DMA_REGION10_HIGH_REG register * Region10 end address configuration register */ -#define PMS_DMA_REGION10_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x5c) +#define PMS_DMA_REGION10_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x5c) /** PMS_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region10. */ @@ -304,7 +304,7 @@ extern "C" { /** PMS_DMA_REGION11_LOW_REG register * Region11 start address configuration register */ -#define PMS_DMA_REGION11_LOW_REG (DR_REG_PMS_DMA_BASE + 0x60) +#define PMS_DMA_REGION11_LOW_REG (DR_REG_DMA_PMS_BASE + 0x60) /** PMS_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region11. */ @@ -316,7 +316,7 @@ extern "C" { /** PMS_DMA_REGION11_HIGH_REG register * Region11 end address configuration register */ -#define PMS_DMA_REGION11_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x64) +#define PMS_DMA_REGION11_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x64) /** PMS_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region11. */ @@ -328,7 +328,7 @@ extern "C" { /** PMS_DMA_REGION12_LOW_REG register * Region12 start address configuration register */ -#define PMS_DMA_REGION12_LOW_REG (DR_REG_PMS_DMA_BASE + 0x68) +#define PMS_DMA_REGION12_LOW_REG (DR_REG_DMA_PMS_BASE + 0x68) /** PMS_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region12. */ @@ -340,7 +340,7 @@ extern "C" { /** PMS_DMA_REGION12_HIGH_REG register * Region12 end address configuration register */ -#define PMS_DMA_REGION12_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x6c) +#define PMS_DMA_REGION12_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x6c) /** PMS_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region12. */ @@ -352,7 +352,7 @@ extern "C" { /** PMS_DMA_REGION13_LOW_REG register * Region13 start address configuration register */ -#define PMS_DMA_REGION13_LOW_REG (DR_REG_PMS_DMA_BASE + 0x70) +#define PMS_DMA_REGION13_LOW_REG (DR_REG_DMA_PMS_BASE + 0x70) /** PMS_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region13. */ @@ -364,7 +364,7 @@ extern "C" { /** PMS_DMA_REGION13_HIGH_REG register * Region13 end address configuration register */ -#define PMS_DMA_REGION13_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x74) +#define PMS_DMA_REGION13_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x74) /** PMS_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region13. */ @@ -376,7 +376,7 @@ extern "C" { /** PMS_DMA_REGION14_LOW_REG register * Region14 start address configuration register */ -#define PMS_DMA_REGION14_LOW_REG (DR_REG_PMS_DMA_BASE + 0x78) +#define PMS_DMA_REGION14_LOW_REG (DR_REG_DMA_PMS_BASE + 0x78) /** PMS_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region14. */ @@ -388,7 +388,7 @@ extern "C" { /** PMS_DMA_REGION14_HIGH_REG register * Region14 end address configuration register */ -#define PMS_DMA_REGION14_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x7c) +#define PMS_DMA_REGION14_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x7c) /** PMS_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region14. */ @@ -400,7 +400,7 @@ extern "C" { /** PMS_DMA_REGION15_LOW_REG register * Region15 start address configuration register */ -#define PMS_DMA_REGION15_LOW_REG (DR_REG_PMS_DMA_BASE + 0x80) +#define PMS_DMA_REGION15_LOW_REG (DR_REG_DMA_PMS_BASE + 0x80) /** PMS_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region15. */ @@ -412,7 +412,7 @@ extern "C" { /** PMS_DMA_REGION15_HIGH_REG register * Region15 end address configuration register */ -#define PMS_DMA_REGION15_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x84) +#define PMS_DMA_REGION15_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x84) /** PMS_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region15. */ @@ -424,7 +424,7 @@ extern "C" { /** PMS_DMA_REGION16_LOW_REG register * Region16 start address configuration register */ -#define PMS_DMA_REGION16_LOW_REG (DR_REG_PMS_DMA_BASE + 0x88) +#define PMS_DMA_REGION16_LOW_REG (DR_REG_DMA_PMS_BASE + 0x88) /** PMS_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region16. */ @@ -436,7 +436,7 @@ extern "C" { /** PMS_DMA_REGION16_HIGH_REG register * Region16 end address configuration register */ -#define PMS_DMA_REGION16_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x8c) +#define PMS_DMA_REGION16_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x8c) /** PMS_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region16. */ @@ -448,7 +448,7 @@ extern "C" { /** PMS_DMA_REGION17_LOW_REG register * Region17 start address configuration register */ -#define PMS_DMA_REGION17_LOW_REG (DR_REG_PMS_DMA_BASE + 0x90) +#define PMS_DMA_REGION17_LOW_REG (DR_REG_DMA_PMS_BASE + 0x90) /** PMS_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region17. */ @@ -460,7 +460,7 @@ extern "C" { /** PMS_DMA_REGION17_HIGH_REG register * Region17 end address configuration register */ -#define PMS_DMA_REGION17_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x94) +#define PMS_DMA_REGION17_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x94) /** PMS_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region17. */ @@ -472,7 +472,7 @@ extern "C" { /** PMS_DMA_REGION18_LOW_REG register * Region18 start address configuration register */ -#define PMS_DMA_REGION18_LOW_REG (DR_REG_PMS_DMA_BASE + 0x98) +#define PMS_DMA_REGION18_LOW_REG (DR_REG_DMA_PMS_BASE + 0x98) /** PMS_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region18. */ @@ -484,7 +484,7 @@ extern "C" { /** PMS_DMA_REGION18_HIGH_REG register * Region18 end address configuration register */ -#define PMS_DMA_REGION18_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x9c) +#define PMS_DMA_REGION18_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x9c) /** PMS_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region18. */ @@ -496,7 +496,7 @@ extern "C" { /** PMS_DMA_REGION19_LOW_REG register * Region19 start address configuration register */ -#define PMS_DMA_REGION19_LOW_REG (DR_REG_PMS_DMA_BASE + 0xa0) +#define PMS_DMA_REGION19_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa0) /** PMS_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region19. */ @@ -508,7 +508,7 @@ extern "C" { /** PMS_DMA_REGION19_HIGH_REG register * Region19 end address configuration register */ -#define PMS_DMA_REGION19_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xa4) +#define PMS_DMA_REGION19_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xa4) /** PMS_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region19. */ @@ -520,7 +520,7 @@ extern "C" { /** PMS_DMA_REGION20_LOW_REG register * Region20 start address configuration register */ -#define PMS_DMA_REGION20_LOW_REG (DR_REG_PMS_DMA_BASE + 0xa8) +#define PMS_DMA_REGION20_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa8) /** PMS_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region20. */ @@ -532,7 +532,7 @@ extern "C" { /** PMS_DMA_REGION20_HIGH_REG register * Region20 end address configuration register */ -#define PMS_DMA_REGION20_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xac) +#define PMS_DMA_REGION20_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xac) /** PMS_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region20. */ @@ -544,7 +544,7 @@ extern "C" { /** PMS_DMA_REGION21_LOW_REG register * Region21 start address configuration register */ -#define PMS_DMA_REGION21_LOW_REG (DR_REG_PMS_DMA_BASE + 0xb0) +#define PMS_DMA_REGION21_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb0) /** PMS_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region21. */ @@ -556,7 +556,7 @@ extern "C" { /** PMS_DMA_REGION21_HIGH_REG register * Region21 end address configuration register */ -#define PMS_DMA_REGION21_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xb4) +#define PMS_DMA_REGION21_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xb4) /** PMS_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region21. */ @@ -568,7 +568,7 @@ extern "C" { /** PMS_DMA_REGION22_LOW_REG register * Region22 start address configuration register */ -#define PMS_DMA_REGION22_LOW_REG (DR_REG_PMS_DMA_BASE + 0xb8) +#define PMS_DMA_REGION22_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb8) /** PMS_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region22. */ @@ -580,7 +580,7 @@ extern "C" { /** PMS_DMA_REGION22_HIGH_REG register * Region22 end address configuration register */ -#define PMS_DMA_REGION22_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xbc) +#define PMS_DMA_REGION22_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xbc) /** PMS_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region22. */ @@ -592,7 +592,7 @@ extern "C" { /** PMS_DMA_REGION23_LOW_REG register * Region23 start address configuration register */ -#define PMS_DMA_REGION23_LOW_REG (DR_REG_PMS_DMA_BASE + 0xc0) +#define PMS_DMA_REGION23_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc0) /** PMS_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region23. */ @@ -604,7 +604,7 @@ extern "C" { /** PMS_DMA_REGION23_HIGH_REG register * Region23 end address configuration register */ -#define PMS_DMA_REGION23_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xc4) +#define PMS_DMA_REGION23_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc4) /** PMS_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region23. */ @@ -616,7 +616,7 @@ extern "C" { /** PMS_DMA_REGION24_LOW_REG register * Region24 start address configuration register */ -#define PMS_DMA_REGION24_LOW_REG (DR_REG_PMS_DMA_BASE + 0xc8) +#define PMS_DMA_REGION24_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc8) /** PMS_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region24. */ @@ -628,7 +628,7 @@ extern "C" { /** PMS_DMA_REGION24_HIGH_REG register * Region24 end address configuration register */ -#define PMS_DMA_REGION24_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xcc) +#define PMS_DMA_REGION24_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xcc) /** PMS_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region24. */ @@ -640,7 +640,7 @@ extern "C" { /** PMS_DMA_REGION25_LOW_REG register * Region25 start address configuration register */ -#define PMS_DMA_REGION25_LOW_REG (DR_REG_PMS_DMA_BASE + 0xd0) +#define PMS_DMA_REGION25_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd0) /** PMS_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region25. */ @@ -652,7 +652,7 @@ extern "C" { /** PMS_DMA_REGION25_HIGH_REG register * Region25 end address configuration register */ -#define PMS_DMA_REGION25_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xd4) +#define PMS_DMA_REGION25_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xd4) /** PMS_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region25. */ @@ -664,7 +664,7 @@ extern "C" { /** PMS_DMA_REGION26_LOW_REG register * Region26 start address configuration register */ -#define PMS_DMA_REGION26_LOW_REG (DR_REG_PMS_DMA_BASE + 0xd8) +#define PMS_DMA_REGION26_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd8) /** PMS_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region26. */ @@ -676,7 +676,7 @@ extern "C" { /** PMS_DMA_REGION26_HIGH_REG register * Region26 end address configuration register */ -#define PMS_DMA_REGION26_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xdc) +#define PMS_DMA_REGION26_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xdc) /** PMS_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region26. */ @@ -688,7 +688,7 @@ extern "C" { /** PMS_DMA_REGION27_LOW_REG register * Region27 start address configuration register */ -#define PMS_DMA_REGION27_LOW_REG (DR_REG_PMS_DMA_BASE + 0xe0) +#define PMS_DMA_REGION27_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe0) /** PMS_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region27. */ @@ -700,7 +700,7 @@ extern "C" { /** PMS_DMA_REGION27_HIGH_REG register * Region27 end address configuration register */ -#define PMS_DMA_REGION27_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xe4) +#define PMS_DMA_REGION27_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xe4) /** PMS_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region27. */ @@ -712,7 +712,7 @@ extern "C" { /** PMS_DMA_REGION28_LOW_REG register * Region28 start address configuration register */ -#define PMS_DMA_REGION28_LOW_REG (DR_REG_PMS_DMA_BASE + 0xe8) +#define PMS_DMA_REGION28_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe8) /** PMS_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region28. */ @@ -724,7 +724,7 @@ extern "C" { /** PMS_DMA_REGION28_HIGH_REG register * Region28 end address configuration register */ -#define PMS_DMA_REGION28_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xec) +#define PMS_DMA_REGION28_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xec) /** PMS_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region28. */ @@ -736,7 +736,7 @@ extern "C" { /** PMS_DMA_REGION29_LOW_REG register * Region29 start address configuration register */ -#define PMS_DMA_REGION29_LOW_REG (DR_REG_PMS_DMA_BASE + 0xf0) +#define PMS_DMA_REGION29_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf0) /** PMS_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region29. */ @@ -748,7 +748,7 @@ extern "C" { /** PMS_DMA_REGION29_HIGH_REG register * Region29 end address configuration register */ -#define PMS_DMA_REGION29_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xf4) +#define PMS_DMA_REGION29_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xf4) /** PMS_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region29. */ @@ -760,7 +760,7 @@ extern "C" { /** PMS_DMA_REGION30_LOW_REG register * Region30 start address configuration register */ -#define PMS_DMA_REGION30_LOW_REG (DR_REG_PMS_DMA_BASE + 0xf8) +#define PMS_DMA_REGION30_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf8) /** PMS_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region30. */ @@ -772,7 +772,7 @@ extern "C" { /** PMS_DMA_REGION30_HIGH_REG register * Region30 end address configuration register */ -#define PMS_DMA_REGION30_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xfc) +#define PMS_DMA_REGION30_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xfc) /** PMS_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region30. */ @@ -784,7 +784,7 @@ extern "C" { /** PMS_DMA_REGION31_LOW_REG register * Region31 start address configuration register */ -#define PMS_DMA_REGION31_LOW_REG (DR_REG_PMS_DMA_BASE + 0x100) +#define PMS_DMA_REGION31_LOW_REG (DR_REG_DMA_PMS_BASE + 0x100) /** PMS_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0; * Configures the high 20 bits of the start address for region31. */ @@ -796,7 +796,7 @@ extern "C" { /** PMS_DMA_REGION31_HIGH_REG register * Region31 end address configuration register */ -#define PMS_DMA_REGION31_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x104) +#define PMS_DMA_REGION31_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x104) /** PMS_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575; * Configures the high 20 bits of the end address for region31. */ @@ -808,7 +808,7 @@ extern "C" { /** PMS_DMA_GDMA_CH0_R_PMS_REG register * GDMA ch0 read permission control register */ -#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x108) +#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x108) /** PMS_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch0 to read 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -823,7 +823,7 @@ extern "C" { /** PMS_DMA_GDMA_CH0_W_PMS_REG register * GDMA ch0 write permission control register */ -#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x10c) +#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x10c) /** PMS_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch0 to write 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -838,7 +838,7 @@ extern "C" { /** PMS_DMA_GDMA_CH1_R_PMS_REG register * GDMA ch1 read permission control register */ -#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x110) +#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x110) /** PMS_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch1 to read 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -853,7 +853,7 @@ extern "C" { /** PMS_DMA_GDMA_CH1_W_PMS_REG register * GDMA ch1 write permission control register */ -#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x114) +#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x114) /** PMS_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch1 to write 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -868,7 +868,7 @@ extern "C" { /** PMS_DMA_GDMA_CH2_R_PMS_REG register * GDMA ch2 read permission control register */ -#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x118) +#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x118) /** PMS_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch2 to read 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -883,7 +883,7 @@ extern "C" { /** PMS_DMA_GDMA_CH2_W_PMS_REG register * GDMA ch2 write permission control register */ -#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x11c) +#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x11c) /** PMS_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch2 to write 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -898,7 +898,7 @@ extern "C" { /** PMS_DMA_GDMA_CH3_R_PMS_REG register * GDMA ch3 read permission control register */ -#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x120) +#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x120) /** PMS_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch3 to read 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -913,7 +913,7 @@ extern "C" { /** PMS_DMA_GDMA_CH3_W_PMS_REG register * GDMA ch3 write permission control register */ -#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x124) +#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x124) /** PMS_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures the permission for GDMA ch3 to write 32 address regions. Bit 0 * corresponds to region0, and so on. @@ -928,7 +928,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_ADC_R_PMS_REG register * GDMA-AHB ADC read permission control register */ -#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x128) +#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x128) /** PMS_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by ADC. Bit 0 * corresponds to region0, and so on. @@ -943,7 +943,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_ADC_W_PMS_REG register * GDMA-AHB ADC write permission control register */ -#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x12c) +#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x12c) /** PMS_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by ADC. Bit 0 * corresponds to region0, and so on. @@ -958,7 +958,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG register * GDMA-AHB I2S0 read permission control register */ -#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x130) +#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x130) /** PMS_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by I2S0. Bit 0 * corresponds to region0, and so on. @@ -973,7 +973,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG register * GDMA-AHB I2S0 write permission control register */ -#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x134) +#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x134) /** PMS_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by I2S0. Bit 0 * corresponds to region0, and so on. @@ -988,7 +988,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG register * GDMA-AHB I2S1 read permission control register */ -#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x138) +#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x138) /** PMS_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by I2S1. Bit 0 * corresponds to region0, and so on. @@ -1003,7 +1003,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG register * GDMA-AHB I2S1 write permission control register */ -#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x13c) +#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x13c) /** PMS_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by I2S1. Bit 0 * corresponds to region0, and so on. @@ -1018,7 +1018,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG register * GDMA-AHB I2S2 read permission control register */ -#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x140) +#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x140) /** PMS_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by I2S2. Bit 0 * corresponds to region0, and so on. @@ -1033,7 +1033,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG register * GDMA-AHB I2S2 write permission control register */ -#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x144) +#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x144) /** PMS_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by I2S2. Bit 0 * corresponds to region0, and so on. @@ -1048,7 +1048,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register * GDMA-AHB I3C MST read permission control register */ -#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x148) +#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x148) /** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by I3C master. * Bit 0 corresponds to region0, and so on. @@ -1063,7 +1063,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register * GDMA-AHB I3C MST write permission control register */ -#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x14c) +#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x14c) /** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by I3C master. * Bit 0 corresponds to region0, and so on. @@ -1078,7 +1078,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG register * GDMA-AHB UHCI read permission control register */ -#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x150) +#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x150) /** PMS_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by UHCI. Bit 0 * corresponds to region0, and so on. @@ -1093,7 +1093,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG register * GDMA-AHB UHCI write permission control register */ -#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x154) +#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x154) /** PMS_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by UHCI. Bit 0 * corresponds to region0, and so on. @@ -1108,7 +1108,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_RMT_R_PMS_REG register * GDMA-AHB RMT read permission control register */ -#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x158) +#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x158) /** PMS_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by RMT. Bit 0 * corresponds to region0, and so on. @@ -1123,7 +1123,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_RMT_W_PMS_REG register * GDMA-AHB RMT write permission control register */ -#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x170) +#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x170) /** PMS_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by RMT. Bit 0 * corresponds to region0, and so on. @@ -1138,7 +1138,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register * GDMA-AXI LCD_CAM read permission control register */ -#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x174) +#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x174) /** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by LCD_CAM. Bit * 0 corresponds to region0, and so on. @@ -1153,7 +1153,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register * GDMA-AXI LCD_CAM write permission control register */ -#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x178) +#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x178) /** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by LCD_CAM. Bit * 0 corresponds to region0, and so on. @@ -1168,7 +1168,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register * GDMA-AXI GPSPI2 read permission control register */ -#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x17c) +#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x17c) /** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI2. Bit * 0 corresponds to region0, and so on. @@ -1183,7 +1183,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register * GDMA-AXI GPSPI2 write permission control register */ -#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x180) +#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x180) /** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI2. Bit * 0 corresponds to region0, and so on. @@ -1198,7 +1198,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register * GDMA-AXI GPSPI3 read permission control register */ -#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x184) +#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x184) /** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI3. Bit * 0 corresponds to region0, and so on. @@ -1213,7 +1213,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register * AXI PDMA GPSPI3 write permission control register */ -#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x188) +#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x188) /** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI3. Bit * 0 corresponds to region0, and so on. @@ -1228,7 +1228,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG register * GDMA-AXI PARLIO read permission control register */ -#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x18c) +#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x18c) /** PMS_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by PARLIO * (Parallel IO Controller). Bit 0 corresponds to region0, and so on. @@ -1243,7 +1243,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG register * GDMA-AXI PARLIO write permission control register */ -#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x190) +#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x190) /** PMS_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by PARLIO. Bit * 0 corresponds to region0, and so on. @@ -1258,7 +1258,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_AES_R_PMS_REG register * GDMA-AXI AES read permission control register */ -#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x194) +#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x194) /** PMS_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by AES. Bit 0 * corresponds to region0, and so on. @@ -1273,7 +1273,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_AES_W_PMS_REG register * GDMA-AXI AES write permission control register */ -#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x198) +#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x198) /** PMS_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by AES. Bit 0 * corresponds to region0, and so on. @@ -1288,7 +1288,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_SHA_R_PMS_REG register * GDMA-AXI SHA read permission control register */ -#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x19c) +#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x19c) /** PMS_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by SHA. Bit 0 * corresponds to region0, and so on. @@ -1303,7 +1303,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_SHA_W_PMS_REG register * GDMA-AXI SHA write permission control register */ -#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x1a0) +#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x1a0) /** PMS_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by SHA. Bit 0 * corresponds to region0, and so on. @@ -1318,7 +1318,7 @@ extern "C" { /** PMS_DMA_DMA2D_JPEG_PMS_R_REG register * 2D-DMA JPEG read permission control register */ -#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1a4) +#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1a4) /** PMS_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to read 32 address ranges requested by JPEG. Bit 0 * corresponds to region0, and so on. @@ -1333,7 +1333,7 @@ extern "C" { /** PMS_DMA_DMA2D_JPEG_PMS_W_REG register * 2D-DMA JPEG write permission control register */ -#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1a8) +#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1a8) /** PMS_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to write 32 address ranges requested by JPEG. Bit 0 * corresponds to region0, and so on. @@ -1348,7 +1348,7 @@ extern "C" { /** PMS_DMA_USB_PMS_R_REG register * High-speed USB 2.0 OTG read permission control register */ -#define PMS_DMA_USB_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1ac) +#define PMS_DMA_USB_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ac) /** PMS_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for high-speed USB 2.0 OTG to access 32 address ranges. * Bit 0 corresponds to region0, and so on. @@ -1363,7 +1363,7 @@ extern "C" { /** PMS_DMA_USB_PMS_W_REG register * High-speed USB 2.0 OTG write permission control register */ -#define PMS_DMA_USB_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1b0) +#define PMS_DMA_USB_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b0) /** PMS_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for high-speed USB 2.0 OTG to access 32 address ranges. * Bit 0 corresponds to region0, and so on. @@ -1378,7 +1378,7 @@ extern "C" { /** PMS_DMA_GMAC_PMS_R_REG register * EMAC read permission control register */ -#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1b4) +#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1b4) /** PMS_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for EMAC to access 32 address ranges. Bit 0 corresponds * to region0, and so on. @@ -1393,7 +1393,7 @@ extern "C" { /** PMS_DMA_GMAC_PMS_W_REG register * EMAC write permission control register */ -#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1b8) +#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b8) /** PMS_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for EMAC to access 32 address ranges. Bit 0 corresponds * to region0, and so on. @@ -1408,7 +1408,7 @@ extern "C" { /** PMS_DMA_SDMMC_PMS_R_REG register * SDMMC read permission control register */ -#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1bc) +#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1bc) /** PMS_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for SDMMC to access 32 address ranges. Bit 0 corresponds * to region0, and so on. @@ -1423,7 +1423,7 @@ extern "C" { /** PMS_DMA_SDMMC_PMS_W_REG register * SDMMC write permission control register */ -#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1c0) +#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c0) /** PMS_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for SDMMC to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1438,7 +1438,7 @@ extern "C" { /** PMS_DMA_USBOTG11_PMS_R_REG register * Full-speed USB 2.0 OTG full-speed read permission control register */ -#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1c4) +#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1c4) /** PMS_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for full-speed USB 2.0 OTG to access 32 address ranges. * Bit 0 corresponds to region0, and so on. @@ -1453,7 +1453,7 @@ extern "C" { /** PMS_DMA_USBOTG11_PMS_W_REG register * Full-speed USB 2.0 OTG full-speed write permission control register */ -#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1c8) +#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c8) /** PMS_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for full-speed USB 2.0 OTG to access 32 address ranges. * Bit 0 corresponds to region0, and so on. @@ -1468,7 +1468,7 @@ extern "C" { /** PMS_DMA_TRACE0_PMS_R_REG register * TRACE0 read permission control register */ -#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1cc) +#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1cc) /** PMS_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for TRACE0 to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1483,7 +1483,7 @@ extern "C" { /** PMS_DMA_TRACE0_PMS_W_REG register * TRACE0 write permission control register */ -#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1d0) +#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d0) /** PMS_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for TRACE0 to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1498,7 +1498,7 @@ extern "C" { /** PMS_DMA_TRACE1_PMS_R_REG register * TRACE1 read permission control register */ -#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1d4) +#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1d4) /** PMS_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for TRACE1 to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1513,7 +1513,7 @@ extern "C" { /** PMS_DMA_TRACE1_PMS_W_REG register * TRACE1 write permission control register */ -#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1d8) +#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d8) /** PMS_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for TRACE1 to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1528,7 +1528,7 @@ extern "C" { /** PMS_DMA_L2MEM_MON_PMS_R_REG register * L2MEM Monitor read permission control register */ -#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1dc) +#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1dc) /** PMS_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for L2MEM MON. Each bit corresponds to a region. Bit 0 * corresponds to region0, and so on. @@ -1543,7 +1543,7 @@ extern "C" { /** PMS_DMA_L2MEM_MON_PMS_W_REG register * L2MEM Monitor write permission control register */ -#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1e0) +#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e0) /** PMS_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for L2MEM monitor to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1558,7 +1558,7 @@ extern "C" { /** PMS_DMA_TCM_MON_PMS_R_REG register * TCM Monitor read permission control register */ -#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1e4) +#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4) /** PMS_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0 * corresponds to region0, and so on. @@ -1573,7 +1573,7 @@ extern "C" { /** PMS_DMA_TCM_MON_PMS_W_REG register * TCM Monitor write permission control register */ -#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1e8) +#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8) /** PMS_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for TCM monitor to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1588,7 +1588,7 @@ extern "C" { /** PMS_DMA_REGDMA_PMS_R_REG register * REGDMA read permission control register */ -#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1ec) +#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec) /** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0 * corresponds to region0, and so on. @@ -1603,7 +1603,7 @@ extern "C" { /** PMS_DMA_REGDMA_PMS_W_REG register * REGDMA write permission control register */ -#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1f0) +#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0) /** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0 * corresponds to region0, and so on. @@ -1618,7 +1618,7 @@ extern "C" { /** PMS_DMA_H264_PMS_R_REG register * H264 DMA read permission control register */ -#define PMS_DMA_H264_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1fc) +#define PMS_DMA_H264_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1fc) /** PMS_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures read permission for H264 DMA to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1633,7 +1633,7 @@ extern "C" { /** PMS_DMA_H264_PMS_W_REG register * H264 DMA write permission control register */ -#define PMS_DMA_H264_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x200) +#define PMS_DMA_H264_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x200) /** PMS_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures write permission for H264 DMA to access 32 address ranges. Bit 0 * corresponds to region0, and so on. @@ -1648,7 +1648,7 @@ extern "C" { /** PMS_DMA_DMA2D_PPA_PMS_R_REG register * 2D-DMA PPA read permission control register */ -#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x204) +#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x204) /** PMS_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to read 32 address ranges requested by PPA * (Pixel-Processing Accelerator). Bit 0 corresponds to region0, and so on. @@ -1663,7 +1663,7 @@ extern "C" { /** PMS_DMA_DMA2D_PPA_PMS_W_REG register * 2D-DMA PPA write permission control register */ -#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x208) +#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x208) /** PMS_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to write 32 address ranges requested by PPA. Bit 0 * corresponds to region0, and so on. @@ -1678,7 +1678,7 @@ extern "C" { /** PMS_DMA_DMA2D_DUMMY_PMS_R_REG register * 2D-DMA dummy read permission control register */ -#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x20c) +#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x20c) /** PMS_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to read 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. @@ -1693,7 +1693,7 @@ extern "C" { /** PMS_DMA_DMA2D_DUMMY_PMS_W_REG register * 2D-DMA dummy write permission control register */ -#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x210) +#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x210) /** PMS_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures 2D-DMA permission to write 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. @@ -1708,7 +1708,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG register * GDMA-AHB dummy read permission control register */ -#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x214) +#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x214) /** PMS_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to read 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. @@ -1723,7 +1723,7 @@ extern "C" { /** PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG register * GDMA-AHB dummy write permission control register */ -#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x218) +#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x218) /** PMS_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AHB permission to write 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. @@ -1738,7 +1738,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG register * GDMA-AXI dummy read permission control register */ -#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x21c) +#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x21c) /** PMS_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to read 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. @@ -1753,7 +1753,7 @@ extern "C" { /** PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG register * GDMA-AXI dummy write permission control register */ -#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x220) +#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x220) /** PMS_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; * Configures GDMA-AXI permission to write 32 address ranges requested by Dummy. Bit 0 * corresponds to region0, and so on. diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h index e4135f4f89..903bfc178b 100644 --- a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h +++ b/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { /** PMS_HP2LP_PERI_PMS_DATE_REG register * Version control register */ -#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0) +#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0) /** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790; * Version control register */ @@ -26,7 +26,7 @@ extern "C" { /** PMS_HP2LP_PERI_PMS_CLK_EN_REG register * Clock gating register */ -#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4) +#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4) /** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: Enable automatic clock gating @@ -40,7 +40,7 @@ extern "C" { /** PMS_HP_CORE0_MM_PMS_REG0_REG register * Permission control register0 for HP CPU0 in machine mode */ -#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8) +#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8) /** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access LP System * Registers. @@ -267,7 +267,7 @@ extern "C" { /** PMS_HP_CORE0_UM_PMS_REG0_REG register * Permission control register0 for HP CPU0 in user mode */ -#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0xc) +#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc) /** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in user mode has permission to access LP System * Registers. @@ -492,7 +492,7 @@ extern "C" { /** PMS_HP_CORE1_MM_PMS_REG0_REG register * Permission control register0 for HP CPU1 in machine mode */ -#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x10) +#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10) /** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access LP System * Registers. @@ -719,7 +719,7 @@ extern "C" { /** PMS_HP_CORE1_UM_PMS_REG0_REG register * Permission control register0 for HP CPU1 in user mode */ -#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x14) +#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14) /** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in user mode has permission to access LP System * Registers. @@ -944,7 +944,7 @@ extern "C" { /** PMS_REGDMA_LP_PERI_PMS_REG register * LP Peripheral Permission register for REGDMA */ -#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_PMS_BASE + 0x18) +#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18) /** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether REGDMA has permission to access LP SRAM. * 0: Not allowed diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h index c7c82bec2f..a097d8e43f 100644 --- a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h +++ b/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { /** PMS_HP_PERI_PMS_DATE_REG register * Version control register */ -#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0) +#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0) /** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537; * Version control register. */ @@ -26,7 +26,7 @@ extern "C" { /** PMS_HP_PERI_PMS_CLK_EN_REG register * Clock gating register */ -#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4) +#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_HP_PERI_PMS_BASE + 0x4) /** PMS_HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: Enable automatic clock gating @@ -40,7 +40,7 @@ extern "C" { /** PMS_CORE0_MM_HP_PERI_PMS_REG0_REG register * Permission control register0 for HP CPU0 in machine mode */ -#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8) +#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x8) /** PMS_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access external RAM * without going through cache. @@ -140,7 +140,7 @@ extern "C" { /** PMS_CORE0_MM_HP_PERI_PMS_REG1_REG register * Permission control register1 for HP CPU0 in machine mode */ -#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0xc) +#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0xc) /** PMS_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP high-speed * USB 2.0 OTG. @@ -421,7 +421,7 @@ extern "C" { /** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU0 in machine mode */ -#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x10) +#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x10) /** PMS_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP MCPWM0. * 0: Not allowed @@ -702,7 +702,7 @@ extern "C" { /** PMS_CORE0_MM_HP_PERI_PMS_REG3_REG register * Permission control register3 for HP CPU0 in machine mode */ -#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x14) +#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x14) /** PMS_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in machine mode has permission to access HP GPIO Matrix. * 0: Not allowed @@ -754,7 +754,7 @@ extern "C" { /** PMS_CORE0_UM_HP_PERI_PMS_REG0_REG register * Permission control register0 for HP CPU0 in user mode */ -#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x18) +#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x18) /** PMS_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in user mode has permission to access external RAM * without going through cache. @@ -853,7 +853,7 @@ extern "C" { /** PMS_CORE0_UM_HP_PERI_PMS_REG1_REG register * Permission control register1 for HP CPU0 in user mode */ -#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x1c) +#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x1c) /** PMS_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP high-speed USB * 2.0 OTG. @@ -1128,7 +1128,7 @@ extern "C" { /** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU0 in user mode */ -#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x20) +#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x20) /** PMS_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP MCPWM0. * 0: Not allowed @@ -1407,7 +1407,7 @@ extern "C" { /** PMS_CORE0_UM_HP_PERI_PMS_REG3_REG register * Permission control register3 for HP CPU0 in user mode */ -#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x24) +#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x24) /** PMS_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU0 in user mode has permission to access HP GPIO Matrix. * 0: Not allowed @@ -1458,7 +1458,7 @@ extern "C" { /** PMS_CORE1_MM_HP_PERI_PMS_REG0_REG register * Permission control register0 for HP CPU1 in machine mode */ -#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x28) +#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x28) /** PMS_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access external RAM * without going through cache. @@ -1558,7 +1558,7 @@ extern "C" { /** PMS_CORE1_MM_HP_PERI_PMS_REG1_REG register * Permission control register1 for HP CPU1 in machine mode */ -#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x2c) +#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x2c) /** PMS_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP high-speed * USB 2.0 OTG. @@ -1839,7 +1839,7 @@ extern "C" { /** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU1 in machine mode */ -#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x30) +#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x30) /** PMS_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP MCPWM0. * 0: Not allowed @@ -2120,7 +2120,7 @@ extern "C" { /** PMS_CORE1_MM_HP_PERI_PMS_REG3_REG register * Permission control register3 for HP CPU1 in machine mode */ -#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x34) +#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x34) /** PMS_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in machine mode has permission to access HP GPIO Matrix. * 0: Not allowed @@ -2172,7 +2172,7 @@ extern "C" { /** PMS_CORE1_UM_HP_PERI_PMS_REG0_REG register * Permission control register0 for HP CPU1 in user mode */ -#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x38) +#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x38) /** PMS_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in user mode has permission to access external RAM * without going through cache. @@ -2271,7 +2271,7 @@ extern "C" { /** PMS_CORE1_UM_HP_PERI_PMS_REG1_REG register * Permission control register1 for HP CPU1 in user mode */ -#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x3c) +#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x3c) /** PMS_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP high-speed USB * 2.0 OTG. @@ -2546,7 +2546,7 @@ extern "C" { /** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register * Permission control register2 for HP CPU1 in user mode */ -#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x40) +#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x40) /** PMS_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP MCPWM0. * 0: Not allowed @@ -2825,7 +2825,7 @@ extern "C" { /** PMS_CORE1_UM_HP_PERI_PMS_REG3_REG register * Permission control register3 for HP CPU1 in user mode */ -#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x44) +#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x44) /** PMS_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether HP CPU1 in user mode has permission to access HP GPIO Matrix. * 0: Not allowed @@ -2876,7 +2876,7 @@ extern "C" { /** PMS_REGDMA_PERI_PMS_REG register * Permission register for REGDMA */ -#define PMS_REGDMA_PERI_PMS_REG (DR_REG_PMS_BASE + 0x48) +#define PMS_REGDMA_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48) /** PMS_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether REGDMA has permission to access all HP peripheral (including CPU * peripherals). diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h index 6e115cb703..ba58a6cfde 100644 --- a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h +++ b/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { /** PMS_LP2HP_PERI_PMS_DATE_REG register * Version control register */ -#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0) +#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0) /** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790; * Version control register. */ @@ -26,7 +26,7 @@ extern "C" { /** PMS_LP2HP_PERI_PMS_CLK_EN_REG register * Clock gating register */ -#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4) +#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4) /** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: Enable automatic clock gating. @@ -40,7 +40,7 @@ extern "C" { /** PMS_LP_MM_PMS_REG0_REG register * Permission control register0 for the LP CPU in machine mode */ -#define PMS_LP_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8) +#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8) /** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether the LP CPU in machine mode has permission to access external RAM * without going through cache. @@ -141,7 +141,7 @@ extern "C" { /** PMS_LP_MM_PMS_REG1_REG register * Permission control register1 for the LP CPU in machine mode */ -#define PMS_LP_MM_PMS_REG1_REG (DR_REG_PMS_BASE + 0x30) +#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30) /** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP * high-speed USB 2.0 OTG. @@ -422,7 +422,7 @@ extern "C" { /** PMS_LP_MM_PMS_REG2_REG register * Permission control register2 for the LP CPU in machine mode */ -#define PMS_LP_MM_PMS_REG2_REG (DR_REG_PMS_BASE + 0xa4) +#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4) /** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP MCPWM0. * 0: Not allowed @@ -703,7 +703,7 @@ extern "C" { /** PMS_LP_MM_PMS_REG3_REG register * Permission control register3 for the LP CPU in machine mode */ -#define PMS_LP_MM_PMS_REG3_REG (DR_REG_PMS_BASE + 0x11c) +#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c) /** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether the LP CPU in machine mode has permission to access HP GPIO * Matrix. diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h index f95a5a3b85..7074bc5236 100644 --- a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h +++ b/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h @@ -14,7 +14,7 @@ extern "C" { /** PMS_LP_PERI_PMS_DATE_REG register * Version control register */ -#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0) +#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0) /** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537; * Version control register */ @@ -26,7 +26,7 @@ extern "C" { /** PMS_LP_PERI_PMS_CLK_EN_REG register * Clock gating register */ -#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4) +#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4) /** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: Enable automatic clock gating @@ -40,7 +40,7 @@ extern "C" { /** PMS_LP_MM_LP_PERI_PMS_REG0_REG register * Permission control register0 for LP CPU in machine mode */ -#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8) +#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8) /** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; * Configures whether LP CPU in machine mode has permission to access LP system * registers. @@ -272,7 +272,7 @@ extern "C" { /** PMS_PERI_REGION0_LOW_REG register * Region0 start address configuration register */ -#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc) +#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc) /** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0; * Configures the high 30 bits of the start address of peripheral register's region0. */ @@ -284,7 +284,7 @@ extern "C" { /** PMS_PERI_REGION0_HIGH_REG register * Region0 end address configuration register */ -#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10) +#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10) /** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823; * Configures the high 30 bits of the end address of peripheral register's region0. */ @@ -296,7 +296,7 @@ extern "C" { /** PMS_PERI_REGION1_LOW_REG register * Region1 start address configuration register */ -#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14) +#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14) /** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0; * Configures the high 30 bits of the start address of peripheral register's region1. */ @@ -308,7 +308,7 @@ extern "C" { /** PMS_PERI_REGION1_HIGH_REG register * Region1 end address configuration register */ -#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18) +#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18) /** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823; * Configures the high 30 bits of the end address of peripheral register's region1. */ @@ -320,7 +320,7 @@ extern "C" { /** PMS_PERI_REGION_PMS_REG register * Permission register of region */ -#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c) +#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c) /** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3; * Configures whether LP core in machine mode has permission to access address region0 * and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.