From ad1605a46489b7eb9117a8bc4e90319023284b6b Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 9 Jun 2023 17:19:24 +0800 Subject: [PATCH] bugfix: fix esp32s3 psram access failed when dfs is enabled --- components/esp_hw_support/mspi_timing_tuning.c | 4 ++-- components/esp_hw_support/sleep_modes.c | 11 ++++++----- components/esp_pm/pm_impl.c | 16 +++++++++++++++- 3 files changed, 23 insertions(+), 8 deletions(-) diff --git a/components/esp_hw_support/mspi_timing_tuning.c b/components/esp_hw_support/mspi_timing_tuning.c index 64f05074b9..12c3901802 100644 --- a/components/esp_hw_support/mspi_timing_tuning.c +++ b/components/esp_hw_support/mspi_timing_tuning.c @@ -561,8 +561,8 @@ void mspi_timing_enter_high_speed_mode(bool control_spi1) void mspi_timing_change_speed_mode_cache_safe(bool switch_down) { - Cache_Freeze_ICache_Enable(1); - Cache_Freeze_DCache_Enable(1); + Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY); + Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY); if (switch_down) { //enter MSPI low speed mode, extra delays should be removed mspi_timing_enter_low_speed_mode(false); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 97f939000b..4589def89b 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -512,7 +512,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo pd_flags &= ~RTC_SLEEP_PD_INT_8M; } - // Turn down mspi clock speed + // Will switch to XTAL turn down MSPI speed #if SOC_SPI_MEM_SUPPORT_TIME_TUNING mspi_timing_change_speed_mode_cache_safe(true); #endif @@ -704,14 +704,15 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo } // Set mspi clock to ROM default one. + if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) { #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT - spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT); + spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT); #endif - - // Speed up mspi clock freq #if SOC_SPI_MEM_SUPPORT_TIME_TUNING - mspi_timing_change_speed_mode_cache_safe(false); + // Turn up MSPI speed if switch to PLL + mspi_timing_change_speed_mode_cache_safe(false); #endif + } if (!deep_sleep) { s_config.ccount_ticks_record = esp_cpu_get_cycle_count(); diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 9b7f6e608a..0ebd883b70 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -31,6 +31,10 @@ #include "xtensa/core-macros.h" #endif +#if SOC_SPI_MEM_SUPPORT_TIME_TUNING +#include "esp_private/mspi_timing_tuning.h" +#endif + #include "esp_private/pm_impl.h" #include "esp_private/pm_trace.h" #include "esp_private/esp_timer_private.h" @@ -475,7 +479,17 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode) if (switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); } - rtc_clk_cpu_freq_set_config_fast(&new_config); + if (new_config.source == SOC_CPU_CLK_SRC_PLL) { + rtc_clk_cpu_freq_set_config_fast(&new_config); +#if SOC_SPI_MEM_SUPPORT_TIME_TUNING + mspi_timing_change_speed_mode_cache_safe(false); +#endif + } else { +#if SOC_SPI_MEM_SUPPORT_TIME_TUNING + mspi_timing_change_speed_mode_cache_safe(true); +#endif + rtc_clk_cpu_freq_set_config_fast(&new_config); + } if (!switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); }