From 75cf388b99aec1deed1446db4b8a206a8c8e818a Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 3 Jul 2024 22:11:22 +0800 Subject: [PATCH 1/4] feat(soc): add modem register header files for ESP32C61 --- .../esp32c61/include/modem/modem_lpcon_reg.h | 378 +++++++++++ .../include/modem/modem_lpcon_struct.h | 251 ++++++++ .../esp32c61/include/modem/modem_syscon_reg.h | 594 ++++++++++++++++++ .../include/modem/modem_syscon_struct.h | 175 ++++++ .../soc/esp32c61/include/modem/reg_base.h | 9 + .../soc/esp32c61/ld/esp32c61.peripherals.ld | 2 + 6 files changed, 1409 insertions(+) create mode 100644 components/soc/esp32c61/include/modem/modem_lpcon_reg.h create mode 100644 components/soc/esp32c61/include/modem/modem_lpcon_struct.h create mode 100644 components/soc/esp32c61/include/modem/modem_syscon_reg.h create mode 100644 components/soc/esp32c61/include/modem/modem_syscon_struct.h create mode 100644 components/soc/esp32c61/include/modem/reg_base.h diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_reg.h b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h new file mode 100644 index 0000000000..2e16b2e54c --- /dev/null +++ b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h @@ -0,0 +1,378 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "modem/reg_base.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_EN (BIT(0)) +#define MODEM_LPCON_CLK_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_S 0 + +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) +/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 +/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 + +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 + +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 +/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_V 0x1 +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 + +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) +/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_V 0x1 +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 + +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 +/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 + +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_V 0x1 +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_V 0x1 +#define MODEM_LPCON_RST_I2C_MST_S 2 +/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (BIT(1)) +#define MODEM_LPCON_RST_COEX_V 0x1 +#define MODEM_LPCON_RST_COEX_S 1 +/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_S 0 + +#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 + +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 +/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 +/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 +/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 +#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) +#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 +#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 +/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_S 15 +/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_MODE 0x00000007 +#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) +#define MODEM_LPCON_BC_MEM_MODE_V 0x7 +#define MODEM_LPCON_BC_MEM_MODE_S 12 +/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 +/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 +#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) +#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 +#define MODEM_LPCON_PBUS_MEM_MODE_S 8 +/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_S 7 +/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 +#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) +#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 +#define MODEM_LPCON_AGC_MEM_MODE_S 4 +/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_S 3 +/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_MODE 0x00000007 +#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) +#define MODEM_LPCON_DC_MEM_MODE_V 0x7 +#define MODEM_LPCON_DC_MEM_MODE_S 0 + +#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) +/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 + +#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) +/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 + +#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) +/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_V 0x1 +#define MODEM_LPCON_AGC_MEM_EN_S 2 +/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 +#define MODEM_LPCON_PBUS_MEM_EN_S 1 +/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 + +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) +/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */ +/*description: .*/ +#define MODEM_LPCON_DATE 0x0FFFFFFF +#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) +#define MODEM_LPCON_DATE_V 0xFFFFFFF +#define MODEM_LPCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_struct.h b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h new file mode 100644 index 0000000000..6c695e5413 --- /dev/null +++ b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h @@ -0,0 +1,251 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t clk_lp_timer_sel_osc_slow : 1; + uint32_t clk_lp_timer_sel_osc_fast : 1; + uint32_t clk_lp_timer_sel_xtal : 1; + uint32_t clk_lp_timer_sel_xtal32k : 1; + uint32_t clk_lp_timer_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } lp_timer_conf; + union { + struct { + uint32_t clk_coex_lp_sel_osc_slow : 1; + uint32_t clk_coex_lp_sel_osc_fast : 1; + uint32_t clk_coex_lp_sel_xtal : 1; + uint32_t clk_coex_lp_sel_xtal32k : 1; + uint32_t clk_coex_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } coex_lp_clk_conf; + union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal : 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } wifi_lp_clk_conf; + union { + struct { + uint32_t clk_modem_aon_force : 2; + uint32_t modem_pwr_clk_src_fo : 1; + uint32_t reserved3 : 29; + }; + uint32_t val; + } modem_src_clk_conf; + union { + struct { + uint32_t clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; + }; + uint32_t val; + } modem_32k_clk_conf; + union { + struct { + uint32_t clk_wifipwr_en : 1; + uint32_t clk_coex_en : 1; + uint32_t clk_i2c_mst_en : 1; + uint32_t clk_lp_timer_en : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifipwr_fo : 1; + uint32_t clk_coex_fo : 1; + uint32_t clk_i2c_mst_fo : 1; + uint32_t clk_lp_timer_fo : 1; + uint32_t clk_fe_mem_fo : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 16; + uint32_t clk_wifipwr_st_map : 4; + uint32_t clk_coex_st_map : 4; + uint32_t clk_i2c_mst_st_map : 4; + uint32_t clk_lp_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t rst_wifipwr : 1; + uint32_t rst_coex : 1; + uint32_t rst_i2c_mst : 1; + uint32_t rst_lp_timer : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } rst_conf; + union { + struct { + uint32_t modem_pwr_tick_target : 6; + uint32_t reserved6 : 26; + }; + uint32_t val; + } tick_conf; + union { + struct { + uint32_t dc_mem_mode : 3; + uint32_t dc_mem_force : 1; + uint32_t agc_mem_mode : 3; + uint32_t agc_mem_force : 1; + uint32_t pbus_mem_mode : 3; + uint32_t pbus_mem_force : 1; + uint32_t bc_mem_mode : 3; + uint32_t bc_mem_force : 1; + uint32_t i2c_mst_mem_mode : 3; + uint32_t i2c_mst_mem_force : 1; + uint32_t chan_freq_mem_mode : 3; + uint32_t chan_freq_mem_force : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } mem_conf; + uint32_t mem_rf1_aux_ctrl; + uint32_t mem_rf2_aux_ctrl; + union { + struct { + uint32_t chan_freq_mem_en : 1; + uint32_t pbus_mem_en : 1; + uint32_t agc_mem_en : 1; + uint32_t reserved3 : 29; + }; + uint32_t val; + } apb_mem_sel; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_lpcon_dev_t; + +extern modem_lpcon_dev_t MODEM_LPCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/modem/modem_syscon_reg.h b/components/soc/esp32c61/include/modem/modem_syscon_reg.h new file mode 100644 index 0000000000..bf811fff09 --- /dev/null +++ b/components/soc/esp32c61/include/modem/modem_syscon_reg.h @@ -0,0 +1,594 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "modem/reg_base.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/* MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x1 +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 +/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 +/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 +/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 +/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 +/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 +/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 +/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_EN (BIT(0)) +#define MODEM_SYSCON_CLK_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_S 0 + +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 +/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 +/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 +/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 +/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 +/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 +/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ +/*description: .*/ +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 +/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 + +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 +#define MODEM_SYSCON_CLK_ETM_FO_S 28 +/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 +/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 +/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 +/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 +/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_FO_S 5 +/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 +/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_FO_S 3 +/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 +/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 + +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) +/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 +/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 + +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 +/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_V 0x1 +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 +/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (BIT(22)) +#define MODEM_SYSCON_RST_ETM_V 0x1 +#define MODEM_SYSCON_RST_ETM_S 22 +/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_S 18 +/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_S 16 +/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (BIT(14)) +#define MODEM_SYSCON_RST_FE_V 0x1 +#define MODEM_SYSCON_RST_FE_S 14 +/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_V 0x1 +#define MODEM_SYSCON_RST_FE_AHB_S 13 +/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_ADC_S 12 +/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_V 0x1 +#define MODEM_SYSCON_RST_FE_DAC_S 11 +/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 +/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 +#define MODEM_SYSCON_RST_WIFIMAC_S 9 +/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_V 0x1 +#define MODEM_SYSCON_RST_WIFIBB_S 8 + +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 +/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 +/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 +/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 +/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_EN_S 17 +/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 +/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 +/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 + +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_S 0 + +#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) +/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2401180 ; */ +/*description: .*/ +#define MODEM_SYSCON_DATE 0x0FFFFFFF +#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) +#define MODEM_SYSCON_DATE_V 0xFFFFFFF +#define MODEM_SYSCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/modem/modem_syscon_struct.h b/components/soc/esp32c61/include/modem/modem_syscon_struct.h new file mode 100644 index 0000000000..101c41dd43 --- /dev/null +++ b/components/soc/esp32c61/include/modem/modem_syscon_struct.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t modem_ant_force_sel_bt : 1; + uint32_t modem_ant_force_sel_wifi : 1; + uint32_t fpga_debug_clkswitch : 1; + uint32_t fpga_debug_clk80 : 1; + uint32_t fpga_debug_clk40 : 1; + uint32_t fpga_debug_clk20 : 1; + uint32_t fpga_debug_clk10 : 1; + uint32_t modem_mem_mode_force : 1; + uint32_t modem_dis_wifi6_force : 1; + uint32_t reserved10 : 22; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t pwdet_sar_clock_ena : 1; + uint32_t pwdet_clk_div_num : 8; + uint32_t clk_tx_dac_inv_ena : 1; + uint32_t clk_rx_adc_inv_ena : 1; + uint32_t clk_pwdet_adc_inv_ena : 1; + uint32_t clk_i2c_mst_sel_160m : 1; + uint32_t reserved13 : 8; + uint32_t clk_data_dump_mux : 1; + uint32_t clk_etm_en : 1; + uint32_t clk_zb_apb_en : 1; + uint32_t clk_zbmac_en : 1; + uint32_t clk_modem_sec_ecb_en : 1; + uint32_t clk_modem_sec_ccm_en : 1; + uint32_t clk_modem_sec_bah_en : 1; + uint32_t clk_modem_sec_apb_en : 1; + uint32_t clk_modem_sec_en : 1; + uint32_t clk_ble_timer_en : 1; + uint32_t clk_data_dump_en : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifibb_fo : 1; + uint32_t clk_wifimac_fo : 1; + uint32_t clk_wifi_apb_fo : 1; + uint32_t clk_fe_fo : 1; + uint32_t clk_fe_apb_fo : 1; + uint32_t clk_btbb_fo : 1; + uint32_t clk_btmac_fo : 1; + uint32_t clk_bt_apb_fo : 1; + uint32_t clk_zbmac_fo : 1; + uint32_t clk_zbmac_apb_fo : 1; + uint32_t reserved10 : 13; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t clk_etm_fo : 1; + uint32_t clk_modem_sec_fo : 1; + uint32_t clk_ble_timer_fo : 1; + uint32_t clk_data_dump_fo : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 8; + uint32_t clk_zb_st_map : 4; + uint32_t clk_fe_st_map : 4; + uint32_t clk_bt_st_map : 4; + uint32_t clk_wifi_st_map : 4; + uint32_t clk_modem_peri_st_map : 4; + uint32_t clk_modem_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t reserved0 : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 1; + uint32_t reserved3 : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t rst_wifibb : 1; + uint32_t rst_wifimac : 1; + uint32_t rst_fe_pwdet_adc : 1; + uint32_t rst_fe_dac : 1; + uint32_t rst_fe_adc : 1; + uint32_t rst_fe_ahb : 1; + uint32_t rst_fe : 1; + uint32_t rst_btmac_apb : 1; + uint32_t rst_btmac : 1; + uint32_t rst_btbb_apb : 1; + uint32_t rst_btbb : 1; + uint32_t reserved19 : 3; + uint32_t rst_etm : 1; + uint32_t rst_zbmac_apb : 1; + uint32_t rst_zbmac : 1; + uint32_t rst_modem_ecb : 1; + uint32_t rst_modem_ccm : 1; + uint32_t rst_modem_bah : 1; + uint32_t reserved28 : 1; + uint32_t rst_modem_sec : 1; + uint32_t rst_ble_timer : 1; + uint32_t rst_data_dump : 1; + }; + uint32_t val; + } modem_rst_conf; + union { + struct { + uint32_t clk_wifibb_22m_en : 1; + uint32_t clk_wifibb_40m_en : 1; + uint32_t clk_wifibb_44m_en : 1; + uint32_t clk_wifibb_80m_en : 1; + uint32_t clk_wifibb_40x_en : 1; + uint32_t clk_wifibb_80x_en : 1; + uint32_t clk_wifibb_40x1_en : 1; + uint32_t clk_wifibb_80x1_en : 1; + uint32_t clk_wifibb_160x1_en : 1; + uint32_t clk_wifimac_en : 1; + uint32_t clk_wifi_apb_en : 1; + uint32_t clk_fe_20m_en : 1; + uint32_t clk_fe_40m_en : 1; + uint32_t clk_fe_80m_en : 1; + uint32_t clk_fe_160m_en : 1; + uint32_t clk_fe_apb_en : 1; + uint32_t clk_bt_apb_en : 1; + uint32_t clk_btbb_en : 1; + uint32_t clk_btmac_en : 1; + uint32_t clk_fe_pwdet_adc_en : 1; + uint32_t clk_fe_adc_en : 1; + uint32_t clk_fe_dac_en : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 8; + }; + uint32_t val; + } clk_conf1; + uint32_t wifi_bb_cfg; + uint32_t mem_rf1_conf; + uint32_t mem_rf2_conf; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_syscon_dev_t; + +extern modem_syscon_dev_t MODEM_SYSCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/modem/reg_base.h b/components/soc/esp32c61/include/modem/reg_base.h new file mode 100644 index 0000000000..37b441740c --- /dev/null +++ b/components/soc/esp32c61/include/modem/reg_base.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#define DR_REG_MODEM_SYSCON_BASE 0x600A9C00 +#define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index c2e855216f..e57aeaa7f7 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -35,6 +35,8 @@ PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); PROVIDE ( MISC = 0x6009F000 ); +PROVIDE ( MODEM_SYSCON = 0x600A9C00 ); +PROVIDE ( MODEM_LPCON = 0x600AF000 ); PROVIDE ( MODEM0 = 0x600A0000 ); PROVIDE ( MODEM1 = 0x600AC000 ); PROVIDE ( MODEM_PWR0 = 0x600AD000 ); From a90c9101ff6fe46e30d203900dc32239939e4f8a Mon Sep 17 00:00:00 2001 From: Fu Zhibo Date: Tue, 2 Jul 2024 16:56:16 +0800 Subject: [PATCH 2/4] feat: support regi2c for esp32c61 --- .../src/esp32c5/bootloader_esp32c5.c | 1 - .../src/esp32c61/bootloader_esp32c61.c | 12 +- .../port/esp32c61/CMakeLists.txt | 2 +- .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c61/esp_rom_caps.h | 3 +- .../esp_rom/patches/esp_rom_regi2c_esp32c61.c | 178 ++++++++++++++++++ .../hal/esp32c61/include/hal/regi2c_ctrl_ll.h | 2 - .../soc/esp32c5/include/soc/i2c_ana_mst_reg.h | 80 ++++---- .../soc/esp32c6/include/soc/i2c_ana_mst_reg.h | 82 ++++---- .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 + .../esp32c61/include/soc/i2c_ana_mst_reg.h | 82 ++++---- .../soc/esp32c61/include/soc/reg_base.h | 2 +- .../soc/esp32c61/include/soc/soc_caps.h | 2 +- 13 files changed, 317 insertions(+), 137 deletions(-) create mode 100644 components/esp_rom/patches/esp_rom_regi2c_esp32c61.c diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 7009b9afae..5c5ac3d6ed 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -38,7 +38,6 @@ #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" -#include "hal/clk_tree_ll.h" #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index 5b618fab87..45d26a18db 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -43,6 +43,8 @@ #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" +#include "modem/modem_lpcon_reg.h" +#include "modem/modem_syscon_reg.h" static const char *TAG = "boot.esp32c61"; @@ -94,12 +96,10 @@ static inline void bootloader_hardware_init(void) esp_rom_spiflash_fix_dummylen(1, 1); #endif -//TODO: [ESP32C61] IDF-9276 -#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!"); -#else - ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!"); -#endif + /* Enable analog i2c master clock */ + SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-9274 Remove this? + SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M); } static inline void bootloader_ana_reset_config(void) diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt index 759952944c..7ce5ce6653 100644 --- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt @@ -18,7 +18,7 @@ if(NOT BOOTLOADER_BUILD) endif() -# TODO: [ESP32C61] IDF-9250, [ESP32C61] IDF-9276 +# TODO: [ESP32C61] IDF-9250 if(CONFIG_IDF_TARGET_ESP32C61) list(REMOVE_ITEM srcs "pmu_param.c" diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index e5e00f6047..a3fd389478 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -63,6 +63,10 @@ config ESP_ROM_HAS_SPI_FLASH bool default y +config ESP_ROM_WITHOUT_REGI2C + bool + default y + config ESP_ROM_HAS_NEWLIB bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index ba64361270..341dec7b83 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -21,8 +21,7 @@ #define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk() #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver -// TODO: [ESP32C61] IDF-9276, still should be true, temp commented -// #define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs TODO: IDF-10110 need refactor #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c new file mode 100644 index 0000000000..daffbd513e --- /dev/null +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c @@ -0,0 +1,178 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/pmu_reg.h" // TODO: IDF-9249 Can be removed +#include "modem/modem_lpcon_reg.h" + +#define REGI2C_BIAS_MST_SEL (BIT(8)) +#define REGI2C_BBPLL_MST_SEL (BIT(9)) +#define REGI2C_ULP_CAL_MST_SEL (BIT(10)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(11)) +#define REGI2C_DIG_REG_MST_SEL (BIT(12)) + +#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_ANA_MST_ANA_CONF1_M) +#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_ANA_MST_ANA_CONF1_M) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ + +#define REGI2C_BBPLL (0x66) +#define REGI2C_BBPLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_ULP_CAL (0x61) +#define REGI2C_ULP_CAL_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 + +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + uint32_t i2c_sel = 0; + + REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-9249 Move to pmu_init() + REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-9249 Move to pmu_init() + + /* Before config I2C register, enable corresponding slave. */ + switch (block) { + case REGI2C_BBPLL : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + break; + case REGI2C_BIAS : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + break; + case REGI2C_DIG_REG: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + break; + case REGI2C_ULP_CAL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + break; + case REGI2C_SAR_I2C: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + break; + } + + return (uint8_t)(i2c_sel ? 0: 1); +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + return ret; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + return ret; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h index dcc2f6fe18..dbd84d1dd2 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -15,8 +15,6 @@ extern "C" { #endif -// TODO: [ESP32C61] IDF-9276, inherit from c6 - /** * @brief Start BBPLL self-calibration */ diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h index 4089e68b3e..6e38d22574 100644 --- a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h @@ -14,89 +14,89 @@ extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -124,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -146,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2210310 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h index d0f6d4c843..0f28b3a7a3 100644 --- a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,89 +14,89 @@ extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -124,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -146,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index d5e20a3715..c1669c6086 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -47,6 +47,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_REG_I2C_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y diff --git a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h index 8e80288ead..08aea2d8c9 100644 --- a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h +++ b/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h @@ -9,96 +9,94 @@ #include #include "soc/soc.h" -//TODO: [ESP32C61] IDF-9276, inherit from c6 - #ifdef __cplusplus extern "C" { #endif #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) -/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C0_BUSY_V 0x1 #define I2C_ANA_MST_I2C0_BUSY_S 25 -/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S)) #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C0_CTRL_S 0 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) -/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) #define I2C_ANA_MST_I2C1_BUSY_V 0x1 #define I2C_ANA_MST_I2C1_BUSY_S 25 -/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF -#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S)) #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF #define I2C_ANA_MST_I2C1_CTRL_S 0 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) -/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_STATUS 0x000000FF -#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S)) #define I2C_ANA_MST_I2C0_STATUS_V 0xFF #define I2C_ANA_MST_I2C0_STATUS_S 24 -/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S)) #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C0_CONF_S 0 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) -/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_STATUS 0x000000FF -#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S)) #define I2C_ANA_MST_I2C1_STATUS_V 0xFF #define I2C_ANA_MST_I2C1_STATUS_S 24 -/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF -#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S)) #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF #define I2C_ANA_MST_I2C1_CONF_S 0 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) -/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF -#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_ANA_MST_BURST_CTRL_V)<<(I2C_ANA_MST_BURST_CTRL_S)) #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF #define I2C_ANA_MST_BURST_CTRL_S 0 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) -/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/* I2C_ANA_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF -#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_BURST_TIMEOUT_CNT_S)) #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 -/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* I2C_ANA_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 -/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_ANA_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 -/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_ANA_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define I2C_ANA_MST_BURST_DONE (BIT(0)) #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) @@ -126,7 +124,7 @@ extern "C" { #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_S 24 -/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /*description: .*/ #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) @@ -148,72 +146,72 @@ extern "C" { #define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) -/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) -/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 -/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) -/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) #define I2C_ANA_MST_ARBITER_DIS_V 0x1 #define I2C_ANA_MST_ARBITER_DIS_S 11 -/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F -#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)) #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 -/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ /*description: .*/ #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F -#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)) #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) -/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* I2C_ANA_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: .*/ #define I2C_ANA_MST_NOUSE 0xFFFFFFFF -#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_M ((I2C_ANA_MST_NOUSE_V)<<(I2C_ANA_MST_NOUSE_S)) #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF #define I2C_ANA_MST_NOUSE_S 0 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) -/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ /*description: .*/ #define I2C_ANA_MST_CLK_EN (BIT(28)) #define I2C_ANA_MST_CLK_EN_M (BIT(28)) #define I2C_ANA_MST_CLK_EN_V 0x1 #define I2C_ANA_MST_CLK_EN_S 28 -/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2210310 ; */ /*description: .*/ #define I2C_ANA_MST_DATE 0x0FFFFFFF -#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S)) #define I2C_ANA_MST_DATE_V 0xFFFFFFF #define I2C_ANA_MST_DATE_S 0 diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 4a6a58e388..226a2517f9 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -41,7 +41,7 @@ #define DR_REG_MODEM1_BASE 0x600AC000 #define DR_REG_MODEM_PWR0_BASE 0x600AD000 #define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 //TODO: [ESP32C61] IDF-9276, from verify +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 47ac1eed8b..527b2d1ccb 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -61,7 +61,7 @@ #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314 // \#define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236 // \#define SOC_MODEM_CLOCK_SUPPORTED 1 -// \#define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9276 +#define SOC_REG_I2C_SUPPORTED 1 // \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 // \#define SOC_ETM_SUPPORTED 0 From 3aa27ae9602cc3e8f3c5f44abf14ad14f034bb31 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 8 Jul 2024 22:06:12 +0800 Subject: [PATCH 3/4] refactor(regi2c): add LL function to control analog i2c master clock --- .../src/esp32c5/bootloader_esp32c5.c | 10 ++-- .../src/esp32c6/bootloader_esp32c6.c | 11 ++-- .../src/esp32c61/bootloader_esp32c61.c | 10 ++-- .../src/esp32h2/bootloader_esp32h2.c | 12 ++--- .../src/esp32p4/bootloader_esp32p4.c | 8 ++- components/esp_hw_support/modem_clock.c | 3 +- .../esp_hw_support/port/esp32c5/rtc_clk.c | 6 +-- .../esp_hw_support/port/esp32c6/rtc_clk.c | 7 +-- .../esp_hw_support/port/esp32c61/rtc_clk.c | 6 +-- .../esp_hw_support/port/esp32h2/rtc_clk.c | 7 +-- .../patches/esp_rom_hp_regi2c_esp32c5.c | 4 +- .../patches/esp_rom_hp_regi2c_esp32c6.c | 7 ++- .../esp_rom/patches/esp_rom_regi2c_esp32c61.c | 4 +- .../esp_rom/patches/esp_rom_regi2c_esp32h2.c | 4 +- .../esp_rom/patches/esp_rom_regi2c_esp32p4.c | 8 +-- .../hal/esp32c5/include/hal/modem_lpcon_ll.h | 25 --------- .../hal/esp32c5/include/hal/regi2c_ctrl_ll.h | 54 +++++++++++++++---- .../hal/esp32c6/include/hal/modem_lpcon_ll.h | 27 +--------- .../hal/esp32c6/include/hal/regi2c_ctrl_ll.h | 36 ++++++++++++- .../hal/esp32c61/include/hal/regi2c_ctrl_ll.h | 52 ++++++++++++++---- .../hal/esp32h2/include/hal/modem_lpcon_ll.h | 21 +------- .../hal/esp32h2/include/hal/regi2c_ctrl_ll.h | 37 ++++++++++++- .../hal/esp32p4/include/hal/regi2c_ctrl_ll.h | 35 +++++++++++- .../soc/esp32c5/include/soc/regi2c_defs.h | 16 +----- .../soc/esp32c61/include/soc/regi2c_defs.h | 16 +----- .../esp32p4/include/soc/i2c_ana_mst_struct.h | 3 +- .../soc/esp32p4/ld/esp32p4.peripherals.ld | 2 +- 27 files changed, 242 insertions(+), 189 deletions(-) diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 5c5ac3d6ed..e8a1edd123 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -41,8 +41,7 @@ #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" -#include "modem/modem_lpcon_reg.h" -#include "modem/modem_syscon_reg.h" +#include "hal/regi2c_ctrl_ll.h" static const char *TAG = "boot.esp32c5"; @@ -85,10 +84,9 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { - /* Enable analog i2c master clock */ - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-8667 Remove this? - SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M); + regi2c_ctrl_ll_master_enable_clock(true); + regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this? + regi2c_ctrl_ll_master_configure_clock(); } static inline void bootloader_ana_reset_config(void) diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index 6e0ff2c1a1..1c13100da6 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,7 +43,7 @@ #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" static const char *TAG = "boot.esp32c6"; @@ -95,9 +95,8 @@ static inline void bootloader_hardware_init(void) esp_rom_spiflash_fix_dummylen(1, 1); #endif - /* Enable analog i2c master clock */ - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); + regi2c_ctrl_ll_master_enable_clock(true); + regi2c_ctrl_ll_master_configure_clock(); } static inline void bootloader_ana_reset_config(void) @@ -167,7 +166,7 @@ esp_err_t bootloader_init(void) } #endif // !CONFIG_APP_BUILD_TYPE_RAM - // check whether a WDT reset happend + // check whether a WDT reset happened bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index 45d26a18db..2e83ebccff 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -43,8 +43,7 @@ #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" -#include "modem/modem_lpcon_reg.h" -#include "modem/modem_syscon_reg.h" +#include "hal/regi2c_ctrl_ll.h" static const char *TAG = "boot.esp32c61"; @@ -96,10 +95,9 @@ static inline void bootloader_hardware_init(void) esp_rom_spiflash_fix_dummylen(1, 1); #endif - /* Enable analog i2c master clock */ - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-9274 Remove this? - SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M); + regi2c_ctrl_ll_master_enable_clock(true); + regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this? + regi2c_ctrl_ll_master_configure_clock(); } static inline void bootloader_ana_reset_config(void) diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index 17934d512a..85b261bb40 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,7 +31,6 @@ #include "esp_private/regi2c_ctrl.h" #include "soc/regi2c_lp_bias.h" #include "soc/regi2c_bias.h" -#include "modem/modem_lpcon_reg.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" @@ -43,7 +42,7 @@ #include "soc/lp_wdt_reg.h" #include "soc/pmu_reg.h" #include "hal/efuse_hal.h" -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" static const char *TAG = "boot.esp32h2"; @@ -89,8 +88,9 @@ static inline void bootloader_hardware_init(void) /* Disable RF pll by default */ CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL); SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL); - /* Enable analog i2c master clock */ - SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + + regi2c_ctrl_ll_master_enable_clock(true); + regi2c_ctrl_ll_master_configure_clock(); } static inline void bootloader_ana_reset_config(void) @@ -160,7 +160,7 @@ esp_err_t bootloader_init(void) } #endif // !CONFIG_APP_BUILD_TYPE_RAM - // check whether a WDT reset happend + // check whether a WDT reset happened bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index 1020dc663a..e70a3de9a7 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -48,6 +48,7 @@ #include "soc/regi2c_cpll.h" #include "soc/regi2c_bias.h" #include "esp_private/periph_ctrl.h" +#include "hal/regi2c_ctrl_ll.h" static const char *TAG = "boot.esp32p4"; @@ -92,8 +93,10 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { - int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); - // regi2c is enabled by default on ESP32P4, do nothing + int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV + regi2c_ctrl_ll_master_enable_clock(true); + regi2c_ctrl_ll_master_configure_clock(); + unsigned chip_version = efuse_hal_chip_revision(); if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader @@ -106,6 +109,7 @@ static inline void bootloader_hardware_init(void) REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10); // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used. + int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) { spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL); spimem_ctrlr_ll_set_core_clock(0, 6); diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 292ff23beb..b593f8b4e7 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -17,6 +17,7 @@ #include "esp_sleep.h" #include "hal/efuse_hal.h" #include "hal/clk_tree_ll.h" +#include "hal/regi2c_ctrl_ll.h" // Please define the frequently called modules in the low bit, // which will improve the execution efficiency @@ -117,7 +118,7 @@ static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable) { - modem_lpcon_ll_enable_i2c_master_clock(ctx->hal->lpcon_dev, enable); + regi2c_ctrl_ll_master_enable_clock(enable); } static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable) diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index c550c44d0c..c369fcac4d 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -22,12 +22,8 @@ #include "esp_private/sleep_event.h" #if SOC_MODEM_CLOCK_SUPPORTED -#ifdef BOOTLOADER_BUILD -#include "hal/modem_lpcon_ll.h" -#else #include "esp_private/esp_modem_clock.h" #endif -#endif static const char *TAG = "rtc_clk"; @@ -150,7 +146,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable) { #if SOC_MODEM_CLOCK_SUPPORTED #ifdef BOOTLOADER_BUILD - modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable); + regi2c_ctrl_ll_master_enable_clock(enable); #else if (enable) { modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 228a713ad9..521e2fd03f 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -20,12 +20,7 @@ #include "soc/io_mux_reg.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" - -#ifdef BOOTLOADER_BUILD -#include "hal/modem_lpcon_ll.h" -#else #include "esp_private/esp_modem_clock.h" -#endif static const char *TAG = "rtc_clk"; @@ -147,7 +142,7 @@ static void rtc_clk_bbpll_enable(void) static void rtc_clk_enable_i2c_ana_master_clock(bool enable) { #ifdef BOOTLOADER_BUILD - modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable); + regi2c_ctrl_ll_master_enable_clock(enable); #else if (enable) { modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE); diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index 3a20ede1b9..1f652f17fe 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -22,12 +22,8 @@ #include "esp_private/sleep_event.h" #if SOC_MODEM_CLOCK_SUPPORTED //TODO: [ESP32C61] IDF-9513 -#ifdef BOOTLOADER_BUILD -#include "hal/modem_lpcon_ll.h" -#else #include "esp_private/esp_modem_clock.h" #endif -#endif static const char *TAG = "rtc_clk"; @@ -151,7 +147,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable) // TODO: [ESP32C61] IDF-9513, modem support #if SOC_MODEM_CLOCK_SUPPORTED #ifdef BOOTLOADER_BUILD - modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable); + regi2c_ctrl_ll_master_enable_clock(enable); #else if (enable) { modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE); diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index 27898a95b4..0c6664fdce 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -20,12 +20,7 @@ #include "soc/io_mux_reg.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" - -#ifdef BOOTLOADER_BUILD -#include "hal/modem_lpcon_ll.h" -#else #include "esp_private/esp_modem_clock.h" -#endif static const char *TAG = "rtc_clk"; @@ -163,7 +158,7 @@ static void rtc_clk_bbpll_enable(void) static void rtc_clk_enable_i2c_ana_master_clock(bool enable) { #ifdef BOOTLOADER_BUILD - modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable); + regi2c_ctrl_ll_master_enable_clock(enable); #else if (enable) { modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE); diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c index dedebaee47..4f75c8adff 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c +++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c @@ -6,7 +6,7 @@ #include "esp_rom_sys.h" #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" #define REGI2C_BIAS_MST_SEL (BIT(8)) #define REGI2C_BBPLL_MST_SEL (BIT(9)) @@ -75,7 +75,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + regi2c_ctrl_ll_master_enable_clock(true); /* Before config I2C register, enable corresponding slave. */ switch (block) { diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c index f89538d210..2ae4b905d5 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c +++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "esp_rom_sys.h" #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" /** * BB - 0x67 - BIT0 * TXRF - 0x6B - BIT1 @@ -86,8 +86,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); + regi2c_ctrl_ll_master_enable_clock(true); /* Before config I2C register, enable corresponding slave. */ switch (block) { diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c index daffbd513e..b25b405fcc 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c @@ -7,7 +7,7 @@ #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" #include "soc/pmu_reg.h" // TODO: IDF-9249 Can be removed -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" #define REGI2C_BIAS_MST_SEL (BIT(8)) #define REGI2C_BBPLL_MST_SEL (BIT(9)) @@ -76,7 +76,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + regi2c_ctrl_ll_master_enable_clock(true); REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-9249 Move to pmu_init() REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-9249 Move to pmu_init() diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c b/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c index 05ffae9d6b..58815d15bc 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c @@ -6,7 +6,7 @@ #include "esp_rom_sys.h" #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" -#include "modem/modem_lpcon_reg.h" +#include "hal/regi2c_ctrl_ll.h" /** * BB - 0x67 - BIT0 @@ -86,7 +86,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { uint32_t i2c_sel = 0; - REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + regi2c_ctrl_ll_master_enable_clock(true); /* Before config I2C register, enable corresponding slave. */ switch (block) { diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c index 08fff85a74..5de1ba2827 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "esp_rom_sys.h" #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/lpperi_reg.h" +#include "hal/regi2c_ctrl_ll.h" /** * DIG_REG - 0x6D - BIT10 * PLL_CPU - 0x67 - BIT11 @@ -87,8 +87,8 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { - REG_SET_BIT(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_I2CMST); - SET_PERI_REG_MASK(I2C_ANA_MST_CLK160M_REG, I2C_ANA_MST_CLK_I2C_MST_SEL_160M); + int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // Right now this patch in rom can not depend on esp_hw_support, after IDF-10110 is done, this should be removed, should have spinlock protection + regi2c_ctrl_ll_master_enable_clock(true); REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0); REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0); diff --git a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h index 91bd12b7c1..fd2d537510 100644 --- a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h @@ -133,12 +133,6 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) -{ - // ESP32C5 Not Support -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_set_modem_pwr_clk_src_fo(modem_lpcon_dev_t *hw, bool value) { @@ -169,12 +163,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool hw->clk_conf.clk_coex_en = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf.clk_i2c_mst_en = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) { @@ -193,12 +181,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, hw->clk_conf_force_on.clk_coex_fo = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf_force_on.clk_i2c_mst_fo = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) { @@ -267,13 +249,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) hw->rst_conf.rst_coex = 0; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) -{ - hw->rst_conf.rst_i2c_mst = 1; - hw->rst_conf.rst_i2c_mst = 0; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw) { diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h index 597cbdf368..81db4b07fc 100644 --- a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,18 +10,54 @@ #include #include "soc/soc.h" #include "soc/regi2c_defs.h" +#include "modem/modem_lpcon_struct.h" +#include "modem/modem_syscon_struct.h" +#include "soc/i2c_ana_mst_reg.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; +} + +/** + * @brief Reset analog I2C master + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +{ + MODEM_LPCON.rst_conf.rst_i2c_mst = 1; + MODEM_LPCON.rst_conf.rst_i2c_mst = 0; +} + +/** + * @brief Force enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en; +} + +/** + * @brief Configure analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) +{ + MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1; +} + /** * @brief Start BBPLL self-calibration */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); } /** @@ -29,8 +65,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); } /** @@ -40,7 +76,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) { - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } /** @@ -48,8 +84,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati */ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) { - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + // TODO: IDF-8727 } /** @@ -57,8 +92,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) */ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) { - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); + // TODO: IDF-8727 } #ifdef __cplusplus diff --git a/components/hal/esp32c6/include/hal/modem_lpcon_ll.h b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h index b29c231cc0..55d81ff5cc 100644 --- a/components/hal/esp32c6/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -133,12 +133,6 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->i2c_mst_clk_conf.clk_i2c_mst_sel_160m = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src) { @@ -157,12 +151,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool hw->clk_conf.clk_coex_en = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf.clk_i2c_mst_en = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) { @@ -181,12 +169,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, hw->clk_conf_force_on.clk_coex_fo = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf_force_on.clk_i2c_mst_fo = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) { @@ -255,13 +237,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) hw->rst_conf.rst_coex = 0; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) -{ - hw->rst_conf.rst_i2c_mst = 1; - hw->rst_conf.rst_i2c_mst = 0; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw) { diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h index 597cbdf368..984ef04126 100644 --- a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,11 +10,45 @@ #include #include "soc/soc.h" #include "soc/regi2c_defs.h" +#include "modem/modem_lpcon_struct.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; +} + +/** + * @brief Reset analog I2C master + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +{ + MODEM_LPCON.rst_conf.rst_i2c_mst = 1; + MODEM_LPCON.rst_conf.rst_i2c_mst = 0; +} + +/** + * @brief Force enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en; +} + +/** + * @brief Configure analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) +{ + MODEM_LPCON.i2c_mst_clk_conf.clk_i2c_mst_sel_160m = 1; +} + /** * @brief Start BBPLL self-calibration */ diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h index dbd84d1dd2..9e94417baa 100644 --- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h @@ -10,18 +10,54 @@ #include #include "soc/soc.h" #include "soc/regi2c_defs.h" +#include "modem/modem_lpcon_struct.h" +#include "modem/modem_syscon_struct.h" +#include "soc/i2c_ana_mst_reg.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; +} + +/** + * @brief Reset analog I2C master + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +{ + MODEM_LPCON.rst_conf.rst_i2c_mst = 1; + MODEM_LPCON.rst_conf.rst_i2c_mst = 0; +} + +/** + * @brief Force enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en; +} + +/** + * @brief Configure analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) +{ + MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1; +} + /** * @brief Start BBPLL self-calibration */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); } /** @@ -29,8 +65,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) { - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); } /** @@ -40,7 +76,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati */ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) { - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); + return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); } /** @@ -48,8 +84,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati */ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) { - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + // TODO: IDF-9322 } /** @@ -57,8 +92,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) */ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) { - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); + // TODO: IDF-9322 } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/modem_lpcon_ll.h b/components/hal/esp32h2/include/hal/modem_lpcon_ll.h index b465124d7b..d4e23893ce 100644 --- a/components/hal/esp32h2/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32h2/include/hal/modem_lpcon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -67,12 +67,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool hw->clk_conf.clk_coex_en = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf.clk_i2c_mst_en = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en) { @@ -85,12 +79,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, hw->clk_conf_force_on.clk_coex_fo = en; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) -{ - hw->clk_conf_force_on.clk_i2c_mst_fo = en; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en) { @@ -104,13 +92,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) hw->rst_conf.rst_coex = 0; } -__attribute__((always_inline)) -static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) -{ - hw->rst_conf.rst_i2c_mst = 1; - hw->rst_conf.rst_i2c_mst = 0; -} - __attribute__((always_inline)) static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw) { diff --git a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h index d728e53f67..179fd2db3e 100644 --- a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,12 +11,45 @@ #include "soc/soc.h" #include "soc/regi2c_defs.h" #include "soc/i2c_ana_mst_reg.h" - +#include "modem/modem_lpcon_struct.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; +} + +/** + * @brief Reset analog I2C master + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +{ + MODEM_LPCON.rst_conf.rst_i2c_mst = 1; + MODEM_LPCON.rst_conf.rst_i2c_mst = 0; +} + +/** + * @brief Force enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en) +{ + MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en; +} + +/** + * @brief Configure analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) +{ + // Nothing to configure +} + /** * @brief Start BBPLL self-calibration */ diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h index 5647164b23..75744b44d4 100644 --- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,11 +11,44 @@ #include "soc/soc.h" #include "soc/regi2c_defs.h" #include "soc/hp_sys_clkrst_reg.h" +#include "soc/lpperi_struct.h" +#include "soc/i2c_ana_mst_struct.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Enable analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en) +{ + LPPERI.clk_en.ck_en_lp_i2cmst = en; +} + +// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__) + +/** + * @brief Reset analog I2C master + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void) +{ + LPPERI.reset_en.rst_en_lp_i2cmst = 1; + LPPERI.reset_en.rst_en_lp_i2cmst = 0; +} + +// LPPERI.reset_en is a shared register, so this function must be used in an atomic way +#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_reset(__VA_ARGS__) + +/** + * @brief Configure analog I2C master clock + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void) +{ + I2C_ANA_MST.clk160m.clk_i2c_mst_sel_160m = 1; +} + /** * @brief Start CPLL self-calibration */ diff --git a/components/soc/esp32c5/include/soc/regi2c_defs.h b/components/soc/esp32c5/include/soc/regi2c_defs.h index 0cfa9d75a0..546da9fee6 100644 --- a/components/soc/esp32c5/include/soc/regi2c_defs.h +++ b/components/soc/esp32c5/include/soc/regi2c_defs.h @@ -9,21 +9,7 @@ #include "esp_bit_defs.h" /* Analog function control register */ -#define I2C_MST_ANA_CONF0_REG 0x600AF818 +// I2C_ANA_MST_ANA_CONF0_REG #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24)) - - -#define ANA_CONFIG_REG 0x600AF81C -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) - -#define ANA_I2C_SAR_FORCE_PD BIT(18) -#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - - -#define ANA_CONFIG2_REG 0x600AF820 -#define ANA_CONFIG2_M BIT(18) - -#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32c61/include/soc/regi2c_defs.h b/components/soc/esp32c61/include/soc/regi2c_defs.h index 9de6bd6385..a3eb90d9c7 100644 --- a/components/soc/esp32c61/include/soc/regi2c_defs.h +++ b/components/soc/esp32c61/include/soc/regi2c_defs.h @@ -9,21 +9,7 @@ #include "esp_bit_defs.h" /* Analog function control register */ -#define I2C_MST_ANA_CONF0_REG 0x600AF818 +// I2C_ANA_MST_ANA_CONF0_REG #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) #define I2C_MST_BBPLL_CAL_DONE (BIT(24)) - - -#define ANA_CONFIG_REG 0x600AF81C -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) - -#define ANA_I2C_SAR_FORCE_PD BIT(18) -#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - - -#define ANA_CONFIG2_REG 0x600AF820 -#define ANA_CONFIG2_M BIT(18) - -#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h index bbf169b28b..94a722bb2b 100644 --- a/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h +++ b/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h @@ -275,7 +275,7 @@ typedef union { } i2c_ana_mst_date_reg_t; -typedef struct { +typedef struct i2c_ana_mst_dev_t { volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl; volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; @@ -293,6 +293,7 @@ typedef struct { volatile i2c_ana_mst_date_reg_t date; } i2c_ana_mst_dev_t; +extern i2c_ana_mst_dev_t I2C_ANA_MST; #ifndef __cplusplus _Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure"); diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 82b7bd46b7..a0ae5ba367 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -85,7 +85,7 @@ PROVIDE ( LP_TOUCH = 0x50128000 ); PROVIDE ( LP_GPIO = 0x5012A000 ); PROVIDE ( LP_PERI_PMS = 0x5012E000 ); PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 ); -PROVIDE ( LP_I2C_ANA_MST = 0x50124000 ); +PROVIDE ( I2C_ANA_MST = 0x50124000 ); PROVIDE ( LP_ANA_PERI = 0x50113000 ); PROVIDE ( AHB_DMA = 0x50085000 ); PROVIDE ( AXI_DMA = 0x5008a000 ); From 71d37f9ea83df3ad9f23254518270d5e8c85a0df Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 24 Jul 2024 15:45:21 +0800 Subject: [PATCH 4/4] fix(ci): wrap sleep related code with porper caps for ble throughput_app --- .../components/cmd_system/cmd_system.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c index 59fe12c6e8..b39ba53ff6 100644 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c +++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,8 +30,12 @@ static void register_free(void); static void register_heap(void); static void register_version(void); static void register_restart(void); +#if SOC_DEEP_SLEEP_SUPPORTED static void register_deep_sleep(void); +#endif +#if SOC_LIGHT_SLEEP_SUPPORTED static void register_light_sleep(void); +#endif #if WITH_TASKS_INFO static void register_tasks(void); #endif @@ -42,8 +46,12 @@ void register_system(void) register_heap(); register_version(); register_restart(); +#if SOC_DEEP_SLEEP_SUPPORTED register_deep_sleep(); +#endif +#if SOC_LIGHT_SLEEP_SUPPORTED register_light_sleep(); +#endif #if WITH_TASKS_INFO register_tasks(); #endif @@ -61,7 +69,7 @@ static int get_version(int argc, char **argv) } printf("IDF Version:%s\r\n", esp_get_idf_version()); printf("Chip info:\r\n"); - printf("\tmodel:%s\r\n", info.model == CHIP_ESP32 ? "ESP32" : "Unknow"); + printf("\tmodel:%s\r\n", info.model == CHIP_ESP32 ? "ESP32" : "Unknown"); printf("\tcores:%d\r\n", info.cores); printf("\tfeature:%s%s%s%s%" PRIu32 "%s\r\n", info.features & CHIP_FEATURE_WIFI_BGN ? "/802.11bgn" : "", @@ -122,7 +130,7 @@ static void register_free(void) ESP_ERROR_CHECK( esp_console_cmd_register(&cmd) ); } -/* 'heap' command prints minumum heap size */ +/* 'heap' command prints minimum heap size */ static int heap_size(int argc, char **argv) { uint32_t heap_size = heap_caps_get_minimum_free_size(MALLOC_CAP_DEFAULT); @@ -177,6 +185,7 @@ static void register_tasks(void) #endif // WITH_TASKS_INFO +#if SOC_DEEP_SLEEP_SUPPORTED /** 'deep_sleep' command puts the chip into deep sleep mode */ static struct { @@ -250,7 +259,9 @@ static void register_deep_sleep(void) }; ESP_ERROR_CHECK( esp_console_cmd_register(&cmd) ); } +#endif // SOC_DEEP_SLEEP_SUPPORTED +#if SOC_LIGHT_SLEEP_SUPPORTED /** 'light_sleep' command puts the chip into light sleep mode */ static struct { @@ -345,3 +356,4 @@ static void register_light_sleep(void) }; ESP_ERROR_CHECK( esp_console_cmd_register(&cmd) ); } +#endif // SOC_LIGHT_SLEEP_SUPPORTED