diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c index 410f60e79b..ae3460ee06 100644 --- a/components/esp_driver_gpio/src/dedic_gpio.c +++ b/components/esp_driver_gpio/src/dedic_gpio.c @@ -15,7 +15,7 @@ #include "esp_log.h" #include "esp_check.h" #include "esp_cpu.h" -#include "soc/soc_caps.h" +#include "soc/soc_caps_full.h" #include "soc/io_mux_reg.h" #include "hal/dedic_gpio_cpu_ll.h" #include "esp_private/gpio.h" @@ -25,10 +25,10 @@ #include "driver/dedic_gpio.h" #include "soc/dedic_gpio_periph.h" -#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS +#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS #include "soc/dedic_gpio_struct.h" #endif -#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE #include "hal/dedic_gpio_ll.h" #endif @@ -50,11 +50,11 @@ struct dedic_gpio_platform_t { uint32_t in_occupied_mask; // mask of input channels that already occupied #if SOC_DEDIC_GPIO_HAS_INTERRUPT intr_handle_t intr_hdl; // interrupt handle - dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // array of callback function for input channel - void *cb_args[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // array of callback arguments for input channel - dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // which bundle belongs to for input channel + dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback function for input channel + void *cb_args[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // array of callback arguments for input channel + dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel #endif -#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS +#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS dedic_dev_t *dev; #endif }; @@ -81,18 +81,18 @@ static esp_err_t dedic_gpio_build_platform(int core_id) // initialize platform members s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; // initial occupy_mask: 1111...100...0 - s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1); - s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1); -#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS + s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1); + s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1); +#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS s_platform[core_id]->dev = &DEDIC_GPIO; -#endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS -#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE +#endif // DEDIC_GPIO_LL_ALLOW_REG_ACCESS +#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE // enable dedicated GPIO register clock PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(true); dedic_gpio_ll_reset_register(); } -#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE } } _lock_release(&s_platform_mutexlock[core_id]); @@ -113,12 +113,12 @@ static void dedic_gpio_break_platform(int core_id) if (s_platform[core_id]) { free(s_platform[core_id]); s_platform[core_id] = NULL; -#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE +#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE // disable the register clock if no GPIO channel is in use PERIPH_RCC_ATOMIC() { dedic_gpio_ll_enable_bus_clock(false); } -#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE +#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE } _lock_release(&s_platform_mutexlock[core_id]); } @@ -222,11 +222,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure outwards channels uint32_t out_offset = 0; if (config->flags.out_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM, ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM); + ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size; i++) { + for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) { out_mask = pattern << i; out_offset = i; @@ -235,7 +235,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ } if (out_mask) { s_platform[core_id]->out_occupied_mask |= out_mask; -#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS +#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS // always enable instruction to access output GPIO, which has better performance than register access dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true); #endif @@ -248,11 +248,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ // configure inwards channels uint32_t in_offset = 0; if (config->flags.in_en) { - ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM, ESP_ERR_INVALID_ARG, err, TAG, - "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM); + ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG, + "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)); // prevent install bundle concurrently portENTER_CRITICAL(&s_platform[core_id]->spinlock); - for (size_t i = 0; i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size; i++) { + for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU) - config->array_size; i++) { if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) { in_mask = pattern << i; in_offset = i; @@ -280,9 +280,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false); } -#if !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE dedic_gpio_cpu_ll_enable_output(s_platform[core_id]->out_occupied_mask); -#endif // !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE } // it's safe to initialize bundle members without locks here @@ -322,8 +320,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle) portENTER_CRITICAL(&s_platform[core_id]->spinlock); s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask); s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask); - if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1)) && - s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1))) { + if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1)) && + s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1))) { recycle_all = true; } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index 9b3f73635e..7f8f5362c0 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,16 +11,17 @@ #include "unity.h" #include "unity_test_utils.h" #include "esp_rom_sys.h" -#include "soc/soc_caps.h" +#include "soc/soc_caps_full.h" +#include "soc/dedic_gpio_periph.h" #include "hal/dedic_gpio_cpu_ll.h" #include "driver/gpio.h" #include "driver/dedic_gpio.h" TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") { - const int test_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2] = {0}; - const int test2_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2 + 1] = {0}; - const int test3_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + 1] = {0}; + const int test_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2] = {0}; + const int test2_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2 + 1] = {0}; + const int test3_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) + 1] = {0}; dedic_gpio_bundle_handle_t test_bundle, test_bundle2, test_bundle3 = NULL; dedic_gpio_bundle_config_t bundle_config = { .gpio_array = test_gpios, @@ -47,7 +48,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]") TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, dedic_gpio_new_bundle(&bundle_config, &test_bundle), "create bundle with half channels failed"); uint32_t mask = 0; TEST_ESP_OK(dedic_gpio_get_out_mask(test_bundle, &mask)); - TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2)) - 1, mask, "wrong out mask"); + TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask"); TEST_ESP_OK(dedic_gpio_get_in_mask(test_bundle, &mask)); TEST_ASSERT_EQUAL_MESSAGE(0, mask, "wrong in mask"); diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c index 081d9ab2ec..58994204a1 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,7 @@ #include "unity.h" #include "driver/gpio_filter.h" #include "driver/dedic_gpio.h" -#include "soc/soc_caps.h" +#include "soc/soc_caps_full.h" #if CONFIG_IDF_TARGET_ESP32P4 #define TEST_FILTER_GPIO 20 @@ -79,7 +79,7 @@ TEST_CASE("GPIO flex glitch filter life cycle", "[gpio_filter]") * @note Because the CPU instruction / CSR register is not compatible in all ESP chips, * at the moment, this test only works for Espressif's RISC-V core (e.g. ESP32C6) */ -#if SOC_DEDICATED_GPIO_SUPPORTED +#if SOC_HAS(DEDICATED_GPIO) #include "hal/dedic_gpio_cpu_ll.h" @@ -182,5 +182,5 @@ TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]") vSemaphoreDelete(sem); } -#endif // SOC_DEDICATED_GPIO_SUPPORTED +#endif // SOC_HAS(DEDICATED_GPIO) #endif // SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0 diff --git a/components/esp_driver_ledc/include/driver/ledc.h b/components/esp_driver_ledc/include/driver/ledc.h index 984e265abb..07d1211684 100644 --- a/components/esp_driver_ledc/include/driver/ledc.h +++ b/components/esp_driver_ledc/include/driver/ledc.h @@ -45,6 +45,9 @@ typedef struct { struct ledc_channel_flags { unsigned int output_invert: 1; /*!< Enable (1) or disable (0) gpio output invert */ } flags; /*!< Extra configuration flags for LEDC channel */ + bool deconfigure; /*!< Set this field to de-configure a LEDC channel which has been configured before + The driver only does limited action to release the pins occupied by this channel only. + When this field is set, gpio_num, timer_sel, duty, hpoint, sleep_mode, flags fields are ignored. */ } ledc_channel_config_t; /** diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 3ab3483dcb..89e578ad16 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -94,6 +94,7 @@ typedef struct { bool channel_keep_alive[LEDC_CHANNEL_MAX]; /*!< Records whether each channel needs to keep output during sleep */ uint8_t timer_xpd_ref_cnt[LEDC_TIMER_MAX]; /*!< Records the timer (glb_clk) not power down during sleep requirement */ bool glb_clk_xpd; /*!< Records the power strategy applied to the global clock */ + uint64_t occupied_pin_mask[LEDC_CHANNEL_MAX]; /*!< Records the pins occupied by each channel */ } ledc_obj_t; static ledc_obj_t *p_ledc_obj[LEDC_SPEED_MODE_MAX] = { @@ -285,6 +286,7 @@ static IRAM_ATTR esp_err_t ledc_duty_config(ledc_mode_t speed_mode, ledc_channel static bool ledc_glb_clk_set_sleep_mode(ledc_mode_t speed_mode, bool xpd) { bool glb_clk_xpd_err = false; +#if SOC_LIGHT_SLEEP_SUPPORTED if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_RC_FAST) { esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_RC_FAST_MODE, xpd); p_ledc_obj[speed_mode]->glb_clk_xpd = xpd; @@ -300,6 +302,7 @@ static bool ledc_glb_clk_set_sleep_mode(ledc_mode_t speed_mode, bool xpd) glb_clk_xpd_err = true; } } +#endif return glb_clk_xpd_err; } @@ -761,6 +764,7 @@ static esp_err_t ledc_timer_del(ledc_mode_t speed_mode, ledc_timer_t timer_sel) ledc_glb_clk_set_sleep_mode(speed_mode, false); } } + ledc_ll_enable_timer_power(LEDC_LL_GET_HW(), speed_mode, timer_sel, false); } portEXIT_CRITICAL(&ledc_spinlock); ESP_RETURN_ON_FALSE(is_configured && is_deleted, ESP_ERR_INVALID_STATE, LEDC_TAG, "timer hasn't been configured, or it is still running, please stop it with ledc_timer_pause first"); @@ -789,6 +793,10 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf) return ESP_ERR_NO_MEM; } + portENTER_CRITICAL(&ledc_spinlock); + ledc_ll_enable_timer_power(LEDC_LL_GET_HW(), speed_mode, timer_num, true); + portEXIT_CRITICAL(&ledc_spinlock); + esp_err_t ret = ledc_set_timer_div(speed_mode, timer_num, timer_conf->clk_cfg, freq_hz, duty_resolution); if (ret == ESP_OK) { /* Make sure timer is running and reset the timer. */ @@ -798,7 +806,7 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf) return ret; } -esp_err_t _ledc_set_pin(int gpio_num, bool out_inv, ledc_mode_t speed_mode, ledc_channel_t channel) +static esp_err_t _ledc_set_pin(int gpio_num, bool out_inv, ledc_mode_t speed_mode, ledc_channel_t channel) { // reserve the GPIO output path, because we don't expect another peripheral to signal to the same GPIO uint64_t old_gpio_rsv_mask = esp_gpio_reserve(BIT64(gpio_num)); @@ -807,6 +815,9 @@ esp_err_t _ledc_set_pin(int gpio_num, bool out_inv, ledc_mode_t speed_mode, ledc ESP_LOGW(LEDC_TAG, "GPIO %d is not usable, maybe conflict with others", gpio_num); } gpio_matrix_output(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + channel, out_inv, false); + portENTER_CRITICAL(&ledc_spinlock); + p_ledc_obj[speed_mode]->occupied_pin_mask[channel] |= BIT64(gpio_num); + portEXIT_CRITICAL(&ledc_spinlock); return ESP_OK; } @@ -816,9 +827,31 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t chan LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num"); + LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); return _ledc_set_pin(gpio_num, false, speed_mode, channel); } +static esp_err_t ledc_channel_del(ledc_mode_t speed_mode, ledc_channel_t channel) +{ + LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); + + portENTER_CRITICAL(&ledc_spinlock); + // release all the pins occupied by this channel + while (p_ledc_obj[speed_mode]->occupied_pin_mask[channel]) { + int gpio_num = __builtin_ffsll(p_ledc_obj[speed_mode]->occupied_pin_mask[channel]) - 1; + gpio_output_disable(gpio_num); + esp_gpio_revoke(BIT64(gpio_num)); + p_ledc_obj[speed_mode]->occupied_pin_mask[channel] &= ~BIT64(gpio_num); + } + ledc_ll_enable_channel_power(LEDC_LL_GET_HW(), speed_mode, channel, false); + portEXIT_CRITICAL(&ledc_spinlock); + + // p_ledc_obj[speed_mode]->channel_keep_alive[channel] = false; + // TODO: dealing whether need to release the timer clock source xpd + // TODO: dealing whether can downgrade the sleep mode, so that retention link can be freed or peripheral clock can be gated during sleep + return ESP_OK; +} + esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) { LEDC_ARG_CHECK(ledc_conf, "ledc_conf"); @@ -831,6 +864,11 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) bool output_invert = ledc_conf->flags.output_invert; LEDC_ARG_CHECK(ledc_channel < LEDC_CHANNEL_MAX, "ledc_channel"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); + + if (ledc_conf->deconfigure) { + return ledc_channel_del(speed_mode, ledc_channel); + } + LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num"); LEDC_ARG_CHECK(timer_select < LEDC_TIMER_MAX, "timer_select"); LEDC_ARG_CHECK(ledc_conf->sleep_mode < LEDC_SLEEP_MODE_INVALID, "sleep_mode"); @@ -844,7 +882,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) if (!new_speed_mode_ctx_created && !p_ledc_obj[speed_mode]) { return ESP_ERR_NO_MEM; } -#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61) +#if LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT // On such targets, the default ledc core(global) clock does not connect to any clock source // Set channel configurations and update bits before core clock is on could lead to error // Therefore, we should connect the core clock to a real clock source to make it on before any ledc register operation @@ -853,13 +891,17 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) else if (new_speed_mode_ctx_created) { portENTER_CRITICAL(&ledc_spinlock); if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_UNINIT) { - ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true)); + esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true); ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), LEDC_LL_GLOBAL_CLK_DEFAULT); } portEXIT_CRITICAL(&ledc_spinlock); } #endif + portENTER_CRITICAL(&ledc_spinlock); + ledc_ll_enable_channel_power(LEDC_LL_GET_HW(), speed_mode, ledc_channel, true); + portEXIT_CRITICAL(&ledc_spinlock); + /*set channel parameters*/ /* channel parameters decide how the waveform looks like in one period */ /* set channel duty and hpoint value, duty range is [0, (2**duty_res)], hpoint range is [0, (2**duty_res)-1] */ @@ -929,6 +971,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) } #endif +#if SOC_LIGHT_SLEEP_SUPPORTED if (ledc_conf->sleep_mode == LEDC_SLEEP_MODE_KEEP_ALIVE) { // 1. timer clock source should not be powered down during sleep bool timer_xpd_err = false; @@ -956,6 +999,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) esp_sleep_clock_config(ESP_SLEEP_CLOCK_IOMUX, ESP_SLEEP_CLOCK_OPTION_UNGATE); #endif } +#endif return ret; } diff --git a/components/esp_driver_ledc/test_apps/ledc/README.md b/components/esp_driver_ledc/test_apps/ledc/README.md index 7b96141437..44f3780f1d 100644 --- a/components/esp_driver_ledc/test_apps/ledc/README.md +++ b/components/esp_driver_ledc/test_apps/ledc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt b/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt index 42ff0f2307..b68eb188e2 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt +++ b/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt @@ -1,9 +1,9 @@ set(srcs "test_app_main.c" - "test_ledc.c" - "test_ledc_utils.c") + "test_ledc.cpp" + "test_ledc_utils.cpp") if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) - list(APPEND srcs "test_ledc_sleep.c") + list(APPEND srcs "test_ledc_sleep.cpp") endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c b/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c index 50ecab4232..001b3eda72 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c @@ -10,8 +10,8 @@ #include "esp_newlib.h" // Some resources are lazy allocated in LEDC driver, the threshold is left for that case -// This leak is large since LEDC driver does not provide channel delete mechanism -#define TEST_MEMORY_LEAK_THRESHOLD (500) +// This leak is large since LEDC driver does not provide context free mechanism +#define TEST_MEMORY_LEAK_THRESHOLD (550) void setUp(void) { diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.cpp similarity index 87% rename from components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c rename to components/esp_driver_ledc/test_apps/ledc/main/test_ledc.cpp index 3d8f548f41..f101238c9e 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.cpp @@ -32,10 +32,21 @@ static void fade_setup(void) TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); vTaskDelay(5 / portTICK_PERIOD_MS); - //initialize fade service + // initialize fade service TEST_ESP_OK(ledc_fade_func_install(0)); } +static void fade_teardown(void) +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + + // deinitialize fade service + ledc_fade_func_uninstall(); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); +} + static void timer_duty_set_get(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty) { TEST_ESP_OK(ledc_set_duty(speed_mode, channel, duty)); @@ -67,6 +78,9 @@ static void timer_duty_test(ledc_channel_t channel, ledc_timer_bit_t timer_bit, timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 1 << (timer_bit - 1)); // 50% duty timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << timer_bit) - 1); timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << timer_bit) - 2); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } TEST_CASE("LEDC channel config wrong gpio", "[ledc]") @@ -100,7 +114,9 @@ TEST_CASE("LEDC wrong timer", "[ledc]") TEST_CASE("LEDC channel config basic parameter test", "[ledc]") { ledc_channel_config_t ledc_ch_config = initialize_channel_config(); - TEST_ASSERT_EQUAL(ESP_OK, ledc_channel_config(&ledc_ch_config)); + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } TEST_CASE("LEDC wrong duty resolution", "[ledc]") @@ -148,6 +164,9 @@ TEST_CASE("LEDC output idle level test", "[ledc]") TEST_ASSERT_EQUAL_INT32(!current_level, gpio_get_level(PULSE_IO)); esp_rom_delay_us(50); } + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } TEST_CASE("LEDC iterate over all channel and timer configs", "[ledc]") @@ -168,6 +187,10 @@ TEST_CASE("LEDC iterate over all channel and timer configs", "[ledc]") ledc_time_config.timer_num = (ledc_timer_t)k; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + ledc_ch_config.deconfigure = false; } } } @@ -191,6 +214,9 @@ TEST_CASE("LEDC memory leak test", "[ledc]") } TEST_ASSERT_INT32_WITHIN(100, size, esp_get_free_heap_size()); TEST_ESP_OK(ledc_stop(ledc_time_config.speed_mode, LEDC_CHANNEL_0, 0)); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } // duty should be manually checked from the waveform using a logic analyzer @@ -222,8 +248,7 @@ TEST_CASE("LEDC fade with time", "[ledc]") vTaskDelay(210 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT32(0, ledc_get_duty(test_speed_mode, LEDC_CHANNEL_0)); - //deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } TEST_CASE("LEDC fade with step", "[ledc]") @@ -245,8 +270,7 @@ TEST_CASE("LEDC fade with step", "[ledc]") //scaler=0 check TEST_ASSERT(ledc_set_fade_with_step(test_speed_mode, LEDC_CHANNEL_0, 4000, 0, 1) == ESP_ERR_INVALID_ARG); - //deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } TEST_CASE("LEDC fast switching duty with fade_wait_done", "[ledc]") @@ -276,8 +300,7 @@ TEST_CASE("LEDC fast switching duty with fade_wait_done", "[ledc]") vTaskDelay(5 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT32(500, ledc_get_duty(test_speed_mode, LEDC_CHANNEL_0)); - //deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } TEST_CASE("LEDC fast switching duty with fade_no_wait", "[ledc]") @@ -310,8 +333,7 @@ TEST_CASE("LEDC fast switching duty with fade_no_wait", "[ledc]") vTaskDelay(5 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT32(500, ledc_get_duty(test_speed_mode, LEDC_CHANNEL_0)); - //deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } #if SOC_LEDC_SUPPORT_FADE_STOP @@ -343,8 +365,7 @@ TEST_CASE("LEDC fade stop test", "[ledc]") TEST_ASSERT_EQUAL_INT32(duty_after_stop, ledc_get_duty(test_speed_mode, LEDC_CHANNEL_0)); TEST_ASSERT_NOT_EQUAL(4000, duty_after_stop); - //deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } #endif // SOC_LEDC_SUPPORT_FADE_STOP @@ -376,8 +397,7 @@ TEST_CASE("LEDC gamma ram write and read test", "[ledc]") TEST_ASSERT_EQUAL_INT32(i + 3, scale); } - // Deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } TEST_CASE("LEDC multi fade test", "[ledc]") @@ -387,13 +407,13 @@ TEST_CASE("LEDC multi fade test", "[ledc]") // Construct fade parameters const ledc_fade_param_config_t fade_params[] = { - {.dir = 1, .step_num = 100, .cycle_num = 1, .scale = 1}, - {.dir = 1, .step_num = 50, .cycle_num = 2, .scale = 2}, - {.dir = 1, .step_num = 200, .cycle_num = 10, .scale = 5}, - {.dir = 0, .step_num = 100, .cycle_num = 5, .scale = 5}, - {.dir = 1, .step_num = 1000, .cycle_num = 1, .scale = 1}, - {.dir = 0, .step_num = 200, .cycle_num = 1, .scale = 1}, - {.dir = 1, .step_num = 1, .cycle_num = 1000, .scale = 1000}, + {.dir = 1, .cycle_num = 1, .scale = 1, .step_num = 100}, + {.dir = 1, .cycle_num = 2, .scale = 2, .step_num = 50}, + {.dir = 1, .cycle_num = 10, .scale = 5, .step_num = 200}, + {.dir = 0, .cycle_num = 5, .scale = 5, .step_num = 100}, + {.dir = 1, .cycle_num = 1, .scale = 1, .step_num = 1000}, + {.dir = 0, .cycle_num = 1, .scale = 1, .step_num = 200}, + {.dir = 1, .cycle_num = 1000, .scale = 1000, .step_num = 1}, }; uint32_t fade_range = 7; int32_t start_duty = 2000; @@ -417,8 +437,7 @@ TEST_CASE("LEDC multi fade test", "[ledc]") // Check the duty at the end of the fade TEST_ASSERT_EQUAL_INT32((uint32_t)end_duty, ledc_get_duty(test_speed_mode, LEDC_CHANNEL_0)); - // Deinitialize fade service - ledc_fade_func_uninstall(); + fade_teardown(); } #endif // SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED @@ -436,13 +455,12 @@ static void frequency_set_get(ledc_mode_t speed_mode, ledc_timer_t timer, uint32 static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_bit, ledc_timer_t timer, ledc_mode_t speed_mode) { - ledc_timer_config_t ledc_time_config = { - .speed_mode = speed_mode, - .duty_resolution = timer_bit, - .timer_num = timer, - .freq_hz = TEST_PWM_FREQ, - .clk_cfg = TEST_DEFAULT_CLK_CFG, - }; + ledc_timer_config_t ledc_time_config = {}; + ledc_time_config.speed_mode = speed_mode; + ledc_time_config.duty_resolution = timer_bit; + ledc_time_config.timer_num = timer; + ledc_time_config.freq_hz = TEST_PWM_FREQ; + ledc_time_config.clk_cfg = TEST_DEFAULT_CLK_CFG; TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); TEST_ESP_OK(ledc_bind_channel_timer(speed_mode, channel, timer)); @@ -482,6 +500,9 @@ TEST_CASE("LEDC set and get frequency", "[ledc][timeout=60]") timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_HIGH_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_HIGH_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_3, LEDC_HIGH_SPEED_MODE); + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + ledc_ch_config.deconfigure = false; #endif // SOC_LEDC_SUPPORT_HS_MODE ledc_ch_config.speed_mode = LEDC_LOW_SPEED_MODE; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); @@ -489,19 +510,20 @@ TEST_CASE("LEDC set and get frequency", "[ledc][timeout=60]") timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_12_BIT, LEDC_TIMER_1, LEDC_LOW_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_12_BIT, LEDC_TIMER_2, LEDC_LOW_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_12_BIT, LEDC_TIMER_3, LEDC_LOW_SPEED_MODE); + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } #if SOC_CLK_TREE_SUPPORTED -static void timer_set_clk_src_and_freq_test(ledc_mode_t speed_mode, ledc_clk_cfg_t clk_src, uint32_t duty_res, +static void timer_set_clk_src_and_freq_test(ledc_mode_t speed_mode, ledc_clk_cfg_t clk_src, ledc_timer_bit_t duty_res, uint32_t freq_hz) { - ledc_timer_config_t ledc_time_config = { - .speed_mode = speed_mode, - .duty_resolution = duty_res, - .timer_num = LEDC_TIMER_0, - .freq_hz = freq_hz, - .clk_cfg = clk_src, - }; + ledc_timer_config_t ledc_time_config = {}; + ledc_time_config.speed_mode = speed_mode; + ledc_time_config.duty_resolution = duty_res; + ledc_time_config.timer_num = LEDC_TIMER_0; + ledc_time_config.freq_hz = freq_hz; + ledc_time_config.clk_cfg = clk_src; TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); TEST_ESP_OK(ledc_update_duty(speed_mode, LEDC_CHANNEL_0)); // Start vTaskDelay(100 / portTICK_PERIOD_MS); @@ -518,44 +540,45 @@ static void timer_set_clk_src_and_freq_test(ledc_mode_t speed_mode, ledc_clk_cfg TEST_CASE("LEDC timer select specific clock source", "[ledc]") { const ledc_mode_t test_speed_mode = TEST_SPEED_MODE; - ledc_channel_config_t ledc_ch_config = { - .gpio_num = PULSE_IO, - .speed_mode = test_speed_mode, - .channel = LEDC_CHANNEL_0, - .intr_type = LEDC_INTR_DISABLE, - .timer_sel = LEDC_TIMER_0, - .duty = 800, - .hpoint = 0, - }; + ledc_channel_config_t ledc_ch_config = {}; + ledc_ch_config.gpio_num = PULSE_IO; + ledc_ch_config.speed_mode = test_speed_mode; + ledc_ch_config.channel = LEDC_CHANNEL_0; + ledc_ch_config.timer_sel = LEDC_TIMER_0; + ledc_ch_config.duty = 800; + ledc_ch_config.hpoint = 0; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); if (test_speed_mode == LEDC_LOW_SPEED_MODE) { #if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION // Otherwise, the frequency of output PWM signal may not be very accurate printf("Check LEDC_USE_RC_FAST_CLK for a 100Hz signal\n"); - timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_RC_FAST_CLK, 10, 100); + timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_RC_FAST_CLK, LEDC_TIMER_10_BIT, 100); #endif #if SOC_LEDC_SUPPORT_XTAL_CLOCK printf("Check LEDC_USE_XTAL_CLK for a 400Hz signal\n"); - timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_XTAL_CLK, 13, 400); + timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_XTAL_CLK, LEDC_TIMER_13_BIT, 400); #endif } #if SOC_LEDC_SUPPORT_REF_TICK printf("Check LEDC_USE_REF_TICK for a 250Hz signal\n"); - timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_REF_TICK, 10, 250); + timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_REF_TICK, LEDC_TIMER_10_BIT, 250); #endif #if SOC_LEDC_SUPPORT_APB_CLOCK printf("Check LEDC_USE_APB_CLK for a 500Hz signal\n"); - timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_APB_CLK, 13, 500); + timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_APB_CLK, LEDC_TIMER_13_BIT, 500); #endif #if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK printf("Check LEDC_USE_PLL_DIV_CLK for a 500Hz signal\n"); - timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_PLL_DIV_CLK, 13, 500); + timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_PLL_DIV_CLK, LEDC_TIMER_13_BIT, 500); #endif printf("Bind channel 0 to timer 0\n"); TEST_ESP_OK(ledc_bind_channel_timer(test_speed_mode, LEDC_CHANNEL_0, LEDC_TIMER_0)); vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT32(ledc_get_freq(test_speed_mode, LEDC_TIMER_0), 500); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } #endif //SOC_CLK_TREE_SUPPORTED @@ -564,24 +587,21 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]") const ledc_mode_t test_speed_mode = TEST_SPEED_MODE; int count; - ledc_timer_config_t ledc_time_config = { - .speed_mode = test_speed_mode, - .duty_resolution = LEDC_TIMER_13_BIT, - .timer_num = LEDC_TIMER_0, - .freq_hz = TEST_PWM_FREQ, - .clk_cfg = TEST_DEFAULT_CLK_CFG, - }; + ledc_timer_config_t ledc_time_config = {}; + ledc_time_config.speed_mode = test_speed_mode; + ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT; + ledc_time_config.timer_num = LEDC_TIMER_0; + ledc_time_config.freq_hz = TEST_PWM_FREQ; + ledc_time_config.clk_cfg = TEST_DEFAULT_CLK_CFG; TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); - ledc_channel_config_t ledc_ch_config = { - .gpio_num = PULSE_IO, - .speed_mode = test_speed_mode, - .channel = LEDC_CHANNEL_0, - .intr_type = LEDC_INTR_DISABLE, - .timer_sel = LEDC_TIMER_0, - .duty = 4000, - .hpoint = 0, - }; + ledc_channel_config_t ledc_ch_config = {}; + ledc_ch_config.gpio_num = PULSE_IO; + ledc_ch_config.speed_mode = test_speed_mode; + ledc_ch_config.channel = LEDC_CHANNEL_0; + ledc_ch_config.timer_sel = LEDC_TIMER_0; + ledc_ch_config.duty = 4000; + ledc_ch_config.hpoint = 0; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); vTaskDelay(10 / portTICK_PERIOD_MS); @@ -608,6 +628,9 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]") vTaskDelay(100 / portTICK_PERIOD_MS); count = wave_count(200); TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ * 200 / 1000, count); + + ledc_ch_config.deconfigure = true; + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); } static void ledc_cpu_reset_test_first_stage(void) diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.cpp similarity index 96% rename from components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c rename to components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.cpp index bcd98eb398..0ed3f50927 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.cpp @@ -92,7 +92,7 @@ TEST_CASE("ledc can output after light sleep (LEDC power domain pd)", "[ledc]") } #endif -static const ledc_clk_src_t test_ledc_clk_in_slp[] = { +static const ledc_clk_cfg_t test_ledc_clk_in_slp[] = { LEDC_USE_RC_FAST_CLK, #if SOC_LEDC_SUPPORT_XTAL_CLOCK LEDC_USE_XTAL_CLK, @@ -107,7 +107,7 @@ static void ledc_output_monitor(void) unity_wait_for_signal("Go to light sleep for 3 seconds"); vTaskDelay(500 / portTICK_PERIOD_MS); int pulse_count = wave_count(200); - uint32_t acceptable_delta = (test_ledc_clk_in_slp[i] == (ledc_clk_src_t)LEDC_USE_RC_FAST_CLK) ? 20 : 5; // RC_FAST as the clk src has a bigger error range is reasonable + uint32_t acceptable_delta = (test_ledc_clk_in_slp[i] == LEDC_USE_RC_FAST_CLK) ? 20 : 5; // RC_FAST as the clk src has a bigger error range is reasonable TEST_ASSERT_UINT32_WITHIN(acceptable_delta, TEST_PWM_LOW_FREQ * 200 / 1000, pulse_count); unity_wait_for_signal("Waked up!"); } diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.cpp similarity index 87% rename from components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c rename to components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.cpp index 8dece59874..b0478bc706 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.cpp @@ -13,8 +13,7 @@ ledc_channel_config_t initialize_channel_config(void) { - ledc_channel_config_t config; - memset(&config, 0, sizeof(ledc_channel_config_t)); + ledc_channel_config_t config = {}; config.gpio_num = PULSE_IO; config.speed_mode = TEST_SPEED_MODE; config.channel = LEDC_CHANNEL_0; @@ -26,8 +25,7 @@ ledc_channel_config_t initialize_channel_config(void) ledc_timer_config_t create_default_timer_config(void) { - ledc_timer_config_t ledc_time_config; - memset(&ledc_time_config, 0, sizeof(ledc_timer_config_t)); + ledc_timer_config_t ledc_time_config = {}; ledc_time_config.speed_mode = TEST_SPEED_MODE; ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT; ledc_time_config.timer_num = LEDC_TIMER_0; diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h index 41beedc138..dfe08929a6 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h @@ -6,8 +6,9 @@ #include "soc/soc_caps.h" #include "driver/ledc.h" +#include "soc/gpio_num.h" -#define PULSE_IO 5 +#define PULSE_IO GPIO_NUM_2 #define TEST_PWM_FREQ 2000 #define TEST_PWM_LOW_FREQ 200 diff --git a/components/hal/esp32/include/hal/ledc_ll.h b/components/hal/esp32/include/hal/ledc_ll.h index 198c56bd5d..d7d3da9c49 100644 --- a/components/hal/esp32/include/hal/ledc_ll.h +++ b/components/hal/esp32/include/hal/ledc_ll.h @@ -102,6 +102,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) //resolve for compatibility } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on ESP32 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-7), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on ESP32 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h index aa7577464e..cd03b348d6 100644 --- a/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32c2/include/hal/ledc_ll.h b/components/hal/esp32c2/include/hal/ledc_ll.h index 04d2517f77..2c415b4d92 100644 --- a/components/hal/esp32c2/include/hal/ledc_ll.h +++ b/components/hal/esp32c2/include/hal/ledc_ll.h @@ -32,8 +32,8 @@ extern "C" { LEDC_SLOW_CLK_XTAL, \ LEDC_SLOW_CLK_RC_FAST, \ } - -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1 +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on /** * @brief Enable peripheral register clock @@ -88,6 +88,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) //resolve for compatibility } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on C2 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on C2 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h index defab88dc2..12d6ba3bac 100644 --- a/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32c3/include/hal/ledc_ll.h b/components/hal/esp32c3/include/hal/ledc_ll.h index ae7dfcc94e..6ed34c630d 100644 --- a/components/hal/esp32c3/include/hal/ledc_ll.h +++ b/components/hal/esp32c3/include/hal/ledc_ll.h @@ -34,7 +34,8 @@ extern "C" { LEDC_SLOW_CLK_RC_FAST, \ } -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1 +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on /** * @brief Enable peripheral register clock @@ -89,6 +90,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) //resolve for compatibility } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on C3 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on C3 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h index 00ee9296a3..7c929195cf 100644 --- a/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32c5/include/hal/ledc_ll.h b/components/hal/esp32c5/include/hal/ledc_ll.h index 3e237c6801..977fb08e8f 100644 --- a/components/hal/esp32c5/include/hal/ledc_ll.h +++ b/components/hal/esp32c5/include/hal/ledc_ll.h @@ -73,6 +73,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) PCR.ledc_sclk_conf.ledc_sclk_en = en; } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on C5 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on C5 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h index 0b08505346..7c929195cf 100644 --- a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32c6/include/hal/ledc_ll.h b/components/hal/esp32c6/include/hal/ledc_ll.h index e6a0c73e3f..e3d691de20 100644 --- a/components/hal/esp32c6/include/hal/ledc_ll.h +++ b/components/hal/esp32c6/include/hal/ledc_ll.h @@ -32,7 +32,8 @@ extern "C" { #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) #define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1 +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on /** * @brief Enable peripheral register clock @@ -57,7 +58,7 @@ static inline void ledc_ll_enable_reset_reg(bool enable) */ static inline void ledc_ll_enable_mem_power(bool enable) { - // No register to control the power for LEDC memory block on C6 + // No LEDC memory block on C6 } /** @@ -74,6 +75,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) PCR.ledc_sclk_conf.ledc_sclk_en = en; } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on C6 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on C6 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h index 00ee9296a3..7c929195cf 100644 --- a/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32c61/include/hal/ledc_ll.h b/components/hal/esp32c61/include/hal/ledc_ll.h index 4cd0f760ae..333238be17 100644 --- a/components/hal/esp32c61/include/hal/ledc_ll.h +++ b/components/hal/esp32c61/include/hal/ledc_ll.h @@ -73,6 +73,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) PCR.ledc_sclk_conf.ledc_sclk_en = en; } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on C61 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on C61 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h index e7c424a5d9..db955ea2b9 100644 --- a/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32h2/include/hal/ledc_ll.h b/components/hal/esp32h2/include/hal/ledc_ll.h index 8351003001..d17c51b037 100644 --- a/components/hal/esp32h2/include/hal/ledc_ll.h +++ b/components/hal/esp32h2/include/hal/ledc_ll.h @@ -55,7 +55,7 @@ static inline void ledc_ll_enable_reset_reg(bool enable) */ static inline void ledc_ll_enable_mem_power(bool enable) { - // No register to control the power for LEDC memory block on H2 + // No LEDC memory block on H2 } /** @@ -72,6 +72,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) PCR.ledc_sclk_conf.ledc_sclk_en = en; } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on H2 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on H2 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32h21/include/hal/ledc_ll.h b/components/hal/esp32h21/include/hal/ledc_ll.h new file mode 100644 index 0000000000..2e4f6e5840 --- /dev/null +++ b/components/hal/esp32h21/include/hal/ledc_ll.h @@ -0,0 +1,710 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for LEDC register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "hal/ledc_types.h" +#include "soc/ledc_struct.h" +#include "soc/ledc_reg.h" +#include "soc/pcr_struct.h" +#include "soc/clk_tree_defs.h" +#include "hal/assert.h" +#include "esp_rom_sys.h" //for sync issue workaround +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_LL_GET_HW() &LEDC + +#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_DUTY_NUM_V) +#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_DUTY_CYCLE_V) +#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_SCALE_V) +#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) +#define LEDC_LL_FRACTIONAL_BITS (8) +#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS + +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) +{ + PCR.ledc_conf.ledc_clk_en = enable; +} + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) +{ + PCR.ledc_conf.ledc_rst_en = enable; +} + +/** + * @brief Enable the power for LEDC memory block + */ +static inline void ledc_ll_enable_mem_power(bool enable) +{ + // No LEDC memory block on H21 +} + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) +{ + (void)hw; + PCR.ledc_sclk_conf.ledc_sclk_en = en; +} + +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on H21 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on H21 +} + +/** + * @brief Set LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel) +{ + (void)hw; + uint32_t clk_sel_val = 3; + if (slow_clk_sel == LEDC_SLOW_CLK_XTAL) { + clk_sel_val = 0; + } else if (slow_clk_sel == LEDC_SLOW_CLK_RC_FAST) { + clk_sel_val = 1; + } else if (slow_clk_sel == LEDC_SLOW_CLK_PLL_DIV) { + clk_sel_val = 2; + } + PCR.ledc_sclk_conf.ledc_sclk_sel = clk_sel_val; +} + +/** + * @brief Get LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel) +{ + (void)hw; + uint32_t clk_sel_val = PCR.ledc_sclk_conf.ledc_sclk_sel; + if (clk_sel_val == 0) { + *slow_clk_sel = LEDC_SLOW_CLK_XTAL; + } else if (clk_sel_val == 1) { + *slow_clk_sel = LEDC_SLOW_CLK_RC_FAST; + } else if (clk_sel_val == 2) { + *slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV; + } else { + abort(); + } +} + +/** + * @brief Update LEDC low speed timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1; + // Here, we don't wait for the bit gets cleared since it can take quite long depends on the pwm frequency +} + +/** + * @brief Reset LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1; + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0; +} + +/** + * @brief Pause LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1; +} + +/** + * @brief Resume LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0; +} + +/** + * @brief Set LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider; +} + +/** + * @brief Get LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider) +{ + *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div; +} + +/** + * @brief Get LEDC timer clock source + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_src Pointer to accept the timer clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) +{ + // The target has no timer-specific clock source option + *clk_src = LEDC_SCLK; +} + +/** + * @brief Set LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution; +} + +/** + * @brief Get LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits. + * + * @return None + */ +static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution) +{ + *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res; +} + +/** + * @brief Get LEDC max duty + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param max_duty Pointer to accept the max duty + * + * @return None + */ +static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty) +{ + *max_duty = (1 << (LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_res)); +} + +/** + * @brief Update channel configure when select low speed mode + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1; +} + +/** + * @brief Set LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param hpoint_val LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val) +{ + hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; +} + +/** + * @brief Get LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val) +{ + *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint; +} + +/** + * @brief Set LEDC the integer part of duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val) +{ + hw->channel_group[speed_mode].channel[channel_num].duty.duty = duty_val << 4; +} + +/** + * @brief Get LEDC duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_val Pointer to accept the LEDC duty value + * + * @return None + */ +static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) +{ + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_rd.duty_r >> 4); +} + +/** + * @brief Set LEDC duty change direction + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_direction LEDC duty change direction, increase or decrease + * + * @return None + */ +static inline void ledc_ll_set_duty_direction(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].wr.gamma_duty_inc = duty_direction; +} + +/** + * @brief Set the number of increased or decreased times + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_num The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_duty_num(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_num) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].wr.gamma_duty_num = duty_num; +} + +/** + * @brief Set the duty cycles of increase or decrease + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_cycle The duty cycles + * + * @return None + */ +static inline void ledc_ll_set_duty_cycle(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_cycle) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].wr.gamma_duty_cycle = duty_cycle; +} + +/** + * @brief Set the step scale of increase or decrease + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_scale The step scale + * + * @return None + */ +static inline void ledc_ll_set_duty_scale(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_scale) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].wr.gamma_scale = duty_scale; +} + +/** + * @brief Function to set fade parameters all-in-one + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + uint32_t val = (dir << LEDC_CH0_GAMMA_DUTY_INC_S) | (cycle << LEDC_CH0_GAMMA_DUTY_CYCLE_S) | (scale << LEDC_CH0_GAMMA_SCALE_S) | (step << LEDC_CH0_GAMMA_DUTY_NUM_S); + hw->channel_gamma_group[speed_mode].channel[channel_num].wr.val = val; +} + +/** + * @brief Set the range number of the specified duty configurations to be written from gamma_wr register to gamma ram + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_range Range index (0 - (SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX-1)), it specifies to which range in gamma ram to write + * + * @return None + */ +static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_range) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].wr_addr.gamma_wr_addr = duty_range; +} + +/** + * @brief Function to set fade parameters all-in-one for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX); + // To workaround sync issue + // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + + ledc_ll_set_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + + // To workaround sync issue + // This is to ensure the fade param in gamma_wr register can be written to the correct wr_addr + esp_rom_delay_us(5); +} + +/** + * @brief Set the total number of ranges in one fading + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range_num Total number of ranges (1 - SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX) of the fading configured + * + * @return None + */ +static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num) +{ + hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num = range_num; +} + +/** + * @brief Get the total number of ranges in one fading + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range_num Pointer to accept fade range number + * + * @return None + */ +static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num) +{ + *range_num = hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num; +} + +/** + * @brief Set the range number of the specified duty configurations to be read from gamma ram to gamma_rd register + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_range Range index (0 - (SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX-1)), it specifies to which range in gamma ram to read + * + * @return None + */ +static inline void ledc_ll_set_duty_range_rd_addr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_range) +{ + hw->channel_gamma_group[speed_mode].channel[channel_num].rd_addr.gamma_rd_addr = duty_range; +} + +/** + * @brief Get fade configurations in gamma_rd register + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param dir Pointer to accept fade direction value + * @param cycle Pointer to accept fade cycle value + * @param scale Pointer to accept fade scale value + * @param step Pointer to accept fade step value + * + * @return None + */ +static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) +{ + uint32_t val = hw->channel_gamma_group[speed_mode].channel[channel_num].rd_data.gamma_rd_data; + *dir = (val & LEDC_CH0_GAMMA_DUTY_INC_M) >> LEDC_CH0_GAMMA_DUTY_INC_S; + *cycle = (val & LEDC_CH0_GAMMA_DUTY_CYCLE_M) >> LEDC_CH0_GAMMA_DUTY_CYCLE_S; + *scale = (val & LEDC_CH0_GAMMA_SCALE_M) >> LEDC_CH0_GAMMA_SCALE_S; + *step = (val & LEDC_CH0_GAMMA_DUTY_NUM_M) >> LEDC_CH0_GAMMA_DUTY_NUM_S; +} + +/** + * @brief Get fade configurations for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir Pointer to accept fade direction value + * @param cycle Pointer to accept fade cycle value + * @param scale Pointer to accept fade scale value + * @param step Pointer to accept fade step value + * + * @return None + */ +static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) +{ + // On ESP32H21, gamma ram read/write has the APB and LEDC clock domain sync issue + // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization + ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); +} + +/** + * @brief Set the output enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param sig_out_en The output enable status + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en; +} + +/** + * @brief Set the duty start + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = 1; +} + +/** + * @brief Set output idle level + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param idle_level The output idle level + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1; +} + +/** + * @brief Set fade end interrupt enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param fade_end_intr_en The fade end interrupt enable status + * + * @return None + */ +static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en) +{ + uint32_t value = hw->int_ena.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num)))); +} + +/** + * @brief Get fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param intr_status The fade end interrupt status + * + * @return None + */ +static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status) +{ + uint32_t value = hw->int_st.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + *intr_status = (value >> int_en_base) & 0xff; +} + +/** + * @brief Clear fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_clr.val = BIT(int_en_base + channel_num); +} + +/** + * @brief Set timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel; +} + +/** + * @brief Get timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param timer_sel Pointer to accept the LEDC timer index + * + * @return None + */ +static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel) +{ + *timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/ledc_ll.h b/components/hal/esp32h4/include/hal/ledc_ll.h new file mode 100644 index 0000000000..e18f309acf --- /dev/null +++ b/components/hal/esp32h4/include/hal/ledc_ll.h @@ -0,0 +1,539 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for LEDC register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "hal/assert.h" +#include "hal/ledc_types.h" +#include "soc/ledc_struct.h" +#include "soc/ledc_reg.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_LL_GET_HW() &LEDC + +#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_FADE_PARAM_DUTY_NUM_V) +#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V) +#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_FADE_PARAM_SCALE_V) +#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) +#define LEDC_LL_FRACTIONAL_BITS (8) +#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS + +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) +{ + PCR.ledc_conf.ledc_clk_en = enable; +} + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) +{ + PCR.ledc_conf.ledc_rst_en = enable; +} + +/** + * @brief Enable the power for LEDC memory block + */ +static inline void ledc_ll_enable_mem_power(bool enable) +{ + // No LEDC memory block on H4 +} + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) +{ + (void)hw; + PCR.ledc_sclk_conf.ledc_sclk_en = en; +} + +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + if (en) { + hw->ch_power_up_conf.val |= BIT(speed_mode * SOC_LEDC_CHANNEL_NUM + channel_num); + } else { + hw->ch_power_up_conf.val &= ~BIT(speed_mode * SOC_LEDC_CHANNEL_NUM + channel_num); + } +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + if (en) { + hw->timer_power_up_conf.val |= BIT(speed_mode * SOC_LEDC_TIMER_NUM + timer_sel); + } else { + hw->timer_power_up_conf.val &= ~BIT(speed_mode * SOC_LEDC_TIMER_NUM + timer_sel); + } +} + +/** + * @brief Set LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel) +{ + (void) hw; + uint32_t clk_sel_val = 3; + switch (slow_clk_sel) + { + case LEDC_SLOW_CLK_XTAL: + clk_sel_val = 0; + break; + case LEDC_SLOW_CLK_RC_FAST: + clk_sel_val = 1; + break; + case LEDC_SLOW_CLK_PLL_DIV: + clk_sel_val = 2; + break; + default: + abort(); + } + + PCR.ledc_sclk_conf.ledc_sclk_sel = clk_sel_val; +} + +/** + * @brief Get LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel) +{ + (void) hw; + switch (PCR.ledc_sclk_conf.ledc_sclk_sel) + { + case 0: + *slow_clk_sel = LEDC_SLOW_CLK_XTAL; + break; + case 1: + *slow_clk_sel = LEDC_SLOW_CLK_RC_FAST; + break; + case 2: + *slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV; + break; + default: + abort(); + } +} + +/** + * @brief Update LEDC low speed timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1; + // Here, we don't wait for the bit gets cleared since it can take quite long depends on the pwm frequency +} + +/** + * @brief Reset LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1; + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0; +} + +/** + * @brief Pause LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1; +} + +/** + * @brief Resume LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0; +} + +/** + * @brief Set LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider; +} + +/** + * @brief Get LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider) +{ + *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div; +} + +/** + * @brief Get LEDC timer clock source + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_src Pointer to accept the timer clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) +{ + // The target has no timer-specific clock source option + *clk_src = LEDC_SCLK; +} + +/** + * @brief Set LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution; +} + +/** + * @brief Get LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits. + * + * @return None + */ +static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution) +{ + *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res; +} + +/** + * @brief Get LEDC max duty + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param max_duty Pointer to accept the max duty + * + * @return None + */ +static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty) +{ + *max_duty = (1 << (hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res)); +} + +/** + * @brief Update channel configure when select low speed mode + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1; +} + +/** + * @brief Set LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param hpoint_val LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val) +{ + hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; +} + +/** + * @brief Get LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val) +{ + *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint; +} + +/** + * @brief Set LEDC the integer part of duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val) +{ + hw->channel_group[speed_mode].channel[channel_num].duty_init.duty = duty_val << 4; +} + +/** + * @brief Get LEDC duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val Pointer to accept the LEDC duty value + * + * @return None + */ +static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) +{ + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4); +} + +/** + * @brief Function to set fade parameters all-in-one + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + ledc_chn_fade_param_reg_t fade_param = { + .duty_inc = dir, + .duty_cycle = cycle, + .scale = scale, + .duty_num = step, + }; + hw->channel_fade_param_group[speed_mode].channel[channel_num].fade_param.val = fade_param.val; +} + +/** + * @brief Set the output enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param sig_out_en The output enable status + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en; +} + +/** + * @brief Set the duty start + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = 1; +} + +/** + * @brief Set output idle level + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param idle_level The output idle level + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1; +} + +/** + * @brief Set fade end interrupt enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param fade_end_intr_en The fade end interrupt enable status + * + * @return None + */ +static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en) +{ + uint32_t value = hw->int_ena.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num)))); +} + +/** + * @brief Get fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param intr_status The fade end interrupt status + * + * @return None + */ +static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status) +{ + uint32_t value = hw->int_st.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + *intr_status = (value >> int_en_base) & 0xff; +} + +/** + * @brief Clear fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_clr.val = BIT(int_en_base + channel_num); +} + +/** + * @brief Set timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel; +} + +/** + * @brief Get timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param timer_sel Pointer to accept the LEDC timer index + * + * @return None + */ +static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel) +{ + *timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h index 8277b8ed0f..347d247375 100644 --- a/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,14 +9,17 @@ #include #include "riscv/csr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*fast gpio*/ #define CSR_GPIO_OEN_USER 0x803 #define CSR_GPIO_IN_USER 0x804 #define CSR_GPIO_OUT_USER 0x805 -#ifdef __cplusplus -extern "C" { -#endif +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 __attribute__((always_inline)) static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 76ce621674..1445e85ec3 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -92,6 +92,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) ledc_ll_enable_clock(__VA_ARGS__); \ } while(0) +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on P4 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on P4 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h index 4ea9a31595..2cb4013077 100644 --- a/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,12 @@ extern "C" { #endif +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + // Dedicated GPIO output attribution is enabled automatically on the target +} + __attribute__((always_inline)) static inline uint32_t dedic_gpio_cpu_ll_read_in(void) { diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h index cc09619fad..6c6d9967b6 100644 --- a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h +++ b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h @@ -5,16 +5,18 @@ */ #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include #include "hal/misc.h" #include "soc/dedic_gpio_struct.h" #include "soc/system_reg.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS 1 /*!< Allow access dedicated GPIO channel by register */ + static inline void _dedic_gpio_ll_enable_bus_clock(bool enable) { uint32_t reg_val = READ_PERI_REG(DPORT_CPU_PERI_CLK_EN_REG); diff --git a/components/hal/esp32s2/include/hal/ledc_ll.h b/components/hal/esp32s2/include/hal/ledc_ll.h index 266d18b72a..fc44fefe7c 100644 --- a/components/hal/esp32s2/include/hal/ledc_ll.h +++ b/components/hal/esp32s2/include/hal/ledc_ll.h @@ -39,7 +39,8 @@ extern "C" { #define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) ((CLK) == LEDC_USE_REF_TICK) -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1 +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on /** * @brief Enable peripheral register clock @@ -102,6 +103,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) //resolve for compatibility } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on S2 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-7), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on S2 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h index faeb9cdfff..2a48826ac9 100644 --- a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h @@ -12,6 +12,12 @@ extern "C" { #endif +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + // Dedicated GPIO output attribution is enabled automatically on the target +} + __attribute__((always_inline)) static inline uint32_t dedic_gpio_cpu_ll_read_in(void) { diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_ll.h index 3e98e81902..fea01aa021 100644 --- a/components/hal/esp32s3/include/hal/dedic_gpio_ll.h +++ b/components/hal/esp32s3/include/hal/dedic_gpio_ll.h @@ -5,14 +5,14 @@ */ #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include #include "soc/system_struct.h" +#ifdef __cplusplus +extern "C" { +#endif + static inline void _dedic_gpio_ll_enable_bus_clock(bool enable) { SYSTEM.cpu_peri_clk_en.clk_en_dedicated_gpio = enable; diff --git a/components/hal/esp32s3/include/hal/ledc_ll.h b/components/hal/esp32s3/include/hal/ledc_ll.h index e012868178..1a689d6dee 100644 --- a/components/hal/esp32s3/include/hal/ledc_ll.h +++ b/components/hal/esp32s3/include/hal/ledc_ll.h @@ -34,7 +34,8 @@ extern "C" { LEDC_SLOW_CLK_RC_FAST, \ } -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +#define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT 1 +#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST // The temporal global clock source to set to at least make the LEDC core clock on /** * @brief Enable peripheral register clock @@ -89,6 +90,32 @@ static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) //resolve for compatibility } +/** + * @brief Enable the power for LEDC channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en) +{ + // No per channel power control on S3 +} + +/** + * @brief Enable the power for LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-7), select from ledc_timer_t + * @param en True to enable, false to disable + */ +static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en) +{ + // No per timer power control on S3 +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/include/hal/ledc_types.h b/components/hal/include/hal/ledc_types.h index d0e6109f59..9f6f006c28 100644 --- a/components/hal/include/hal/ledc_types.h +++ b/components/hal/include/hal/ledc_types.h @@ -50,8 +50,6 @@ typedef enum { #if SOC_LEDC_SUPPORT_XTAL_CLOCK LEDC_SLOW_CLK_XTAL = LEDC_USE_XTAL_CLK, /*!< LEDC low speed timer clock source XTAL clock*/ #endif - - LEDC_SLOW_CLK_RTC8M __attribute__((deprecated)) = LEDC_SLOW_CLK_RC_FAST, /*!< Alias of 'LEDC_SLOW_CLK_RC_FAST'*/ } ledc_slow_clk_sel_t; /** diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index d0d74a5292..65d768e109 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -335,18 +335,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_I2C_NUM int default 1 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index facf692980..a6e96e72bb 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -154,11 +154,6 @@ // "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-C2 has 1 I2C #define SOC_I2C_NUM (1U) diff --git a/components/soc/esp32c2/include/soc/soc_caps_full.h b/components/soc/esp32c2/include/soc/soc_caps_full.h index 3d94d0e63b..a3277e8a93 100644 --- a/components/soc/esp32c2/include/soc/soc_caps_full.h +++ b/components/soc/esp32c2/include/soc/soc_caps_full.h @@ -19,3 +19,7 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group + +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 07d3891d96..40730abf27 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -431,18 +431,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_I2C_NUM int default 1 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index f56e816ff8..95e1421682 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -193,11 +193,6 @@ // "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-C3 has 1 I2C #define SOC_I2C_NUM (1U) diff --git a/components/soc/esp32c3/include/soc/soc_caps_full.h b/components/soc/esp32c3/include/soc/soc_caps_full.h index 63d2d2eec5..a86519dfb5 100644 --- a/components/soc/esp32c3/include/soc/soc_caps_full.h +++ b/components/soc/esp32c3/include/soc/soc_caps_full.h @@ -23,3 +23,7 @@ /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance + +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 8dfb2e7e3a..f5d8a5c822 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -623,18 +623,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 4c3b57edf9..7f301dbbd5 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -257,12 +257,10 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*------------------------- Analog Comparator CAPS ---------------------------*/ diff --git a/components/soc/esp32c5/include/soc/soc_caps_full.h b/components/soc/esp32c5/include/soc/soc_caps_full.h index 95748b6bc6..b28c26cdbf 100644 --- a/components/soc/esp32c5/include/soc/soc_caps_full.h +++ b/components/soc/esp32c5/include/soc/soc_caps_full.h @@ -20,6 +20,10 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ + /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 324b173594..8e4e985521 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -559,18 +559,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index b9f94b5022..2f68ede25a 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -237,12 +237,10 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- I2C CAPS ----------------------------------------*/ diff --git a/components/soc/esp32c6/include/soc/soc_caps_full.h b/components/soc/esp32c6/include/soc/soc_caps_full.h index 95748b6bc6..b28c26cdbf 100644 --- a/components/soc/esp32c6/include/soc/soc_caps_full.h +++ b/components/soc/esp32c6/include/soc/soc_caps_full.h @@ -20,6 +20,10 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ + /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 41067596a2..07b79e6fee 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -503,18 +503,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_ANA_CMPR_NUM int default 1 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 004f469001..35607db54d 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -161,6 +161,7 @@ #define SOC_AHB_GDMA_SUPPORT_PSRAM 1 #define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION 1 +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- GPIO CAPS ---------------------------------------*/ @@ -216,11 +217,6 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - /*------------------------- Analog Comparator CAPS ---------------------------*/ #define SOC_ANA_CMPR_NUM (1U) #define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE (1) // Support positive/negative/any cross interrupt diff --git a/components/soc/esp32c61/include/soc/soc_caps_full.h b/components/soc/esp32c61/include/soc/soc_caps_full.h index 0f0c3fe392..59637b63cc 100644 --- a/components/soc/esp32c61/include/soc/soc_caps_full.h +++ b/components/soc/esp32c61/include/soc/soc_caps_full.h @@ -20,6 +20,10 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ + /*--------------------------- ETM (Event Task Matrix) ----------------------------*/ #define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances #define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index af9e2b89d6..3809d59521 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -563,18 +563,6 @@ config SOC_RTCIO_HOLD_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 5505ecc227..d7b6721057 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -257,12 +257,10 @@ #define SOC_RTCIO_PIN_COUNT (8U) #define SOC_RTCIO_HOLD_SUPPORTED (1) -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*------------------------- Analog Comparator CAPS ---------------------------*/ diff --git a/components/soc/esp32h2/include/soc/soc_caps_full.h b/components/soc/esp32h2/include/soc/soc_caps_full.h index 95748b6bc6..b28c26cdbf 100644 --- a/components/soc/esp32h2/include/soc/soc_caps_full.h +++ b/components/soc/esp32h2/include/soc/soc_caps_full.h @@ -20,6 +20,10 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ + /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 0258d480c0..37b4f65ac7 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -47,6 +47,10 @@ config SOC_GPSPI_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -395,18 +399,6 @@ config SOC_RTCIO_HOLD_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_ANA_CMPR_NUM int default 1 @@ -471,10 +463,46 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH bool default y +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_TIMER_NUM + int + default 4 + config SOC_LEDC_CHANNEL_NUM int default 6 +config SOC_LEDC_TIMER_BIT_WIDTH + int + default 20 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED + bool + default y + +config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + int + default 16 + +config SOC_LEDC_FADE_PARAMS_BIT_WIDTH + int + default 10 + +config SOC_LEDC_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE bool default y diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index 69a7ff64f2..a98d21ce06 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -268,6 +268,23 @@ typedef enum { I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ } soc_periph_i2c_clk_src_t; +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +} soc_periph_ledc_clk_src_legacy_t; + /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index f7db4d907e..38629c0db3 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -45,7 +45,7 @@ // #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608 // #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573 #define SOC_GPSPI_SUPPORTED 1 -// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568 +#define SOC_LEDC_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660 @@ -233,7 +233,10 @@ // #define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) // #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- RTCIO CAPS --------------------------------------*/ @@ -242,11 +245,6 @@ #define SOC_RTCIO_PIN_COUNT (7U) #define SOC_RTCIO_HOLD_SUPPORTED (1) -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - /*------------------------- Analog Comparator CAPS ---------------------------*/ #define SOC_ANA_CMPR_NUM (1U) #define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1) @@ -287,14 +285,16 @@ // #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ /*-------------------------- LEDC CAPS ---------------------------------------*/ -// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) -// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) -#define SOC_LEDC_CHANNEL_NUM (6) // Check, todo IDF-11568 -// #define SOC_LEDC_TIMER_BIT_WIDTH (20) -// #define SOC_LEDC_SUPPORT_FADE_STOP (1) -// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) -// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) -// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) +#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +#define SOC_LEDC_TIMER_NUM (4) +#define SOC_LEDC_CHANNEL_NUM (6) +#define SOC_LEDC_TIMER_BIT_WIDTH (20) +#define SOC_LEDC_SUPPORT_FADE_STOP (1) +#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) +#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) +#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) +#define SOC_LEDC_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- MPU CAPS ----------------------------------------*/ // #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 diff --git a/components/soc/esp32h21/ledc_periph.c b/components/soc/esp32h21/ledc_periph.c new file mode 100644 index 0000000000..2eedbe2f59 --- /dev/null +++ b/components/soc/esp32h21/ledc_periph.c @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; + +/** + * LEDC registers to be saved for sleep retention + * + * channel: + * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG, + * + * timer: + * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG, + * + * common: + * LEDC_INT_ENA_REG, + * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG, + * LEDC_CONF_REG, + * + * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore. + * We won't start a fade automatically after wake-up. + * Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep. + * + * Note 2: For timer/channel registers to get synced, update bits need to be set + * + * Note 3: Retention backup/restore does not rely on LEDC function clock enabled + */ +#define LEDC_COMMON_RETENTION_REGS_CNT 5 +#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8) +static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0}; +static const regdma_entries_config_t ledc_common_regdma_entries[] = { + // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). + // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, +}; + +#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ +} + +#define LEDC_CHANNEL_RETENTION_REGS_CNT 2 +static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; +#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ + LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ + ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ + ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ +} + +static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0); +static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1); +static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2); +static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3); + +static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0); +static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1); +static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2); +static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3); +static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4); +static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5); + +const ledc_reg_retention_info_t ledc_reg_retention_info = { + .common = { + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, +}; diff --git a/components/soc/esp32h21/register/soc/ledc_struct.h b/components/soc/esp32h21/register/soc/ledc_struct.h index 60d7229989..fc088ed2fa 100644 --- a/components/soc/esp32h21/register/soc/ledc_struct.h +++ b/components/soc/esp32h21/register/soc/ledc_struct.h @@ -16,43 +16,43 @@ extern "C" { */ typedef union { struct { - /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + /** timer_sel : R/W; bitpos: [1:0]; default: 0; * This field is used to select one of timers for channel n. * * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 */ - uint32_t timer_sel_chn:2; - /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; * Set this bit to enable signal output on channel n. */ - uint32_t sig_out_en_chn:1; - /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; * This bit is used to control the output value when channel n is inactive (when * LEDC_SIG_OUT_EN_CHn is 0). */ - uint32_t idle_lv_chn:1; - /** para_up_chn : WT; bitpos: [4]; default: 0; + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; * This bit is used to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel * n, and will be automatically cleared by hardware. */ - uint32_t para_up_chn:1; - /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; * This register is used to configure the maximum times of overflow minus 1. * * The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for * (LEDC_OVF_NUM_CHn + 1) times. */ - uint32_t ovf_num_chn:10; - /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; * This bit is used to enable the ovf_cnt of channel n. */ - uint32_t ovf_cnt_en_chn:1; - /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; * Set this bit to reset the ovf_cnt of channel n. */ - uint32_t ovf_cnt_reset_chn:1; + uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; }; uint32_t val; @@ -64,11 +64,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:31; - /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; * Other configured fields in LEDC_CHn_CONF1_REG will start to take effect when this * bit is set to 1. */ - uint32_t duty_start_chn:1; + uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; @@ -396,33 +396,33 @@ typedef union { uint32_t val; } ledc_evt_task_en2_reg_t; -/** Type of timern_cmp register - * Ledc timern compare value register. +/** Type of timerx_cmp register + * Ledc timer x compare value register. */ typedef union { struct { - /** timern_cmp : R/W; bitpos: [19:0]; default: 0; - * This register stores ledc timern compare value. + /** cmp : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer x compare value. */ - uint32_t timern_cmp:20; + uint32_t cmp:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_cmp_reg_t; +} ledc_timerx_cmp_reg_t; -/** Type of timern_cnt_cap register - * Ledc timern count value capture register. +/** Type of timerx_cnt_cap register + * Ledc timer x count value capture register. */ typedef union { struct { - /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; - * This register stores ledc timern count value. + /** cnt_cap : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer x count value. */ - uint32_t timern_cnt_cap:20; + uint32_t cnt_cap:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_cnt_cap_reg_t; +} ledc_timerx_cnt_cap_reg_t; /** Type of conf register * Global ledc configuration register @@ -496,11 +496,11 @@ typedef union { */ typedef union { struct { - /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + /** hpoint : R/W; bitpos: [19:0]; default: 0; * The output value changes to high when the selected timers has reached the value * specified by this register. */ - uint32_t hpoint_chn:20; + uint32_t hpoint:20; uint32_t reserved_20:12; }; uint32_t val; @@ -513,12 +513,12 @@ typedef union { */ typedef union { struct { - /** duty_chn : R/W; bitpos: [24:0]; default: 0; + /** duty : R/W; bitpos: [24:0]; default: 0; * This register is used to change the output duty by controlling the Lpoint. * * The output value turns to low when the selected timers has reached the Lpoint. */ - uint32_t duty_chn:25; + uint32_t duty:25; uint32_t reserved_25:7; }; uint32_t val; @@ -529,10 +529,10 @@ typedef union { */ typedef union { struct { - /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * This register stores the current duty of output signal on channel n. */ - uint32_t duty_chn_r:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; @@ -540,52 +540,52 @@ typedef union { /** Group: Timer Register */ -/** Type of timern_conf register - * Timer n configuration +/** Type of timerx_conf register + * Timer x configuration */ typedef union { struct { - /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; - * This register is used to control the range of the counter in timer n. + /** duty_res : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer x. */ - uint32_t timern_duty_res:5; - /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; - * This register is used to configure the divisor for the divider in timer n. + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer x. * * The least significant eight bits represent the fractional part. */ - uint32_t clk_div_timern:18; - /** timern_pause : R/W; bitpos: [23]; default: 0; - * This bit is used to suspend the counter in timer n. + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer x. */ - uint32_t timern_pause:1; - /** timern_rst : R/W; bitpos: [24]; default: 1; - * This bit is used to reset timer n. The counter will show 0 after reset. + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer x. The counter will show 0 after reset. */ - uint32_t timern_rst:1; + uint32_t rst:1; uint32_t reserved_25:1; - /** timern_para_up : WT; bitpos: [26]; default: 0; + /** para_up : WT; bitpos: [26]; default: 0; * Set this bit to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. */ - uint32_t timern_para_up:1; + uint32_t para_up:1; uint32_t reserved_27:5; }; uint32_t val; -} ledc_timern_conf_reg_t; +} ledc_timerx_conf_reg_t; -/** Type of timern_value register - * Timer n current counter value +/** Type of timerx_value register + * Timer x current counter value */ typedef union { struct { - /** timern_cnt : RO; bitpos: [19:0]; default: 0; - * This register stores the current counter value of timer n. + /** timer_cnt : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer x. */ - uint32_t timern_cnt:20; + uint32_t timer_cnt:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_value_reg_t; +} ledc_timerx_value_reg_t; /** Group: Interrupt Register */ @@ -924,28 +924,28 @@ typedef union { */ typedef union { struct { - /** chn_gamma_duty_inc : R/W; bitpos: [0]; default: 0; + /** gamma_duty_inc : R/W; bitpos: [0]; default: 0; * Ledc chn gamma duty inc of current ram write address.This register is used to * increase or decrease the duty of output signal on channel n. * * 1: Increase 0: Decrease. */ - uint32_t chn_gamma_duty_inc:1; - /** chn_gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0; + uint32_t gamma_duty_inc:1; + /** gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0; * Ledc chn gamma duty cycle of current ram write address.The duty will change every * LEDC_CHn_GAMMA_DUTY_CYCLE on channel n. */ - uint32_t chn_gamma_duty_cycle:10; - /** chn_gamma_scale : R/W; bitpos: [20:11]; default: 0; + uint32_t gamma_duty_cycle:10; + /** gamma_scale : R/W; bitpos: [20:11]; default: 0; * Ledc chn gamma scale of current ram write address.This register is used to * configure the changing step scale of duty on channel n. */ - uint32_t chn_gamma_scale:10; - /** chn_gamma_duty_num : R/W; bitpos: [30:21]; default: 0; + uint32_t gamma_scale:10; + /** gamma_duty_num : R/W; bitpos: [30:21]; default: 0; * Ledc chn gamma duty num of current ram write address.This register is used to * control the number of times the duty cycle will be changed. */ - uint32_t chn_gamma_duty_num:10; + uint32_t gamma_duty_num:10; uint32_t reserved_31:1; }; uint32_t val; @@ -956,10 +956,10 @@ typedef union { */ typedef union { struct { - /** chn_gamma_wr_addr : R/W; bitpos: [3:0]; default: 0; + /** gamma_wr_addr : R/W; bitpos: [3:0]; default: 0; * Ledc chn gamma ram write address. */ - uint32_t chn_gamma_wr_addr:4; + uint32_t gamma_wr_addr:4; uint32_t reserved_4:28; }; uint32_t val; @@ -970,10 +970,10 @@ typedef union { */ typedef union { struct { - /** chn_gamma_rd_addr : R/W; bitpos: [3:0]; default: 0; + /** gamma_rd_addr : R/W; bitpos: [3:0]; default: 0; * Ledc chn gamma ram read address. */ - uint32_t chn_gamma_rd_addr:4; + uint32_t gamma_rd_addr:4; uint32_t reserved_4:28; }; uint32_t val; @@ -984,10 +984,10 @@ typedef union { */ typedef union { struct { - /** chn_gamma_rd_data : RO; bitpos: [30:0]; default: 0; + /** gamma_rd_data : RO; bitpos: [30:0]; default: 0; * Ledc chn gamma ram read data. */ - uint32_t chn_gamma_rd_data:31; + uint32_t gamma_rd_data:31; uint32_t reserved_31:1; }; uint32_t val; @@ -1000,18 +1000,18 @@ typedef union { */ typedef union { struct { - /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; * Ledc chn gamma entry num. */ - uint32_t chn_gamma_entry_num:5; - /** chn_gamma_pause : WT; bitpos: [5]; default: 0; + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; * Ledc chn gamma pause, write 1 to pause. */ - uint32_t chn_gamma_pause:1; - /** chn_gamma_resume : WT; bitpos: [6]; default: 0; + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; * Ledc chn gamma resume, write 1 to resume. */ - uint32_t chn_gamma_resume:1; + uint32_t gamma_resume:1; uint32_t reserved_7:25; }; uint32_t val; @@ -1035,83 +1035,69 @@ typedef union { typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; - volatile ledc_chn_conf0_reg_t ch1_conf0; - volatile ledc_chn_hpoint_reg_t ch1_hpoint; - volatile ledc_chn_duty_reg_t ch1_duty; - volatile ledc_chn_conf1_reg_t ch1_conf1; - volatile ledc_chn_duty_r_reg_t ch1_duty_r; - volatile ledc_chn_conf0_reg_t ch2_conf0; - volatile ledc_chn_hpoint_reg_t ch2_hpoint; - volatile ledc_chn_duty_reg_t ch2_duty; - volatile ledc_chn_conf1_reg_t ch2_conf1; - volatile ledc_chn_duty_r_reg_t ch2_duty_r; - volatile ledc_chn_conf0_reg_t ch3_conf0; - volatile ledc_chn_hpoint_reg_t ch3_hpoint; - volatile ledc_chn_duty_reg_t ch3_duty; - volatile ledc_chn_conf1_reg_t ch3_conf1; - volatile ledc_chn_duty_r_reg_t ch3_duty_r; - volatile ledc_chn_conf0_reg_t ch4_conf0; - volatile ledc_chn_hpoint_reg_t ch4_hpoint; - volatile ledc_chn_duty_reg_t ch4_duty; - volatile ledc_chn_conf1_reg_t ch4_conf1; - volatile ledc_chn_duty_r_reg_t ch4_duty_r; - volatile ledc_chn_conf0_reg_t ch5_conf0; - volatile ledc_chn_hpoint_reg_t ch5_hpoint; - volatile ledc_chn_duty_reg_t ch5_duty; - volatile ledc_chn_conf1_reg_t ch5_conf1; - volatile ledc_chn_duty_r_reg_t ch5_duty_r; + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_rd; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[6]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timerx_conf_reg_t conf; + volatile ledc_timerx_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_wr_reg_t wr; + volatile ledc_chn_gamma_wr_addr_reg_t wr_addr; + volatile ledc_chn_gamma_rd_addr_reg_t rd_addr; + volatile ledc_chn_gamma_rd_data_reg_t rd_data; +} ledc_chn_gamma_reg_t; + +typedef struct { + volatile ledc_chn_gamma_reg_t channel[6]; +} ledc_ch_gamma_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_conf_reg_t gamma_conf[6]; +} ledc_ch_gamma_conf_group_reg_t; + +typedef struct { + volatile ledc_timerx_cmp_reg_t cmp[4]; +} ledc_timer_cmp_group_reg_t; + +typedef struct { + volatile ledc_timerx_cnt_cap_reg_t cnt_cap[4]; +} ledc_timer_cnt_cap_group_reg_t; + + +typedef struct ledc_dev_t { + volatile ledc_ch_group_reg_t channel_group[1]; uint32_t reserved_078[10]; - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; - volatile ledc_timern_conf_reg_t timer1_conf; - volatile ledc_timern_value_reg_t timer1_value; - volatile ledc_timern_conf_reg_t timer2_conf; - volatile ledc_timern_value_reg_t timer2_value; - volatile ledc_timern_conf_reg_t timer3_conf; - volatile ledc_timern_value_reg_t timer3_value; + volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; - volatile ledc_chn_gamma_wr_reg_t ch0_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch0_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch0_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch0_gamma_rd_data; - volatile ledc_chn_gamma_wr_reg_t ch1_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch1_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch1_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch1_gamma_rd_data; - volatile ledc_chn_gamma_wr_reg_t ch2_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch2_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch2_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch2_gamma_rd_data; - volatile ledc_chn_gamma_wr_reg_t ch3_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch3_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch3_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch3_gamma_rd_data; - volatile ledc_chn_gamma_wr_reg_t ch4_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch4_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch4_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch4_gamma_rd_data; - volatile ledc_chn_gamma_wr_reg_t ch5_gamma_wr; - volatile ledc_chn_gamma_wr_addr_reg_t ch5_gamma_wr_addr; - volatile ledc_chn_gamma_rd_addr_reg_t ch5_gamma_rd_addr; - volatile ledc_chn_gamma_rd_data_reg_t ch5_gamma_rd_data; + volatile ledc_ch_gamma_group_reg_t channel_gamma_group[1]; uint32_t reserved_160[8]; - volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6]; + volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1]; uint32_t reserved_198[2]; volatile ledc_evt_task_en0_reg_t evt_task_en0; volatile ledc_evt_task_en1_reg_t evt_task_en1; volatile ledc_evt_task_en2_reg_t evt_task_en2; uint32_t reserved_1ac; - volatile ledc_timern_cmp_reg_t timern_cmp[4]; - volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1]; + volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1]; uint32_t reserved_1d0[8]; volatile ledc_conf_reg_t conf; uint32_t reserved_1f4[2]; diff --git a/components/soc/esp32h21/register/soc/pcr_reg.h b/components/soc/esp32h21/register/soc/pcr_reg.h index 38c2a4f8c7..6770cd20b0 100644 --- a/components/soc/esp32h21/register/soc/pcr_reg.h +++ b/components/soc/esp32h21/register/soc/pcr_reg.h @@ -493,8 +493,8 @@ extern "C" { */ #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3: XTAL. + * set this field to select clock-source. 0(default): XTAL, 1: + * FOSC, 2: 96MHz. */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) diff --git a/components/soc/esp32h21/register/soc/pcr_struct.h b/components/soc/esp32h21/register/soc/pcr_struct.h index b9af452e5f..851b06fabd 100644 --- a/components/soc/esp32h21/register/soc/pcr_struct.h +++ b/components/soc/esp32h21/register/soc/pcr_struct.h @@ -358,8 +358,8 @@ typedef union { struct { uint32_t reserved_0:20; /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3: XTAL. + * set this field to select clock-source. 0(default): XTAL, 1: + * FOSC, 2: 96MHz. */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index e3466ac7bb..a52b7385dd 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -63,6 +63,10 @@ config SOC_GPSPI_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -503,9 +507,37 @@ config SOC_I2S_SUPPORT_SLEEP_RETENTION bool default y +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_TIMER_NUM + int + default 4 + config SOC_LEDC_CHANNEL_NUM int - default 6 + default 8 + +config SOC_LEDC_TIMER_BIT_WIDTH + int + default 20 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_LEDC_FADE_PARAMS_BIT_WIDTH + int + default 10 + +config SOC_LEDC_SUPPORT_SLEEP_RETENTION + bool + default y config SOC_MMU_PAGE_SIZE_CONFIGURABLE bool diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index d6c9e0a1a6..e72ed637b7 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -338,6 +338,23 @@ typedef enum { I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ } soc_periph_i2c_clk_src_t; +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +} soc_periph_ledc_clk_src_legacy_t; + ///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index c69b1311f2..9e6fba8899 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -58,7 +58,7 @@ #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 #define SOC_GPSPI_SUPPORTED 1 -// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12343 +#define SOC_LEDC_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12375 IDF-12377 // #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253 @@ -240,12 +240,10 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- I2C CAPS ----------------------------------------*/ @@ -291,14 +289,14 @@ #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ /*-------------------------- LEDC CAPS ---------------------------------------*/ -// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) -// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) -#define SOC_LEDC_CHANNEL_NUM (6) // TODO: [ESP32H4] IDF-12343 -// #define SOC_LEDC_TIMER_BIT_WIDTH (20) -// #define SOC_LEDC_SUPPORT_FADE_STOP (1) -// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) -// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) -// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) +#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +#define SOC_LEDC_TIMER_NUM (4) +#define SOC_LEDC_CHANNEL_NUM (8) +#define SOC_LEDC_TIMER_BIT_WIDTH (20) +#define SOC_LEDC_SUPPORT_FADE_STOP (1) +#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) +#define SOC_LEDC_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- MMU CAPS ----------------------------------------*/ #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) diff --git a/components/soc/esp32h4/ledc_periph.c b/components/soc/esp32h4/ledc_periph.c new file mode 100644 index 0000000000..a5dd818aa9 --- /dev/null +++ b/components/soc/esp32h4/ledc_periph.c @@ -0,0 +1,181 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; + +/** + * LEDC registers to be saved for sleep retention + * + * channel: + * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG, + * LEDC_CHx_FADE_CONF_REG, LEDC_CHx_FADE_PARAM_REG + * + * timer: + * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG, + * + * common: + * LEDC_INT_ENA_REG, + * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG, + * LEDC_CONF_REG, + * LEDC_CH_POWER_UP_CONF_REG, LEDC_TIMER_POWER_UP_CONF_REG + * + * Note 1: Fade parameter registers are backuped and restored. But we won't start a fade automatically after wake-up. + * Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep. + * + * Note 2: For timer/channel registers to get synced, update bits need to be set + * + * Note 3: Retention backup/restore does not rely on LEDC function clock enabled + */ +#define LEDC_COMMON_RETENTION_REGS_CNT 7 +#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8) +static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x1c00, 0x0, 0x0}; +static const regdma_entries_config_t ledc_common_regdma_entries[] = { + // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up). + // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG. + [0] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), + LEDC_INT_ENA_REG, 0, + (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1), + .owner = LEDC_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), + LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE, + LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, + ledc_common_regs_map[0], ledc_common_regs_map[1], + ledc_common_regs_map[2], ledc_common_regs_map[3]), + .owner = LEDC_RETENTION_ENTRY + }, +}; + +#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \ + LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ +} + +#define LEDC_CHANNEL_RETENTION_REGS_CNT 2 +static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0}; +static const uint32_t ledc_channel_gamma_regs_map[4] = {0x1, 0x0, 0x0, 0x0}; +#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \ + LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \ + LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \ + ledc_channel_regs_map[0], ledc_channel_regs_map[1], \ + ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \ + LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \ + LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \ + LEDC_DUTY_START_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \ + LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \ + LEDC_PARA_UP_CH##chan##_M, 1, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \ + LEDC_CH##chan##_FADE_CONF_REG, LEDC_CH##chan##_FADE_CONF_REG, \ + 1, 0, 0), \ + .owner = LEDC_RETENTION_ENTRY }, \ + [5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \ + LEDC_CH##chan##_FADE_PARAM_REG, LEDC_CH##chan##_FADE_PARAM_REG, \ + 1, 0, 0, \ + ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \ + ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \ + .owner = LEDC_RETENTION_ENTRY }, \ +} + +static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0); +static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1); +static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2); +static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3); + +static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0); +static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1); +static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2); +static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3); +static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4); +static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5); +static const regdma_entries_config_t ledc_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(6); +static const regdma_entries_config_t ledc_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(7); + +const ledc_reg_retention_info_t ledc_reg_retention_info = { + .common = { + .regdma_entry_array = ledc_common_regdma_entries, + .array_size = ARRAY_SIZE(ledc_common_regdma_entries), + }, + .timer[0] = { + .regdma_entry_array = ledc_timer0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer0_regdma_entries), + }, + .timer[1] = { + .regdma_entry_array = ledc_timer1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer1_regdma_entries), + }, + .timer[2] = { + .regdma_entry_array = ledc_timer2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer2_regdma_entries), + }, + .timer[3] = { + .regdma_entry_array = ledc_timer3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_timer3_regdma_entries), + }, + .channel[0] = { + .regdma_entry_array = ledc_channel0_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel0_regdma_entries), + }, + .channel[1] = { + .regdma_entry_array = ledc_channel1_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel1_regdma_entries), + }, + .channel[2] = { + .regdma_entry_array = ledc_channel2_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel2_regdma_entries), + }, + .channel[3] = { + .regdma_entry_array = ledc_channel3_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel3_regdma_entries), + }, + .channel[4] = { + .regdma_entry_array = ledc_channel4_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel4_regdma_entries), + }, + .channel[5] = { + .regdma_entry_array = ledc_channel5_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel5_regdma_entries), + }, + .channel[6] = { + .regdma_entry_array = ledc_channel6_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel6_regdma_entries), + }, + .channel[7] = { + .regdma_entry_array = ledc_channel7_regdma_entries, + .array_size = ARRAY_SIZE(ledc_channel7_regdma_entries), + }, + .module_id = SLEEP_RETENTION_MODULE_LEDC, +}; diff --git a/components/soc/esp32h4/register/soc/ledc_reg.h b/components/soc/esp32h4/register/soc/ledc_reg.h index 05993e8751..1f420beb3a 100644 --- a/components/soc/esp32h4/register/soc/ledc_reg.h +++ b/components/soc/esp32h4/register/soc/ledc_reg.h @@ -3194,6 +3194,192 @@ extern "C" { #define LEDC_LEDC_DATE_V 0x0FFFFFFFU #define LEDC_LEDC_DATE_S 0 +/** LEDC fade parameter config registers + * 1 words (32bit) per channel * 8 channels + */ +#define LEDC_CH0_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x400) +/* LEDC_CH0_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH0_FADE_PARAM_DUTY_NUM_M ((LEDC_CH0_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH0_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH0_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH0_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH0_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH0_FADE_PARAM_SCALE_M ((LEDC_CH0_FADE_PARAM_SCALE_V)<<(LEDC_CH0_FADE_PARAM_SCALE_S)) +#define LEDC_CH0_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH0_FADE_PARAM_SCALE_S 11 +/* LEDC_CH0_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH0_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH0_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH0_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH0_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH1_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x440) +/* LEDC_CH1_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH1_FADE_PARAM_DUTY_NUM_M ((LEDC_CH1_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH1_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH1_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH1_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH1_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH1_FADE_PARAM_SCALE_M ((LEDC_CH1_FADE_PARAM_SCALE_V)<<(LEDC_CH1_FADE_PARAM_SCALE_S)) +#define LEDC_CH1_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH1_FADE_PARAM_SCALE_S 11 +/* LEDC_CH1_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH1_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH1_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH1_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH1_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH1_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH2_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x480) +/* LEDC_CH2_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH2_FADE_PARAM_DUTY_NUM_M ((LEDC_CH2_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH2_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH2_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH2_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH2_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH2_FADE_PARAM_SCALE_M ((LEDC_CH2_FADE_PARAM_SCALE_V)<<(LEDC_CH2_FADE_PARAM_SCALE_S)) +#define LEDC_CH2_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH2_FADE_PARAM_SCALE_S 11 +/* LEDC_CH2_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH2_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH2_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH2_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH2_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH2_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH3_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x4c0) +/* LEDC_CH3_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH3_FADE_PARAM_DUTY_NUM_M ((LEDC_CH3_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH3_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH3_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH3_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH3_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH3_FADE_PARAM_SCALE_M ((LEDC_CH3_FADE_PARAM_SCALE_V)<<(LEDC_CH3_FADE_PARAM_SCALE_S)) +#define LEDC_CH3_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH3_FADE_PARAM_SCALE_S 11 +/* LEDC_CH3_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH3_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH3_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH3_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH3_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH3_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH4_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x500) +/* LEDC_CH4_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH4_FADE_PARAM_DUTY_NUM_M ((LEDC_CH4_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH4_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH4_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH4_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH4_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH4_FADE_PARAM_SCALE_M ((LEDC_CH4_FADE_PARAM_SCALE_V)<<(LEDC_CH4_FADE_PARAM_SCALE_S)) +#define LEDC_CH4_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH4_FADE_PARAM_SCALE_S 11 +/* LEDC_CH4_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH4_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH4_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH4_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH4_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH4_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH5_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x540) +/* LEDC_CH5_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH5_FADE_PARAM_DUTY_NUM_M ((LEDC_CH5_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH5_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH5_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH5_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH5_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH5_FADE_PARAM_SCALE_M ((LEDC_CH5_FADE_PARAM_SCALE_V)<<(LEDC_CH5_FADE_PARAM_SCALE_S)) +#define LEDC_CH5_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH5_FADE_PARAM_SCALE_S 11 +/* LEDC_CH5_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH5_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH5_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH5_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH5_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH5_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH6_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x580) +/* LEDC_CH6_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH6_FADE_PARAM_DUTY_NUM_M ((LEDC_CH6_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH6_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH6_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH6_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH6_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH6_FADE_PARAM_SCALE_M ((LEDC_CH6_FADE_PARAM_SCALE_V)<<(LEDC_CH6_FADE_PARAM_SCALE_S)) +#define LEDC_CH6_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH6_FADE_PARAM_SCALE_S 11 +/* LEDC_CH6_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH6_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH6_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH6_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH6_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH6_FADE_PARAM_DUTY_INC_S 0 + + +#define LEDC_CH7_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x5c0) +/* LEDC_CH7_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_FADE_PARAM_DUTY_NUM 0x000003FF +#define LEDC_CH7_FADE_PARAM_DUTY_NUM_M ((LEDC_CH7_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH7_FADE_PARAM_DUTY_NUM_S)) +#define LEDC_CH7_FADE_PARAM_DUTY_NUM_V 0x3FF +#define LEDC_CH7_FADE_PARAM_DUTY_NUM_S 21 +/* LEDC_CH7_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_FADE_PARAM_SCALE 0x000003FF +#define LEDC_CH7_FADE_PARAM_SCALE_M ((LEDC_CH7_FADE_PARAM_SCALE_V)<<(LEDC_CH7_FADE_PARAM_SCALE_S)) +#define LEDC_CH7_FADE_PARAM_SCALE_V 0x3FF +#define LEDC_CH7_FADE_PARAM_SCALE_S 11 +/* LEDC_CH7_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH7_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH7_FADE_PARAM_DUTY_CYCLE_S)) +#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_S 1 +/* LEDC_CH7_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_FADE_PARAM_DUTY_INC (BIT(0)) +#define LEDC_CH7_FADE_PARAM_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_FADE_PARAM_DUTY_INC_V 0x1 +#define LEDC_CH7_FADE_PARAM_DUTY_INC_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h4/register/soc/ledc_struct.h b/components/soc/esp32h4/register/soc/ledc_struct.h index 137be624ef..54d1a05d2b 100644 --- a/components/soc/esp32h4/register/soc/ledc_struct.h +++ b/components/soc/esp32h4/register/soc/ledc_struct.h @@ -16,52 +16,52 @@ extern "C" { */ typedef union { struct { - /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + /** timer_sel : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel n selected. * 0: Select timer0 * 1: Select timer1 * 2: Select timer2 * 3: Select timer3 */ - uint32_t timer_sel_chn:2; - /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel n. * 0: Signal output disable * 1: Signal output enable */ - uint32_t sig_out_en_chn:1; - /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; * Configures the output value when channel n is inactive. Valid only when * LEDC_SIG_OUT_EN_CHn is 0. * 0: Output level is low * 1: Output level is high */ - uint32_t idle_lv_chn:1; - /** para_up_chn : WT; bitpos: [4]; default: 0; + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle * range configuration for channel n, and will be automatically cleared by hardware. * 0: Invalid. No effect * 1: Update */ - uint32_t para_up_chn:1; - /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. */ - uint32_t ovf_num_chn:10; - /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel n. * 0: Disable * 1: Enable */ - uint32_t ovf_cnt_en_chn:1; - /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel n. * 0: Invalid. No effect * 1: Reset the ovf_cnt */ - uint32_t ovf_cnt_reset_chn:1; + uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; }; uint32_t val; @@ -72,11 +72,11 @@ typedef union { */ typedef union { struct { - /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + /** hpoint : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel n. The output value changes to * high when the selected timers has reached the value specified by this register. */ - uint32_t hpoint_chn:20; + uint32_t hpoint:20; uint32_t reserved_20:12; }; uint32_t val; @@ -87,10 +87,10 @@ typedef union { */ typedef union { struct { - /** duty_chn : R/W; bitpos: [24:0]; default: 0; + /** duty : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel n. */ - uint32_t duty_chn:25; + uint32_t duty:25; uint32_t reserved_25:7; }; uint32_t val; @@ -102,53 +102,53 @@ typedef union { typedef union { struct { uint32_t reserved_0:31; - /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect. * 0: Not take effect * 1: Take effect */ - uint32_t duty_start_chn:1; + uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; -/** Type of timern_conf register - * Timer n configuration register +/** Type of timerx_conf register + * Timer x configuration register */ typedef union { struct { - /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; - * Configures the bit width of the counter in timer n. Valid values are 1 to 20. + /** duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the bit width of the counter in timer x. Valid values are 1 to 20. */ - uint32_t timern_duty_res:5; - /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer n.The least significant eight bits + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer x.The least significant eight bits * represent the fractional part. */ - uint32_t clk_div_timern:18; - /** timern_pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n. + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer x. * 0: Normal * 1: Pause */ - uint32_t timern_pause:1; - /** timern_rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after reset. + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer x. The counter will show 0 after reset. * 0: Not reset * 1: Reset */ - uint32_t timern_rst:1; + uint32_t rst:1; uint32_t reserved_25:1; - /** timern_para_up : WT; bitpos: [26]; default: 0; + /** para_up : WT; bitpos: [26]; default: 0; * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. * 0: Invalid. No effect * 1: Update */ - uint32_t timern_para_up:1; + uint32_t para_up:1; uint32_t reserved_27:5; }; uint32_t val; -} ledc_timern_conf_reg_t; +} ledc_timerx_conf_reg_t; /** Type of chn_fade_conf register * Ledc chn fade config register. @@ -156,18 +156,18 @@ typedef union { typedef union { struct { uint32_t reserved_0:5; - /** chn_fade_pause : WT; bitpos: [5]; default: 0; + /** fade_pause : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC chn. * 0: Invalid. No effect * 1: Pause */ - uint32_t chn_fade_pause:1; - /** chn_fade_resume : WT; bitpos: [6]; default: 0; + uint32_t fade_pause:1; + /** fade_resume : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC chn. * 0: Invalid. No effect * 1: Resume */ - uint32_t chn_fade_resume:1; + uint32_t fade_resume:1; uint32_t reserved_7:25; }; uint32_t val; @@ -733,19 +733,19 @@ typedef union { uint32_t val; } ledc_evt_task_en2_reg_t; -/** Type of timern_cmp register - * Ledc timern compare value register. +/** Type of timerx_cmp register + * Ledc timer x compare value register. */ typedef union { struct { - /** timern_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. + /** cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer x. */ - uint32_t timern_cmp:20; + uint32_t cmp:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_cmp_reg_t; +} ledc_timerx_cmp_reg_t; /** Type of conf register * LEDC global configuration register @@ -934,42 +934,42 @@ typedef union { */ typedef union { struct { - /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty_chn_r:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; } ledc_chn_duty_r_reg_t; -/** Type of timern_value register - * Timer n current counter value register +/** Type of timerx_value register + * Timer x current counter value register */ typedef union { struct { - /** timern_cnt : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer n. + /** cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer x. */ - uint32_t timern_cnt:20; + uint32_t cnt:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_value_reg_t; +} ledc_timerx_value_reg_t; -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. +/** Type of timerx_cnt_cap register + * Ledc timer x captured count value register. */ typedef union { struct { - /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. + /** cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer x count value. */ - uint32_t timern_cnt_cap:20; + uint32_t cnt_cap:20; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_cnt_cap_reg_t; +} ledc_timerx_cnt_cap_reg_t; /** Group: Interrupt Register */ @@ -1391,77 +1391,89 @@ typedef union { typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; - volatile ledc_chn_conf0_reg_t ch1_conf0; - volatile ledc_chn_hpoint_reg_t ch1_hpoint; - volatile ledc_chn_duty_reg_t ch1_duty; - volatile ledc_chn_conf1_reg_t ch1_conf1; - volatile ledc_chn_duty_r_reg_t ch1_duty_r; - volatile ledc_chn_conf0_reg_t ch2_conf0; - volatile ledc_chn_hpoint_reg_t ch2_hpoint; - volatile ledc_chn_duty_reg_t ch2_duty; - volatile ledc_chn_conf1_reg_t ch2_conf1; - volatile ledc_chn_duty_r_reg_t ch2_duty_r; - volatile ledc_chn_conf0_reg_t ch3_conf0; - volatile ledc_chn_hpoint_reg_t ch3_hpoint; - volatile ledc_chn_duty_reg_t ch3_duty; - volatile ledc_chn_conf1_reg_t ch3_conf1; - volatile ledc_chn_duty_r_reg_t ch3_duty_r; - volatile ledc_chn_conf0_reg_t ch4_conf0; - volatile ledc_chn_hpoint_reg_t ch4_hpoint; - volatile ledc_chn_duty_reg_t ch4_duty; - volatile ledc_chn_conf1_reg_t ch4_conf1; - volatile ledc_chn_duty_r_reg_t ch4_duty_r; - volatile ledc_chn_conf0_reg_t ch5_conf0; - volatile ledc_chn_hpoint_reg_t ch5_hpoint; - volatile ledc_chn_duty_reg_t ch5_duty; - volatile ledc_chn_conf1_reg_t ch5_conf1; - volatile ledc_chn_duty_r_reg_t ch5_duty_r; - volatile ledc_chn_conf0_reg_t ch6_conf0; - volatile ledc_chn_hpoint_reg_t ch6_hpoint; - volatile ledc_chn_duty_reg_t ch6_duty; - volatile ledc_chn_conf1_reg_t ch6_conf1; - volatile ledc_chn_duty_r_reg_t ch6_duty_r; - volatile ledc_chn_conf0_reg_t ch7_conf0; - volatile ledc_chn_hpoint_reg_t ch7_hpoint; - volatile ledc_chn_duty_reg_t ch7_duty; - volatile ledc_chn_conf1_reg_t ch7_conf1; - volatile ledc_chn_duty_r_reg_t ch7_duty_r; - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; - volatile ledc_timern_conf_reg_t timer1_conf; - volatile ledc_timern_value_reg_t timer1_value; - volatile ledc_timern_conf_reg_t timer2_conf; - volatile ledc_timern_value_reg_t timer2_value; - volatile ledc_timern_conf_reg_t timer3_conf; - volatile ledc_timern_value_reg_t timer3_value; + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty_init; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_r; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[8]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timerx_conf_reg_t conf; + volatile ledc_timerx_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_chn_fade_conf_reg_t fade_conf[8]; +} ledc_ch_fade_conf_group_reg_t; + +typedef struct { + volatile ledc_timerx_cmp_reg_t cmp[4]; +} ledc_timer_cmp_group_reg_t; + +typedef struct { + volatile ledc_timerx_cnt_cap_reg_t cnt_cap[4]; +} ledc_timer_cnt_cap_group_reg_t; + +/** + * Fade param register type + */ +typedef union { + struct { + uint32_t duty_inc :1; + uint32_t duty_cycle :10; + uint32_t scale :10; + uint32_t duty_num :10; + uint32_t reserved :1; + }; + uint32_t val; +} ledc_chn_fade_param_reg_t; + +typedef struct { + volatile ledc_chn_fade_param_reg_t fade_param; + uint32_t reserved[15]; +} ledc_chn_fade_param_t; + +typedef struct { + volatile ledc_chn_fade_param_t channel[8]; +} ledc_ch_fade_param_group_t; + +typedef struct ledc_dev_t { + volatile ledc_ch_group_reg_t channel_group[1]; + volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; - volatile ledc_chn_fade_conf_reg_t chn_fade_conf[8]; + volatile ledc_ch_fade_conf_group_reg_t channel_fade_conf_group[1]; volatile ledc_evt_task_en0_reg_t evt_task_en0; volatile ledc_evt_task_en1_reg_t evt_task_en1; volatile ledc_evt_task_en2_reg_t evt_task_en2; uint32_t reserved_12c[5]; - volatile ledc_timern_cmp_reg_t timern_cmp[4]; - volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1]; + volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1]; uint32_t reserved_160[4]; volatile ledc_conf_reg_t conf; volatile ledc_ch_power_up_conf_reg_t ch_power_up_conf; volatile ledc_timer_power_up_conf_reg_t timer_power_up_conf; volatile ledc_date_reg_t date; + uint32_t reserved_180[160]; + volatile ledc_ch_fade_param_group_t channel_fade_param_group[1]; } ledc_dev_t; extern ledc_dev_t LEDC; #ifndef __cplusplus -_Static_assert(sizeof(ledc_dev_t) == 0x180, "Invalid size of ledc_dev_t structure"); +_Static_assert(sizeof(ledc_dev_t) == 0x600, "Invalid size of ledc_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h4/register/soc/pcr_reg.h b/components/soc/esp32h4/register/soc/pcr_reg.h index 9d65e0d2fa..b1dbccde1b 100644 --- a/components/soc/esp32h4/register/soc/pcr_reg.h +++ b/components/soc/esp32h4/register/soc/pcr_reg.h @@ -571,7 +571,7 @@ extern "C" { * Configures the clock source of LEDC. * 0 (default): XTAL_CLK * 1: RC_FAST_CLK - * 2: PLL_F80M_CLK + * 2: PLL_F96M_CLK */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) diff --git a/components/soc/esp32h4/register/soc/pcr_struct.h b/components/soc/esp32h4/register/soc/pcr_struct.h index 0bc022d385..0753805af8 100644 --- a/components/soc/esp32h4/register/soc/pcr_struct.h +++ b/components/soc/esp32h4/register/soc/pcr_struct.h @@ -482,7 +482,7 @@ typedef union { * Configures the clock source of LEDC. * 0 (default): XTAL_CLK * 1: RC_FAST_CLK - * 2: PLL_F48M_CLK + * 2: PLL_F96M_CLK */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 0; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 75d680fdbd..3ca4fdf4d7 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -747,18 +747,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - config SOC_SDM_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index fa0e2373a0..e916122d65 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -289,12 +289,10 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1 -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ - +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS -----------------------------------*/ #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*------------------------- Analog Comparator CAPS ---------------------------*/ diff --git a/components/soc/esp32p4/include/soc/soc_caps_full.h b/components/soc/esp32p4/include/soc/soc_caps_full.h index 1992d8cc7d..7ccb01cd48 100644 --- a/components/soc/esp32p4/include/soc/soc_caps_full.h +++ b/components/soc/esp32p4/include/soc/soc_caps_full.h @@ -20,6 +20,10 @@ /*--------------------------- Watch Dog ------------------------------------------*/ #define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ + /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/ #define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances #define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 95d67be84c..65ea10de0c 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -411,26 +411,10 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_ALLOW_REG_ACCESS - bool - default y - config SOC_DEDIC_GPIO_HAS_INTERRUPT bool default y -config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE - bool - default y - config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index adef439f9a..2c0e3a7929 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -192,11 +192,7 @@ #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */ #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ -#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-S2 has 2 I2C diff --git a/components/soc/esp32s2/include/soc/soc_caps_full.h b/components/soc/esp32s2/include/soc/soc_caps_full.h index 3e0297910a..6f49d58aaa 100644 --- a/components/soc/esp32s2/include/soc/soc_caps_full.h +++ b/components/soc/esp32s2/include/soc/soc_caps_full.h @@ -29,3 +29,7 @@ #define _SOC_CAPS_PCNT_UNITS_PER_INST 4 // Number of units in each PCNT instance #define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit #define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit + +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 39220f92b1..e26c2642c9 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -495,18 +495,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP bool default y -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE - bool - default y - config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 696f1426d8..a52048b9af 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -207,11 +207,6 @@ // RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) -/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ -#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ -#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ -#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-S3 has 2 I2C #define SOC_I2C_NUM (2U) diff --git a/components/soc/esp32s3/include/soc/soc_caps_full.h b/components/soc/esp32s3/include/soc/soc_caps_full.h index ce9945f26a..d811597a3e 100644 --- a/components/soc/esp32s3/include/soc/soc_caps_full.h +++ b/components/soc/esp32s3/include/soc/soc_caps_full.h @@ -29,3 +29,7 @@ #define _SOC_CAPS_PCNT_UNITS_PER_INST 4 // Number of units in each PCNT instance #define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit #define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit + +/*------------------------------- Dedicated GPIO ------------------------------*/ +#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */ +#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/include/soc/dedic_gpio_periph.h b/components/soc/include/soc/dedic_gpio_periph.h index c0b6720b70..fe32aa9a8b 100644 --- a/components/soc/include/soc/dedic_gpio_periph.h +++ b/components/soc/include/soc/dedic_gpio_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,25 +7,27 @@ #pragma once #include -#include "soc/soc.h" -#include "soc/soc_caps.h" -#include "soc/periph_defs.h" +#include "soc/interrupts.h" +#include "soc/soc_caps_full.h" #ifdef __cplusplus extern "C" { #endif -#if SOC_DEDICATED_GPIO_SUPPORTED +#if SOC_HAS(DEDICATED_GPIO) +// helper macros to access module attributes +#define SOC_DEDIC_GPIO_ATTR(_attr) SOC_MODULE_ATTR(DEDIC_GPIO, _attr) + typedef struct { const int irq; // Interrupt resource (-1 means no interrupt supported) struct { - const int in_sig_per_channel[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; - const int out_sig_per_channel[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM]; + const int in_sig_per_channel[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; + const int out_sig_per_channel[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)]; } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix } dedic_gpio_signal_conn_t; extern const dedic_gpio_signal_conn_t dedic_gpio_periph_signals; -#endif // SOC_DEDICATED_GPIO_SUPPORTED +#endif // SOC_HAS(DEDICATED_GPIO) #ifdef __cplusplus } diff --git a/docs/docs_not_updated/esp32h21.txt b/docs/docs_not_updated/esp32h21.txt index 6cb47eefdc..3bfa3a3019 100644 --- a/docs/docs_not_updated/esp32h21.txt +++ b/docs/docs_not_updated/esp32h21.txt @@ -162,8 +162,6 @@ api-reference/peripherals/lcd/spi_lcd.rst api-reference/peripherals/lcd/rgb_lcd.rst api-reference/peripherals/lcd/parl_lcd.rst api-reference/peripherals/spi_features.rst -api-reference/peripherals/ppa.rst -api-reference/peripherals/ledc.rst api-reference/system/random.rst api-reference/system/app_trace.rst api-reference/system/esp_https_ota.rst diff --git a/docs/docs_not_updated/esp32h4.txt b/docs/docs_not_updated/esp32h4.txt index fde5afaaee..874bdbe339 100644 --- a/docs/docs_not_updated/esp32h4.txt +++ b/docs/docs_not_updated/esp32h4.txt @@ -169,7 +169,6 @@ api-reference/peripherals/lcd/rgb_lcd.rst api-reference/peripherals/lcd/parl_lcd.rst api-reference/peripherals/ppa.rst api-reference/peripherals/ldo_regulator.rst -api-reference/peripherals/ledc.rst api-reference/system/random.rst api-reference/system/app_trace.rst api-reference/system/mm_sync.rst diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index e0a7fab376..fdc2fa6dd0 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -1,7 +1,7 @@ LED Control (LEDC) ================== -{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16", esp32c61="16"} +{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16", esp32c61="16", esp32h21="16"} :link_to_translation:`zh_CN:[中文]` @@ -207,6 +207,25 @@ The source clock can also limit the PWM frequency. The higher the source clock f - 32 MHz - Dynamic Frequency Scaling compatible +.. only:: esp32h21 or esp32h4 + + .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks + :widths: 15 15 30 + :header-rows: 1 + + * - Clock name + - Clock freq + - Clock capabilities + * - PLL_96M_CLK + - 96 MHz + - / + * - RC_FAST_CLK + - ~ 20 MHz + - Dynamic Frequency Scaling compatible, Light-sleep compatible + * - XTAL_CLK + - 32 MHz + - Dynamic Frequency Scaling compatible + .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION diff --git a/docs/en/migration-guides/release-6.x/6.0/peripherals.rst b/docs/en/migration-guides/release-6.x/6.0/peripherals.rst index 6a0762c492..4411efc975 100644 --- a/docs/en/migration-guides/release-6.x/6.0/peripherals.rst +++ b/docs/en/migration-guides/release-6.x/6.0/peripherals.rst @@ -66,6 +66,8 @@ LEDC - ``LEDC_APB_CLK_HZ`` and ``LEDC_REF_CLK_HZ`` have been removed. +- ``LEDC_SLOW_CLK_RTC8M`` macro has been removed. Please use ``LEDC_SLOW_CLK_RC_FAST`` instead. + - Removed esp_driver_gpio as a public required component from esp_driver_ledc. - :func:`ledc_isr_register` has been deprecated. LEDC interrupt handling is implemented by driver itself, please only register event callbacks if necessary. diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 0c3f9a0ab0..8e8bfa6e77 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -1,7 +1,7 @@ LED PWM 控制器 ============== -{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16", esp32c61="16"} +{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16", esp32c61="16", esp32h21="16"} :link_to_translation:`en:[English]` @@ -207,6 +207,25 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - 32 MHz - 支持动态调频 (DFS) 功能 +.. only:: esp32h21 or esp32h4 + + .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks + :widths: 15 15 30 + :header-rows: 1 + + * - 时钟名称 + - 时钟频率 + - 时钟功能 + * - PLL_96M_CLK + - 96 MHz + - / + * - RC_FAST_CLK + - ~ 20 MHz + - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式 + * - XTAL_CLK + - 32 MHz + - 支持动态调频 (DFS) 功能 + .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION diff --git a/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst b/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst index 3013c78502..f7aef66a27 100644 --- a/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst +++ b/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst @@ -66,6 +66,8 @@ LEDC - ``LEDC_APB_CLK_HZ`` 和 ``LEDC_REF_CLK_HZ`` 已被移除。 +- ``LEDC_SLOW_CLK_RTC8M`` 宏已被移除。请使用 ``LEDC_SLOW_CLK_RC_FAST`` 代替。 + - esp_driver_gpio 不再作为 esp_driver_ledc 的公共依赖组件。 - :func:`ledc_isr_register` 已被弃用。LEDC 中断处理由驱动内部实现，如果需要注册中断回调，仅需要注册事件回调即可。 diff --git a/examples/peripherals/gpio/generic_gpio/README.md b/examples/peripherals/gpio/generic_gpio/README.md index 6ad5f50027..59c151893b 100644 --- a/examples/peripherals/gpio/generic_gpio/README.md +++ b/examples/peripherals/gpio/generic_gpio/README.md @@ -21,12 +21,7 @@ This test code shows how to configure GPIO and how to use it with interruption. 2. Connect CONFIG_GPIO_OUTPUT_1 with CONFIG_GPIO_INPUT_1 3. Generate pulses on CONFIG_GPIO_OUTPUT_0/1, that triggers interrupt on CONFIG_GPIO_INPUT_0/1 - **Note:** The following pin assignments are used by default, you can change them by `idf.py menuconfig` > `Example Configuration`. - -| | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 | -| ------------------------- | -------------------- | -------------------- | ------------------- | ------------------- | -| ESP32C2/H2/C5/C61/H21 | 8 | 9 | 4 | 5 | -| All other chips | 18 | 19 | 4 | 5 | + **Note:** The specific pin assignments can be viewed and changed in `idf.py menuconfig` > `Example Configuration`. ## How to use example diff --git a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild index 3b2ca6981a..658611d327 100644 --- a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild +++ b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild @@ -23,6 +23,7 @@ menu "Example Configuration" config GPIO_INPUT_0 int "GPIO input pin 0" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX + default 2 if IDF_TARGET_ESP32H4 default 4 help GPIO pin number to be used as GPIO_INPUT_IO_0. @@ -30,6 +31,7 @@ menu "Example Configuration" config GPIO_INPUT_1 int "GPIO input pin 1" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX + default 3 if IDF_TARGET_ESP32H4 default 5 help GPIO pin number to be used as GPIO_INPUT_IO_1. diff --git a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c index d095032f0e..b259f65c9b 100644 --- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c +++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c @@ -18,18 +18,17 @@ * This test code shows how to configure gpio and how to use gpio interrupt. * * GPIO status: - * GPIO18: output (ESP32C2/ESP32H2 uses GPIO8 as the second output pin) - * GPIO19: output (ESP32C2/ESP32H2 uses GPIO9 as the second output pin) - * GPIO4: input, pulled up, interrupt from rising edge and falling edge - * GPIO5: input, pulled up, interrupt from rising edge. + * GPIO_OUTPUT_IO_0: output + * GPIO_OUTPUT_IO_1: output + * GPIO_INPUT_IO_0: input, pulled up, interrupt from rising edge and falling edge + * GPIO_INPUT_IO_1: input, pulled up, interrupt from rising edge. * - * Note. These are the default GPIO pins to be used in the example. You can - * change IO pins in menuconfig. + * Note. You can check the default GPIO pins to be used in menuconfig, and the IOs can be changed. * * Test: - * Connect GPIO18(8) with GPIO4 - * Connect GPIO19(9) with GPIO5 - * Generate pulses on GPIO18(8)/19(9), that triggers interrupt on GPIO4/5 + * Connect GPIO_OUTPUT_IO_0 with GPIO_INPUT_IO_0 + * Connect GPIO_OUTPUT_IO_1 with GPIO_INPUT_IO_1 + * Generate pulses on GPIO_OUTPUT_IO_0/1, that triggers interrupt on GPIO_INPUT_IO_0/1 * */ diff --git a/examples/peripherals/ledc/ledc_basic/README.md b/examples/peripherals/ledc/ledc_basic/README.md index 1811c0f560..a1ceaceb0c 100644 --- a/examples/peripherals/ledc/ledc_basic/README.md +++ b/examples/peripherals/ledc/ledc_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | # _LEDC Basic Example_ @@ -19,7 +19,7 @@ Connect the GPIO to an oscilloscope to see the generated signal: |ledc channel| GPIO | |:----------:|:-----:| -| Channel 0 | GPIO5 | +| Channel 0 | GPIO2 | ### Configure the project diff --git a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c index c3ce8d240f..df8352731d 100644 --- a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c +++ b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c @@ -12,7 +12,7 @@ #define LEDC_TIMER LEDC_TIMER_0 #define LEDC_MODE LEDC_LOW_SPEED_MODE -#define LEDC_OUTPUT_IO (5) // Define the output GPIO +#define LEDC_OUTPUT_IO (2) // Define the output GPIO #define LEDC_CHANNEL LEDC_CHANNEL_0 #define LEDC_DUTY_RES LEDC_TIMER_13_BIT // Set duty resolution to 13 bits #define LEDC_DUTY (4096) // Set duty to 50%. (2 ** 13) * 50% = 4096 diff --git a/examples/peripherals/ledc/ledc_fade/README.md b/examples/peripherals/ledc/ledc_fade/README.md index c2fd5ce529..a2edc8731c 100644 --- a/examples/peripherals/ledc/ledc_fade/README.md +++ b/examples/peripherals/ledc/ledc_fade/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | # _LEDC Fade Example_ @@ -19,7 +19,7 @@ Connect four LEDs to the following LEDC channels / individual GPIOs: | | Channel 0 | Channel 1 | Channel 2 | Channel 3 | | --------------- | --------- | --------- | --------- | --------- | | ESP32 | GPIO18 | GPIO19 | GPIO4 | GPIO5 | -| All other chips | GPIO8 | GPIO9 | GPIO4 | GPIO5 | +| All other chips | GPIO8 | GPIO9 | GPIO2 | GPIO3 | ### Configure the project diff --git a/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c b/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c index 7c962c4d49..fa99420d19 100644 --- a/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c +++ b/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c @@ -44,19 +44,24 @@ #define LEDC_HS_CH0_CHANNEL LEDC_CHANNEL_0 #define LEDC_HS_CH1_GPIO (19) #define LEDC_HS_CH1_CHANNEL LEDC_CHANNEL_1 -#endif #define LEDC_LS_TIMER LEDC_TIMER_1 #define LEDC_LS_MODE LEDC_LOW_SPEED_MODE -#if !CONFIG_IDF_TARGET_ESP32 -#define LEDC_LS_CH0_GPIO (8) -#define LEDC_LS_CH0_CHANNEL LEDC_CHANNEL_0 -#define LEDC_LS_CH1_GPIO (9) -#define LEDC_LS_CH1_CHANNEL LEDC_CHANNEL_1 -#endif #define LEDC_LS_CH2_GPIO (4) #define LEDC_LS_CH2_CHANNEL LEDC_CHANNEL_2 #define LEDC_LS_CH3_GPIO (5) #define LEDC_LS_CH3_CHANNEL LEDC_CHANNEL_3 +#else +#define LEDC_LS_TIMER LEDC_TIMER_1 +#define LEDC_LS_MODE LEDC_LOW_SPEED_MODE +#define LEDC_LS_CH0_GPIO (8) +#define LEDC_LS_CH0_CHANNEL LEDC_CHANNEL_0 +#define LEDC_LS_CH1_GPIO (9) +#define LEDC_LS_CH1_CHANNEL LEDC_CHANNEL_1 +#define LEDC_LS_CH2_GPIO (2) +#define LEDC_LS_CH2_CHANNEL LEDC_CHANNEL_2 +#define LEDC_LS_CH3_GPIO (3) +#define LEDC_LS_CH3_CHANNEL LEDC_CHANNEL_3 +#endif #define LEDC_TEST_CH_NUM (4) #define LEDC_TEST_DUTY (4000) diff --git a/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md b/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md index 5a766af177..c751ac3961 100644 --- a/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md +++ b/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | +| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | # _LEDC Gamma Curve Fade Example_