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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/p4_lp_core' into 'master'
feat(ulp/lp_core): Added basic support for building and running a LP-Core app on ESP32P4 Closes IDF-7534 See merge request espressif/esp-idf!26869
This commit is contained in:
Marius Vikhammer
114
components/hal/esp32c6/include/hal/lp_core_ll.h
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114
components/hal/esp32c6/include/hal/lp_core_ll.h
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use it in application code.
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******************************************************************************/
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#pragma once
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#include <stdbool.h>
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#include "soc/lpperi_struct.h"
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#include "soc/pmu_struct.h"
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#include "soc/lp_aon_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt
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#define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(3) // Enable wake-up by ETM event
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER BIT(4) // Enable wake-up by LP timer
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/**
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* @brief Enable the bus clock for LP-core
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*
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* @param enable Enable if true, disable if false
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*/
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static inline void lp_core_ll_enable_bus_clock(bool enable)
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{
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/* ESP32C6 does not have clk/rst periph control for LP-core */
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(void)enable;
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}
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/**
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* @brief Reset the lp_core module
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*
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*/
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static inline void lp_core_ll_reset_register(void)
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{
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/* ESP32C6 does not have clk/rst periph control for LP-core */
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}
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/**
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* @brief Enable fast access of LP memory
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*
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* @note When fast access is activated, LP-core cannot access LP mem during deep sleep
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*
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* @param enable Enable if true, disable if false
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*/
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static inline void lp_core_ll_fast_lp_mem_enable(bool enable)
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{
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LP_AON.lpbus.fast_mem_mux_sel = enable;
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LP_AON.lpbus.fast_mem_mux_sel_update = 1;
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}
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/**
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* @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the LP-core
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*
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*/
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static inline void lp_core_ll_hp_wake_lp(void)
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{
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PMU.hp_lp_cpu_comm.hp_trigger_lp = 1;
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}
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/**
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* @brief Enable the debug module of LP-core, allowing JTAG to connect
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*
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* @param enable Enable if true, disable if false
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*/
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static inline void lp_core_ll_debug_module_enable(bool enable)
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{
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LPPERI.cpu.lpcore_dbgm_unavaliable = !enable;
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}
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/**
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* @brief Enable CPU reset at sleep
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*
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* @param enable Enable if true, disable if false
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*/
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static inline void lp_core_ll_rst_at_sleep_enable(bool enable)
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{
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PMU.lp_ext.pwr0.slp_reset_en = enable;
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}
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/**
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* @brief Stall LP-core at sleep requests
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*
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* @param enable Enable if true, disable if false
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*/
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static inline void lp_core_ll_stall_at_sleep_request(bool enable)
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{
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PMU.lp_ext.pwr0.slp_stall_en = enable;
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}
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/**
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* @brief Set wake-up sources for the LP-core
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*
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* @param flags Wake-up sources
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*/
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static inline void lp_core_ll_set_wakeup_source(uint32_t flags)
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{
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PMU.lp_ext.pwr1.wakeup_en = flags;
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}
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#ifdef __cplusplus
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}
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#endif
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138
components/hal/esp32p4/include/hal/lp_core_ll.h
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138
components/hal/esp32p4/include/hal/lp_core_ll.h
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use it in application code.
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******************************************************************************/
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#pragma once
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#include <stdbool.h>
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#include "soc/lpperi_struct.h"
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#include "soc/pmu_struct.h"
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#include "soc/lp_system_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(9)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(10)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_0 BIT(13)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_BOD BIT(14)
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#define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(17)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 BIT(18)
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_I2S BIT(19)
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#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(22)
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/* Use lp timer 1 as the normal wakeup timer, timer 0 is used by deep sleep */
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#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1
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/**
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* @brief Enable the bus clock for LP-coree
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*
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* @param enable true to enable, false to disable
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*/
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static inline void lp_core_ll_enable_bus_clock(bool enable)
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{
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LPPERI.clk_en.ck_en_lp_core = enable;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define lp_core_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the lp_core module
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*
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*/
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static inline void lp_core_ll_reset_register(void)
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{
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LPPERI.reset_en.rst_en_lp_core = 1;
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LPPERI.reset_en.rst_en_lp_core = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define lp_core_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_reset_register(__VA_ARGS__)
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/**
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* @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core
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*
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*/
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static inline void lp_core_ll_hp_wake_lp(void)
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{
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PMU.hp_lp_cpu_comm.hp_trigger_lp = 1;
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}
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/**
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* @brief Enables the LP core debug module, allowing JTAG to connect
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*
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* @param enable enable if true, disable if false
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*/
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static inline void lp_core_ll_debug_module_enable(bool enable)
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{
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LPPERI.cpu.lpcore_dbgm_unavailable = !enable;
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}
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/**
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* @brief Enables CPU reset at sleep
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*
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* @param enable enable if true, disable if false
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*/
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static inline void lp_core_ll_rst_at_sleep_enable(bool enable)
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{
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PMU.lp_cpu_pwr0.lp_cpu_slp_reset_en = enable;
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}
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/**
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* @brief Stall lp core cpu at sleep request
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*
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* @param enable enable if true, disable if false
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*/
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static inline void lp_core_ll_stall_at_sleep_request(bool enable)
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{
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PMU.lp_cpu_pwr0.lp_cpu_slp_stall_en = enable;
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}
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/**
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* @brief Set the wake-up source for the lp-core
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*
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* @param flags wake-up sources
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*/
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static inline void lp_core_ll_set_wakeup_source(uint32_t flags)
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{
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PMU.lp_cpu_pwr2.lp_cpu_wakeup_en = flags;
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}
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/**
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* @brief Set boot address for lp core
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*
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* @param boot_address address which the lp core will start booting from
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*/
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static inline void lp_core_ll_set_boot_address(intptr_t boot_address)
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{
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LP_SYS.lp_core_boot_addr.lp_cpu_boot_addr = boot_address;
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}
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/**
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* @brief Set address LP-ROM bootloader will jump to after initialization
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*
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* @param boot_address address which the LP-ROM bootloader will jump to
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*/
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static inline void lp_core_ll_set_app_boot_address(intptr_t boot_address)
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{
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LP_SYS.boot_addr_hp_lp_reg.boot_addr_hp_lp = boot_address;
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}
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#ifdef __cplusplus
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}
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#endif
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72
components/hal/esp32p4/include/hal/lp_timer_ll.h
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72
components/hal/esp32p4/include/hal/lp_timer_ll.h
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@@ -0,0 +1,72 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-P4 LP_Timer register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/lp_timer_struct.h"
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#include "soc/lp_system_reg.h"
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#include "hal/lp_timer_types.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
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{
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dev->target[timer_id].hi.target_hi = (value >> 32) & 0xFFFF;
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dev->target[timer_id].lo.target_lo = value & 0xFFFFFFFF;
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}
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FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
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{
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dev->target[timer_id].hi.enable = en;
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}
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FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
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{
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return dev->counter[timer_id].lo.counter_lo;
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}
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FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
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{
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return dev->counter[timer_id].hi.counter_hi;
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}
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FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
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{
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dev->update.main_timer_update = 1;
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}
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FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
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{
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dev->int_clr.soc_wakeup_int_clr = 1;
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}
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FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
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{
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dev->int_clr.overflow_clr = 1;
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}
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FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
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{
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dev->lp_int_clr.main_timer_lp_int_clr = 1;
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}
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FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
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{
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uint32_t slow_clk_value = REG_READ(LP_SYSTEM_REG_LP_STORE1_REG);
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return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
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}
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#ifdef __cplusplus
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}
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#endif
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