From ae6d9e2b936dfda31109a53ba08c0071bb99ef1b Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 20 Jul 2023 12:20:42 +0800 Subject: [PATCH] fix(cache): added alignment check for M2C direction --- components/esp_mm/esp_cache.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/components/esp_mm/esp_cache.c b/components/esp_mm/esp_cache.c index 83f6ea71d0..4784bfad90 100644 --- a/components/esp_mm/esp_cache.c +++ b/components/esp_mm/esp_cache.c @@ -26,9 +26,13 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags) ESP_RETURN_ON_FALSE_ISR(mmu_hal_check_valid_ext_vaddr_region(0, (uint32_t)addr, size, MMU_VADDR_DATA), ESP_ERR_INVALID_ARG, TAG, "invalid address"); bool both_dir = (flags & ESP_CACHE_MSYNC_FLAG_DIR_C2M) && (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C); ESP_RETURN_ON_FALSE_ISR(!both_dir, ESP_ERR_INVALID_ARG, TAG, "both C2M and M2C directions are selected, you should only select one"); + uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA); + if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) { + bool aligned_addr = (((uint32_t)addr % data_cache_line_size) == 0) && ((size % data_cache_line_size) == 0); + ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address, end address or the size is(are) not aligned with the data cache line size (%d)B", data_cache_line_size); + } uint32_t vaddr = (uint32_t)addr; - if (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C) { ESP_EARLY_LOGD(TAG, "M2C DIR"); @@ -41,12 +45,6 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags) ESP_EARLY_LOGD(TAG, "C2M DIR"); #if SOC_CACHE_WRITEBACK_SUPPORTED - uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA); - - if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) { - bool aligned_addr = (((uint32_t)addr % data_cache_line_size) == 0) && ((size % data_cache_line_size) == 0); - ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address, end address or the size is(are) not aligned with the data cache line size (%d)B", data_cache_line_size); - } esp_os_enter_critical_safe(&s_spinlock); cache_hal_writeback_addr(vaddr, size);