From aeba99290fa8f219b900c1e610936f4adf56d426 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Tue, 17 Jun 2025 21:37:41 +0800 Subject: [PATCH] feat(hal): add esp32h4 PAU initial support --- .../hal/esp32h4/include/hal/lp_aon_ll.h | 141 +++++++++++++ components/hal/esp32h4/include/hal/pau_ll.h | 193 ++++++++++++++++++ components/hal/esp32h4/pau_hal.c | 63 ++++++ 3 files changed, 397 insertions(+) create mode 100644 components/hal/esp32h4/include/hal/lp_aon_ll.h create mode 100644 components/hal/esp32h4/include/hal/pau_ll.h create mode 100644 components/hal/esp32h4/pau_hal.c diff --git a/components/hal/esp32h4/include/hal/lp_aon_ll.h b/components/hal/esp32h4/include/hal/lp_aon_ll.h new file mode 100644 index 0000000000..b56e36f2e0 --- /dev/null +++ b/components/hal/esp32h4/include/hal/lp_aon_ll.h @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H4 LP_AON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/lp_aon_struct.h" +#include "hal/misc.h" +#include "esp32h4/rom/rtc.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get ext1 wakeup source status + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl1, aon_ext_wakeup_status); +} + +/** + * @brief Clear the ext1 wakeup source status + */ +static inline void lp_aon_ll_ext1_clear_wakeup_status(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl1, aon_ext_wakeup_status_clr, 1); +} + +/** + * @brief Set the wake-up LP_IO of the ext1 wake-up source + * @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7 + * @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level + * each bit's corresponding position is set to 0, the wakeup level will be low + * on the contrary, each bit's corresponding position is set to 1, the wakeup + * level will be high + */ +static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) +{ + uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); + wakeup_sel_mask |= io_mask; + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, wakeup_sel_mask); + + uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv); + wakeup_level_mask |= io_mask & level_mask; + wakeup_level_mask &= ~(io_mask & ~level_mask); + + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv, wakeup_level_mask); +} + +/** + * @brief Clear all ext1 wakup-source setting + */ +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, 0); +} + +/** + * @brief Get ext1 wakeup source setting + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); +} + + +/** + * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. + * Set the flag to inform + * @param true: deepsleep false: lightsleep + */ +static inline void lp_aon_ll_inform_wakeup_type(bool dslp) +{ + if (dslp) { + REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ + + } else { + REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ + } +} + +/** + * @brief Set the maximum number of linked lists supported by REGDMA + * @param count: the maximum number of regdma link + */ +static inline void lp_aon_ll_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); +} + +static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); +} + +/** + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. + * @param count: the maximum number of loop + */ +static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); +} + +/** + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing + * registers and gets stuck on the bus, a timeout will be triggered. + * @param count: the maximum number of time + */ +static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); +} + +static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); +} + +static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/pau_ll.h b/components/hal/esp32h4/include/hal/pau_ll.h new file mode 100644 index 0000000000..ebdf1b3a8e --- /dev/null +++ b/components/hal/esp32h4/include/hal/pau_ll.h @@ -0,0 +1,193 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H4 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "soc/pcr_struct.h" +#include "hal/pau_types.h" +#include "hal/assert.h" +#include "soc/lp_aon_struct.h" +#include "soc/lp_aon_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void pau_ll_enable_bus_clock(bool enable) +{ + if (enable) { + PCR.regdma_conf.regdma_clk_en = 1; + PCR.regdma_conf.regdma_rst_en = 0; + } else { + PCR.regdma_conf.regdma_clk_en = 0; + PCR.regdma_conf.regdma_rst_en = 1; + } +} + +static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ + return LP_AON.backup_dma_cfg0.aon_regdma_error; +} + +static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ + dev->regdma_conf.link_sel = link; +} + +static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 1; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 0; +} + +static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) +{ + LP_AON.backup_dma_cfg2.aon_link_addr_aon = (uint32_t)link_addr; +} + +static inline void pau_ll_set_regdma_timeout_link_backup_wait(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_BACKUP_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_read_interval(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_READ_INTERVAL_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_burst_limit(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_BURST_LIMIT_AON, thres); +} +static inline void pau_ll_set_regdma_timeout_max_link_work(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WORK_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_read_mode_try_time(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WAIT_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_branch_max_link(pau_dev_t *dev, uint32_t max_link_len) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_BRANCH_LINK_LENGTH_AON, max_link_len); +} + +static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ + return dev->regdma_current_link_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ + return dev->regdma_peri_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ + return dev->regdma_mem_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ + return dev->int_raw.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ + return dev->int_st.val; +} + +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 1; +} + +static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 0; +} + +static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 1; +} + +static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 0; +} + +static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ + dev->int_clr.done_int_clr = 1; +} + +static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ + dev->int_clr.error_int_clr = 1; +} + +static inline void pau_ll_arbiter_auto_retry_enable(pau_dev_t *dev, bool ena) +{ + dev->regdma_conf.sw_retry_en = ena; +} + +static inline void pau_ll_arbiter_fix_priority_enable(pau_dev_t *dev, bool ena) +{ + dev->regdma_conf.fix_pri_en = ena; +} + +/** + * arbiter result coding: + * 1: mac_req + * 2: pmu_req + * 3: sw_req + * 4: etm0_req + * 5: etm1_req + * 6: etm2_req + * 7: etm3_req +*/ +static inline uint32_t pau_ll_arbiter_get_start_result(pau_dev_t *dev) +{ + return dev->regdma_grant_result.grant_start_result; +} + +static inline uint32_t pau_ll_arbiter_get_done_result(pau_dev_t *dev) +{ + return dev->regdma_grant_result.grant_done_result; +} + +static inline void pau_ll_arbiter_clr_result_flag(pau_dev_t *dev) +{ + dev->regdma_grant_result.grant_result_clr = 1; +} + +static inline bool pau_ll_is_busy(pau_dev_t *dev) +{ + return dev->regdma_conf.paudma_busy; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/pau_hal.c b/components/hal/esp32h4/pau_hal.c new file mode 100644 index 0000000000..72f95eeba1 --- /dev/null +++ b/components/hal/esp32h4/pau_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PAU (ESP32-H4 specific part) + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pau_hal.h" +#include "hal/pau_types.h" +#include "hal/lp_aon_ll.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); +} + +void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules. + * It is also used as software trigger REGDMA to backup and restore, and is + * used by the UT to test module driver retention function. + */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +#if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE +void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) +{ + HAL_ASSERT(count > 0); + lp_aon_ll_set_regdma_link_count(count - 1); +} +#endif + +void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) +{ + HAL_ASSERT(loop_num > 0 && time > 0); + lp_aon_ll_set_regdma_link_loop_threshold(loop_num); + lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); +} + +void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) +{ + HAL_ASSERT(count > 0 && interval > 0); + lp_aon_ll_set_regdma_link_wait_retry_count(count); + lp_aon_ll_set_regdma_link_wait_read_interval(interval); +}