From b055bff580a1a93256777bf1b58db410f1cf4065 Mon Sep 17 00:00:00 2001 From: fuzhibo Date: Thu, 13 Jun 2019 19:34:01 +0800 Subject: [PATCH] 1.update touch driver; 2.update adc/dac driver; 3.add temp sensor driver; --- .../src/bootloader_random.c | 37 +- components/driver/CMakeLists.txt | 2 + components/driver/include/driver/adc.h | 30 + components/driver/include/driver/dac.h | 8 + .../driver/include/driver/temp_sensor.h | 36 + components/driver/include/driver/touch_pad.h | 178 ++ components/driver/rtc_module.c | 216 +- components/driver/rtc_tempsensor.c | 99 + components/driver/rtc_touchpad.c | 738 ++++++ components/esp32s2beta/sleep_modes.c | 2 +- .../esp32s2beta/include/soc/rtc_cntl_reg.h | 4 +- .../esp32s2beta/include/soc/rtc_cntl_struct.h | 517 ++-- .../soc/esp32s2beta/include/soc/sens_reg.h | 2291 ++++++++++------- .../soc/esp32s2beta/include/soc/sens_struct.h | 586 +++-- .../esp32s2beta/include/soc/touch_channel.h | 50 +- components/ulp/ulp.c | 4 + .../peripherals/adc/main/adc1_example_main.c | 41 +- .../peripherals/adc2/main/adc2_example_main.c | 1 - .../peripherals/temp_sensor/CMakeLists.txt | 6 + examples/peripherals/temp_sensor/Makefile | 9 + examples/peripherals/temp_sensor/README.md | 0 .../temp_sensor/main/CMakeLists.txt | 4 + .../peripherals/temp_sensor/main/component.mk | 3 + .../temp_sensor/main/temp_sensor_main.c | 46 + .../main/tp_interrupt_main.c | 187 ++ .../touch_pad_read/main/tp_read_main.c | 73 + 26 files changed, 3793 insertions(+), 1375 deletions(-) create mode 100644 components/driver/include/driver/temp_sensor.h create mode 100644 components/driver/rtc_tempsensor.c create mode 100644 components/driver/rtc_touchpad.c create mode 100644 examples/peripherals/temp_sensor/CMakeLists.txt create mode 100644 examples/peripherals/temp_sensor/Makefile create mode 100644 examples/peripherals/temp_sensor/README.md create mode 100644 examples/peripherals/temp_sensor/main/CMakeLists.txt create mode 100644 examples/peripherals/temp_sensor/main/component.mk create mode 100644 examples/peripherals/temp_sensor/main/temp_sensor_main.c diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index 04fa10d9c4..99766abd72 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -20,6 +20,7 @@ #include "soc/dport_reg.h" #include "soc/i2s_periph.h" #include "esp_log.h" +#include "soc/io_mux_reg.h" #ifndef BOOTLOADER_BUILD #include "esp_system.h" @@ -81,11 +82,25 @@ void bootloader_random_enable(void) */ SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S); SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + /* Disable IO1 digital function for random function. */ + PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U); + WRITE_PERI_REG(SYSCON_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF); + + SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); + CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP); +#endif + // Test pattern configuration byte 0xAD: //--[7:4] channel_sel: 10-->en_test //--[3:2] bit_width : 3-->12bit @@ -94,10 +109,15 @@ void bootloader_random_enable(void) WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); - +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); + SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); +#endif + #if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); #endif @@ -137,18 +157,25 @@ void bootloader_random_disable(void) CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); /* Restore SYSCON mode registers */ +#if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); +#endif +#if CONFIG_IDF_TARGET_ESP32 /* Restore SAR ADC mode */ CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); -#if CONFIG_IDF_TARGET_ESP32 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); -#endif SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); + CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); + SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); +#endif + #if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S); #endif diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 8e2ab494ba..743d213322 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -6,6 +6,8 @@ set(COMPONENT_SRCS "can.c" "periph_ctrl.c" "rmt.c" "rtc_module.c" + "rtc_tempsensor.c" + "rtc_touchpad.c" "sdspi_crc.c" "sdspi_host.c" "sdspi_transaction.c" diff --git a/components/driver/include/driver/adc.h b/components/driver/include/driver/adc.h index 91eb18fd2f..a890a8ab22 100644 --- a/components/driver/include/driver/adc.h +++ b/components/driver/include/driver/adc.h @@ -52,6 +52,7 @@ typedef enum { #define ADC_WIDTH_11Bit ADC_WIDTH_BIT_11 #define ADC_WIDTH_12Bit ADC_WIDTH_BIT_12 +#if CONFIG_IDF_TARGET_ESP32 typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */ ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO37 */ @@ -77,6 +78,35 @@ typedef enum { ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 */ ADC2_CHANNEL_MAX, } adc2_channel_t; +#elif CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */ + ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO2 */ + ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO3 */ + ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO4 */ + ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO5 */ + ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO6 */ + ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO7 */ + ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO8 */ + ADC1_CHANNEL_8, /*!< ADC1 channel 6 is GPIO9 */ + ADC1_CHANNEL_9, /*!< ADC1 channel 7 is GPIO10 */ + ADC1_CHANNEL_MAX, +} adc1_channel_t; + +typedef enum { + ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO11 */ + ADC2_CHANNEL_1, /*!< ADC2 channel 1 is GPIO12 */ + ADC2_CHANNEL_2, /*!< ADC2 channel 2 is GPIO13 */ + ADC2_CHANNEL_3, /*!< ADC2 channel 3 is GPIO14 */ + ADC2_CHANNEL_4, /*!< ADC2 channel 4 is GPIO15 */ + ADC2_CHANNEL_5, /*!< ADC2 channel 5 is GPIO16 */ + ADC2_CHANNEL_6, /*!< ADC2 channel 6 is GPIO17 */ + ADC2_CHANNEL_7, /*!< ADC2 channel 7 is GPIO18 */ + ADC2_CHANNEL_8, /*!< ADC2 channel 8 is GPIO19 */ + ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO20 */ + ADC2_CHANNEL_MAX, +} adc2_channel_t; +#endif typedef enum { ADC_CHANNEL_0 = 0, /*!< ADC channel */ diff --git a/components/driver/include/driver/dac.h b/components/driver/include/driver/dac.h index 1e60263c2f..cdde967398 100644 --- a/components/driver/include/driver/dac.h +++ b/components/driver/include/driver/dac.h @@ -23,11 +23,19 @@ extern "C" { #include "esp_err.h" #include "soc/dac_periph.h" +#if CONFIG_IDF_TARGET_ESP32 typedef enum { DAC_CHANNEL_1 = 1, /*!< DAC channel 1 is GPIO25 */ DAC_CHANNEL_2, /*!< DAC channel 2 is GPIO26 */ DAC_CHANNEL_MAX, } dac_channel_t; +#elif CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + DAC_CHANNEL_1 = 1, /*!< DAC channel 1 is GPIO17 */ + DAC_CHANNEL_2, /*!< DAC channel 2 is GPIO18 */ + DAC_CHANNEL_MAX, +} dac_channel_t; +#endif /** * @brief Get the gpio number of a specific DAC channel. diff --git a/components/driver/include/driver/temp_sensor.h b/components/driver/include/driver/temp_sensor.h new file mode 100644 index 0000000000..eaf7c2cbcb --- /dev/null +++ b/components/driver/include/driver/temp_sensor.h @@ -0,0 +1,36 @@ +#ifndef _TEMP_SENSOR_H_ +#define _TEMP_SENSOR_H_ + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + TEMP_SENSOR_DAC_L0 = 5, // offset = -2, range: 50℃ ~ 125℃, error < 3℃. + TEMP_SENSOR_DAC_L1 = 7, // offset = -1, range: 20℃ ~ 100℃, error < 2℃. + TEMP_SENSOR_DAC_L2 = 15, // offset = 0, range:-10℃ ~ 80℃, error < 1℃. + TEMP_SENSOR_DAC_L3 = 11, // offset = 1, range:-30℃ ~ 50℃, error < 2℃. + TEMP_SENSOR_DAC_L4 = 10, // offset = 2, range:-40℃ ~ 20℃, error < 3℃. + TEMP_SENSOR_DAC_DEFAULT = TEMP_SENSOR_DAC_L2, +} temp_sensor_dac_offset_t;; + +typedef struct temp_sensor { + temp_sensor_dac_offset_t dac_offset; + uint8_t clk_div; +} temp_sensor_t; + +esp_err_t temp_sensor_set_config(temp_sensor_t temps); +esp_err_t temp_sensor_get_config(temp_sensor_t *temps); +esp_err_t temp_sensor_start(void); +esp_err_t temp_sensor_stop(void); +esp_err_t temp_sensor_read(uint8_t *temp_out); +#endif + +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/components/driver/include/driver/touch_pad.h b/components/driver/include/driver/touch_pad.h index 0c3884ded9..bbfab6ab72 100644 --- a/components/driver/include/driver/touch_pad.h +++ b/components/driver/include/driver/touch_pad.h @@ -32,6 +32,13 @@ typedef enum { TOUCH_PAD_NUM7, /*!< Touch pad channel 7 is GPIO27*/ TOUCH_PAD_NUM8, /*!< Touch pad channel 8 is GPIO33*/ TOUCH_PAD_NUM9, /*!< Touch pad channel 9 is GPIO32*/ +#if CONFIG_IDF_TARGET_ESP32S2BETA + TOUCH_PAD_NUM10, /*!< Touch pad channel 6 is */ + TOUCH_PAD_NUM11, /*!< Touch pad channel 7 is */ + TOUCH_PAD_NUM12, /*!< Touch pad channel 8 is */ + TOUCH_PAD_NUM13, /*!< Touch pad channel 9 is */ + TOUCH_PAD_NUM14, /*!< Touch pad channel 9 is */ +#endif TOUCH_PAD_MAX, } touch_pad_t; @@ -98,9 +105,104 @@ typedef enum { TOUCH_FSM_MODE_MAX, } touch_fsm_mode_t; +#if CONFIG_IDF_TARGET_ESP32S2BETA +typedef enum { + TOUCH_PAD_INTR_DONE = 0, //each channel measure done. + TOUCH_PAD_INTR_ACTIVE = 1, + TOUCH_PAD_INTR_INACTIVE = 2, + TOUCH_PAD_INTR_ALL, + TOUCH_PAD_INTR_MAX +} touch_pad_intr_type_t; + +typedef enum { + TOUCH_PAD_INTR_MASK_DONE = BIT(0), //each channel measure done. + TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1), + TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2), + TOUCH_PAD_INTR_MASK_ALL = BIT(2)|BIT(1)|BIT(0), + TOUCH_PAD_INTR_MASK_MAX +}touch_pad_intr_mask_t; + +typedef enum { + TOUCH_PAD_DENOISE_BIT12 = 0, + TOUCH_PAD_DENOISE_BIT10 = 1, + TOUCH_PAD_DENOISE_BIT8 = 2, + TOUCH_PAD_DENOISE_BIT4 = 3, + TOUCH_PAD_DENOISE_MAX +} touch_pad_denoise_grade_t; + +typedef enum { + TOUCH_PAD_DENOISE_CAP_L0 = 0, // 0pf + TOUCH_PAD_DENOISE_CAP_L1 = 4, // 1.4pf + TOUCH_PAD_DENOISE_CAP_L2 = 2, // 2.8pf + TOUCH_PAD_DENOISE_CAP_L3 = 6, // 4.2pf + TOUCH_PAD_DENOISE_CAP_L4 = 1, // 5.6pf + TOUCH_PAD_DENOISE_CAP_L5 = 5, // 7.0pf + TOUCH_PAD_DENOISE_CAP_L6 = 3, // 8.4pf + TOUCH_PAD_DENOISE_CAP_L7 = 7, // 9.8pf + TOUCH_PAD_DENOISE_CAP_MAX +} touch_pad_denoise_cap_t; + +typedef struct touch_pad_denoise { + touch_pad_denoise_grade_t grade; + touch_pad_denoise_cap_t cap_level; +} touch_pad_denoise_t; + +typedef enum { + TOUCH_PAD_SHIELD_DRV_L0 = 0, // 40pf + TOUCH_PAD_SHIELD_DRV_L1, // 80pf + TOUCH_PAD_SHIELD_DRV_L2, // 120pf + TOUCH_PAD_SHIELD_DRV_L3, // 160pf + TOUCH_PAD_SHIELD_DRV_L4, // 200pf + TOUCH_PAD_SHIELD_DRV_L5, // 240pf + TOUCH_PAD_SHIELD_DRV_L6, // 280pf + TOUCH_PAD_SHIELD_DRV_L7, // 320pf + TOUCH_PAD_SHIELD_DRV_MAX +} touch_pad_shield_driver_t; + +typedef struct touch_pad_waterproof { + touch_pad_t guard_ring_pad; + touch_pad_shield_driver_t shield_driver; +} touch_pad_waterproof_t; + +typedef struct touch_pad_approach { + touch_pad_t select_pad0; + touch_pad_t select_pad1; + touch_pad_t select_pad2; + uint8_t means_num; +} touch_pad_approach_t; + +typedef enum { + TOUCH_PAD_CONN_HIGHZ = 0, + TOUCH_PAD_CONN_GND = 1, + TOUCH_PAD_CONN_MAX +} touch_pad_conn_type_t; + +typedef enum { + TOUCH_PAD_FILTER_IIR_2 = 0, + TOUCH_PAD_FILTER_IIR_4, + TOUCH_PAD_FILTER_IIR_8, + TOUCH_PAD_FILTER_JITTER, + TOUCH_PAD_FILTER_MAX +} touch_filter_mode_t; + +typedef struct touch_filter_config { + touch_filter_mode_t mode; + uint8_t debounce_cnt; //0 ~ 7. + uint8_t hysteresis_thr; //0 ~ 3. 0: 1/8; 1: 3/32; 2: 1/16; 3: 1/32; + uint8_t noise_thr; //0 ~ 3. 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; + uint8_t noise_neg_thr; //0 ~ 3. 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; + uint8_t neg_noise_limit;//0 ~ 15. + uint8_t jitter_step; //0 ~ 15. +} touch_filter_config_t; + +#define TOUCH_PAD_THRESHOLD_MAX 0x1FFFFF//0x3FFFFF + +#endif typedef intr_handle_t touch_isr_handle_t; +#if CONFIG_IDF_TARGET_ESP32 + #define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0x1000) /*! +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "esp_log.h" +#include "soc/rtc_io_reg.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_reg.h" +#include "soc/sens_struct.h" +#include "temp_sensor.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/ets_sys.h" +#endif + +#if CONFIG_IDF_TARGET_ESP32S2BETA + +#define TEMP_SENSOR_XPD_WAIT_DEFAULT 0xFF /* Set wait cycle time(8MHz) from power up to reset enable. */ + +portMUX_TYPE rtc_temp_spinlock = portMUX_INITIALIZER_UNLOCKED; +static SemaphoreHandle_t rtc_touch_mux = NULL; + +esp_err_t temp_sensor_set_config(temp_sensor_t temps) +{ + portENTER_CRITICAL(&rtc_temp_spinlock); + SENS.sar_tctrl.tsens_dac = temps.dac_offset; + SENS.sar_tctrl.tsens_clk_div = temps.clk_div; + SENS.sar_tctrl.tsens_power_up_force = 1; + SENS.sar_tctrl2.tsens_xpd_wait = TEMP_SENSOR_XPD_WAIT_DEFAULT; + SENS.sar_tctrl2.tsens_xpd_force = 1; + SENS.sar_tctrl2.tsens_reset = 1;// Reset the temp sensor. + SENS.sar_tctrl2.tsens_reset = 0;// Clear the reset status. + portEXIT_CRITICAL(&rtc_temp_spinlock); + return ESP_OK; +} + +esp_err_t temp_sensor_get_config(temp_sensor_t *temps) +{ + if(temps) { + portENTER_CRITICAL(&rtc_temp_spinlock); + temps->dac_offset = SENS.sar_tctrl.tsens_dac; + temps->clk_div = SENS.sar_tctrl.tsens_clk_div; + portEXIT_CRITICAL(&rtc_temp_spinlock); + return ESP_OK; + } else { + return ESP_FAIL; + } +} + +esp_err_t temp_sensor_start(void) +{ + portENTER_CRITICAL(&rtc_temp_spinlock); + SENS.sar_tctrl.tsens_dump_out = 0; + SENS.sar_tctrl2.tsens_clkgate_en = 1; + SENS.sar_tctrl.tsens_power_up = 1; + portEXIT_CRITICAL(&rtc_temp_spinlock); + return ESP_OK; +} + +esp_err_t temp_sensor_stop(void) +{ + portENTER_CRITICAL(&rtc_temp_spinlock); + SENS.sar_tctrl.tsens_power_up = 0; + SENS.sar_tctrl2.tsens_clkgate_en = 0; + portEXIT_CRITICAL(&rtc_temp_spinlock); + return ESP_OK; +} + +esp_err_t temp_sensor_read(uint8_t *temp_out) +{ + if(temp_out) { + portENTER_CRITICAL(&rtc_temp_spinlock); + SENS.sar_tctrl.tsens_dump_out = 1; + while(!SENS.sar_tctrl.tsens_ready); + *temp_out = SENS.sar_tctrl.tsens_out; + SENS.sar_tctrl.tsens_dump_out = 0; + portEXIT_CRITICAL(&rtc_temp_spinlock); + return ESP_OK; + } else { + return ESP_FAIL; + } +} +#endif \ No newline at end of file diff --git a/components/driver/rtc_touchpad.c b/components/driver/rtc_touchpad.c new file mode 100644 index 0000000000..5843d5665d --- /dev/null +++ b/components/driver/rtc_touchpad.c @@ -0,0 +1,738 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include "esp_log.h" +#include "soc/rtc_periph.h" +#include "soc/sens_periph.h" +#include "soc/rtc_io_reg.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_reg.h" +#include "soc/sens_struct.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_cntl_struct.h" +#include "soc/rtc.h" +#include "soc/periph_defs.h" +#include "rtc_io.h" +#include "touch_pad.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "freertos/semphr.h" +#include "freertos/timers.h" +#include "esp_intr_alloc.h" +#include "sys/lock.h" +#include "driver/rtc_cntl.h" +#include "driver/gpio.h" +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/ets_sys.h" +#endif + +#ifndef NDEBUG +// Enable built-in checks in queue.h in debug builds +#define INVARIANTS +#endif +#include "sys/queue.h" + +#if CONFIG_IDF_TARGET_ESP32S2BETA + +#define TOUCH_PAD_FILTER_FACTOR_DEFAULT (4) // IIR filter coefficient. +#define TOUCH_PAD_SHIFT_DEFAULT (4) // Increase computing accuracy. +#define TOUCH_PAD_SHIFT_ROUND_DEFAULT (8) // ROUND = 2^(n-1); rounding off for fractional. +#define DAC_ERR_STR_CHANNEL_ERROR "DAC channel error" + +static portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED; +static const char *RTC_MODULE_TAG = "RTC_MODULE"; + +#define RTC_MODULE_CHECK(a, str, ret_val) if (!(a)) { \ + ESP_LOGE(RTC_MODULE_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \ + return (ret_val); \ +} + +#define RTC_RES_CHECK(res, ret_val) if ( (a) != ESP_OK) { \ + ESP_LOGE(RTC_MODULE_TAG,"%s:%d (%s)", __FILE__, __LINE__, __FUNCTION__); \ + return (ret_val); \ +} +static SemaphoreHandle_t rtc_touch_mux = NULL; + +// check if touch pad be inited. +static uint16_t s_touch_pad_init_bit = 0x0000; + +/*--------------------------------------------------------------- + Touch Pad +---------------------------------------------------------------*/ +esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg, touch_pad_intr_mask_t intr_mask) +{ + RTC_MODULE_CHECK(intr_mask < TOUCH_PAD_INTR_MASK_MAX, "intr mask err", ESP_ERR_INVALID_ARG); + RTC_MODULE_CHECK(fn, "Touch_Pad ISR null", ESP_ERR_INVALID_ARG); + return rtc_isr_register(fn, arg, intr_mask << RTC_CNTL_TOUCH_DONE_INT_ENA_S); +} + +esp_err_t touch_pad_isr_deregister(intr_handler_t fn, void *arg) +{ + return rtc_isr_deregister(fn, arg); +} + +esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_cycle) +{ + xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); + portENTER_CRITICAL(&rtc_spinlock); + // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK( can be 150k or 32k depending on the options) + RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_cycle; + //touch sensor measure time= meas_cycle / 8Mhz + RTCCNTL.touch_ctrl1.touch_meas_num = meas_cycle; + //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + RTCCNTL.touch_ctrl2.touch_xpd_wait = 255; //wait volt stable + portEXIT_CRITICAL(&rtc_spinlock); + xSemaphoreGive(rtc_touch_mux); + return ESP_OK; +} + +esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_cycle) +{ + RTC_MODULE_CHECK(sleep_cycle != NULL, "parameter is NULL", ESP_ERR_INVALID_ARG); + RTC_MODULE_CHECK(meas_cycle != NULL, "parameter is NULL", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + *sleep_cycle = RTCCNTL.touch_ctrl1.touch_sleep_cycles; + *meas_cycle = RTCCNTL.touch_ctrl1.touch_meas_num; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_set_inactive_connect(touch_pad_conn_type_t type) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_inactive_connection = type; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_inactive_connect(touch_pad_conn_type_t *type) +{ + if(type) { + *type = RTCCNTL.touch_scan_ctrl.touch_inactive_connection; + return ESP_FAIL; + } else { + return ESP_OK; + } +} + +esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten) +{ + portENTER_CRITICAL(&rtc_spinlock); + if (refh > TOUCH_HVOLT_KEEP) { + RTCCNTL.touch_ctrl2.touch_drefh = refh; + } + if (refl > TOUCH_LVOLT_KEEP) { + RTCCNTL.touch_ctrl2.touch_drefl = refl; + } + if (atten > TOUCH_HVOLT_ATTEN_KEEP) { + RTCCNTL.touch_ctrl2.touch_drange = atten; + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten) +{ + portENTER_CRITICAL(&rtc_spinlock); + if (refh) { + *refh = RTCCNTL.touch_ctrl2.touch_drefh; + } + if (refl) { + *refl = RTCCNTL.touch_ctrl2.touch_drefl; + } + if (atten) { + *atten = RTCCNTL.touch_ctrl2.touch_drange; + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCIO.touch_pad[touch_num].tie_opt = TOUCH_PAD_TIE_OPT_LOW; + RTCIO.touch_pad[touch_num].dac = slope; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope) +{ + portENTER_CRITICAL(&rtc_spinlock); + if(slope) { + *slope = RTCIO.touch_pad[touch_num].dac; + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_io_init(touch_pad_t touch_num) +{ + RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG); + RTC_MODULE_CHECK((touch_num > TOUCH_PAD_NUM0), "touch IO error", ESP_ERR_INVALID_ARG); + gpio_num_t gpio_num = GPIO_NUM_1; + gpio_num = touch_num; + rtc_gpio_init(gpio_num); + rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED); + rtc_gpio_pulldown_dis(gpio_num); + rtc_gpio_pullup_dis(gpio_num); + return ESP_OK; +} + +esp_err_t touch_pad_wait_init_done() +{ + // TODO + return ESP_FAIL; +} + +/*touch_pad_fsm_start_vf, after set mask*/ +esp_err_t touch_pad_fsm_start(touch_fsm_mode_t mode) +{ + RTC_MODULE_CHECK((mode < TOUCH_FSM_MODE_MAX), "touch fsm mode error", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_ctrl2.touch_start_en = 0; //stop touch fsm + RTCCNTL.touch_ctrl2.touch_start_force = mode; + RTCCNTL.touch_ctrl2.touch_slp_timer_en = (mode == TOUCH_FSM_MODE_TIMER ? 1 : 0); + RTCCNTL.touch_ctrl2.touch_clkgate_en = 1; //enable touch clock for FSM. or force enable. + SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_MAX; // clear baseline + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_fsm_stop() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_ctrl2.touch_start_en = 0; //stop touch fsm + RTCCNTL.touch_ctrl2.touch_slp_timer_en = 0; + RTCCNTL.touch_ctrl2.touch_clkgate_en = 0; //enable touch clock for FSM. or force enable. + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode) +{ + if (mode) { + *mode = RTCCNTL.touch_ctrl2.touch_start_force; + } + return ESP_OK; +} + +/* + * If doing measure, the flag will be self-clear. + * After measure, the flag will be set. + */ +uint8_t touch_pad_means_is_done() +{ + return SENS.sar_touch_chn_st.touch_meas_done; +} + +/* return the current scan channel. */ +esp_err_t touch_pad_sw_start(touch_pad_t *current_scan) +{ + RTC_MODULE_CHECK((RTCCNTL.touch_ctrl2.touch_start_force == TOUCH_FSM_MODE_SW), + "touch IO error", ESP_FAIL); + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_ctrl2.touch_start_en = 0; + RTCCNTL.touch_ctrl2.touch_start_en = 1; + portEXIT_CRITICAL(&rtc_spinlock); + if(current_scan) { + *current_scan = SENS.sar_touch_status0.touch_scan_curr; + } + return ESP_OK; +} + +/* If set "TOUCH_PAD_THRESHOLD_MAX", the filter is not triger. */ +esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold) +{ + RTC_MODULE_CHECK((threshold != 0), "threshold error", ESP_ERR_INVALID_ARG); + RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG); + RTC_MODULE_CHECK((touch_num > TOUCH_PAD_NUM0), "touch0 no thresh", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + SENS.touch_thresh[touch_num-1].thresh = threshold; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold) +{ + RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG); + if (threshold) { + *threshold = SENS.touch_thresh[touch_num-1].thresh; + } + return ESP_OK; +} + +/* If set mask, the FSM timer should be stop firsty. + * Noitce: The touchpad that in scan map ,should be deinit digital function firstly. + * */ +esp_err_t touch_pad_set_group_mask(uint16_t enable_mask) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_scan_pad_map |= (enable_mask&TOUCH_PAD_BIT_MASK_MAX); + SENS.sar_touch_conf.touch_outen |= (enable_mask&TOUCH_PAD_BIT_MASK_MAX); + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_get_group_mask(uint16_t *enable_mask) +{ + portENTER_CRITICAL(&rtc_spinlock); + *enable_mask = SENS.sar_touch_conf.touch_outen \ + & RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \ + & TOUCH_PAD_BIT_MASK_MAX; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +/* If clear all mask, the FSM timer should be stop firsty. */ +esp_err_t touch_pad_clear_group_mask(uint16_t enable_mask) +{ + portENTER_CRITICAL(&rtc_spinlock); + SENS.sar_touch_conf.touch_outen &= ~(enable_mask&TOUCH_PAD_BIT_MASK_MAX); + RTCCNTL.touch_scan_ctrl.touch_scan_pad_map &= ~(enable_mask&TOUCH_PAD_BIT_MASK_MAX); + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +uint32_t IRAM_ATTR touch_pad_get_int_status() +{ + return REG_READ(RTC_CNTL_INT_ST_REG) >> (RTC_CNTL_TOUCH_DONE_INT_ST_S) & (TOUCH_PAD_INTR_MASK_ALL); +} + +/* + * The "touch_pad_active" will be change auto. + * If status bit is 1, this pad is be active, else, this pad is inactive. + */ +uint32_t IRAM_ATTR touch_pad_get_status() +{ + return (SENS.sar_touch_chn_st.touch_pad_active & TOUCH_PAD_BIT_MASK_MAX); +} +// get current scan channel. note: in interrupt and set a litter sleep time. +uint32_t IRAM_ATTR touch_pad_get_scan_curr() +{ + return (SENS.sar_touch_status0.touch_scan_curr); +} + +/* + * Normaly, Should't call this function manual. . + */ +esp_err_t IRAM_ATTR touch_pad_clear_status() +{ + portENTER_CRITICAL(&rtc_spinlock); + SENS.sar_touch_conf.touch_status_clr = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_intr_enable(touch_pad_intr_type_t type) +{ + portENTER_CRITICAL(&rtc_spinlock); + if(type == TOUCH_PAD_INTR_DONE) { + RTCCNTL.int_ena.rtc_touch_done = 1; + } else if(type == TOUCH_PAD_INTR_ACTIVE) { + RTCCNTL.int_ena.rtc_touch_active = 1; + } else if(type == TOUCH_PAD_INTR_INACTIVE) { + RTCCNTL.int_ena.rtc_touch_inactive = 1; + } else if(type == TOUCH_PAD_INTR_ALL){ + RTCCNTL.int_ena.rtc_touch_done = 1; + RTCCNTL.int_ena.rtc_touch_active = 1; + RTCCNTL.int_ena.rtc_touch_inactive = 1; + } else { + ESP_LOGE(RTC_MODULE_TAG, "no this intr type"); + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_intr_disable(touch_pad_intr_type_t type) +{ + portENTER_CRITICAL(&rtc_spinlock); + if(type == TOUCH_PAD_INTR_DONE) { + RTCCNTL.int_ena.rtc_touch_done = 0; + } else if(type == TOUCH_PAD_INTR_ACTIVE) { + RTCCNTL.int_ena.rtc_touch_active = 0; + } else if(type == TOUCH_PAD_INTR_INACTIVE) { + RTCCNTL.int_ena.rtc_touch_inactive = 0; + } else if(type == TOUCH_PAD_INTR_ALL){ + RTCCNTL.int_ena.rtc_touch_done = 0; + RTCCNTL.int_ena.rtc_touch_active = 0; + RTCCNTL.int_ena.rtc_touch_inactive = 0; + } else { + ESP_LOGE(RTC_MODULE_TAG, "no this intr type"); + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +uint32_t IRAM_ATTR touch_pad_intr_get_mask() +{ + return REG_READ(RTC_CNTL_INT_ENA_REG) >> (RTC_CNTL_TOUCH_DONE_INT_ENA_S) & (TOUCH_PAD_INTR_MASK_ALL); +} + +esp_err_t touch_pad_config(touch_pad_t touch_num) +{ + RTC_MODULE_CHECK(rtc_touch_mux != NULL, "Touch pad not initialized", ESP_FAIL); + RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG); + + touch_pad_io_init(touch_num); + touch_pad_set_cnt_mode(touch_num, TOUCH_PAD_SLOPE_7); + touch_pad_set_thresh(touch_num, TOUCH_PAD_THRESHOLD_MAX); + touch_pad_set_group_mask(BIT(touch_num)); + + return ESP_OK; +} + +esp_err_t touch_pad_init() +{ + if (rtc_touch_mux == NULL) { + rtc_touch_mux = xSemaphoreCreateMutex(); + } + if (rtc_touch_mux == NULL) { + return ESP_FAIL; + } + touch_pad_intr_disable(TOUCH_PAD_INTR_ALL); + touch_pad_clear_group_mask(TOUCH_PAD_BIT_MASK_MAX); + touch_pad_clear_status(); + touch_pad_set_meas_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT, TOUCH_PAD_MEASURE_CYCLE_DEFAULT); + // Set reference voltage for charging/discharging + touch_pad_set_voltage(TOUCH_HVOLT_2V7, TOUCH_LVOLT_0V5, TOUCH_HVOLT_ATTEN_0V5); + touch_pad_set_inactive_connect(TOUCH_PAD_CONN_GND); + return ESP_OK; +} + +esp_err_t touch_pad_deinit() +{ + RTC_MODULE_CHECK(rtc_touch_mux != NULL, "Touch pad not initialized", ESP_FAIL); + xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); + s_touch_pad_init_bit = 0x0000; + touch_pad_fsm_stop(); + touch_pad_clear_status(); + touch_pad_intr_disable(TOUCH_PAD_INTR_ALL); + xSemaphoreGive(rtc_touch_mux); + vSemaphoreDelete(rtc_touch_mux); + rtc_touch_mux = NULL; + return ESP_OK; +} + +/*raw data 的单位是时间，单位是 1/8MHz */ +IRAM_ATTR esp_err_t touch_pad_read_raw(touch_pad_t touch_num, uint32_t *raw_data) +{ + RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL); + if (raw_data) { + *raw_data = SENS.touch_meas[touch_num].meas_out; + } + return ESP_OK; +} + + +IRAM_ATTR esp_err_t touch_pad_filter_baseline_read(touch_pad_t touch_num, uint32_t *basedata) +{ + RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL); + if (basedata) { + *basedata = SENS.sar_touch_status[touch_num-1].touch_pad_baseline; + } + return ESP_OK; +} + +IRAM_ATTR esp_err_t touch_pad_read_debounce(touch_pad_t touch_num, uint32_t *debounce) +{ + RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL); + if (debounce) { + *debounce = SENS.sar_touch_status[touch_num-1].touch_pad_debounce; + } + return ESP_OK; +} + +IRAM_ATTR esp_err_t touch_pad_read_thresh(touch_pad_t touch_num, uint32_t *thresh_out) +{ + RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL); + if (thresh_out) { + *thresh_out = SENS.touch_thresh[touch_num-1].thresh; + } + return ESP_OK; +} + +/* Should be call after clk enable and filter enable. */ +esp_err_t touch_pad_filter_baseline_reset(touch_pad_t touch_num) +{ + RTC_MODULE_CHECK(touch_num <= TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG); + portENTER_CRITICAL(&rtc_spinlock); + if(touch_num == TOUCH_PAD_MAX) { + SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_MAX; + } else { + SENS.sar_touch_chn_st.touch_channel_clr = BIT(touch_num); + } + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_filter_set_config(touch_filter_config_t filter_info) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_filter_ctrl.touch_filter_mode = filter_info.mode; + RTCCNTL.touch_filter_ctrl.touch_debounce = filter_info.debounce_cnt; + RTCCNTL.touch_filter_ctrl.touch_hysteresis = filter_info.hysteresis_thr; + RTCCNTL.touch_filter_ctrl.touch_noise_thres = filter_info.noise_thr; + RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres = filter_info.noise_neg_thr; + RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit = filter_info.neg_noise_limit; + RTCCNTL.touch_filter_ctrl.touch_jitter_step = filter_info.jitter_step; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info) +{ + portENTER_CRITICAL(&rtc_spinlock); + filter_info->mode = RTCCNTL.touch_filter_ctrl.touch_filter_mode; + filter_info->debounce_cnt = RTCCNTL.touch_filter_ctrl.touch_debounce; + filter_info->hysteresis_thr = RTCCNTL.touch_filter_ctrl.touch_hysteresis; + filter_info->noise_thr = RTCCNTL.touch_filter_ctrl.touch_noise_thres; + filter_info->noise_neg_thr = RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_filter_start() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_filter_ctrl.touch_filter_en = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_filter_stop() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_filter_ctrl.touch_filter_en = 0; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_denoise_enable() +{ + touch_pad_clear_group_mask(BIT(TOUCH_PAD_NUM0)); + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_denoise_en = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_denoise_disable() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_denoise_set_config(touch_pad_denoise_t denoise) +{ + touch_pad_set_cnt_mode(TOUCH_PAD_NUM0, TOUCH_PAD_SLOPE_7); + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_ctrl2.touch_refc = denoise.cap_level; + RTCCNTL.touch_scan_ctrl.touch_denoise_res = denoise.grade; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise) +{ + if(denoise) { + denoise->grade = RTCCNTL.touch_scan_ctrl.touch_denoise_res; + denoise->cap_level = RTCCNTL.touch_ctrl2.touch_refc; + return ESP_OK; + } else { + return ESP_FAIL; + } +} + +esp_err_t touch_pad_denoise_data_get(uint32_t *data) +{ + *data = SENS.sar_touch_status0.touch_denoise_data; + return ESP_OK; +} + +/* + * waterproof function include two setting part: 'shield pad driver' and 'guard ring pad num' + * @note waterproof and touch function are mutually exclusive. if config touch14, dont use shield. + * @note self-calibration is implemented in hardware. + * @note touch_out_ring point to touch0, can disable the guatd ring function ? + * @note "touch_bufdrv" should user config ? + */ +esp_err_t touch_pad_waterproof_set_config(touch_pad_waterproof_t waterproof) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_out_ring = waterproof.guard_ring_pad; + RTCCNTL.touch_scan_ctrl.touch_bufdrv = waterproof.shield_driver; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof) +{ + if(waterproof) { + waterproof->guard_ring_pad = RTCCNTL.touch_scan_ctrl.touch_out_ring; + waterproof->shield_driver = RTCCNTL.touch_scan_ctrl.touch_bufdrv; + return ESP_OK; + } else { + return ESP_FAIL; + } +} + +esp_err_t touch_pad_waterproof_enable() +{ + touch_pad_clear_group_mask(BIT(TOUCH_PAD_NUM14)); + touch_pad_io_init(TOUCH_PAD_NUM14); + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_waterproof_disable() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 0; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +/* + * @note approach pad can set three pin. + * @note if clear the approach pad, point this pad to touch0 and then reset this channel baseline. + * @note the approach thresh is abs value. + * @note TODO: add channel reset reg. + */ +esp_err_t touch_pad_approach_set_config(touch_pad_approach_t approach) +{ + portENTER_CRITICAL(&rtc_spinlock); + if(approach.select_pad0) { + SENS.sar_touch_conf.touch_approach_pad0 = approach.select_pad0; + } + if(approach.select_pad1) { + SENS.sar_touch_conf.touch_approach_pad1 = approach.select_pad1; + } + if(approach.select_pad2) { + SENS.sar_touch_conf.touch_approach_pad2 = approach.select_pad2; + } + RTCCNTL.touch_approach.touch_approach_meas_time = approach.means_num; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +esp_err_t touch_pad_approach_get_config(touch_pad_approach_t *approach) +{ + if(approach) { + approach->select_pad0 = SENS.sar_touch_conf.touch_approach_pad0; + approach->select_pad1 = SENS.sar_touch_conf.touch_approach_pad1; + approach->select_pad2 = SENS.sar_touch_conf.touch_approach_pad2; + approach->means_num = RTCCNTL.touch_approach.touch_approach_meas_time; + return ESP_OK; + } else { + return ESP_FAIL; + } +} + +uint32_t touch_pad_approach_get_cnt(uint8_t pad) +{ + uint32_t cnt = 0; + if(pad == 0){ + cnt = SENS.sar_touch_status16.touch_approach_pad0_cnt; + } else if(pad == 1) { + cnt = SENS.sar_touch_status16.touch_approach_pad1_cnt; + } else if(pad == 2) { + cnt = SENS.sar_touch_status16.touch_approach_pad2_cnt; + } else if(pad == 3) { + cnt = SENS.sar_touch_status16.touch_slp_approach_cnt; + } + return cnt; +} + +/* TODO */ +esp_err_t touch_pad_approach_disable() +{ + portENTER_CRITICAL(&rtc_spinlock); + SENS.sar_touch_conf.touch_approach_pad0 = 0; + SENS.sar_touch_conf.touch_approach_pad1 = 0; + SENS.sar_touch_conf.touch_approach_pad2 = 0; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +/* After touch_clkgate_en = 0, reset the whole of touch module. */ +esp_err_t touch_pad_reset() +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_ctrl2.touch_reset = 0; + RTCCNTL.touch_ctrl2.touch_reset = 1; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +/************** sleep pad setting ***********************/ + +esp_err_t touch_pad_sleep_pad_config(touch_pad_t pad, uint32_t sleep_thr, uint8_t is_approach) +{ + portENTER_CRITICAL(&rtc_spinlock); + RTCCNTL.touch_slp_thres.touch_slp_pad = pad; + RTCCNTL.touch_slp_thres.touch_slp_th = sleep_thr; + RTCCNTL.touch_slp_thres.touch_slp_approach_en = is_approach?1:0; + portEXIT_CRITICAL(&rtc_spinlock); + return ESP_OK; +} + +/** + * Get sleep touch pad baseline data. + * + * @param baseline + */ +void touch_sleep_baseline_get(uint32_t *baseline) +{ + *baseline = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_BASELINE); +} + +/** + * Get sleep touch pad debounce data. + * + * @param debounce + */ +void touch_sleep_debounce_get(uint32_t *debounce) +{ + *debounce = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_DEBOUNCE); +} + +/** + * Get sleep touch pad approach cnt data. + * + * @param approach_cnt + */ +void touch_sleep_approach_cnt_get(uint32_t *approach_cnt) +{ + *approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS16_REG, SENS_TOUCH_SLP_APPROACH_CNT); +} + +esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num) +{ + uint32_t touch_mask = SENS.sar_touch_chn_st.touch_pad_active; + *pad_num = __builtin_ffs(touch_mask) - 1; + return ESP_OK; +} + +#endif \ No newline at end of file diff --git a/components/esp32s2beta/sleep_modes.c b/components/esp32s2beta/sleep_modes.c index 7bc6835f60..c5e5181fd4 100644 --- a/components/esp32s2beta/sleep_modes.c +++ b/components/esp32s2beta/sleep_modes.c @@ -406,7 +406,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status() if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) { return TOUCH_PAD_MAX; } - uint32_t touch_mask = REG_GET_FIELD(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN); + uint32_t touch_mask = REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_MEAS_NUM); assert(touch_mask != 0 && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero"); return (touch_pad_t) (__builtin_ffs(touch_mask) - 1); } diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h index 54bf7764e3..bdf0d5bbc8 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h @@ -336,7 +336,7 @@ extern "C" { #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ /*description: CK8M wait cycles in slow_clk_rtc*/ #define RTC_CNTL_CK8M_WAIT 0x000000FF @@ -1451,7 +1451,7 @@ extern "C" { #define RTC_CNTL_DBG_ATTEN_V 0xF #define RTC_CNTL_DBG_ATTEN_S 22 /* reserved for driver to check */ -#define RTC_CNTL_DBG_ATTEN_DEFAULT 3 +#define RTC_CNTL_DBG_ATTEN_DEFAULT 15 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h index 44ce111137..03f2ec0f58 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -64,37 +64,34 @@ typedef volatile struct { } slp_timer1; union { struct { - uint32_t reserved0: 30; + uint32_t reserved0: 27; + uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ uint32_t valid: 1; /*To indicate the register is updated*/ uint32_t update: 1; /*Set 1: to update register with RTC timer*/ }; uint32_t val; } time_update; - uint32_t time0; /*RTC timer low 32 bits*/ + uint32_t time_low0; /*RTC timer low 32 bits*/ union { struct { - uint32_t time_hi: 16; /*RTC timer high 16 bits*/ - uint32_t reserved16: 16; + uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; }; uint32_t val; - } time1; + } time_high0; union { struct { - uint32_t reserved0: 18; - uint32_t cocpu_wakeup: 1; /*riscV cocpu wake up register*/ - uint32_t cocpu_wakeup_force_en: 1; /*riscV cocpu force wake up*/ - uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ - uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ - uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ - uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ - uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ - uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/ - uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/ - uint32_t reserved27: 1; - uint32_t sdio_active_ind: 1; /*SDIO active indication*/ - uint32_t slp_wakeup: 1; /*leep wakeup bit*/ - uint32_t slp_reject: 1; /*leep reject bit*/ - uint32_t sleep_en: 1; /*sleep enable bit*/ + uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2: 20; + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ + uint32_t reserved23: 5; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*leep wakeup bit*/ + uint32_t slp_reject: 1; /*leep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ }; uint32_t val; } state0; @@ -136,10 +133,10 @@ typedef volatile struct { } timer4; union { struct { - uint32_t ulp_cp_subtimer_prediv: 8; - uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ - uint32_t rtcmem_wait_timer: 9; - uint32_t rtcmem_powerup_timer: 7; + uint32_t reserved0: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; }; uint32_t val; } timer5; @@ -153,9 +150,7 @@ typedef volatile struct { } timer6; union { struct { - uint32_t reserved0: 19; - uint32_t pkdet_cal_force_en: 2; /*pkdet force option*/ - uint32_t pwdet_cal_force_en: 2; /*pwdet force option*/ + uint32_t reserved0: 23; uint32_t plla_force_pd: 1; /*PLLA force power down*/ uint32_t plla_force_pu: 1; /*PLLA force power up*/ uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ @@ -180,95 +175,130 @@ typedef volatile struct { } reset_state; union { struct { - uint32_t wakeup_cause: 12; /*wakeup cause*/ - uint32_t rtc_wakeup_ena: 12; /*wakeup enable bitmap*/ + uint32_t wakeup_cause: 15; /*wakeup cause*/ + uint32_t rtc_wakeup_ena: 15; /*wakeup enable bitmap*/ uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ - uint32_t reserved25: 7; + uint32_t reserved31: 1; }; uint32_t val; } wakeup_state; union { struct { - uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ - uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch: 1; /*enable touch interrupt*/ - uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens: 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/ - uint32_t reserved13: 19; + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_cocpu_trap: 1; + uint32_t reserved18: 14; }; uint32_t val; } int_ena; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ - uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ - uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ - uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ - uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ - uint32_t rtc_touch: 1; /*touch interrupt raw*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ - uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/ - uint32_t rtc_tsens: 1; /*tsens interrupt raw*/ - uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/ - uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/ - uint32_t reserved13: 19; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch_done: 1; /*touch interrupt raw*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/ + uint32_t rtc_tsens: 1; /*tsens interrupt raw*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/ + uint32_t reserved18: 14; }; uint32_t val; } int_raw; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*sleep reject interrupt state*/ - uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ - uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ - uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ - uint32_t rtc_touch: 1; /*touch interrupt state*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ - uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/ - uint32_t rtc_tsens: 1; /*tsens interrupt state*/ - uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/ - uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/ - uint32_t reserved13: 19; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/ + uint32_t reserved18: 14; }; uint32_t val; } int_st; union { struct { - uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ - uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ - uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ - uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ - uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ - uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ - uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/ - uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/ - uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/ - uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/ - uint32_t reserved13: 19; + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/ + uint32_t reserved18: 14; }; uint32_t val; } int_clr; uint32_t store[4]; /**/ union { struct { - uint32_t reserved0: 30; - uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ - uint32_t ctr_en: 1; + uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k: 6; /*DAC_XTAL_32K*/ + uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/ + uint32_t reserved24: 6; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ + uint32_t ctr_en: 1; }; uint32_t val; } ext_xtl_conf; @@ -282,12 +312,10 @@ typedef volatile struct { } ext_wakeup_conf; union { struct { - uint32_t reserved0: 24; - uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ - uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ - uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ - uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ - uint32_t reject_cause: 4; + uint32_t reject_cause: 15; /*sleep reject cause*/ + uint32_t rtc_sleep_reject_ena:15; /*sleep reject enable*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ }; uint32_t val; } slp_reject_conf; @@ -331,12 +359,7 @@ typedef volatile struct { } clk_conf; union { struct { - uint32_t reserved0: 14; - uint32_t dbias_xtal_32k: 2; /*DBIAS_XTAL_32K*/ - uint32_t dres_xtal_32k: 2; /*DRES_XTAL_32K*/ - uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ - uint32_t dac_xtal_32k: 2; /*DAC_XTAL_32K*/ - uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/ + uint32_t reserved0: 22; uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set vld to actually switch the clk*/ uint32_t rtc_ana_clk_div: 8; uint32_t slow_clk_next_edge: 1; @@ -345,22 +368,30 @@ typedef volatile struct { } slow_clk_conf; union { struct { - uint32_t reserved0: 21; - uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ - uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ - uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ - uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ - uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t xpd_sdio: 1; + uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8: 1; + uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us.*/ + uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k*/ + uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim: 1; /*select current limit mode*/ + uint32_t sdio_encurlim: 1; /*enable current limit*/ + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; }; uint32_t val; } sdio_conf; union { struct { - uint32_t reserved0: 24; - uint32_t dbg_atten: 2; /*DBG_ATTEN*/ + uint32_t reserved0: 22; + uint32_t dbg_atten: 4; /*DBG_ATTEN*/ uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ @@ -408,14 +439,8 @@ typedef volatile struct { uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/ uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/ uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/ - uint32_t rtc_pad_autohold: 1; /*read only register to indicate rtc pad auto-hold status*/ - uint32_t clr_rtc_pad_autohold: 1; /*wtite only register to clear rtc pad auto-hold*/ - uint32_t rtc_pad_autohold_en: 1; /*rtc pad enable auto-hold*/ - uint32_t rtc_pad_force_noiso: 1; /*rtc pad force no ISO*/ - uint32_t rtc_pad_force_iso: 1; /*rtc pad force ISO*/ - uint32_t rtc_pad_force_unhold: 1; /*rtc pad force un-hold*/ uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ - uint32_t reserved28: 4; + uint32_t reserved22: 10; }; uint32_t val; } rtc_pwc; @@ -487,15 +512,14 @@ typedef volatile struct { } dig_iso; union { struct { - uint32_t reserved0: 7; + uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ uint32_t sys_reset_length: 3; /*system reset counter length*/ uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ - uint32_t level_int_en: 1; /*N/A*/ - uint32_t edge_int_en: 1; /*N/A*/ uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ @@ -518,7 +542,22 @@ typedef volatile struct { uint32_t wdt_wprotect; /**/ union { struct { - uint32_t reserved0: 29; + uint32_t swd_reset_flag: 1; /*swd reset flag*/ + uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ + uint32_t reserved2: 16; + uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ + uint32_t swd_feed: 1; /*Sw feed swd*/ + uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ + }; + uint32_t val; + } swd_conf; + uint32_t swd_wprotect; /*swd write protect*/ + union { + struct { + uint32_t reserved0: 28; + uint32_t ent_tsens: 1; /*ENT_TSENS*/ uint32_t ent_rtc: 1; /*ENT_RTC*/ uint32_t dtest_rtc: 2; }; @@ -547,14 +586,14 @@ typedef volatile struct { uint32_t xpd_wifi: 1; /*wifi wrap power down*/ uint32_t dig_iso: 1; /*digital wrap iso*/ uint32_t xpd_dig: 1; /*digital wrap power down*/ - uint32_t rtc_touch_start: 1; /*touch should start to work*/ + uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ - uint32_t rtc_touch_slp: 1; /*touch is in sleep state*/ - uint32_t rtc_touch_done: 1; /*touch is done*/ - uint32_t rtc_cocpu_start: 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done: 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ - uint32_t rtc_cocpu_slp: 1; /*ulp/cocpu is in sleep state*/ - uint32_t rtc_cocpu_done: 1; /*ulp/cocpu is done*/ + uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ @@ -573,62 +612,216 @@ typedef volatile struct { uint32_t diag0; /**/ union { struct { - uint32_t adc1_hold_force: 1; - uint32_t adc2_hold_force: 1; - uint32_t pdac1_hold_force: 1; - uint32_t pdac2_hold_force: 1; - uint32_t sense1_hold_force: 1; - uint32_t sense2_hold_force: 1; - uint32_t sense3_hold_force: 1; - uint32_t sense4_hold_force: 1; - uint32_t touch_pad0_hold_force: 1; - uint32_t touch_pad1_hold_force: 1; - uint32_t touch_pad2_hold_force: 1; - uint32_t touch_pad3_hold_force: 1; - uint32_t touch_pad4_hold_force: 1; - uint32_t touch_pad5_hold_force: 1; - uint32_t touch_pad6_hold_force: 1; - uint32_t touch_pad7_hold_force: 1; - uint32_t x32p_hold_force: 1; - uint32_t x32n_hold_force: 1; - uint32_t reserved18: 14; + uint32_t touch_pad0_hold: 1; + uint32_t touch_pad1_hold: 1; + uint32_t touch_pad2_hold: 1; + uint32_t touch_pad3_hold: 1; + uint32_t touch_pad4_hold: 1; + uint32_t touch_pad5_hold: 1; + uint32_t touch_pad6_hold: 1; + uint32_t touch_pad7_hold: 1; + uint32_t touch_pad8_hold: 1; + uint32_t touch_pad9_hold: 1; + uint32_t touch_pad10_hold: 1; + uint32_t touch_pad11_hold: 1; + uint32_t touch_pad12_hold: 1; + uint32_t touch_pad13_hold: 1; + uint32_t touch_pad14_hold: 1; + uint32_t x32p_hold: 1; + uint32_t x32n_hold: 1; + uint32_t pdac1_hold: 1; + uint32_t pdac2_hold: 1; + uint32_t rtc_pad19_hold: 1; + uint32_t rtc_pad20_hold: 1; + uint32_t rtc_pad21_hold: 1; + uint32_t reserved22: 10; }; uint32_t val; - } hold_force; + } pad_hold; uint32_t dig_pad_hold; /**/ union { struct { - uint32_t sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/ uint32_t status_clr: 1; /*clear ext wakeup1 status*/ - uint32_t reserved19: 13; + uint32_t reserved23: 9; }; uint32_t val; } ext_wakeup1; union { struct { - uint32_t status: 18; /*ext wakeup1 status*/ - uint32_t reserved18: 14; + uint32_t status: 22; /*ext wakeup1 status*/ + uint32_t reserved22: 10; }; uint32_t val; } ext_wakeup1_status; union { struct { - uint32_t reserved0: 14; + uint32_t reserved0: 4; + uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ uint32_t rst_wait: 10; /*brown out reset wait cycles*/ uint32_t rst_ena: 1; /*enable brown out reset*/ - uint32_t thres: 3; /*brown out threshold*/ + uint32_t reserved27: 2; + uint32_t cnt_clr: 1; /*clear brown out counter*/ uint32_t ena: 1; /*enable brown out*/ uint32_t det: 1; }; uint32_t val; } brown_out; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; + uint32_t time_low1; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time_high1; + uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ + union { + struct { + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time 32k is regarded as dead*/ + uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this it is regarded as stable*/ + }; + uint32_t val; + } xtal32k_conf; + union { + struct { + uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/ + uint32_t reserved11: 1; + uint32_t ulp_cp_timer_slp_cycle:16; /*sleep cycles for ULP-coprocessor timer*/ + uint32_t reserved28: 1; + uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/ + uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + }; + uint32_t val; + } ulp_cp_timer; + union { + struct { + uint32_t ulp_cp_mem_addr_init: 11; + uint32_t ulp_cp_mem_addr_size: 11; + uint32_t ulp_cp_mem_offst_clr: 1; + uint32_t reserved23: 5; + uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/ + uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/ + uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/ + uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/ + }; + uint32_t val; + } ulp_cp_ctrl; + union { + struct { + uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/ + uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/ + uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/ + uint32_t cocpu_shut: 1; /*to shut cocpu*/ + uint32_t cocpu_shut_2_clk_dis: 6; /*time from shut cocpu to disable clk*/ + uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/ + uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/ + uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/ + uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/ + uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } cocpu_ctrl; + union { + struct { + uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/ + uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/ + }; + uint32_t val; + } touch_ctrl1; + union { + struct { + uint32_t reserved0: 2; + uint32_t touch_drange: 2; /*TOUCH_DRANGE*/ + uint32_t touch_drefl: 2; /*TOUCH_DREFL*/ + uint32_t touch_drefh: 2; /*TOUCH_DREFH*/ + uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/ + uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/ + uint32_t reserved12: 1; + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ + uint32_t touch_start_en: 1; /*1: start touch fsm*/ + uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/ + uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ + uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active sleep cycle could be divided by this number*/ + uint32_t reserved27: 2; + uint32_t touch_reset: 1; /*reset upgrade touch*/ + uint32_t touch_clk_fo: 1; /*touch clock force on*/ + uint32_t touch_clkgate_en: 1; /*touch clock enable*/ + }; + uint32_t val; + } touch_ctrl2; + union { + struct { + uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/ + uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/ + uint32_t reserved3: 5; + uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ + uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/ + uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/ + uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/ + uint32_t touch_out_ring: 4; /*select out ring pad*/ + }; + uint32_t val; + } touch_scan_ctrl; + union { + struct { + uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/ + uint32_t reserved22: 4; + uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/ + uint32_t touch_slp_pad: 5; + }; + uint32_t val; + } touch_slp_thres; + union { + struct { + uint32_t reserved0: 23; + uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/ + uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/ + }; + uint32_t val; + } touch_approach; + union { + struct { + uint32_t reserved0: 12; + uint32_t touch_jitter_step: 4; /*touch jitter step*/ + uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/ + uint32_t touch_neg_noise_thres: 2; + uint32_t touch_noise_thres: 2; + uint32_t touch_hysteresis: 2; + uint32_t touch_debounce: 3; /*debounce counter*/ + uint32_t touch_filter_mode: 2; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ + uint32_t touch_filter_en: 1; /*touch filter enable*/ + }; + uint32_t val; + } touch_filter_ctrl; + union { + struct { + uint32_t usb_vrefh: 2; + uint32_t usb_vrefl: 2; + uint32_t usb_vref_override: 1; + uint32_t usb_pad_pull_override: 1; + uint32_t usb_dp_pullup: 1; + uint32_t usb_dp_pulldown: 1; + uint32_t usb_dm_pullup: 1; + uint32_t usb_dm_pulldown: 1; + uint32_t usb_pullup_value: 1; + uint32_t usb_pad_enable_override: 1; + uint32_t usb_pad_enable: 1; + uint32_t usb_txm: 1; + uint32_t usb_txp: 1; + uint32_t usb_tx_en: 1; + uint32_t usb_tx_en_override: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } usb_conf; union { struct { uint32_t date: 28; diff --git a/components/soc/esp32s2beta/include/soc/sens_reg.h b/components/soc/esp32s2beta/include/soc/sens_reg.h index a00c59c9a7..13c454ae08 100644 --- a/components/soc/esp32s2beta/include/soc/sens_reg.h +++ b/components/soc/esp32s2beta/include/soc/sens_reg.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -19,19 +19,19 @@ extern "C" { #endif #include "soc.h" -#define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0000) +#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000) +/* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: enable saradc1 to send out interrupt*/ +#define SENS_SAR1_INT_EN (BIT(29)) +#define SENS_SAR1_INT_EN_M (BIT(29)) +#define SENS_SAR1_INT_EN_V 0x1 +#define SENS_SAR1_INT_EN_S 29 /* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ /*description: Invert SAR ADC1 data*/ #define SENS_SAR1_DATA_INV (BIT(28)) #define SENS_SAR1_DATA_INV_M (BIT(28)) #define SENS_SAR1_DATA_INV_V 0x1 #define SENS_SAR1_DATA_INV_S 28 -/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/ -#define SENS_SAR1_DIG_FORCE (BIT(27)) -#define SENS_SAR1_DIG_FORCE_M (BIT(27)) -#define SENS_SAR1_DIG_FORCE_V 0x1 -#define SENS_SAR1_DIG_FORCE_S 27 /* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ /*description: */ #define SENS_SAR1_SAMPLE_NUM 0x000000FF @@ -45,8 +45,7 @@ extern "C" { #define SENS_SAR1_CLK_GATED_V 0x1 #define SENS_SAR1_CLK_GATED_S 18 /* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ -/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width - 11: for 12-bit width*/ +/*description: 00: for 9-bit width*/ #define SENS_SAR1_SAMPLE_BIT 0x00000003 #define SENS_SAR1_SAMPLE_BIT_M ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S)) #define SENS_SAR1_SAMPLE_BIT_V 0x3 @@ -64,7 +63,7 @@ extern "C" { #define SENS_SAR1_CLK_DIV_V 0xFF #define SENS_SAR1_CLK_DIV_S 0 -#define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x0004) +#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004) /* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SENS_SAR1_READER_STATUS 0xFFFFFFFF @@ -72,457 +71,65 @@ extern "C" { #define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF #define SENS_SAR1_READER_STATUS_S 0 -#define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x0008) -/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008) +/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ /*description: */ -#define SENS_SAR_AMP_WAIT2 0x0000FFFF -#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) -#define SENS_SAR_AMP_WAIT2_V 0xFFFF -#define SENS_SAR_AMP_WAIT2_S 16 -/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 +/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ /*description: */ -#define SENS_SAR_AMP_WAIT1 0x0000FFFF -#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) -#define SENS_SAR_AMP_WAIT1_V 0xFFFF -#define SENS_SAR_AMP_WAIT1_S 0 - -#define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0x000c) -/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */ +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) +#define SENS_AMP_SHORT_REF_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_FORCE_S 28 +/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ /*description: */ -#define SENS_SAR2_RSTB_WAIT 0x000000FF -#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) -#define SENS_SAR2_RSTB_WAIT_V 0xFF -#define SENS_SAR2_RSTB_WAIT_S 20 -/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define SENS_FORCE_XPD_SAR 0x00000003 -#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) -#define SENS_FORCE_XPD_SAR_V 0x3 -#define SENS_FORCE_XPD_SAR_S 18 -/* reserved for driver to check */ -#define SENS_FORCE_XPD_SAR_SW_M (BIT1) -#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down -#define SENS_FORCE_XPD_SAR_PD 2 // Force power down -#define SENS_FORCE_XPD_SAR_PU 3 // Force power up -/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) +#define SENS_AMP_RST_FB_FORCE_V 0x3 +#define SENS_AMP_RST_FB_FORCE_S 26 +/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ /*description: */ #define SENS_FORCE_XPD_AMP 0x00000003 #define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) #define SENS_FORCE_XPD_AMP_V 0x3 -#define SENS_FORCE_XPD_AMP_S 16 -#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down -#define SENS_FORCE_XPD_AMP_PD 2 // Force power down -#define SENS_FORCE_XPD_AMP_PU 3 // Force power up -/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT3 0x0000FFFF -#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) -#define SENS_SAR_AMP_WAIT3_V 0xFFFF -#define SENS_SAR_AMP_WAIT3_S 0 - -#define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x0010) -/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ -/*description: */ -#define SENS_SAR2_XPD_WAIT 0x000000FF -#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) -#define SENS_SAR2_XPD_WAIT_V 0xFF -#define SENS_SAR2_XPD_WAIT_S 24 -/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM 0x0000000F -#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) -#define SENS_SAR_RSTB_FSM_V 0xF -#define SENS_SAR_RSTB_FSM_S 20 -/* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM 0x0000000F -#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) -#define SENS_XPD_SAR_FSM_V 0xF -#define SENS_XPD_SAR_FSM_S 16 -/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) -#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF -#define SENS_AMP_SHORT_REF_GND_FSM_S 12 -/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) -#define SENS_AMP_SHORT_REF_FSM_V 0xF -#define SENS_AMP_SHORT_REF_FSM_S 8 -/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM 0x0000000F -#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) -#define SENS_AMP_RST_FB_FSM_V 0xF -#define SENS_AMP_RST_FB_FSM_S 4 -/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM 0x0000000F -#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) -#define SENS_XPD_SAR_AMP_FSM_V 0xF -#define SENS_XPD_SAR_AMP_FSM_S 0 - -#define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x0014) -/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR2_READER_STATUS 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) -#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_S 0 - -#define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x0018) -/* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer*/ -#define SENS_SLEEP_CYCLES_S0 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S0_M ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S)) -#define SENS_SLEEP_CYCLES_S0_V 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S0_S 0 - -#define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x001c) -/* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */ -/*description: */ -#define SENS_SLEEP_CYCLES_S1 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S1_M ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S)) -#define SENS_SLEEP_CYCLES_S1_V 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S1_S 0 - -#define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x0020) -/* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */ -/*description: */ -#define SENS_SLEEP_CYCLES_S2 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S2_M ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S)) -#define SENS_SLEEP_CYCLES_S2_V 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S2_S 0 - -#define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x0024) -/* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */ -/*description: */ -#define SENS_SLEEP_CYCLES_S3 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S3_M ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S)) -#define SENS_SLEEP_CYCLES_S3_V 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S3_S 0 - -#define SENS_ULP_CP_SLEEP_CYC4_REG (DR_REG_SENS_BASE + 0x0028) -/* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */ -/*description: */ -#define SENS_SLEEP_CYCLES_S4 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S4_M ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S)) -#define SENS_SLEEP_CYCLES_S4_V 0xFFFFFFFF -#define SENS_SLEEP_CYCLES_S4_S 0 - -#define SENS_SAR_START_FORCE_REG (DR_REG_SENS_BASE + 0x002c) -/* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: N/A*/ -#define SENS_SAR2_PWDET_EN (BIT(24)) -#define SENS_SAR2_PWDET_EN_M (BIT(24)) -#define SENS_SAR2_PWDET_EN_V 0x1 -#define SENS_SAR2_PWDET_EN_S 24 -/* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */ +#define SENS_FORCE_XPD_AMP_S 24 +/* SENS_SAR1_STOP : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: stop SAR ADC1 conversion*/ -#define SENS_SAR1_STOP (BIT(23)) -#define SENS_SAR1_STOP_M (BIT(23)) +#define SENS_SAR1_STOP (BIT(2)) +#define SENS_SAR1_STOP_M (BIT(2)) #define SENS_SAR1_STOP_V 0x1 -#define SENS_SAR1_STOP_S 23 -/* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: stop SAR ADC2 conversion*/ -#define SENS_SAR2_STOP (BIT(22)) -#define SENS_SAR2_STOP_M (BIT(22)) -#define SENS_SAR2_STOP_V 0x1 -#define SENS_SAR2_STOP_S 22 -/* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */ -/*description: initialized PC for ULP-coprocessor*/ -#define SENS_PC_INIT 0x000007FF -#define SENS_PC_INIT_M ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S)) -#define SENS_PC_INIT_V 0x7FF -#define SENS_PC_INIT_S 11 -/* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SARCLK_EN (BIT(10)) -#define SENS_SARCLK_EN_M (BIT(10)) -#define SENS_SARCLK_EN_V 0x1 -#define SENS_SARCLK_EN_S 10 -/* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top - = 1*/ -#define SENS_ULP_CP_START_TOP (BIT(9)) -#define SENS_ULP_CP_START_TOP_M (BIT(9)) -#define SENS_ULP_CP_START_TOP_V 0x1 -#define SENS_ULP_CP_START_TOP_S 9 -/* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/ -#define SENS_ULP_CP_FORCE_START_TOP (BIT(8)) -#define SENS_ULP_CP_FORCE_START_TOP_M (BIT(8)) -#define SENS_ULP_CP_FORCE_START_TOP_V 0x1 -#define SENS_ULP_CP_FORCE_START_TOP_S 8 -/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ -/*description: SAR2_PWDET_CCT PA power detector capacitance tuning.*/ -#define SENS_SAR2_PWDET_CCT 0x00000007 -#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) -#define SENS_SAR2_PWDET_CCT_V 0x7 -#define SENS_SAR2_PWDET_CCT_S 5 -/* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/ -#define SENS_SAR2_EN_TEST (BIT(4)) -#define SENS_SAR2_EN_TEST_M (BIT(4)) -#define SENS_SAR2_EN_TEST_V 0x1 -#define SENS_SAR2_EN_TEST_S 4 -/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ -/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ -#define SENS_SAR2_BIT_WIDTH 0x00000003 -#define SENS_SAR2_BIT_WIDTH_M ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S)) -#define SENS_SAR2_BIT_WIDTH_V 0x3 -#define SENS_SAR2_BIT_WIDTH_S 2 +#define SENS_SAR1_STOP_S 2 /* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ -/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ +/*description: 00: 9 bit*/ #define SENS_SAR1_BIT_WIDTH 0x00000003 #define SENS_SAR1_BIT_WIDTH_M ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S)) #define SENS_SAR1_BIT_WIDTH_V 0x3 #define SENS_SAR1_BIT_WIDTH_S 0 -#define SENS_SAR_MEM_WR_CTRL_REG (DR_REG_SENS_BASE + 0x0030) -/* SENS_ULP_CP_CLK_FO : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk force on*/ -#define SENS_ULP_CP_CLK_FO (BIT(23)) -#define SENS_ULP_CP_CLK_FO_M (BIT(23)) -#define SENS_ULP_CP_CLK_FO_V 0x1 -#define SENS_ULP_CP_CLK_FO_S 23 -/* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define SENS_RTC_MEM_WR_OFFST_CLR (BIT(22)) -#define SENS_RTC_MEM_WR_OFFST_CLR_M (BIT(22)) -#define SENS_RTC_MEM_WR_OFFST_CLR_V 0x1 -#define SENS_RTC_MEM_WR_OFFST_CLR_S 22 -/* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ -/*description: */ -#define SENS_MEM_WR_ADDR_SIZE 0x000007FF -#define SENS_MEM_WR_ADDR_SIZE_M ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S)) -#define SENS_MEM_WR_ADDR_SIZE_V 0x7FF -#define SENS_MEM_WR_ADDR_SIZE_S 11 -/* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ -/*description: */ -#define SENS_MEM_WR_ADDR_INIT 0x000007FF -#define SENS_MEM_WR_ADDR_INIT_M ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S)) -#define SENS_MEM_WR_ADDR_INIT_V 0x7FF -#define SENS_MEM_WR_ADDR_INIT_S 0 - -#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0034) -/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ -#define SENS_SAR1_ATTEN 0xFFFFFFFF -#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) -#define SENS_SAR1_ATTEN_V 0xFFFFFFFF -#define SENS_SAR1_ATTEN_S 0 -#define SENS_SAR1_ATTEN_VAL_MASK 0x3 -#define SENS_SAR2_ATTEN_VAL_MASK 0x3 - -#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) -/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ -#define SENS_SAR2_ATTEN 0xFFFFFFFF -#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) -#define SENS_SAR2_ATTEN_V 0xFFFFFFFF -#define SENS_SAR2_ATTEN_S 0 - -#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x003c) -/* SENS_SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ -/*description: */ -#define SENS_SARADC_MEAS_STATUS 0x000000FF -#define SENS_SARADC_MEAS_STATUS_M ((SENS_SARADC_MEAS_STATUS_V)<<(SENS_SARADC_MEAS_STATUS_S)) -#define SENS_SARADC_MEAS_STATUS_V 0xFF -#define SENS_SARADC_MEAS_STATUS_S 22 -/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR0 0x000007FF -#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) -#define SENS_I2C_SLAVE_ADDR0_V 0x7FF -#define SENS_I2C_SLAVE_ADDR0_S 11 -/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR1 0x000007FF -#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) -#define SENS_I2C_SLAVE_ADDR1_V 0x7FF -#define SENS_I2C_SLAVE_ADDR1_S 0 - -#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0040) -/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR2 0x000007FF -#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) -#define SENS_I2C_SLAVE_ADDR2_V 0x7FF -#define SENS_I2C_SLAVE_ADDR2_S 11 -/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR3 0x000007FF -#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) -#define SENS_I2C_SLAVE_ADDR3_V 0x7FF -#define SENS_I2C_SLAVE_ADDR3_S 0 - -#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0044) -/* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: indicate temperature sensor out ready*/ -#define SENS_TSENS_RDY_OUT (BIT(30)) -#define SENS_TSENS_RDY_OUT_M (BIT(30)) -#define SENS_TSENS_RDY_OUT_V 0x1 -#define SENS_TSENS_RDY_OUT_S 30 -/* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */ -/*description: temperature sensor data out*/ -#define SENS_TSENS_OUT 0x000000FF -#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) -#define SENS_TSENS_OUT_V 0xFF -#define SENS_TSENS_OUT_S 22 -/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR4 0x000007FF -#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) -#define SENS_I2C_SLAVE_ADDR4_V 0x7FF -#define SENS_I2C_SLAVE_ADDR4_S 11 -/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR5 0x000007FF -#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) -#define SENS_I2C_SLAVE_ADDR5_V 0x7FF -#define SENS_I2C_SLAVE_ADDR5_S 0 - -#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x0048) -/* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: indicate I2C done*/ -#define SENS_I2C_DONE (BIT(30)) -#define SENS_I2C_DONE_M (BIT(30)) -#define SENS_I2C_DONE_V 0x1 -#define SENS_I2C_DONE_S 30 -/* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */ -/*description: I2C read data*/ -#define SENS_I2C_RDATA 0x000000FF -#define SENS_I2C_RDATA_M ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S)) -#define SENS_I2C_RDATA_V 0xFF -#define SENS_I2C_RDATA_S 22 -/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR6 0x000007FF -#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) -#define SENS_I2C_SLAVE_ADDR6_V 0x7FF -#define SENS_I2C_SLAVE_ADDR6_S 11 -/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR7 0x000007FF -#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) -#define SENS_I2C_SLAVE_ADDR7_V 0x7FF -#define SENS_I2C_SLAVE_ADDR7_S 0 - -#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x004c) -/* SENS_TSENS_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: select saradc_reg 0: select efuse*/ -#define SENS_TSENS_FORCE (BIT(31)) -#define SENS_TSENS_FORCE_M (BIT(31)) -#define SENS_TSENS_FORCE_V 0x1 -#define SENS_TSENS_FORCE_S 31 -/* SENS_TSENS_DOS : R/W ;bitpos:[30:27] ;default: 4'd7 ; */ -/*description: Temperature sensor calibration bits*/ -#define SENS_TSENS_DOS 0x0000000F -#define SENS_TSENS_DOS_M ((SENS_TSENS_DOS_V)<<(SENS_TSENS_DOS_S)) -#define SENS_TSENS_DOS_V 0xF -#define SENS_TSENS_DOS_S 27 -/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ -#define SENS_TSENS_DUMP_OUT (BIT(26)) -#define SENS_TSENS_DUMP_OUT_M (BIT(26)) -#define SENS_TSENS_DUMP_OUT_V 0x1 -#define SENS_TSENS_DUMP_OUT_S 26 -/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: dump out & power up controlled by SW 0: by FSM*/ -#define SENS_TSENS_POWER_UP_FORCE (BIT(25)) -#define SENS_TSENS_POWER_UP_FORCE_M (BIT(25)) -#define SENS_TSENS_POWER_UP_FORCE_V 0x1 -#define SENS_TSENS_POWER_UP_FORCE_S 25 -/* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: temperature sensor power up*/ -#define SENS_TSENS_POWER_UP (BIT(24)) -#define SENS_TSENS_POWER_UP_M (BIT(24)) -#define SENS_TSENS_POWER_UP_V 0x1 -#define SENS_TSENS_POWER_UP_S 24 -/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */ -/*description: temperature sensor clock divider*/ -#define SENS_TSENS_CLK_DIV 0x000000FF -#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) -#define SENS_TSENS_CLK_DIV_V 0xFF -#define SENS_TSENS_CLK_DIV_S 16 -/* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: invert temperature sensor data*/ -#define SENS_TSENS_IN_INV (BIT(15)) -#define SENS_TSENS_IN_INV_M (BIT(15)) -#define SENS_TSENS_IN_INV_V 0x1 -#define SENS_TSENS_IN_INV_S 15 -/* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SENS_TSENS_CLK_GATED (BIT(14)) -#define SENS_TSENS_CLK_GATED_M (BIT(14)) -#define SENS_TSENS_CLK_GATED_V 0x1 -#define SENS_TSENS_CLK_GATED_S 14 -/* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define SENS_TSENS_CLK_INV (BIT(13)) -#define SENS_TSENS_CLK_INV_M (BIT(13)) -#define SENS_TSENS_CLK_INV_V 0x1 -#define SENS_TSENS_CLK_INV_S 13 -/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TSENS_XPD_FORCE (BIT(12)) -#define SENS_TSENS_XPD_FORCE_M (BIT(12)) -#define SENS_TSENS_XPD_FORCE_V 0x1 -#define SENS_TSENS_XPD_FORCE_S 12 -/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ -/*description: */ -#define SENS_TSENS_XPD_WAIT 0x00000FFF -#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) -#define SENS_TSENS_XPD_WAIT_V 0xFFF -#define SENS_TSENS_XPD_WAIT_S 0 - -#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0050) -/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: I2C started by SW 0: I2C started by FSM*/ -#define SENS_SAR_I2C_START_FORCE (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_V 0x1 -#define SENS_SAR_I2C_START_FORCE_S 29 -/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: start I2C only active when reg_sar_i2c_start_force = 1*/ -#define SENS_SAR_I2C_START (BIT(28)) -#define SENS_SAR_I2C_START_M (BIT(28)) -#define SENS_SAR_I2C_START_V 0x1 -#define SENS_SAR_I2C_START_S 28 -/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ -/*description: I2C control data only active when reg_sar_i2c_start_force = 1*/ -#define SENS_SAR_I2C_CTRL 0x0FFFFFFF -#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) -#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF -#define SENS_SAR_I2C_CTRL_S 0 - -#define SENS_SAR_MEAS_START1_REG (DR_REG_SENS_BASE + 0x0054) +#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c) /* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 - pad enable bitmap is controlled by ULP-coprocessor*/ +/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW*/ #define SENS_SAR1_EN_PAD_FORCE (BIT(31)) #define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) #define SENS_SAR1_EN_PAD_FORCE_V 0x1 #define SENS_SAR1_EN_PAD_FORCE_S 31 /* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/ +/*description: SAR ADC1 pad enable bitmap*/ #define SENS_SAR1_EN_PAD 0x00000FFF #define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) #define SENS_SAR1_EN_PAD_V 0xFFF #define SENS_SAR1_EN_PAD_S 19 /* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 - controller is started by ULP-coprocessor*/ +/*description: 1: SAR ADC1 controller (in RTC) is started by SW*/ #define SENS_MEAS1_START_FORCE (BIT(18)) #define SENS_MEAS1_START_FORCE_M (BIT(18)) #define SENS_MEAS1_START_FORCE_V 0x1 #define SENS_MEAS1_START_FORCE_S 18 /* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC1 controller (in RTC) starts conversion only active when - reg_meas1_start_force = 1*/ +/*description: SAR ADC1 controller (in RTC) starts conversion*/ #define SENS_MEAS1_START_SAR (BIT(17)) #define SENS_MEAS1_START_SAR_M (BIT(17)) #define SENS_MEAS1_START_SAR_V 0x1 @@ -540,283 +147,143 @@ extern "C" { #define SENS_MEAS1_DATA_SAR_V 0xFFFF #define SENS_MEAS1_DATA_SAR_S 0 -#define SENS_SAR_TOUCH_CTRL1_REG (DR_REG_SENS_BASE + 0x0058) -/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled - by FSM in ULP-coprocessor*/ -#define SENS_HALL_PHASE_FORCE (BIT(27)) -#define SENS_HALL_PHASE_FORCE_M (BIT(27)) -#define SENS_HALL_PHASE_FORCE_V 0x1 -#define SENS_HALL_PHASE_FORCE_S 27 -/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by - FSM in ULP-coprocessor*/ -#define SENS_XPD_HALL_FORCE (BIT(26)) -#define SENS_XPD_HALL_FORCE_M (BIT(26)) -#define SENS_XPD_HALL_FORCE_V 0x1 -#define SENS_XPD_HALL_FORCE_S 26 -/* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: 1: wakeup interrupt is generated if SET1 is “touched” 0: - wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/ -#define SENS_TOUCH_OUT_1EN (BIT(25)) -#define SENS_TOUCH_OUT_1EN_M (BIT(25)) -#define SENS_TOUCH_OUT_1EN_V 0x1 -#define SENS_TOUCH_OUT_1EN_S 25 -/* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: when the counter is greater then the threshold the touch - pad is considered as “touched” 0: when the counter is less than the threshold the touch pad is considered as “touched”*/ -#define SENS_TOUCH_OUT_SEL (BIT(24)) -#define SENS_TOUCH_OUT_SEL_M (BIT(24)) -#define SENS_TOUCH_OUT_SEL_V 0x1 -#define SENS_TOUCH_OUT_SEL_S 24 -/* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */ -/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ -#define SENS_TOUCH_XPD_WAIT 0x000000FF -#define SENS_TOUCH_XPD_WAIT_M ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S)) -#define SENS_TOUCH_XPD_WAIT_V 0xFF -#define SENS_TOUCH_XPD_WAIT_S 16 -/* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: the meas length (in 8MHz)*/ -#define SENS_TOUCH_MEAS_DELAY 0x0000FFFF -#define SENS_TOUCH_MEAS_DELAY_M ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S)) -#define SENS_TOUCH_MEAS_DELAY_V 0xFFFF -#define SENS_TOUCH_MEAS_DELAY_S 0 +#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010) +/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL*/ +#define SENS_SAR1_DIG_FORCE (BIT(31)) +#define SENS_SAR1_DIG_FORCE_M (BIT(31)) +#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_S 31 -#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x005c) -/* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 0*/ -#define SENS_TOUCH_OUT_TH0 0x0000FFFF -#define SENS_TOUCH_OUT_TH0_M ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S)) -#define SENS_TOUCH_OUT_TH0_V 0xFFFF -#define SENS_TOUCH_OUT_TH0_S 16 -/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 1*/ -#define SENS_TOUCH_OUT_TH1 0x0000FFFF -#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) -#define SENS_TOUCH_OUT_TH1_V 0xFFFF -#define SENS_TOUCH_OUT_TH1_S 0 +#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014) +/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad*/ +#define SENS_SAR1_ATTEN 0xFFFFFFFF +#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) +#define SENS_SAR1_ATTEN_V 0xFFFFFFFF +#define SENS_SAR1_ATTEN_S 0 -#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0060) -/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 2*/ -#define SENS_TOUCH_OUT_TH2 0x0000FFFF -#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) -#define SENS_TOUCH_OUT_TH2_V 0xFFFF -#define SENS_TOUCH_OUT_TH2_S 16 -/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 3*/ -#define SENS_TOUCH_OUT_TH3 0x0000FFFF -#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) -#define SENS_TOUCH_OUT_TH3_V 0xFFFF -#define SENS_TOUCH_OUT_TH3_S 0 +#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018) +/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT2 0x0000FFFF +#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) +#define SENS_SAR_AMP_WAIT2_V 0xFFFF +#define SENS_SAR_AMP_WAIT2_S 16 +/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT1 0x0000FFFF +#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) +#define SENS_SAR_AMP_WAIT1_V 0xFFFF +#define SENS_SAR_AMP_WAIT1_S 0 -#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0064) -/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 4*/ -#define SENS_TOUCH_OUT_TH4 0x0000FFFF -#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) -#define SENS_TOUCH_OUT_TH4_V 0xFFFF -#define SENS_TOUCH_OUT_TH4_S 16 -/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 5*/ -#define SENS_TOUCH_OUT_TH5 0x0000FFFF -#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) -#define SENS_TOUCH_OUT_TH5_V 0xFFFF -#define SENS_TOUCH_OUT_TH5_S 0 +#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c) +/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT3 0x0000FFFF +#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) +#define SENS_SAR_AMP_WAIT3_V 0xFFFF +#define SENS_SAR_AMP_WAIT3_S 16 +/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 +#define SENS_SAR_RSTB_FSM_IDLE_S 6 +/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_FSM_IDLE_S 5 +/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 +/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 +/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SENS_AMP_RST_FB_FSM_IDLE_S 2 +/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 +/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 -#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x0068) -/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 6*/ -#define SENS_TOUCH_OUT_TH6 0x0000FFFF -#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) -#define SENS_TOUCH_OUT_TH6_V 0xFFFF -#define SENS_TOUCH_OUT_TH6_S 16 -/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 7*/ -#define SENS_TOUCH_OUT_TH7 0x0000FFFF -#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) -#define SENS_TOUCH_OUT_TH7_V 0xFFFF -#define SENS_TOUCH_OUT_TH7_S 0 +#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020) +/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM 0x0000000F +#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) +#define SENS_SAR_RSTB_FSM_V 0xF +#define SENS_SAR_RSTB_FSM_S 24 +/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM 0x0000000F +#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) +#define SENS_XPD_SAR_FSM_V 0xF +#define SENS_XPD_SAR_FSM_S 20 +/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF +#define SENS_AMP_SHORT_REF_GND_FSM_S 16 +/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) +#define SENS_AMP_SHORT_REF_FSM_V 0xF +#define SENS_AMP_SHORT_REF_FSM_S 12 +/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM 0x0000000F +#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) +#define SENS_AMP_RST_FB_FSM_V 0xF +#define SENS_AMP_RST_FB_FSM_S 8 +/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM 0x0000000F +#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) +#define SENS_XPD_SAR_AMP_FSM_V 0xF +#define SENS_XPD_SAR_AMP_FSM_S 4 +/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM 0x0000000F +#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) +#define SENS_SAR1_DAC_XPD_FSM_V 0xF +#define SENS_SAR1_DAC_XPD_FSM_S 0 -#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x006c) -/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 8*/ -#define SENS_TOUCH_OUT_TH8 0x0000FFFF -#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) -#define SENS_TOUCH_OUT_TH8_V 0xFFFF -#define SENS_TOUCH_OUT_TH8_S 16 -/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the threshold for touch pad 9*/ -#define SENS_TOUCH_OUT_TH9 0x0000FFFF -#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) -#define SENS_TOUCH_OUT_TH9_V 0xFFFF -#define SENS_TOUCH_OUT_TH9_S 0 - -#define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x0070) -/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the counter for touch pad 0*/ -#define SENS_TOUCH_MEAS_OUT0 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT0_M ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S)) -#define SENS_TOUCH_MEAS_OUT0_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT0_S 16 -/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the counter for touch pad 1*/ -#define SENS_TOUCH_MEAS_OUT1 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT1_M ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S)) -#define SENS_TOUCH_MEAS_OUT1_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT1_S 0 - -#define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x0074) -/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the counter for touch pad 2*/ -#define SENS_TOUCH_MEAS_OUT2 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT2_M ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S)) -#define SENS_TOUCH_MEAS_OUT2_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT2_S 16 -/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the counter for touch pad 3*/ -#define SENS_TOUCH_MEAS_OUT3 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT3_M ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S)) -#define SENS_TOUCH_MEAS_OUT3_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT3_S 0 - -#define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x0078) -/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the counter for touch pad 4*/ -#define SENS_TOUCH_MEAS_OUT4 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT4_M ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S)) -#define SENS_TOUCH_MEAS_OUT4_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT4_S 16 -/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the counter for touch pad 5*/ -#define SENS_TOUCH_MEAS_OUT5 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT5_M ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S)) -#define SENS_TOUCH_MEAS_OUT5_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT5_S 0 - -#define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x007c) -/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the counter for touch pad 6*/ -#define SENS_TOUCH_MEAS_OUT6 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT6_M ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S)) -#define SENS_TOUCH_MEAS_OUT6_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT6_S 16 -/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the counter for touch pad 7*/ -#define SENS_TOUCH_MEAS_OUT7 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT7_M ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S)) -#define SENS_TOUCH_MEAS_OUT7_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT7_S 0 - -#define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x0080) -/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: the counter for touch pad 8*/ -#define SENS_TOUCH_MEAS_OUT8 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT8_M ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S)) -#define SENS_TOUCH_MEAS_OUT8_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT8_S 16 -/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: the counter for touch pad 9*/ -#define SENS_TOUCH_MEAS_OUT9 0x0000FFFF -#define SENS_TOUCH_MEAS_OUT9_M ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S)) -#define SENS_TOUCH_MEAS_OUT9_V 0xFFFF -#define SENS_TOUCH_MEAS_OUT9_S 0 - -#define SENS_SAR_TOUCH_CTRL2_REG (DR_REG_SENS_BASE + 0x0084) -/* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: to clear reg_touch_meas_en*/ -#define SENS_TOUCH_MEAS_EN_CLR (BIT(30)) -#define SENS_TOUCH_MEAS_EN_CLR_M (BIT(30)) -#define SENS_TOUCH_MEAS_EN_CLR_V 0x1 -#define SENS_TOUCH_MEAS_EN_CLR_S 30 -/* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */ -/*description: sleep cycles for timer*/ -#define SENS_TOUCH_SLEEP_CYCLES 0x0000FFFF -#define SENS_TOUCH_SLEEP_CYCLES_M ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S)) -#define SENS_TOUCH_SLEEP_CYCLES_V 0xFFFF -#define SENS_TOUCH_SLEEP_CYCLES_S 14 -/* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */ -/*description: 1: to start touch fsm by SW 0: to start touch fsm by timer*/ -#define SENS_TOUCH_START_FORCE (BIT(13)) -#define SENS_TOUCH_START_FORCE_M (BIT(13)) -#define SENS_TOUCH_START_FORCE_V 0x1 -#define SENS_TOUCH_START_FORCE_S 13 -/* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: 1: start touch fsm valid when reg_touch_start_force is set*/ -#define SENS_TOUCH_START_EN (BIT(12)) -#define SENS_TOUCH_START_EN_M (BIT(12)) -#define SENS_TOUCH_START_EN_V 0x1 -#define SENS_TOUCH_START_EN_S 12 -/* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START - & TOUCH_XPD is controlled by registers*/ -#define SENS_TOUCH_START_FSM_EN (BIT(11)) -#define SENS_TOUCH_START_FSM_EN_M (BIT(11)) -#define SENS_TOUCH_START_FSM_EN_V 0x1 -#define SENS_TOUCH_START_FSM_EN_S 11 -/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */ -/*description: fsm set 1 to indicate touch touch meas is done*/ -#define SENS_TOUCH_MEAS_DONE (BIT(10)) -#define SENS_TOUCH_MEAS_DONE_M (BIT(10)) -#define SENS_TOUCH_MEAS_DONE_V 0x1 -#define SENS_TOUCH_MEAS_DONE_S 10 -/* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: 10-bit register to indicate which pads are “touched”*/ -#define SENS_TOUCH_MEAS_EN 0x000003FF -#define SENS_TOUCH_MEAS_EN_M ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S)) -#define SENS_TOUCH_MEAS_EN_V 0x3FF -#define SENS_TOUCH_MEAS_EN_S 0 - -#define SENS_SAR_TOUCH_ENABLE_REG (DR_REG_SENS_BASE + 0x008c) -/* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */ -/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is - “touched” only if at least one of touch pad in SET1 is “touched”.*/ -#define SENS_TOUCH_PAD_OUTEN1 0x000003FF -#define SENS_TOUCH_PAD_OUTEN1_M ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S)) -#define SENS_TOUCH_PAD_OUTEN1_V 0x3FF -#define SENS_TOUCH_PAD_OUTEN1_S 20 -/* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */ -/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is - “touched” only if at least one of touch pad in SET2 is “touched”.*/ -#define SENS_TOUCH_PAD_OUTEN2 0x000003FF -#define SENS_TOUCH_PAD_OUTEN2_M ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S)) -#define SENS_TOUCH_PAD_OUTEN2_V 0x3FF -#define SENS_TOUCH_PAD_OUTEN2_S 10 -/* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ -/*description: Bitmap defining the working set during the measurement.*/ -#define SENS_TOUCH_PAD_WORKEN 0x000003FF -#define SENS_TOUCH_PAD_WORKEN_M ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S)) -#define SENS_TOUCH_PAD_WORKEN_V 0x3FF -#define SENS_TOUCH_PAD_WORKEN_S 0 - -#define SENS_SAR_TOUCH_CTRL3_REG (DR_REG_SENS_BASE + 0x0090) -/* SENS_TOUCH_MEAS_RAW : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: touch sensor raw result*/ -#define SENS_TOUCH_MEAS_RAW 0x000003FF -#define SENS_TOUCH_MEAS_RAW_M ((SENS_TOUCH_MEAS_RAW_V)<<(SENS_TOUCH_MEAS_RAW_S)) -#define SENS_TOUCH_MEAS_RAW_V 0x3FF -#define SENS_TOUCH_MEAS_RAW_S 0 - -#define SENS_SAR_READ_CTRL2_REG (DR_REG_SENS_BASE + 0x0094) +#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024) +/* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable saradc2 to send out interrupt*/ +#define SENS_SAR2_INT_EN (BIT(30)) +#define SENS_SAR2_INT_EN_M (BIT(30)) +#define SENS_SAR2_INT_EN_V 0x1 +#define SENS_SAR2_INT_EN_S 30 /* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ /*description: Invert SAR ADC2 data*/ #define SENS_SAR2_DATA_INV (BIT(29)) #define SENS_SAR2_DATA_INV_M (BIT(29)) #define SENS_SAR2_DATA_INV_V 0x1 #define SENS_SAR2_DATA_INV_S 29 -/* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR - ADC2 controlled by RTC ADC2 CTRL*/ -#define SENS_SAR2_DIG_FORCE (BIT(28)) -#define SENS_SAR2_DIG_FORCE_M (BIT(28)) -#define SENS_SAR2_DIG_FORCE_V 0x1 -#define SENS_SAR2_DIG_FORCE_S 28 -/* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR2_PWDET_FORCE (BIT(27)) -#define SENS_SAR2_PWDET_FORCE_M (BIT(27)) -#define SENS_SAR2_PWDET_FORCE_V 0x1 -#define SENS_SAR2_PWDET_FORCE_S 27 /* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ /*description: */ #define SENS_SAR2_SAMPLE_NUM 0x000000FF @@ -830,8 +297,7 @@ extern "C" { #define SENS_SAR2_CLK_GATED_V 0x1 #define SENS_SAR2_CLK_GATED_S 18 /* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ -/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width - 11: for 12-bit width*/ +/*description: 00: for 9-bit width*/ #define SENS_SAR2_SAMPLE_BIT 0x00000003 #define SENS_SAR2_SAMPLE_BIT_M ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S)) #define SENS_SAR2_SAMPLE_BIT_V 0x3 @@ -849,30 +315,91 @@ extern "C" { #define SENS_SAR2_CLK_DIV_V 0xFF #define SENS_SAR2_CLK_DIV_S 0 -#define SENS_SAR_MEAS_START2_REG (DR_REG_SENS_BASE + 0x0098) +#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x0028) +/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR2_READER_STATUS 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) +#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_S 0 + +#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x002c) +/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ +/*description: */ +#define SENS_SAR2_XPD_WAIT 0x000000FF +#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) +#define SENS_SAR2_XPD_WAIT_V 0xFF +#define SENS_SAR2_XPD_WAIT_S 24 +/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ +/*description: */ +#define SENS_SAR2_RSTB_WAIT 0x000000FF +#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) +#define SENS_SAR2_RSTB_WAIT_V 0xFF +#define SENS_SAR2_RSTB_WAIT_S 16 +/* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ +/*description: */ +#define SENS_SAR2_STANDBY_WAIT 0x000000FF +#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S)) +#define SENS_SAR2_STANDBY_WAIT_V 0xFF +#define SENS_SAR2_STANDBY_WAIT_S 8 +/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) +#define SENS_SAR2_RSTB_FORCE_V 0x3 +#define SENS_SAR2_RSTB_FORCE_S 6 +/* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: SAR2_EN_TEST*/ +#define SENS_SAR2_EN_TEST (BIT(5)) +#define SENS_SAR2_EN_TEST_M (BIT(5)) +#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_S 5 +/* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc control pkdet enable*/ +#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_V 0x1 +#define SENS_SAR2_PKDET_CAL_EN_S 4 +/* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc control pwdet enable*/ +#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_V 0x1 +#define SENS_SAR2_PWDET_CAL_EN_S 3 +/* SENS_SAR2_STOP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: stop SAR ADC2 conversion*/ +#define SENS_SAR2_STOP (BIT(2)) +#define SENS_SAR2_STOP_M (BIT(2)) +#define SENS_SAR2_STOP_V 0x1 +#define SENS_SAR2_STOP_S 2 +/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: 00: 9 bit*/ +#define SENS_SAR2_BIT_WIDTH 0x00000003 +#define SENS_SAR2_BIT_WIDTH_M ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S)) +#define SENS_SAR2_BIT_WIDTH_V 0x3 +#define SENS_SAR2_BIT_WIDTH_S 0 + +#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x0030) /* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 - pad enable bitmap is controlled by ULP-coprocessor*/ +/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW*/ #define SENS_SAR2_EN_PAD_FORCE (BIT(31)) #define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) #define SENS_SAR2_EN_PAD_FORCE_V 0x1 #define SENS_SAR2_EN_PAD_FORCE_S 31 /* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/ +/*description: SAR ADC2 pad enable bitmap*/ #define SENS_SAR2_EN_PAD 0x00000FFF #define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) #define SENS_SAR2_EN_PAD_V 0xFFF #define SENS_SAR2_EN_PAD_S 19 /* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 - controller is started by ULP-coprocessor*/ +/*description: 1: SAR ADC2 controller (in RTC) is started by SW*/ #define SENS_MEAS2_START_FORCE (BIT(18)) #define SENS_MEAS2_START_FORCE_M (BIT(18)) #define SENS_MEAS2_START_FORCE_V 0x1 #define SENS_MEAS2_START_FORCE_S 18 /* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC2 controller (in RTC) starts conversion only active when - reg_meas2_start_force = 1*/ +/*description: SAR ADC2 controller (in RTC) starts conversion*/ #define SENS_MEAS2_START_SAR (BIT(17)) #define SENS_MEAS2_START_SAR_M (BIT(17)) #define SENS_MEAS2_START_SAR_V 0x1 @@ -890,7 +417,773 @@ extern "C" { #define SENS_MEAS2_DATA_SAR_V 0xFFFF #define SENS_MEAS2_DATA_SAR_S 0 -#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x009c) +#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x0034) +/* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: in sleep force to use rtc to control ADC*/ +#define SENS_SAR2_RTC_FORCE (BIT(31)) +#define SENS_SAR2_RTC_FORCE_M (BIT(31)) +#define SENS_SAR2_RTC_FORCE_V 0x1 +#define SENS_SAR2_RTC_FORCE_S 31 +/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: SAR2_PWDET_CCT*/ +#define SENS_SAR2_PWDET_CCT 0x00000007 +#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) +#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_S 28 + +#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) +/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad*/ +#define SENS_SAR2_ATTEN 0xFFFFFFFF +#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) +#define SENS_SAR2_ATTEN_V 0xFFFFFFFF +#define SENS_SAR2_ATTEN_S 0 + +#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x003c) +/* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SARCLK_EN (BIT(31)) +#define SENS_SARCLK_EN_M (BIT(31)) +#define SENS_SARCLK_EN_V 0x1 +#define SENS_SARCLK_EN_S 31 +/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ +/*description: */ +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) +#define SENS_FORCE_XPD_SAR_V 0x3 +#define SENS_FORCE_XPD_SAR_S 29 +/* SENS_SAR1_DREF : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: Adjust saradc1 offset*/ +#define SENS_SAR1_DREF 0x00000007 +#define SENS_SAR1_DREF_M ((SENS_SAR1_DREF_V)<<(SENS_SAR1_DREF_S)) +#define SENS_SAR1_DREF_V 0x7 +#define SENS_SAR1_DREF_S 26 +/* SENS_SAR2_DREF : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: Adjust saradc2 offset*/ +#define SENS_SAR2_DREF 0x00000007 +#define SENS_SAR2_DREF_M ((SENS_SAR2_DREF_V)<<(SENS_SAR2_DREF_S)) +#define SENS_SAR2_DREF_V 0x7 +#define SENS_SAR2_DREF_S 23 + +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x0040) +/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: */ +#define SENS_MEAS_STATUS 0x000000FF +#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S)) +#define SENS_MEAS_STATUS_V 0xFF +#define SENS_MEAS_STATUS_S 22 +/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR0 0x000007FF +#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) +#define SENS_I2C_SLAVE_ADDR0_V 0x7FF +#define SENS_I2C_SLAVE_ADDR0_S 11 +/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR1 0x000007FF +#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) +#define SENS_I2C_SLAVE_ADDR1_V 0x7FF +#define SENS_I2C_SLAVE_ADDR1_S 0 + +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0044) +/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR2 0x000007FF +#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) +#define SENS_I2C_SLAVE_ADDR2_V 0x7FF +#define SENS_I2C_SLAVE_ADDR2_S 11 +/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR3 0x000007FF +#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) +#define SENS_I2C_SLAVE_ADDR3_V 0x7FF +#define SENS_I2C_SLAVE_ADDR3_S 0 + +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0048) +/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR4 0x000007FF +#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) +#define SENS_I2C_SLAVE_ADDR4_V 0x7FF +#define SENS_I2C_SLAVE_ADDR4_S 11 +/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR5 0x000007FF +#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) +#define SENS_I2C_SLAVE_ADDR5_V 0x7FF +#define SENS_I2C_SLAVE_ADDR5_S 0 + +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x004c) +/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR6 0x000007FF +#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) +#define SENS_I2C_SLAVE_ADDR6_V 0x7FF +#define SENS_I2C_SLAVE_ADDR6_S 11 +/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR7 0x000007FF +#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) +#define SENS_I2C_SLAVE_ADDR7_V 0x7FF +#define SENS_I2C_SLAVE_ADDR7_S 0 + +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) +/* SENS_TSENS_DAC : R/W ;bitpos:[31:28] ;default: 4'hF ; */ +/*description: Temperature sensor offset dac. 15 for 0 offset 5 for -2 7 for + -1 11 for 1 10 for 2*/ +#define SENS_TSENS_DAC 0x0000000F +#define SENS_TSENS_DAC_M ((SENS_TSENS_DAC_V)<<(SENS_TSENS_DAC_S)) +#define SENS_TSENS_DAC_V 0xF +#define SENS_TSENS_DAC_S 28 +/* SENS_TSENS_DIV_CHOP : R/W ;bitpos:[27:26] ;default: 2'b10 ; */ +/*description: 0 for steady phase 0 1 for steady phase 1 2 for chopping with + ½ frequency of TSENS_CK 3 for chopping with ¼*/ +#define SENS_TSENS_DIV_CHOP 0x00000003 +#define SENS_TSENS_DIV_CHOP_M ((SENS_TSENS_DIV_CHOP_V)<<(SENS_TSENS_DIV_CHOP_S)) +#define SENS_TSENS_DIV_CHOP_V 0x3 +#define SENS_TSENS_DIV_CHOP_S 26 +/* SENS_TSENS_DIZ : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: ADC input short*/ +#define SENS_TSENS_DIZ (BIT(25)) +#define SENS_TSENS_DIZ_M (BIT(25)) +#define SENS_TSENS_DIZ_V 0x1 +#define SENS_TSENS_DIZ_S 25 +/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: temperature sensor dump out*/ +#define SENS_TSENS_DUMP_OUT (BIT(24)) +#define SENS_TSENS_DUMP_OUT_M (BIT(24)) +#define SENS_TSENS_DUMP_OUT_V 0x1 +#define SENS_TSENS_DUMP_OUT_S 24 +/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: dump out & power up controlled by SW*/ +#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_V 0x1 +#define SENS_TSENS_POWER_UP_FORCE_S 23 +/* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: temperature sensor power up*/ +#define SENS_TSENS_POWER_UP (BIT(22)) +#define SENS_TSENS_POWER_UP_M (BIT(22)) +#define SENS_TSENS_POWER_UP_V 0x1 +#define SENS_TSENS_POWER_UP_S 22 +/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ +/*description: temperature sensor clock divider*/ +#define SENS_TSENS_CLK_DIV 0x000000FF +#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) +#define SENS_TSENS_CLK_DIV_V 0xFF +#define SENS_TSENS_CLK_DIV_S 14 +/* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: invert temperature sensor data*/ +#define SENS_TSENS_IN_INV (BIT(13)) +#define SENS_TSENS_IN_INV_M (BIT(13)) +#define SENS_TSENS_IN_INV_V 0x1 +#define SENS_TSENS_IN_INV_S 13 +/* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: enable temperature sensor to send out interrupt*/ +#define SENS_TSENS_INT_EN (BIT(12)) +#define SENS_TSENS_INT_EN_M (BIT(12)) +#define SENS_TSENS_INT_EN_V 0x1 +#define SENS_TSENS_INT_EN_S 12 +/* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: indicate temperature sensor out ready*/ +#define SENS_TSENS_READY (BIT(8)) +#define SENS_TSENS_READY_M (BIT(8)) +#define SENS_TSENS_READY_V 0x1 +#define SENS_TSENS_READY_S 8 +/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: temperature sensor data out*/ +#define SENS_TSENS_OUT 0x000000FF +#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) +#define SENS_TSENS_OUT_V 0xFF +#define SENS_TSENS_OUT_S 0 + +#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x0054) +/* SENS_TSENS_RESET : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: temperature sensor reset*/ +#define SENS_TSENS_RESET (BIT(16)) +#define SENS_TSENS_RESET_M (BIT(16)) +#define SENS_TSENS_RESET_V 0x1 +#define SENS_TSENS_RESET_S 16 +/* SENS_TSENS_CLKGATE_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: temperature sensor clock enable*/ +#define SENS_TSENS_CLKGATE_EN (BIT(15)) +#define SENS_TSENS_CLKGATE_EN_M (BIT(15)) +#define SENS_TSENS_CLKGATE_EN_V 0x1 +#define SENS_TSENS_CLKGATE_EN_S 15 +/* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SENS_TSENS_CLK_INV (BIT(14)) +#define SENS_TSENS_CLK_INV_M (BIT(14)) +#define SENS_TSENS_CLK_INV_V 0x1 +#define SENS_TSENS_CLK_INV_S 14 +/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENS_TSENS_XPD_FORCE 0x00000003 +#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S)) +#define SENS_TSENS_XPD_FORCE_V 0x3 +#define SENS_TSENS_XPD_FORCE_S 12 +/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ +/*description: */ +#define SENS_TSENS_XPD_WAIT 0x00000FFF +#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) +#define SENS_TSENS_XPD_WAIT_V 0xFFF +#define SENS_TSENS_XPD_WAIT_S 0 + +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0058) +/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: I2C started by SW*/ +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_V 0x1 +#define SENS_SAR_I2C_START_FORCE_S 29 +/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: start I2C*/ +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (BIT(28)) +#define SENS_SAR_I2C_START_V 0x1 +#define SENS_SAR_I2C_START_S 28 +/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: I2C control data*/ +#define SENS_SAR_I2C_CTRL 0x0FFFFFFF +#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) +#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF +#define SENS_SAR_I2C_CTRL_S 0 + +#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x005c) +/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad0*/ +#define SENS_TOUCH_APPROACH_PAD0 0x0000000F +#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S)) +#define SENS_TOUCH_APPROACH_PAD0_V 0xF +#define SENS_TOUCH_APPROACH_PAD0_S 28 +/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad1*/ +#define SENS_TOUCH_APPROACH_PAD1 0x0000000F +#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S)) +#define SENS_TOUCH_APPROACH_PAD1_V 0xF +#define SENS_TOUCH_APPROACH_PAD1_S 24 +/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad2*/ +#define SENS_TOUCH_APPROACH_PAD2 0x0000000F +#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S)) +#define SENS_TOUCH_APPROACH_PAD2_V 0xF +#define SENS_TOUCH_APPROACH_PAD2_S 20 +/* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: clear all touch active status*/ +#define SENS_TOUCH_STATUS_CLR (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_V 0x1 +#define SENS_TOUCH_STATUS_CLR_S 15 +/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */ +/*description: touch controller output enable*/ +#define SENS_TOUCH_OUTEN 0x00007FFF +#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S)) +#define SENS_TOUCH_OUTEN_V 0x7FFF +#define SENS_TOUCH_OUTEN_S 0 + +#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x0060) +/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 1*/ +#define SENS_TOUCH_OUT_TH1 0x003FFFFF +#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) +#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH1_S 0 + +#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0064) +/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 2*/ +#define SENS_TOUCH_OUT_TH2 0x003FFFFF +#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) +#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH2_S 0 + +#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0068) +/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 3*/ +#define SENS_TOUCH_OUT_TH3 0x003FFFFF +#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) +#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH3_S 0 + +#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x006c) +/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 4*/ +#define SENS_TOUCH_OUT_TH4 0x003FFFFF +#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) +#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH4_S 0 + +#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x0070) +/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 5*/ +#define SENS_TOUCH_OUT_TH5 0x003FFFFF +#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) +#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH5_S 0 + +#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x0074) +/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 6*/ +#define SENS_TOUCH_OUT_TH6 0x003FFFFF +#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) +#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH6_S 0 + +#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x0078) +/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 7*/ +#define SENS_TOUCH_OUT_TH7 0x003FFFFF +#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) +#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH7_S 0 + +#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x007c) +/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 8*/ +#define SENS_TOUCH_OUT_TH8 0x003FFFFF +#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) +#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH8_S 0 + +#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x0080) +/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 9*/ +#define SENS_TOUCH_OUT_TH9 0x003FFFFF +#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) +#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH9_S 0 + +#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x0084) +/* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 10*/ +#define SENS_TOUCH_OUT_TH10 0x003FFFFF +#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S)) +#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH10_S 0 + +#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x0088) +/* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 11*/ +#define SENS_TOUCH_OUT_TH11 0x003FFFFF +#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S)) +#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH11_S 0 + +#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x008c) +/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 12*/ +#define SENS_TOUCH_OUT_TH12 0x003FFFFF +#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S)) +#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH12_S 0 + +#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x0090) +/* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 13*/ +#define SENS_TOUCH_OUT_TH13 0x003FFFFF +#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S)) +#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH13_S 0 + +#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x0094) +/* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 14*/ +#define SENS_TOUCH_OUT_TH14 0x003FFFFF +#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S)) +#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH14_S 0 + +#define SENS_SAR_TOUCH_OUT0_REG (DR_REG_SENS_BASE + 0x0098) +/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 0*/ +#define SENS_TOUCH_MEAS_OUT0 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT0_M ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S)) +#define SENS_TOUCH_MEAS_OUT0_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT0_S 0 + +#define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x009c) +/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 1*/ +#define SENS_TOUCH_MEAS_OUT1 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT1_M ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S)) +#define SENS_TOUCH_MEAS_OUT1_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT1_S 0 + +#define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x00a0) +/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 2*/ +#define SENS_TOUCH_MEAS_OUT2 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT2_M ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S)) +#define SENS_TOUCH_MEAS_OUT2_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT2_S 0 + +#define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x00a4) +/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 3*/ +#define SENS_TOUCH_MEAS_OUT3 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT3_M ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S)) +#define SENS_TOUCH_MEAS_OUT3_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT3_S 0 + +#define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x00a8) +/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 4*/ +#define SENS_TOUCH_MEAS_OUT4 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT4_M ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S)) +#define SENS_TOUCH_MEAS_OUT4_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT4_S 0 + +#define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x00ac) +/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 5*/ +#define SENS_TOUCH_MEAS_OUT5 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT5_M ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S)) +#define SENS_TOUCH_MEAS_OUT5_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT5_S 0 + +#define SENS_SAR_TOUCH_OUT6_REG (DR_REG_SENS_BASE + 0x00b0) +/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 6*/ +#define SENS_TOUCH_MEAS_OUT6 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT6_M ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S)) +#define SENS_TOUCH_MEAS_OUT6_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT6_S 0 + +#define SENS_SAR_TOUCH_OUT7_REG (DR_REG_SENS_BASE + 0x00b4) +/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 7*/ +#define SENS_TOUCH_MEAS_OUT7 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT7_M ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S)) +#define SENS_TOUCH_MEAS_OUT7_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT7_S 0 + +#define SENS_SAR_TOUCH_OUT8_REG (DR_REG_SENS_BASE + 0x00b8) +/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 8*/ +#define SENS_TOUCH_MEAS_OUT8 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT8_M ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S)) +#define SENS_TOUCH_MEAS_OUT8_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT8_S 0 + +#define SENS_SAR_TOUCH_OUT9_REG (DR_REG_SENS_BASE + 0x00bc) +/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 9*/ +#define SENS_TOUCH_MEAS_OUT9 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT9_M ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S)) +#define SENS_TOUCH_MEAS_OUT9_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT9_S 0 + +#define SENS_SAR_TOUCH_OUT10_REG (DR_REG_SENS_BASE + 0x00c0) +/* SENS_TOUCH_MEAS_OUT10 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 10*/ +#define SENS_TOUCH_MEAS_OUT10 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT10_M ((SENS_TOUCH_MEAS_OUT10_V)<<(SENS_TOUCH_MEAS_OUT10_S)) +#define SENS_TOUCH_MEAS_OUT10_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT10_S 0 + +#define SENS_SAR_TOUCH_OUT11_REG (DR_REG_SENS_BASE + 0x00c4) +/* SENS_TOUCH_MEAS_OUT11 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 11*/ +#define SENS_TOUCH_MEAS_OUT11 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT11_M ((SENS_TOUCH_MEAS_OUT11_V)<<(SENS_TOUCH_MEAS_OUT11_S)) +#define SENS_TOUCH_MEAS_OUT11_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT11_S 0 + +#define SENS_SAR_TOUCH_OUT12_REG (DR_REG_SENS_BASE + 0x00c8) +/* SENS_TOUCH_MEAS_OUT12 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 12*/ +#define SENS_TOUCH_MEAS_OUT12 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT12_M ((SENS_TOUCH_MEAS_OUT12_V)<<(SENS_TOUCH_MEAS_OUT12_S)) +#define SENS_TOUCH_MEAS_OUT12_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT12_S 0 + +#define SENS_SAR_TOUCH_OUT13_REG (DR_REG_SENS_BASE + 0x00cc) +/* SENS_TOUCH_MEAS_OUT13 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 13*/ +#define SENS_TOUCH_MEAS_OUT13 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT13_M ((SENS_TOUCH_MEAS_OUT13_V)<<(SENS_TOUCH_MEAS_OUT13_S)) +#define SENS_TOUCH_MEAS_OUT13_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT13_S 0 + +#define SENS_SAR_TOUCH_OUT14_REG (DR_REG_SENS_BASE + 0x00d0) +/* SENS_TOUCH_MEAS_OUT14 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 14*/ +#define SENS_TOUCH_MEAS_OUT14 0x003FFFFF +#define SENS_TOUCH_MEAS_OUT14_M ((SENS_TOUCH_MEAS_OUT14_V)<<(SENS_TOUCH_MEAS_OUT14_S)) +#define SENS_TOUCH_MEAS_OUT14_V 0x3FFFFF +#define SENS_TOUCH_MEAS_OUT14_S 0 + +#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x00d4) +/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SENS_TOUCH_MEAS_DONE (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_S 31 +/* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ +/*description: Clear touch channel*/ +#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF +#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S)) +#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF +#define SENS_TOUCH_CHANNEL_CLR_S 15 +/* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ +/*description: touch active status*/ +#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF +#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S)) +#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF +#define SENS_TOUCH_PAD_ACTIVE_S 0 + +#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0x00d8) +/* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: */ +#define SENS_TOUCH_SCAN_CURR 0x0000000F +#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S)) +#define SENS_TOUCH_SCAN_CURR_V 0xF +#define SENS_TOUCH_SCAN_CURR_S 22 +/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 0*/ +#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF +#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) +#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF +#define SENS_TOUCH_DENOISE_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0x00dc) +/* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S)) +#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD1_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD1_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD1_BASELINE_M ((SENS_TOUCH_PAD1_BASELINE_V)<<(SENS_TOUCH_PAD1_BASELINE_S)) +#define SENS_TOUCH_PAD1_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD1_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0x00e0) +/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S)) +#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD2_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD2_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD2_BASELINE_M ((SENS_TOUCH_PAD2_BASELINE_V)<<(SENS_TOUCH_PAD2_BASELINE_S)) +#define SENS_TOUCH_PAD2_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD2_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0x00e4) +/* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S)) +#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD3_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD3_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD3_BASELINE_M ((SENS_TOUCH_PAD3_BASELINE_V)<<(SENS_TOUCH_PAD3_BASELINE_S)) +#define SENS_TOUCH_PAD3_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD3_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0x00e8) +/* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S)) +#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD4_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD4_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD4_BASELINE_M ((SENS_TOUCH_PAD4_BASELINE_V)<<(SENS_TOUCH_PAD4_BASELINE_S)) +#define SENS_TOUCH_PAD4_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD4_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0x00ec) +/* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S)) +#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD5_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD5_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD5_BASELINE_M ((SENS_TOUCH_PAD5_BASELINE_V)<<(SENS_TOUCH_PAD5_BASELINE_S)) +#define SENS_TOUCH_PAD5_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD5_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0x00f0) +/* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S)) +#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD6_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD6_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD6_BASELINE_M ((SENS_TOUCH_PAD6_BASELINE_V)<<(SENS_TOUCH_PAD6_BASELINE_S)) +#define SENS_TOUCH_PAD6_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD6_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0x00f4) +/* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S)) +#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD7_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD7_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD7_BASELINE_M ((SENS_TOUCH_PAD7_BASELINE_V)<<(SENS_TOUCH_PAD7_BASELINE_S)) +#define SENS_TOUCH_PAD7_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD7_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0x00f8) +/* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S)) +#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD8_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD8_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD8_BASELINE_M ((SENS_TOUCH_PAD8_BASELINE_V)<<(SENS_TOUCH_PAD8_BASELINE_S)) +#define SENS_TOUCH_PAD8_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD8_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0x00fc) +/* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S)) +#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD9_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD9_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD9_BASELINE_M ((SENS_TOUCH_PAD9_BASELINE_V)<<(SENS_TOUCH_PAD9_BASELINE_S)) +#define SENS_TOUCH_PAD9_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD9_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0x0100) +/* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S)) +#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD10_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD10_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD10_BASELINE_M ((SENS_TOUCH_PAD10_BASELINE_V)<<(SENS_TOUCH_PAD10_BASELINE_S)) +#define SENS_TOUCH_PAD10_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD10_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0x0104) +/* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S)) +#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD11_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD11_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD11_BASELINE_M ((SENS_TOUCH_PAD11_BASELINE_V)<<(SENS_TOUCH_PAD11_BASELINE_S)) +#define SENS_TOUCH_PAD11_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD11_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0x0108) +/* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S)) +#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD12_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD12_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD12_BASELINE_M ((SENS_TOUCH_PAD12_BASELINE_V)<<(SENS_TOUCH_PAD12_BASELINE_S)) +#define SENS_TOUCH_PAD12_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD12_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0x010c) +/* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S)) +#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD13_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD13_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD13_BASELINE_M ((SENS_TOUCH_PAD13_BASELINE_V)<<(SENS_TOUCH_PAD13_BASELINE_S)) +#define SENS_TOUCH_PAD13_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD13_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0x0110) +/* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S)) +#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD14_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD14_BASELINE 0x003FFFFF +#define SENS_TOUCH_PAD14_BASELINE_M ((SENS_TOUCH_PAD14_BASELINE_V)<<(SENS_TOUCH_PAD14_BASELINE_S)) +#define SENS_TOUCH_PAD14_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_PAD14_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) +/* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 +#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S)) +#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 +#define SENS_TOUCH_SLP_DEBOUNCE_S 29 +/* SENS_TOUCH_SLP_BASELINE : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_BASELINE 0x003FFFFF +#define SENS_TOUCH_SLP_BASELINE_M ((SENS_TOUCH_SLP_BASELINE_V)<<(SENS_TOUCH_SLP_BASELINE_S)) +#define SENS_TOUCH_SLP_BASELINE_V 0x3FFFFF +#define SENS_TOUCH_SLP_BASELINE_S 0 + +#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) +/* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF +#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S)) +#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF +#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 +/* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 +/* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 +/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 + +#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x011c) /* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ /*description: 1: invert PDAC_CLK*/ #define SENS_DAC_CLK_INV (BIT(25)) @@ -910,7 +1203,7 @@ extern "C" { #define SENS_DAC_CLK_FORCE_LOW_V 0x1 #define SENS_DAC_CLK_FORCE_LOW_S 23 /* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/ +/*description: 1: DAC1 & DAC2 use DMA*/ #define SENS_DAC_DIG_FORCE (BIT(22)) #define SENS_DAC_DIG_FORCE_M (BIT(22)) #define SENS_DAC_DIG_FORCE_V 0x1 @@ -922,55 +1215,51 @@ extern "C" { #define SENS_DEBUG_BIT_SEL_V 0x1F #define SENS_DEBUG_BIT_SEL_S 17 /* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: enable CW generator 0: disable CW generator*/ +/*description: 1: enable CW generator*/ #define SENS_SW_TONE_EN (BIT(16)) #define SENS_SW_TONE_EN_M (BIT(16)) #define SENS_SW_TONE_EN_V 0x1 #define SENS_SW_TONE_EN_S 16 /* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: frequency step for CW generator can be used to adjust the frequency*/ +/*description: frequency step for CW generator*/ #define SENS_SW_FSTEP 0x0000FFFF #define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S)) #define SENS_SW_FSTEP_V 0xFFFF #define SENS_SW_FSTEP_S 0 -#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x00a0) +#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x0120) /* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to - select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/ +/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]*/ #define SENS_DAC_CW_EN2 (BIT(25)) #define SENS_DAC_CW_EN2_M (BIT(25)) #define SENS_DAC_CW_EN2_V 0x1 #define SENS_DAC_CW_EN2_S 25 /* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to - select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/ +/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]*/ #define SENS_DAC_CW_EN1 (BIT(24)) #define SENS_DAC_CW_EN1_M (BIT(24)) #define SENS_DAC_CW_EN1_V 0x1 #define SENS_DAC_CW_EN1_S 24 /* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB - 11: invert all bits except MSB*/ +/*description: 00: do not invert any bits*/ #define SENS_DAC_INV2 0x00000003 #define SENS_DAC_INV2_M ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S)) #define SENS_DAC_INV2_V 0x3 #define SENS_DAC_INV2_S 22 /* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB - 11: invert all bits except MSB*/ +/*description: 00: do not invert any bits*/ #define SENS_DAC_INV1 0x00000003 #define SENS_DAC_INV1_M ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S)) #define SENS_DAC_INV1_V 0x3 #define SENS_DAC_INV1_S 20 /* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +/*description: 00: no scale*/ #define SENS_DAC_SCALE2 0x00000003 #define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S)) #define SENS_DAC_SCALE2_V 0x3 #define SENS_DAC_SCALE2_S 18 /* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ +/*description: 00: no scale*/ #define SENS_DAC_SCALE1 0x00000003 #define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S)) #define SENS_DAC_SCALE1_V 0x3 @@ -988,259 +1277,329 @@ extern "C" { #define SENS_DAC_DC1_V 0xFF #define SENS_DAC_DC1_S 0 -#define SENS_SAR_MEAS_CTRL2_REG (DR_REG_SENS_BASE + 0x00a4) -/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) -#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_GND_FORCE_S 17 -/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) -#define SENS_AMP_SHORT_REF_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_FORCE_S 15 -/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FORCE 0x00000003 -#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) -#define SENS_AMP_RST_FB_FORCE_V 0x3 -#define SENS_AMP_RST_FB_FORCE_S 13 -/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */ -/*description: */ -#define SENS_SAR2_RSTB_FORCE 0x00000003 -#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) -#define SENS_SAR2_RSTB_FORCE_V 0x3 -#define SENS_SAR2_RSTB_FORCE_S 11 -/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM_IDLE (BIT(10)) -#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(10)) -#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 -#define SENS_SAR_RSTB_FSM_IDLE_S 10 -/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM_IDLE (BIT(9)) -#define SENS_XPD_SAR_FSM_IDLE_M (BIT(9)) -#define SENS_XPD_SAR_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_FSM_IDLE_S 9 -/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(8)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 8 -/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(7)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(7)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_FSM_IDLE_S 7 -/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM_IDLE (BIT(6)) -#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(6)) -#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 -#define SENS_AMP_RST_FB_FSM_IDLE_S 6 -/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(5)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(5)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_AMP_FSM_IDLE_S 5 -/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(4)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(4)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 -#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 4 -/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM 0x0000000F -#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) -#define SENS_SAR1_DAC_XPD_FSM_V 0xF -#define SENS_SAR1_DAC_XPD_FSM_S 0 - -#define SENS_SAR_COCPU_CTRL_REG (DR_REG_SENS_BASE + 0x00a8) -/* SENS_COCPU_TRAP : RO ;bitpos:[28] ;default: 1'b0 ; */ +#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0x0124) +/* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: check cocpu whether in ebreak*/ +#define SENS_COCPU_EBREAK (BIT(30)) +#define SENS_COCPU_EBREAK_M (BIT(30)) +#define SENS_COCPU_EBREAK_V 0x1 +#define SENS_COCPU_EBREAK_S 30 +/* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ /*description: check cocpu whether in trap state*/ -#define SENS_COCPU_TRAP (BIT(28)) -#define SENS_COCPU_TRAP_M (BIT(28)) +#define SENS_COCPU_TRAP (BIT(29)) +#define SENS_COCPU_TRAP_M (BIT(29)) #define SENS_COCPU_TRAP_V 0x1 -#define SENS_COCPU_TRAP_S 28 -/* SENS_COCPU_EOI : RO ;bitpos:[27] ;default: 1'b0 ; */ +#define SENS_COCPU_TRAP_S 29 +/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ /*description: check cocpu whether in interrupt state*/ -#define SENS_COCPU_EOI (BIT(27)) -#define SENS_COCPU_EOI_M (BIT(27)) +#define SENS_COCPU_EOI (BIT(28)) +#define SENS_COCPU_EOI_M (BIT(28)) #define SENS_COCPU_EOI_V 0x1 -#define SENS_COCPU_EOI_S 27 -/* SENS_COCPU_RESET_N : RO ;bitpos:[26] ;default: 1'b0 ; */ +#define SENS_COCPU_EOI_S 28 +/* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ /*description: check cocpu whether in reset state*/ -#define SENS_COCPU_RESET_N (BIT(26)) -#define SENS_COCPU_RESET_N_M (BIT(26)) +#define SENS_COCPU_RESET_N (BIT(27)) +#define SENS_COCPU_RESET_N_M (BIT(27)) #define SENS_COCPU_RESET_N_V 0x1 -#define SENS_COCPU_RESET_N_S 26 -/* SENS_COCPU_CLK_EN : RO ;bitpos:[25] ;default: 1'b0 ; */ +#define SENS_COCPU_RESET_N_S 27 +/* SENS_COCPU_CLK_EN : RO ;bitpos:[26] ;default: 1'b0 ; */ /*description: check cocpu whether clk on*/ -#define SENS_COCPU_CLK_EN (BIT(25)) -#define SENS_COCPU_CLK_EN_M (BIT(25)) +#define SENS_COCPU_CLK_EN (BIT(26)) +#define SENS_COCPU_CLK_EN_M (BIT(26)) #define SENS_COCPU_CLK_EN_V 0x1 -#define SENS_COCPU_CLK_EN_S 25 -/* SENS_COCPU_INT_TRIGGER : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: trigger cocpu register interrupt*/ -#define SENS_COCPU_INT_TRIGGER (BIT(24)) -#define SENS_COCPU_INT_TRIGGER_M (BIT(24)) -#define SENS_COCPU_INT_TRIGGER_V 0x1 -#define SENS_COCPU_INT_TRIGGER_S 24 -/* SENS_COCPU_DONE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: done signal used by riscv to control timer.*/ -#define SENS_COCPU_DONE (BIT(23)) -#define SENS_COCPU_DONE_M (BIT(23)) -#define SENS_COCPU_DONE_V 0x1 -#define SENS_COCPU_DONE_S 23 -/* SENS_COCPU_DONE_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: select riscv done 0: select ulp done*/ -#define SENS_COCPU_DONE_FORCE (BIT(22)) -#define SENS_COCPU_DONE_FORCE_M (BIT(22)) -#define SENS_COCPU_DONE_FORCE_V 0x1 -#define SENS_COCPU_DONE_FORCE_S 22 -/* SENS_COCPU_SEL : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: 1: old ULP 0: new riscV*/ -#define SENS_COCPU_SEL (BIT(21)) -#define SENS_COCPU_SEL_M (BIT(21)) -#define SENS_COCPU_SEL_V 0x1 -#define SENS_COCPU_SEL_S 21 -/* SENS_COCPU_SHUT_RESET_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: to reset cocpu*/ -#define SENS_COCPU_SHUT_RESET_EN (BIT(20)) -#define SENS_COCPU_SHUT_RESET_EN_M (BIT(20)) -#define SENS_COCPU_SHUT_RESET_EN_V 0x1 -#define SENS_COCPU_SHUT_RESET_EN_S 20 -/* SENS_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[19:14] ;default: 6'd24 ; */ -/*description: time from shut cocpu to disable clk*/ -#define SENS_COCPU_SHUT_2_CLK_DIS 0x0000003F -#define SENS_COCPU_SHUT_2_CLK_DIS_M ((SENS_COCPU_SHUT_2_CLK_DIS_V)<<(SENS_COCPU_SHUT_2_CLK_DIS_S)) -#define SENS_COCPU_SHUT_2_CLK_DIS_V 0x3F -#define SENS_COCPU_SHUT_2_CLK_DIS_S 14 -/* SENS_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: to shut cocpu*/ -#define SENS_COCPU_SHUT (BIT(13)) -#define SENS_COCPU_SHUT_M (BIT(13)) -#define SENS_COCPU_SHUT_V 0x1 -#define SENS_COCPU_SHUT_S 13 -/* SENS_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ -/*description: time from start cocpu to give start interrupt*/ -#define SENS_COCPU_START_2_INTR_EN 0x0000003F -#define SENS_COCPU_START_2_INTR_EN_M ((SENS_COCPU_START_2_INTR_EN_V)<<(SENS_COCPU_START_2_INTR_EN_S)) -#define SENS_COCPU_START_2_INTR_EN_V 0x3F -#define SENS_COCPU_START_2_INTR_EN_S 7 -/* SENS_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ -/*description: time from start cocpu to pull down reset*/ -#define SENS_COCPU_START_2_RESET_DIS 0x0000003F -#define SENS_COCPU_START_2_RESET_DIS_M ((SENS_COCPU_START_2_RESET_DIS_V)<<(SENS_COCPU_START_2_RESET_DIS_S)) -#define SENS_COCPU_START_2_RESET_DIS_V 0x3F -#define SENS_COCPU_START_2_RESET_DIS_S 1 -/* SENS_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: cocpu clk force on*/ -#define SENS_COCPU_CLK_FO (BIT(0)) -#define SENS_COCPU_CLK_FO_M (BIT(0)) -#define SENS_COCPU_CLK_FO_V 0x1 -#define SENS_COCPU_CLK_FO_S 0 +#define SENS_COCPU_CLK_EN_S 26 +/* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: trigger cocpu debug registers*/ +#define SENS_COCPU_DBG_TRIGGER (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_V 0x1 +#define SENS_COCPU_DBG_TRIGGER_S 25 -#define SENS_SAR_COCPU_INT_REG (DR_REG_SENS_BASE + 0x00ac) -/* SENS_COCPU_EBREAK_INT : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: int from ebreak*/ -#define SENS_COCPU_EBREAK_INT (BIT(24)) -#define SENS_COCPU_EBREAK_INT_M (BIT(24)) -#define SENS_COCPU_EBREAK_INT_V 0x1 -#define SENS_COCPU_EBREAK_INT_S 24 -/* SENS_COCPU_INT : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: int from register*/ -#define SENS_COCPU_INT (BIT(23)) -#define SENS_COCPU_INT_M (BIT(23)) -#define SENS_COCPU_INT_V 0x1 -#define SENS_COCPU_INT_S 23 -/* SENS_COCPU_START_INT : RO ;bitpos:[22] ;default: 1'b0 ; */ +#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0x0128) +/* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: int from super watch dog*/ +#define SENS_COCPU_SWD_INT_RAW (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_V 0x1 +#define SENS_COCPU_SWD_INT_RAW_S 8 +/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: int from software*/ +#define SENS_COCPU_SW_INT_RAW (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_V 0x1 +#define SENS_COCPU_SW_INT_RAW_S 7 +/* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: int from start*/ -#define SENS_COCPU_START_INT (BIT(22)) -#define SENS_COCPU_START_INT_M (BIT(22)) -#define SENS_COCPU_START_INT_V 0x1 -#define SENS_COCPU_START_INT_S 22 -/* SENS_COCPU_TSENS_INT : RO ;bitpos:[21] ;default: 1'b0 ; */ +#define SENS_COCPU_START_INT_RAW (BIT(6)) +#define SENS_COCPU_START_INT_RAW_M (BIT(6)) +#define SENS_COCPU_START_INT_RAW_V 0x1 +#define SENS_COCPU_START_INT_RAW_S 6 +/* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ /*description: int from tsens*/ -#define SENS_COCPU_TSENS_INT (BIT(21)) -#define SENS_COCPU_TSENS_INT_M (BIT(21)) -#define SENS_COCPU_TSENS_INT_V 0x1 -#define SENS_COCPU_TSENS_INT_S 21 -/* SENS_COCPU_SARADC_INT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: int from saradc*/ -#define SENS_COCPU_SARADC_INT (BIT(20)) -#define SENS_COCPU_SARADC_INT_M (BIT(20)) -#define SENS_COCPU_SARADC_INT_V 0x1 -#define SENS_COCPU_SARADC_INT_S 20 -/* SENS_COCPU_EBREAK_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: int clear entry*/ -#define SENS_COCPU_EBREAK_INT_CLR (BIT(14)) -#define SENS_COCPU_EBREAK_INT_CLR_M (BIT(14)) -#define SENS_COCPU_EBREAK_INT_CLR_V 0x1 -#define SENS_COCPU_EBREAK_INT_CLR_S 14 -/* SENS_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_INT_CLR (BIT(13)) -#define SENS_COCPU_INT_CLR_M (BIT(13)) -#define SENS_COCPU_INT_CLR_V 0x1 -#define SENS_COCPU_INT_CLR_S 13 -/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_CLR (BIT(12)) -#define SENS_COCPU_START_INT_CLR_M (BIT(12)) -#define SENS_COCPU_START_INT_CLR_V 0x1 -#define SENS_COCPU_START_INT_CLR_S 12 -/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_CLR (BIT(11)) -#define SENS_COCPU_TSENS_INT_CLR_M (BIT(11)) -#define SENS_COCPU_TSENS_INT_CLR_V 0x1 -#define SENS_COCPU_TSENS_INT_CLR_S 11 -/* SENS_COCPU_SARADC_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SARADC_INT_CLR (BIT(10)) -#define SENS_COCPU_SARADC_INT_CLR_M (BIT(10)) -#define SENS_COCPU_SARADC_INT_CLR_V 0x1 -#define SENS_COCPU_SARADC_INT_CLR_S 10 -/* SENS_COCPU_EBREAK_INT_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: int enable entry*/ -#define SENS_COCPU_EBREAK_INT_ENA (BIT(4)) -#define SENS_COCPU_EBREAK_INT_ENA_M (BIT(4)) -#define SENS_COCPU_EBREAK_INT_ENA_V 0x1 -#define SENS_COCPU_EBREAK_INT_ENA_S 4 -/* SENS_COCPU_INT_ENA : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SENS_COCPU_INT_ENA (BIT(3)) -#define SENS_COCPU_INT_ENA_M (BIT(3)) -#define SENS_COCPU_INT_ENA_V 0x1 -#define SENS_COCPU_INT_ENA_S 3 -/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA (BIT(2)) -#define SENS_COCPU_START_INT_ENA_M (BIT(2)) -#define SENS_COCPU_START_INT_ENA_V 0x1 -#define SENS_COCPU_START_INT_ENA_S 2 -/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA (BIT(1)) -#define SENS_COCPU_TSENS_INT_ENA_M (BIT(1)) -#define SENS_COCPU_TSENS_INT_ENA_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_S 1 -/* SENS_COCPU_SARADC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENS_COCPU_SARADC_INT_ENA (BIT(0)) -#define SENS_COCPU_SARADC_INT_ENA_M (BIT(0)) -#define SENS_COCPU_SARADC_INT_ENA_V 0x1 -#define SENS_COCPU_SARADC_INT_ENA_S 0 +#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_V 0x1 +#define SENS_COCPU_TSENS_INT_RAW_S 5 +/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: int from saradc2*/ +#define SENS_COCPU_SENS2_INT_RAW (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_V 0x1 +#define SENS_COCPU_SENS2_INT_RAW_S 4 +/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: int from saradc1*/ +#define SENS_COCPU_SENS1_INT_RAW (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_V 0x1 +#define SENS_COCPU_SENS1_INT_RAW_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: int from touch active*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: int from touch inactive*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: int from touch done*/ +#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 -#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x00F8) +#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0x012c) +/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ENA (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_S 8 +/* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int enable*/ +#define SENS_COCPU_SW_INT_ENA (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_V 0x1 +#define SENS_COCPU_SW_INT_ENA_S 7 +/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ENA (BIT(6)) +#define SENS_COCPU_START_INT_ENA_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_V 0x1 +#define SENS_COCPU_START_INT_ENA_S 6 +/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_S 5 +/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ENA (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_V 0x1 +#define SENS_COCPU_SENS2_INT_ENA_S 4 +/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ENA (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_V 0x1 +#define SENS_COCPU_SENS1_INT_ENA_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 + +#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0x0130) +/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ST (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_V 0x1 +#define SENS_COCPU_SWD_INT_ST_S 8 +/* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int status*/ +#define SENS_COCPU_SW_INT_ST (BIT(7)) +#define SENS_COCPU_SW_INT_ST_M (BIT(7)) +#define SENS_COCPU_SW_INT_ST_V 0x1 +#define SENS_COCPU_SW_INT_ST_S 7 +/* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ST (BIT(6)) +#define SENS_COCPU_START_INT_ST_M (BIT(6)) +#define SENS_COCPU_START_INT_ST_V 0x1 +#define SENS_COCPU_START_INT_ST_S 6 +/* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ST (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_V 0x1 +#define SENS_COCPU_TSENS_INT_ST_S 5 +/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ST (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_V 0x1 +#define SENS_COCPU_SENS2_INT_ST_S 4 +/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ST (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_V 0x1 +#define SENS_COCPU_SENS1_INT_ST_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 + +#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0x0134) +/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_CLR (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_V 0x1 +#define SENS_COCPU_SWD_INT_CLR_S 8 +/* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int clear*/ +#define SENS_COCPU_SW_INT_CLR (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_V 0x1 +#define SENS_COCPU_SW_INT_CLR_S 7 +/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_CLR (BIT(6)) +#define SENS_COCPU_START_INT_CLR_M (BIT(6)) +#define SENS_COCPU_START_INT_CLR_V 0x1 +#define SENS_COCPU_START_INT_CLR_S 6 +/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_V 0x1 +#define SENS_COCPU_TSENS_INT_CLR_S 5 +/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_CLR (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_V 0x1 +#define SENS_COCPU_SENS2_INT_CLR_S 4 +/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_CLR (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_V 0x1 +#define SENS_COCPU_SENS1_INT_CLR_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 + +#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0x0138) +/* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ +/*description: cocpu mem address output*/ +#define SENS_COCPU_MEM_ADDR 0x00001FFF +#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S)) +#define SENS_COCPU_MEM_ADDR_V 0x1FFF +#define SENS_COCPU_MEM_ADDR_S 19 +/* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ +/*description: cocpu mem write enable output*/ +#define SENS_COCPU_MEM_WEN 0x0000000F +#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S)) +#define SENS_COCPU_MEM_WEN_V 0xF +#define SENS_COCPU_MEM_WEN_S 15 +/* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: cocpu mem ready input*/ +#define SENS_COCPU_MEM_RDY (BIT(14)) +#define SENS_COCPU_MEM_RDY_M (BIT(14)) +#define SENS_COCPU_MEM_RDY_V 0x1 +#define SENS_COCPU_MEM_RDY_S 14 +/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: cocpu mem valid output*/ +#define SENS_COCPU_MEM_VLD (BIT(13)) +#define SENS_COCPU_MEM_VLD_M (BIT(13)) +#define SENS_COCPU_MEM_VLD_V 0x1 +#define SENS_COCPU_MEM_VLD_S 13 +/* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: cocpu Program counter*/ +#define SENS_COCPU_PC 0x00001FFF +#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S)) +#define SENS_COCPU_PC_V 0x1FFF +#define SENS_COCPU_PC_S 0 + +#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0x013c) +/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled + by FSM in ULP-coprocessor*/ +#define SENS_HALL_PHASE_FORCE (BIT(31)) +#define SENS_HALL_PHASE_FORCE_M (BIT(31)) +#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_S 31 +/* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Reverse phase of hall sensor*/ +#define SENS_HALL_PHASE (BIT(30)) +#define SENS_HALL_PHASE_M (BIT(30)) +#define SENS_HALL_PHASE_V 0x1 +#define SENS_HALL_PHASE_S 30 +/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by + FSM in ULP-coprocessor*/ +#define SENS_XPD_HALL_FORCE (BIT(29)) +#define SENS_XPD_HALL_FORCE_M (BIT(29)) +#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_S 29 +/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define SENS_XPD_HALL (BIT(28)) +#define SENS_XPD_HALL_M (BIT(28)) +#define SENS_XPD_HALL_V 0x1 +#define SENS_XPD_HALL_S 28 + +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x0140) /* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SENS_SAR_NOUSE 0xFFFFFFFF @@ -1248,8 +1607,8 @@ extern "C" { #define SENS_SAR_NOUSE_V 0xFFFFFFFF #define SENS_SAR_NOUSE_S 0 -#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x00FC) -/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1703080 ; */ +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x0144) +/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809210 ; */ /*description: */ #define SENS_SAR_DATE 0x0FFFFFFF #define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/sens_struct.h b/components/soc/esp32s2beta/include/soc/sens_struct.h index fb0ec358f0..7ad7a8570a 100644 --- a/components/soc/esp32s2beta/include/soc/sens_struct.h +++ b/components/soc/esp32s2beta/include/soc/sens_struct.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -20,82 +20,143 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t sar1_clk_div: 8; /*clock divider*/ - uint32_t sar1_sample_cycle: 8; /*sample cycles for SAR ADC1*/ - uint32_t sar1_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/ + uint32_t sar1_clk_div: 8; /*clock divider*/ + uint32_t sar1_sample_cycle: 8; /*sample cycles for SAR ADC1*/ + uint32_t sar1_sample_bit: 2; /*00: for 9-bit width*/ uint32_t sar1_clk_gated: 1; uint32_t sar1_sample_num: 8; - uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/ - uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ - uint32_t reserved29: 3; + uint32_t reserved27: 1; + uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ + uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/ + uint32_t reserved30: 2; }; uint32_t val; - } sar_read_ctrl; - uint32_t sar_read_status1; /**/ + } sar_reader1_ctrl; + uint32_t sar_reader1_status; /**/ + union { + struct { + uint32_t sar1_bit_width: 2; /*00: 9 bit*/ + uint32_t sar1_stop: 1; /*stop SAR ADC1 conversion*/ + uint32_t reserved3: 21; + uint32_t force_xpd_amp: 2; + uint32_t amp_rst_fb_force: 2; + uint32_t amp_short_ref_force: 2; + uint32_t amp_short_ref_gnd_force: 2; + }; + uint32_t val; + } sar_meas1_ctrl1; + union { + struct { + uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ + uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ + uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/ + uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/ + uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/ + uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/ + }; + uint32_t val; + } sar_meas1_ctrl2; + union { + struct { + uint32_t reserved0: 31; + uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ + }; + uint32_t val; + } sar_meas1_mux; + uint32_t sar_atten1; /*2-bit attenuation for each pad*/ union { struct { uint32_t sar_amp_wait1:16; uint32_t sar_amp_wait2:16; }; uint32_t val; - } sar_meas_wait1; + } sar_amp_ctrl1; union { struct { - uint32_t sar_amp_wait3: 16; - uint32_t force_xpd_amp: 2; - uint32_t force_xpd_sar: 2; - uint32_t sar2_rstb_wait: 8; - uint32_t reserved28: 4; + uint32_t sar1_dac_xpd_fsm_idle: 1; + uint32_t xpd_sar_amp_fsm_idle: 1; + uint32_t amp_rst_fb_fsm_idle: 1; + uint32_t amp_short_ref_fsm_idle: 1; + uint32_t amp_short_ref_gnd_fsm_idle: 1; + uint32_t xpd_sar_fsm_idle: 1; + uint32_t sar_rstb_fsm_idle: 1; + uint32_t reserved7: 9; + uint32_t sar_amp_wait3: 16; }; uint32_t val; - } sar_meas_wait2; + } sar_amp_ctrl2; union { struct { + uint32_t sar1_dac_xpd_fsm: 4; uint32_t xpd_sar_amp_fsm: 4; uint32_t amp_rst_fb_fsm: 4; uint32_t amp_short_ref_fsm: 4; uint32_t amp_short_ref_gnd_fsm: 4; uint32_t xpd_sar_fsm: 4; uint32_t sar_rstb_fsm: 4; - uint32_t sar2_xpd_wait: 8; + uint32_t reserved28: 4; }; uint32_t val; - } sar_meas_ctrl; - uint32_t sar_read_status2; /**/ - uint32_t ulp_cp_sleep_cyc0; /*sleep cycles for ULP-coprocessor timer*/ - uint32_t ulp_cp_sleep_cyc1; /**/ - uint32_t ulp_cp_sleep_cyc2; /**/ - uint32_t ulp_cp_sleep_cyc3; /**/ - uint32_t ulp_cp_sleep_cyc4; /**/ + } sar_amp_ctrl3; union { struct { - uint32_t sar1_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ - uint32_t sar2_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ - uint32_t sar2_en_test: 1; /*SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/ - uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT PA power detector capacitance tuning.*/ - uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/ - uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1*/ - uint32_t sarclk_en: 1; - uint32_t pc_init: 11; /*initialized PC for ULP-coprocessor*/ - uint32_t sar2_stop: 1; /*stop SAR ADC2 conversion*/ - uint32_t sar1_stop: 1; /*stop SAR ADC1 conversion*/ - uint32_t sar2_pwdet_en: 1; /*N/A*/ - uint32_t reserved25: 7; + uint32_t sar2_clk_div: 8; /*clock divider*/ + uint32_t sar2_sample_cycle: 8; /*sample cycles for SAR ADC2*/ + uint32_t sar2_sample_bit: 2; /*00: for 9-bit width*/ + uint32_t sar2_clk_gated: 1; + uint32_t sar2_sample_num: 8; + uint32_t reserved27: 2; + uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ + uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/ + uint32_t reserved31: 1; }; uint32_t val; - } sar_start_force; + } sar_reader2_ctrl; + uint32_t sar_reader2_status; /**/ union { struct { - uint32_t mem_wr_addr_init: 11; - uint32_t mem_wr_addr_size: 11; - uint32_t rtc_mem_wr_offst_clr: 1; - uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/ - uint32_t reserved24: 8; + uint32_t sar2_bit_width: 2; /*00: 9 bit*/ + uint32_t sar2_stop: 1; /*stop SAR ADC2 conversion*/ + uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ + uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/ + uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/ + uint32_t sar2_rstb_force: 2; + uint32_t sar2_standby_wait: 8; + uint32_t sar2_rstb_wait: 8; + uint32_t sar2_xpd_wait: 8; }; uint32_t val; - } sar_mem_wr_ctrl; - uint32_t sar_atten1; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ - uint32_t sar_atten2; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ + } sar_meas2_ctrl1; + union { + struct { + uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ + uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ + uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/ + uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/ + uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/ + uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/ + }; + uint32_t val; + } sar_meas2_ctrl2; + union { + struct { + uint32_t reserved0: 28; + uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ + uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/ + }; + uint32_t val; + } sar_meas2_mux; + uint32_t sar_atten2; /*2-bit attenuation for each pad*/ + union { + struct { + uint32_t reserved0: 23; + uint32_t sar2_dref: 3; /*Adjust saradc2 offset*/ + uint32_t sar1_dref: 3; /*Adjust saradc1 offset*/ + uint32_t force_xpd_sar: 2; + uint32_t sarclk_en: 1; + }; + uint32_t val; + } sar_power_xpd_sar; union { struct { uint32_t i2c_slave_addr1: 11; @@ -117,9 +178,7 @@ typedef volatile struct { struct { uint32_t i2c_slave_addr5:11; uint32_t i2c_slave_addr4:11; - uint32_t tsens_out: 8; /*temperature sensor data out*/ - uint32_t tsens_rdy_out: 1; /*indicate temperature sensor out ready*/ - uint32_t reserved31: 1; + uint32_t reserved22: 10; }; uint32_t val; } sar_slave_addr3; @@ -127,236 +186,339 @@ typedef volatile struct { struct { uint32_t i2c_slave_addr7:11; uint32_t i2c_slave_addr6:11; - uint32_t i2c_rdata: 8; /*I2C read data*/ - uint32_t i2c_done: 1; /*indicate I2C done*/ - uint32_t reserved31: 1; + uint32_t reserved22: 10; }; uint32_t val; } sar_slave_addr4; union { struct { - uint32_t tsens_xpd_wait: 12; - uint32_t tsens_xpd_force: 1; - uint32_t tsens_clk_inv: 1; - uint32_t tsens_clk_gated: 1; - uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ - uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ - uint32_t tsens_power_up: 1; /*temperature sensor power up*/ - uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW 0: by FSM*/ - uint32_t tsens_dump_out: 1; /*temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ - uint32_t tsens_dos: 4; /*Temperature sensor calibration bits*/ - uint32_t tsens_force: 1; /*1: select saradc_reg 0: select efuse*/ + uint32_t tsens_out: 8; /*temperature sensor data out*/ + uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ + uint32_t reserved9: 3; + uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/ + uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ + uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ + uint32_t tsens_power_up: 1; /*temperature sensor power up*/ + uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/ + uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/ + uint32_t tsens_diz: 1; /*ADC input short*/ + uint32_t tsens_div_chop: 2; /*0 for steady phase 0 1 for steady phase 1 2 for chopping with ½ frequency of TSENS_CK 3 for chopping with ¼*/ + uint32_t tsens_dac: 4; /*Temperature sensor offset dac. 15 for 0 offset 5 for -2 7 for -1 11 for 1 10 for 2*/ }; uint32_t val; } sar_tctrl; union { struct { - uint32_t sar_i2c_ctrl: 28; /*I2C control data only active when reg_sar_i2c_start_force = 1*/ - uint32_t sar_i2c_start: 1; /*start I2C only active when reg_sar_i2c_start_force = 1*/ - uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW 0: I2C started by FSM*/ + uint32_t tsens_xpd_wait: 12; + uint32_t tsens_xpd_force: 2; + uint32_t tsens_clk_inv: 1; + uint32_t tsens_clkgate_en: 1; /*temperature sensor clock enable*/ + uint32_t tsens_reset: 1; /*temperature sensor reset*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } sar_tctrl2; + union { + struct { + uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ + uint32_t sar_i2c_start: 1; /*start I2C*/ + uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/ uint32_t reserved30: 2; }; uint32_t val; } sar_i2c_ctrl; union { struct { - uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ - uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ - uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1*/ - uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor*/ - uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/ - uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor*/ + uint32_t touch_outen: 15; /*touch controller output enable*/ + uint32_t touch_status_clr: 1; /*clear all touch active status*/ + uint32_t reserved16: 4; + uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ + uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/ + uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/ }; uint32_t val; - } sar_meas_start1; + } sar_touch_conf; union { struct { - uint32_t touch_meas_delay:16; /*the meas length (in 8MHz)*/ - uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ - uint32_t touch_out_sel: 1; /*1: when the counter is greater then the threshold the touch pad is considered as “touched” 0: when the counter is less than the threshold the touch pad is considered as “touched”*/ - uint32_t touch_out_1en: 1; /*1: wakeup interrupt is generated if SET1 is “touched” 0: wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/ - uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ - uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ - uint32_t reserved28: 4; + uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ + uint32_t reserved22: 10; }; uint32_t val; - } sar_touch_ctrl1; + } touch_thresh[14]; union { struct { - uint32_t l_thresh: 16; /*the threshold for touch pad 1*/ - uint32_t h_thresh: 16; /*the threshold for touch pad 0*/ + uint32_t meas_out: 22; /*the counter for touch pad 1*/ + uint32_t reserved22: 10; }; uint32_t val; - } touch_thresh[5]; + } touch_meas[15]; union { struct { - uint32_t l_val: 16; /*the counter for touch pad 1*/ - uint32_t h_val: 16; /*the counter for touch pad 0*/ + uint32_t touch_pad_active: 15; /*touch active status*/ + uint32_t touch_channel_clr:15; /*Clear touch channel*/ + uint32_t reserved30: 1; + uint32_t touch_meas_done: 1; }; uint32_t val; - } touch_meas[5]; + } sar_touch_chn_st; union { struct { - uint32_t touch_meas_en: 10; /*10-bit register to indicate which pads are “touched”*/ - uint32_t touch_meas_done: 1; /*fsm set 1 to indicate touch touch meas is done*/ - uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers*/ - uint32_t touch_start_en: 1; /*1: start touch fsm valid when reg_touch_start_force is set*/ - uint32_t touch_start_force: 1; /*1: to start touch fsm by SW 0: to start touch fsm by timer*/ - uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/ - uint32_t touch_meas_en_clr: 1; /*to clear reg_touch_meas_en*/ - uint32_t reserved31: 1; + uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/ + uint32_t touch_scan_curr: 4; + uint32_t reserved26: 6; }; uint32_t val; - } sar_touch_ctrl2; - uint32_t reserved_88; + } sar_touch_status0; union { struct { - uint32_t touch_pad_worken:10; /*Bitmap defining the working set during the measurement.*/ - uint32_t touch_pad_outen2:10; /*Bitmap defining SET2 for generating wakeup interrupt. SET2 is “touched” only if at least one of touch pad in SET2 is “touched”.*/ - uint32_t touch_pad_outen1:10; /*Bitmap defining SET1 for generating wakeup interrupt. SET1 is “touched” only if at least one of touch pad in SET1 is “touched”.*/ - uint32_t reserved30: 2; + uint32_t touch_pad_baseline: 22; + uint32_t reserved22: 7; + uint32_t touch_pad_debounce: 3; }; uint32_t val; - } sar_touch_enable; + } sar_touch_status[14]; +// union { +// struct { +// uint32_t touch_pad2_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad2_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status2; +// union { +// struct { +// uint32_t touch_pad3_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad3_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status3; +// union { +// struct { +// uint32_t touch_pad4_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad4_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status4; +// union { +// struct { +// uint32_t touch_pad5_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad5_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status5; +// union { +// struct { +// uint32_t touch_pad6_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad6_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status6; +// union { +// struct { +// uint32_t touch_pad7_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad7_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status7; +// union { +// struct { +// uint32_t touch_pad8_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad8_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status8; +// union { +// struct { +// uint32_t touch_pad9_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad9_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status9; +// union { +// struct { +// uint32_t touch_pad10_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad10_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status10; +// union { +// struct { +// uint32_t touch_pad11_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad11_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status11; +// union { +// struct { +// uint32_t touch_pad12_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad12_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status12; +// union { +// struct { +// uint32_t touch_pad13_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad13_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status13; +// union { +// struct { +// uint32_t touch_pad14_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_pad14_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status14; +// union { +// struct { +// uint32_t touch_slp_baseline:22; +// uint32_t reserved22: 7; +// uint32_t touch_slp_debounce: 3; +// }; +// uint32_t val; +// } sar_touch_status15; union { struct { - uint32_t touch_meas_raw:10; /*touch sensor raw result*/ - uint32_t reserved10: 22; + uint32_t touch_approach_pad2_cnt: 8; + uint32_t touch_approach_pad1_cnt: 8; + uint32_t touch_approach_pad0_cnt: 8; + uint32_t touch_slp_approach_cnt: 8; }; uint32_t val; - } sar_touch_ctrl3; + } sar_touch_status16; union { struct { - uint32_t sar2_clk_div: 8; /*clock divider*/ - uint32_t sar2_sample_cycle: 8; /*sample cycles for SAR ADC2*/ - uint32_t sar2_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/ - uint32_t sar2_clk_gated: 1; - uint32_t sar2_sample_num: 8; - uint32_t sar2_pwdet_force: 1; - uint32_t sar2_dig_force: 1; /*1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL*/ - uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ - uint32_t reserved30: 2; - }; - uint32_t val; - } sar_read_ctrl2; - union { - struct { - uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ - uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ - uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1*/ - uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor*/ - uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/ - uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor*/ - }; - uint32_t val; - } sar_meas_start2; - union { - struct { - uint32_t sw_fstep: 16; /*frequency step for CW generator can be used to adjust the frequency*/ - uint32_t sw_tone_en: 1; /*1: enable CW generator 0: disable CW generator*/ + uint32_t sw_fstep: 16; /*frequency step for CW generator*/ + uint32_t sw_tone_en: 1; /*1: enable CW generator*/ uint32_t debug_bit_sel: 5; - uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/ - uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ - uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ - uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ + uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/ + uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ + uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ + uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ uint32_t reserved26: 6; }; uint32_t val; } sar_dac_ctrl1; union { struct { - uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ - uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ - uint32_t dac_scale1: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ - uint32_t dac_scale2: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ - uint32_t dac_inv1: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/ - uint32_t dac_inv2: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/ - uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/ - uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/ + uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ + uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ + uint32_t dac_scale1: 2; /*00: no scale*/ + uint32_t dac_scale2: 2; /*00: no scale*/ + uint32_t dac_inv1: 2; /*00: do not invert any bits*/ + uint32_t dac_inv2: 2; /*00: do not invert any bits*/ + uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/ + uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/ uint32_t reserved26: 6; }; uint32_t val; } sar_dac_ctrl2; union { struct { - uint32_t sar1_dac_xpd_fsm: 4; - uint32_t sar1_dac_xpd_fsm_idle: 1; - uint32_t xpd_sar_amp_fsm_idle: 1; - uint32_t amp_rst_fb_fsm_idle: 1; - uint32_t amp_short_ref_fsm_idle: 1; - uint32_t amp_short_ref_gnd_fsm_idle: 1; - uint32_t xpd_sar_fsm_idle: 1; - uint32_t sar_rstb_fsm_idle: 1; - uint32_t sar2_rstb_force: 2; - uint32_t amp_rst_fb_force: 2; - uint32_t amp_short_ref_force: 2; - uint32_t amp_short_ref_gnd_force: 2; - uint32_t reserved19: 13; + uint32_t reserved0: 25; + uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ + uint32_t clk_en: 1; /*check cocpu whether clk on*/ + uint32_t reset_n: 1; /*check cocpu whether in reset state*/ + uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ + uint32_t trap: 1; /*check cocpu whether in trap state*/ + uint32_t ebreak: 1; /*check cocpu whether in ebreak*/ + uint32_t reserved31: 1; }; uint32_t val; - } sar_meas_ctrl2; + } sar_cocpu_state; union { struct { - uint32_t clk_fo: 1; /*cocpu clk force on*/ - uint32_t start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/ - uint32_t start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/ - uint32_t shut: 1; /*to shut cocpu*/ - uint32_t shut_2_clk_dis: 6; /*time from shut cocpu to disable clk*/ - uint32_t shut_reset_en: 1; /*to reset cocpu*/ - uint32_t sel: 1; /*1: old ULP 0: new riscV*/ - uint32_t done_force: 1; /*1: select riscv done 0: select ulp done*/ - uint32_t done: 1; /*done signal used by riscv to control timer.*/ - uint32_t int_trigger: 1; /*trigger cocpu register interrupt*/ - uint32_t clk_en: 1; /*check cocpu whether clk on*/ - uint32_t reset_n: 1; /*check cocpu whether in reset state*/ - uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ - uint32_t trap: 1; /*check cocpu whether in trap state*/ - uint32_t reserved29: 3; + uint32_t touch_done: 1; /*int from touch done*/ + uint32_t touch_inactive: 1; /*int from touch inactive*/ + uint32_t touch_active: 1; /*int from touch active*/ + uint32_t saradc1: 1; /*int from saradc1*/ + uint32_t saradc2: 1; /*int from saradc2*/ + uint32_t tsens: 1; /*int from tsens*/ + uint32_t start: 1; /*int from start*/ + uint32_t sw: 1; /*int from software*/ + uint32_t swd: 1; /*int from super watch dog*/ + uint32_t reserved9: 23; }; uint32_t val; - } sar_cocpu_ctrl; + } sar_cocpu_int_raw; union { struct { - uint32_t saradc_int_ena: 1; - uint32_t tsens_int_ena: 1; - uint32_t start_int_ena: 1; - uint32_t cocpu_int_ena: 1; - uint32_t ebreak_int_ena: 1; /*int enable entry*/ - uint32_t reserved5: 5; - uint32_t saradc_int_clr: 1; - uint32_t tsens_int_clr: 1; - uint32_t start_int_clr: 1; - uint32_t cocpu_int_clr: 1; - uint32_t ebreak_int_clr: 1; /*int clear entry*/ - uint32_t reserved15: 5; - uint32_t saradc_int: 1; /*int from saradc*/ - uint32_t tsens_int: 1; /*int from tsens*/ - uint32_t start_int: 1; /*int from start*/ - uint32_t cocpu_int: 1; /*int from register*/ - uint32_t ebreak_int: 1; /*int from ebreak*/ - uint32_t reserved25: 7; + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int enable*/ + uint32_t swd: 1; + uint32_t reserved9: 23; }; uint32_t val; - } sar_cocpu_int; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t sar_nouse; /**/ + } sar_cocpu_int_ena; + union { + struct { + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int status*/ + uint32_t swd: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } sar_cocpu_int_st; + union { + struct { + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int clear*/ + uint32_t swd: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } sar_cocpu_int_clr; + union { + struct { + uint32_t pc: 13; /*cocpu Program counter*/ + uint32_t mem_vld: 1; /*cocpu mem valid output*/ + uint32_t mem_rdy: 1; /*cocpu mem ready input*/ + uint32_t mem_wen: 4; /*cocpu mem write enable output*/ + uint32_t mem_addr: 13; /*cocpu mem address output*/ + }; + uint32_t val; + } sar_cocpu_debug; + union { + struct { + uint32_t reserved0: 28; + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ + }; + uint32_t val; + } sar_hall_ctrl; + uint32_t sar_nouse; /**/ union { struct { uint32_t sar_date: 28; diff --git a/components/soc/esp32s2beta/include/soc/touch_channel.h b/components/soc/esp32s2beta/include/soc/touch_channel.h index a9aa838b4e..0ee4389118 100644 --- a/components/soc/esp32s2beta/include/soc/touch_channel.h +++ b/components/soc/esp32s2beta/include/soc/touch_channel.h @@ -16,34 +16,46 @@ #define _SOC_TOUCH_CHANNEL_H //Touch channels -#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0 -#define TOUCH_PAD_NUM0_GPIO_NUM 4 - -#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1 -#define TOUCH_PAD_NUM1_GPIO_NUM 0 +#define TOUCH_PAD_GPIO1_CHANNEL TOUCH_PAD_NUM1 +#define TOUCH_PAD_NUM1_GPIO_NUM 1 #define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2 #define TOUCH_PAD_NUM2_GPIO_NUM 2 -#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3 -#define TOUCH_PAD_NUM3_GPIO_NUM 15 +#define TOUCH_PAD_GPIO3_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 3 -#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4 -#define TOUCH_PAD_NUM4_GPIO_NUM 13 +#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 4 -#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5 -#define TOUCH_PAD_NUM5_GPIO_NUM 12 +#define TOUCH_PAD_GPIO5_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 5 -#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6 -#define TOUCH_PAD_NUM6_GPIO_NUM 14 +#define TOUCH_PAD_GPIO6_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 6 -#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7 -#define TOUCH_PAD_NUM7_GPIO_NUM 27 +#define TOUCH_PAD_GPIO7_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 7 -#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8 -#define TOUCH_PAD_NUM8_GPIO_NUM 33 +#define TOUCH_PAD_GPIO8_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 8 -#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9 -#define TOUCH_PAD_NUM9_GPIO_NUM 32 +#define TOUCH_PAD_GPIO9_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 9 + +#define TOUCH_PAD_GPIO10_CHANNEL TOUCH_PAD_NUM10 +#define TOUCH_PAD_NUM10_GPIO_NUM 10 + +#define TOUCH_PAD_GPIO11_CHANNEL TOUCH_PAD_NUM11 +#define TOUCH_PAD_NUM11_GPIO_NUM 11 + +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM12 +#define TOUCH_PAD_NUM12_GPIO_NUM 12 + +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM13 +#define TOUCH_PAD_NUM13_GPIO_NUM 13 + +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM14 +#define TOUCH_PAD_NUM14_GPIO_NUM 14 #endif diff --git a/components/ulp/ulp.c b/components/ulp/ulp.c index fb5760ebd2..c19130b729 100644 --- a/components/ulp/ulp.c +++ b/components/ulp/ulp.c @@ -48,6 +48,7 @@ static const char* TAG = "ulp"; esp_err_t ulp_run(uint32_t entry_point) { +#if CONFIG_IDF_TARGET_ESP32 // disable ULP timer CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); // wait for at least 1 RTC_SLOW_CLK cycle @@ -64,6 +65,7 @@ esp_err_t ulp_run(uint32_t entry_point) SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M); // enable ULP timer SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); +#endif return ESP_OK; } @@ -112,6 +114,7 @@ esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, siz esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) { +#if CONFIG_IDF_TARGET_ESP32 if (period_index > 4) { return ESP_ERR_INVALID_ARG; } @@ -128,5 +131,6 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) } REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t), SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); +#endif return ESP_OK; } diff --git a/examples/peripherals/adc/main/adc1_example_main.c b/examples/peripherals/adc/main/adc1_example_main.c index 00de0ab8bf..ddedbdc519 100644 --- a/examples/peripherals/adc/main/adc1_example_main.c +++ b/examples/peripherals/adc/main/adc1_example_main.c @@ -12,8 +12,9 @@ #include "freertos/task.h" #include "driver/gpio.h" #include "driver/adc.h" -#include "esp_adc_cal.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp_adc_cal.h" #define DEFAULT_VREF 1100 //Use adc2_vref_to_gpio() to obtain a better estimate #define NO_OF_SAMPLES 64 //Multisampling @@ -89,4 +90,42 @@ void app_main() } } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + +#define NO_OF_SAMPLES 64 //Multisampling + +static const adc_channel_t channel = ADC_CHANNEL_6; // GPIO7 if ADC1, GPIO17 if ADC2 +static const adc_atten_t atten = ADC_ATTEN_DB_11; // Detect 0 ~ 3.6v +static const adc_unit_t unit = ADC_UNIT_2; +static const adc_unit_t width = ADC_WIDTH_BIT_12; + +void app_main() +{ + //Configure ADC + if (unit == ADC_UNIT_1) { + adc1_config_width(width); + adc1_config_channel_atten(channel, atten); + } else { + adc2_config_channel_atten((adc2_channel_t)channel, atten); + } + + //Continuously sample ADC1 + while (1) { + uint32_t adc_reading = 0; + // Multisampling + for (int i = 0; i < NO_OF_SAMPLES; i++) { + if (unit == ADC_UNIT_1) { + adc_reading += adc1_get_raw((adc1_channel_t)channel); + } else { + int raw; + adc2_get_raw((adc2_channel_t)channel, width, &raw); + adc_reading += raw; + } + } + adc_reading /= NO_OF_SAMPLES; + printf("ADC%d CH%d Raw: %d\t\n", unit, channel, adc_reading); + vTaskDelay(pdMS_TO_TICKS(1000)); + } +} +#endif diff --git a/examples/peripherals/adc2/main/adc2_example_main.c b/examples/peripherals/adc2/main/adc2_example_main.c index ccf32b3d5f..bfd305b647 100644 --- a/examples/peripherals/adc2/main/adc2_example_main.c +++ b/examples/peripherals/adc2/main/adc2_example_main.c @@ -15,7 +15,6 @@ #include "driver/adc.h" #include "driver/dac.h" #include "esp_system.h" -#include "esp_adc_cal.h" #define DAC_EXAMPLE_CHANNEL CONFIG_EXAMPLE_DAC_CHANNEL #define ADC2_EXAMPLE_CHANNEL CONFIG_EXAMPLE_ADC2_CHANNEL diff --git a/examples/peripherals/temp_sensor/CMakeLists.txt b/examples/peripherals/temp_sensor/CMakeLists.txt new file mode 100644 index 0000000000..bd14a9425f --- /dev/null +++ b/examples/peripherals/temp_sensor/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(temp_sensor) diff --git a/examples/peripherals/temp_sensor/Makefile b/examples/peripherals/temp_sensor/Makefile new file mode 100644 index 0000000000..7cb5326291 --- /dev/null +++ b/examples/peripherals/temp_sensor/Makefile @@ -0,0 +1,9 @@ +# +# This is a project Makefile. It is assumed the directory this Makefile resides in is a +# project subdirectory. +# + +PROJECT_NAME := temp_sensor + +include $(IDF_PATH)/make/project.mk + diff --git a/examples/peripherals/temp_sensor/README.md b/examples/peripherals/temp_sensor/README.md new file mode 100644 index 0000000000..e69de29bb2 diff --git a/examples/peripherals/temp_sensor/main/CMakeLists.txt b/examples/peripherals/temp_sensor/main/CMakeLists.txt new file mode 100644 index 0000000000..91425ac9f4 --- /dev/null +++ b/examples/peripherals/temp_sensor/main/CMakeLists.txt @@ -0,0 +1,4 @@ +set(COMPONENT_SRCS "temp_sensor_main.c") +set(COMPONENT_ADD_INCLUDEDIRS ".") + +register_component() diff --git a/examples/peripherals/temp_sensor/main/component.mk b/examples/peripherals/temp_sensor/main/component.mk new file mode 100644 index 0000000000..44bd2b5273 --- /dev/null +++ b/examples/peripherals/temp_sensor/main/component.mk @@ -0,0 +1,3 @@ +# +# Main Makefile. This is basically the same as a component makefile. +# diff --git a/examples/peripherals/temp_sensor/main/temp_sensor_main.c b/examples/peripherals/temp_sensor/main/temp_sensor_main.c new file mode 100644 index 0000000000..6d63d764a8 --- /dev/null +++ b/examples/peripherals/temp_sensor/main/temp_sensor_main.c @@ -0,0 +1,46 @@ +/* ADC1 Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#include +#include +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/temp_sensor.h" + +#if CONFIG_IDF_TARGET_ESP32S2BETA + +static const char* TAG = "TempSensor"; + +void tempsensor_example(void *arg) +{ + // Initialize touch pad peripheral, it will start a timer to run a filter + ESP_LOGI(TAG, "Initializing temp sensor"); + uint8_t temp_out; + temp_sensor_t temp_sensor; + temp_sensor_get_config(&temp_sensor); + ESP_LOGI(TAG, "default dac %d, clk_div %d", temp_sensor.dac_offset, temp_sensor.clk_div); + temp_sensor.dac_offset = TEMP_SENSOR_DAC_DEFAULT; // DEFAULT: range:-10℃ ~ 80℃, error < 1℃. + temp_sensor_set_config(temp_sensor); + temp_sensor_start(); + ESP_LOGI(TAG, "temp sensor started"); + while(1) { + vTaskDelay(1000 / portTICK_RATE_MS); + temp_sensor_read(&temp_out); + ESP_LOGI(TAG, "temp out %d", temp_out); + } + ESP_LOGI(TAG, "test over"); + vTaskDelete(NULL); +} + +void app_main() +{ + xTaskCreate(tempsensor_example, "temp", 2048, NULL, 5, NULL); +} +#endif + diff --git a/examples/peripherals/touch_pad_interrupt/main/tp_interrupt_main.c b/examples/peripherals/touch_pad_interrupt/main/tp_interrupt_main.c index 1ed6bcabd3..2381ef8b2f 100644 --- a/examples/peripherals/touch_pad_interrupt/main/tp_interrupt_main.c +++ b/examples/peripherals/touch_pad_interrupt/main/tp_interrupt_main.c @@ -9,6 +9,7 @@ #include #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "freertos/queue.h" #include "esp_log.h" #include "driver/touch_pad.h" @@ -16,6 +17,8 @@ #include "soc/sens_periph.h" static const char* TAG = "Touch pad"; + +#if CONFIG_IDF_TARGET_ESP32 #define TOUCH_THRESH_NO_USE (0) #define TOUCH_THRESH_PERCENT (80) #define TOUCHPAD_FILTER_TOUCH_PERIOD (10) @@ -167,3 +170,187 @@ void app_main() // Start a task to show what pads have been touched xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 2048, NULL, 5, NULL); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + +static QueueHandle_t que_touch = NULL; +typedef struct touch_msg { + touch_pad_intr_mask_t intr_mask; + uint32_t pad_num; + uint32_t pad_status; + uint32_t pad_val; +}touch_event_t; + +#define TOUCH_BUTTON_NUM 4 +#define TOUCH_BUTTON_WATERPROOF_ENABLE 1 +#define TOUCH_BUTTON_DENOISE_ENABLE 1 + +static const touch_pad_t button[TOUCH_BUTTON_NUM] = { + TOUCH_PAD_NUM7, // 'SELECT' button. + TOUCH_PAD_NUM9, // 'MENU' button. + TOUCH_PAD_NUM11, // 'BACK' button. + TOUCH_PAD_NUM13, // Guard ring for waterproof design. + // if this pad be touched, other pads no response. +}; + +/* + * Touch threshold. The threshold determines the sensitivity of the touch. + * This threshold is derived by testing changes in readings from different touch channels. + * If (raw_data - baseline) > baseline * threshold, the pad be actived. + * If (raw_data - baseline) < baseline * threshold, the pad be inactived. + */ +static const float button_threshold[TOUCH_BUTTON_NUM] = { + 0.2, // 20%. + 0.2, // 20%. + 0.2, // 20%. + 0.1, // 10%. +}; + +/* + Handle an interrupt triggered when a pad is touched. + Recognize what pad has been touched and save it in a table. + */ +static void touchsensor_interrupt_cb(void * arg) +{ + int task_awoken = pdFALSE; + touch_event_t evt; + + evt.intr_mask = touch_pad_get_int_status(); + evt.pad_status = touch_pad_get_status(); + evt.pad_num = touch_pad_get_scan_curr(); + + if(evt.intr_mask & TOUCH_PAD_INTR_MASK_DONE) { + touch_pad_filter_baseline_read(evt.pad_num, &evt.pad_val); + } + xQueueSendFromISR(que_touch, &evt, &task_awoken); + if (task_awoken == pdTRUE) { + portYIELD_FROM_ISR(); + } +} + +static void tp_example_set_thresholds(void) +{ + uint32_t touch_value; + for (int i = 0; i