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Merge branch 'bugfix/fix_psram_access_faild_after_pd_cpu_wakeup_v5.1' into 'release/v5.1'

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fix(esp_pm): fix psram access failed after pd_cpu wakeup if uart driver driven console is used (backport v5.1)

See merge request espressif/esp-idf!27051
This commit is contained in:
Jiang Jiang Jian
2023-11-22 17:44:32 +08:00
parent ecbbd3c3d9 46dae91a39
commit b09e1d860d
3 changed files with 30 additions and 11 deletions
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24
components/esp_pm/Kconfig
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@@ -96,18 +96,28 @@ menu "Power Management"
select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
default y default y
help help
If enabled, the CPU will be powered down in light sleep. On esp32c3 soc, enabling this If enabled, the CPU will be powered down in light sleep, ESP chips supports saving and restoring
option will consume 1.68 KB of internal RAM and will reduce sleep current consumption CPU's running context before and after light sleep, the feature provides applications with seamless
by about 100 uA. On esp32s3 soc, enabling this option will consume 8.58 KB of internal CPU powerdowned lightsleep without user awareness.
RAM and will reduce sleep current consumption by about 650 uA. But this will takes up some internal memory. On esp32c3 soc, enabling this option will consume 1.68 KB
of internal RAM and will reduce sleep current consumption by about 100 uA. On esp32s3 soc, enabling this
option will consume 8.58 KB of internal RAM and will reduce sleep current consumption by about 650 uA.
config PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP config PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
bool "Power down I/D-cache tag memory in light sleep" bool "Restore I/D-cache tag memory after power down CPU light sleep"
depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
default y default y
help help
If enabled, the I/D-cache tag memory will be retained in light sleep. Depending on the the Cache tag memory and CPU both belong to the CPU power domain. ESP chips supports saving and restoring
cache configuration, if this option is enabled, it will consume up to 9 KB of internal RAM. Cache tag memory before and after sleep, this feature supports accesses to the external memory that was
cached before sleep still be cached when the CPU wakes up from a powerdowned CPU lightsleep. This option
controls the restore method for Cache tag memory in lightsleep.
If this option is enabled, the I/D-cache tag memory will be backuped to the internal RAM before sleep and
restored upon wakeup. Depending on the the cache configuration, if this option is enabled, it will consume
up to 9 KB of internal RAM.
If this option is disabled, all cached data won't be kept after sleep, the DCache will be writeback before
sleep and invalid all cached data after sleep, all accesses to external memory(Flash/PSRAM) will be cache
missed after waking up, resulting in performance degradation due to increased memory accesses latency.
config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)" bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)"

7
components/esp_pm/pm_impl.c
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@@ -437,8 +437,11 @@ esp_err_t esp_pm_configure(const void* vconfig)
min_freq_mhz, min_freq_mhz,
config->light_sleep_enable ? "ENABLED" : "DISABLED"); config->light_sleep_enable ? "ENABLED" : "DISABLED");
portENTER_CRITICAL(&s_switch_lock); // CPU & Modem power down initialization, which must be initialized before s_light_sleep_en set true,
// to avoid entering idle and sleep in this function.
esp_pm_sleep_configure(config);
portENTER_CRITICAL(&s_switch_lock);
bool res __attribute__((unused)); bool res __attribute__((unused));
res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]); res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]);
assert(res); assert(res);
@@ -451,8 +454,6 @@ esp_err_t esp_pm_configure(const void* vconfig)
s_config_changed = true; s_config_changed = true;
portEXIT_CRITICAL(&s_switch_lock); portEXIT_CRITICAL(&s_switch_lock);
esp_pm_sleep_configure(config);
return ESP_OK; return ESP_OK;
} }

10
components/hal/esp32s3/rtc_cntl_hal.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -68,6 +68,14 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr)
); );
rtc_cntl_ll_enable_cpu_retention_clock(); rtc_cntl_ll_enable_cpu_retention_clock();
rtc_cntl_ll_enable_cpu_retention(); rtc_cntl_ll_enable_cpu_retention();
#if SOC_PM_SUPPORT_TAGMEM_PD
if (!retent->tagmem.dcache.enable) {
// Here we only need to care for the safety of the PSRAM data in the DCache.
// Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be
// modified in the sleep process code after now, so it is safe to writeback here.
Cache_WriteBack_All();
}
#endif
} }
} }
} }