diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 621abdb831..1db5044220 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -573,7 +573,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n #endif ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk); - /* keep ESP_PD_DOMAIN_RTC8M on during light sleep */ + /* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */ esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RTC8M); portENTER_CRITICAL(&ledc_spinlock); diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 0d35e41999..956f768668 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -70,6 +70,9 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_ds.c") endif() + if(CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT) + list(APPEND srcs "modem_clock.c") + endif() else() # Requires "_esp_error_check_failed()" function list(APPEND priv_requires "esp_system") diff --git a/components/esp_hw_support/include/esp_private/esp_modem_clock.h b/components/esp_hw_support/include/esp_private/esp_modem_clock.h new file mode 100644 index 0000000000..8b406550c6 --- /dev/null +++ b/components/esp_hw_support/include/esp_private/esp_modem_clock.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include + +#include "soc/periph_defs.h" +#include "hal/modem_clock_types.h" + +#if SOC_MODEM_CLOCK_IS_INDEPENDENT +#include "hal/modem_clock_hal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the clock of modem module + * + * Solve the clock dependency between modem modules, For example, the wifi + * module depends on the wifi mac, wifi baseband and FE, when wifi module + * clock is enabled, the wifi MAC, baseband and FE clocks will be enabled + * + * @param module modem module + */ +void modem_clock_module_enable(periph_module_t module); + +/** + * @brief Disable the clock of modem module + * + * @param module modem module + */ +void modem_clock_module_disable(periph_module_t module); + +/** + * @brief Initialize the clock gating control signal of each clock domain of the modem + * + * This is a global modem clock gating signal initialization interface, which is + * only configured during system initialization, and each modem module cannot + * use this interface. + */ +void modem_clock_domain_pmu_state_icg_map_init(void); + +/** + * @brief Select the modem module lowpower clock source and configure the clock divider + * + * @param module modem module + * @param src lowpower clock source + * @param divider divider value to lowpower clock source + */ +void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpclk_src_t src, uint32_t divider); + +/** + * @brief Disable lowpower clock source selection + */ +void modem_clock_deselect_lp_clock_source(periph_module_t module); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index 5039def888..17550d8aab 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -47,14 +47,24 @@ typedef enum { ESP_PD_DOMAIN_RTC_FAST_MEM, //!< RTC fast memory #endif ESP_PD_DOMAIN_XTAL, //!< XTAL oscillator +#if SOC_PM_SUPPORT_XTAL32K_PD + ESP_PD_DOMAIN_XTAL32K, +#endif +#if SOC_PM_SUPPORT_RC32K_PD + ESP_PD_DOMAIN_RC32K, +#endif +#if SOC_PM_SUPPORT_RC_FAST_PD + ESP_PD_DOMAIN_RC_FAST, //!< Internal Fast oscillator +#endif #if SOC_PM_SUPPORT_CPU_PD ESP_PD_DOMAIN_CPU, //!< CPU core #endif - ESP_PD_DOMAIN_RTC8M, //!< Internal 8M oscillator ESP_PD_DOMAIN_VDDSDIO, //!< VDD_SDIO ESP_PD_DOMAIN_MAX //!< Number of domains } esp_sleep_pd_domain_t; +#define ESP_PD_DOMAIN_RTC8M _Pragma("GCC warning \"'ESP_PD_DOMAIN_RTC8M' enum is deprecated\"") ESP_PD_DOMAIN_RC_FAST + /** * @brief Power down options */ diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c new file mode 100644 index 0000000000..cd9773ad41 --- /dev/null +++ b/components/esp_hw_support/modem_clock.c @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "soc/soc.h" +#include "freertos/FreeRTOS.h" +#include "hal/clk_gate_ll.h" +#include "esp_private/esp_modem_clock.h" +#include "esp_sleep.h" + +// Please define the frequently called modules in the low bit, +// which will improve the execution efficiency +typedef enum { + MODEM_CLOCK_FE = BIT(0), + MODEM_CLOCK_COEXIST = BIT(1), + MODEM_CLOCK_I2C_MASTER = BIT(2), + MODEM_CLOCK_WIFI_MAC = BIT(3), + MODEM_CLOCK_WIFI_BB = BIT(4), + MODEM_CLOCK_ETM = BIT(5), + MODEM_CLOCK_BLE_MAC = BIT(6), + MODEM_CLOCK_BLE_BB = BIT(7), + MODEM_CLOCK_802154_MAC = BIT(8), + MODEM_CLOCK_DATADUMP = BIT(9), + MODEM_CLOCK_DEVICE_MAX = 10 +} modem_clock_device_t; + + +typedef struct modem_clock_context { + modem_clock_hal_context_t *hal; + portMUX_TYPE lock; + struct { + int16_t refs; + uint16_t reserved; /* reserved for 4 bytes aligned */ + void (*configure)(struct modem_clock_context *, bool); + } dev[MODEM_CLOCK_DEVICE_MAX]; + /* the low-power clock source for each module */ + modem_clock_lpclk_src_t lpclk_src[PERIPH_MODEM_MODULE_NUM]; +} modem_clock_context_t; + + +static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifi_mac_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_wifibb_160x1_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_80x1_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_40x1_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_80x_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_40x_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_80m_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_44m_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_40m_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_wifibb_22m_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_etm_clock(ctx->hal->syscon_dev, enable); + modem_syscom_ll_enable_modem_sec_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_ble_timer_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_ble_bb_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_bt_apb_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_bt_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_ieee802154_mac_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_ieee802154_apb_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_ieee802154_mac_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_lpcon_ll_enable_coex_clock(ctx->hal->lpcon_dev, enable); +} + +static void IRAM_ATTR modem_clock_fe_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_fe_apb_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_cal_160m_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_160m_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_80m_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_lpcon_ll_enable_i2c_master_clock(ctx->hal->lpcon_dev, enable); + modem_lpcon_ll_enable_i2c_master_160m_clock(ctx->hal->lpcon_dev, enable); +} + +static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_etm_clock(ctx->hal->syscon_dev, enable); +} + +static void IRAM_ATTR modem_clock_data_dump_configure(modem_clock_context_t *ctx, bool enable) +{ + modem_syscon_ll_enable_data_dump_clock(ctx->hal->syscon_dev, enable); + modem_syscon_ll_enable_data_dump_mux_clock(ctx->hal->syscon_dev, enable); +} + +modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(void) +{ + /* It should be explicitly defined in the internal RAM */ + static DRAM_ATTR modem_clock_hal_context_t modem_clock_hal = { .syscon_dev = &MODEM_SYSCON, .lpcon_dev = &MODEM_LPCON }; + static DRAM_ATTR modem_clock_context_t modem_clock_context = { + .hal = &modem_clock_hal, .lock = portMUX_INITIALIZER_UNLOCKED, + .dev = { + { .refs = 0, .configure = modem_clock_fe_configure }, + { .refs = 0, .configure = modem_clock_coex_configure }, + { .refs = 0, .configure = modem_clock_i2c_master_configure }, + { .refs = 0, .configure = modem_clock_wifi_mac_configure }, + { .refs = 0, .configure = modem_clock_wifi_bb_configure }, + { .refs = 0, .configure = modem_clock_etm_configure }, + { .refs = 0, .configure = modem_clock_ble_mac_configure }, + { .refs = 0, .configure = modem_clock_ble_bb_configure }, + { .refs = 0, .configure = modem_clock_ieee802154_mac_configure }, + { .refs = 0, .configure = modem_clock_data_dump_configure } + }, + .lpclk_src = { [0 ... PERIPH_MODEM_MODULE_NUM - 1] = MODEM_CLOCK_LPCLK_SRC_INVALID } + }; + return &modem_clock_context; +} + + +// TODO: IDF-5351: move to esp_pmu.h after support pmu driver +#define PMU_SLEEP 0 +#define PMU_MODEM 1 +#define PMU_ACTIVE 2 +#define SLEEP_MODE BIT(PMU_SLEEP) +#define MODEM_MODE BIT(PMU_MODEM) +#define ACTIVE_MODE BIT(PMU_ACTIVE) + +static void IRAM_ATTR modem_clock_domain_power_state_icg_map_init(modem_clock_context_t *ctx) +{ + /* the ICG code's bit 0, 1 and 2 indicates the ICG state + * of pmu SLEEP, MODEM and ACTIVE mode respectively */ + const uint32_t code[MODEM_CLOCK_DOMAIN_MAX] = { + [MODEM_CLOCK_DOMAIN_MODEM_APB] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_WIFI] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_BT] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_FE] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_IEEE802154] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_LP_APB] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_I2C_MASTER] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_COEX] = MODEM_MODE | ACTIVE_MODE, + [MODEM_CLOCK_DOMAIN_WIFIPWR] = MODEM_MODE | ACTIVE_MODE, + }; + for (modem_clock_domain_t domain = MODEM_CLOCK_DOMAIN_MODEM_APB; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) { + modem_clock_hal_set_clock_domain_icg_bitmap(ctx->hal, domain, code[domain]); + } +} + + +#include "soc/pmu_reg.h" +void modem_clock_domain_pmu_state_icg_map_init(void) +{ + // Set modem clock ICG code map, should implement with pmu driver // TODO: IDF-5351 + REG_SET_FIELD(PMU_HP_SLEEP_ICG_MODEM_REG, PMU_HP_SLEEP_DIG_ICG_MODEM_CODE, PMU_SLEEP); + REG_SET_FIELD(PMU_HP_MODEM_ICG_MODEM_REG, PMU_HP_MODEM_DIG_ICG_MODEM_CODE, PMU_MODEM); + REG_SET_FIELD(PMU_HP_ACTIVE_ICG_MODEM_REG, PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE, PMU_ACTIVE); + REG_SET_BIT(PMU_IMM_MODEM_ICG_REG, PMU_UPDATE_DIG_ICG_MODEM_EN); + REG_SET_BIT(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_ICG_SWITCH); + + modem_clock_domain_power_state_icg_map_init(MODEM_CLOCK_instance()); +} + +static void IRAM_ATTR modem_clock_device_enable(modem_clock_context_t *ctx, uint32_t dev_map) +{ + int16_t refs = 0; + portENTER_CRITICAL_SAFE(&ctx->lock); + for (int i = 0; dev_map; dev_map >>= 1, i++) { + if (dev_map & BIT(0)) { + refs = ctx->dev[i].refs++; + if (refs == 0) { + (*ctx->dev[i].configure)(ctx, true); + } + } + } + portEXIT_CRITICAL_SAFE(&ctx->lock); + assert(refs >= 0); +} + +static void IRAM_ATTR modem_clock_device_disable(modem_clock_context_t *ctx, uint32_t dev_map) +{ + int16_t refs = 0; + portENTER_CRITICAL_SAFE(&ctx->lock); + for (int i = 0; dev_map; dev_map >>= 1, i++) { + if (dev_map & BIT(0)) { + refs = --ctx->dev[i].refs; + if (refs == 0) { + (*ctx->dev[i].configure)(ctx, false); + } + } + } + portEXIT_CRITICAL_SAFE(&ctx->lock); + assert(refs >= 0); +} + +#define WIFI_CLOCK_DEPS (MODEM_CLOCK_WIFI_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_WIFI_BB | MODEM_CLOCK_COEXIST) +#define BLE_CLOCK_DEPS (MODEM_CLOCK_BLE_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_BLE_BB | MODEM_CLOCK_ETM | MODEM_CLOCK_COEXIST) +#define IEEE802154_CLOCK_DEPS (MODEM_CLOCK_802154_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_BLE_BB | MODEM_CLOCK_ETM | MODEM_CLOCK_COEXIST) +#define COEXIST_CLOCK_DEPS (MODEM_CLOCK_COEXIST) +#define PHY_CLOCK_DEPS (MODEM_CLOCK_I2C_MASTER) + +void IRAM_ATTR modem_clock_module_enable(periph_module_t module) +{ + assert(IS_MODEM_MODULE(module)); + const int deps = (module == PERIPH_WIFI_MODULE) ? WIFI_CLOCK_DEPS \ + : (module == PERIPH_BT_MODULE) ? BLE_CLOCK_DEPS \ + : (module == PERIPH_IEEE802154_MODULE) ? IEEE802154_CLOCK_DEPS \ + : (module == PERIPH_COEX_MODULE) ? COEXIST_CLOCK_DEPS \ + : (module == PERIPH_PHY_MODULE) ? PHY_CLOCK_DEPS \ + : 0; + modem_clock_device_enable(MODEM_CLOCK_instance(), deps); +} + +void IRAM_ATTR modem_clock_module_disable(periph_module_t module) +{ + assert(IS_MODEM_MODULE(module)); + const int deps = (module == PERIPH_WIFI_MODULE) ? WIFI_CLOCK_DEPS \ + : (module == PERIPH_BT_MODULE) ? BLE_CLOCK_DEPS \ + : (module == PERIPH_IEEE802154_MODULE) ? IEEE802154_CLOCK_DEPS \ + : (module == PERIPH_COEX_MODULE) ? COEXIST_CLOCK_DEPS \ + : (module == PERIPH_PHY_MODULE) ? PHY_CLOCK_DEPS \ + : 0; + modem_clock_device_disable(MODEM_CLOCK_instance(), deps); +} + +void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpclk_src_t src, uint32_t divider) +{ + assert(IS_MODEM_MODULE(module)); + portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); + switch (module) + { + case PERIPH_WIFI_MODULE: + modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_clock_hal_select_wifi_lpclk_source(MODEM_CLOCK_instance()->hal, src); + modem_lpcon_ll_set_wifi_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider); + modem_lpcon_ll_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); + break; + case PERIPH_BT_MODULE: + modem_clock_hal_deselect_all_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_clock_hal_select_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal, src); + modem_lpcon_ll_set_lp_timer_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider); + modem_lpcon_ll_enable_lp_timer_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); + break; + case PERIPH_COEX_MODULE: + modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_clock_hal_select_coex_lpclk_source(MODEM_CLOCK_instance()->hal, src); + modem_lpcon_ll_set_coex_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider); + // modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); // TODO: IDF-5727 + break; + default: + break; + } + modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; + MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = src; + portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); + + /* The power domain of the low-power clock source required by the modem + * module remains powered on during sleep */ + esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ + (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ + : ESP_PD_DOMAIN_MAX); + esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) ( \ + (src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ + : (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ + : (src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \ + : (src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ + : ESP_PD_DOMAIN_MAX); + esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); + esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); +} + +void modem_clock_deselect_lp_clock_source(periph_module_t module) +{ + assert(IS_MODEM_MODULE(module)); + portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); + switch (module) + { + case PERIPH_WIFI_MODULE: + modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_lpcon_ll_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); + break; + case PERIPH_BT_MODULE: + modem_clock_hal_deselect_all_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_lpcon_ll_enable_lp_timer_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); + break; + case PERIPH_COEX_MODULE: + modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal); + // modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); // TODO: IDF-5727 + break; + default: + break; + } + modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; + MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = MODEM_CLOCK_LPCLK_SRC_INVALID; + portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); + + esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ + (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \ + : (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ + : ESP_PD_DOMAIN_MAX); + esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); +} diff --git a/components/esp_hw_support/periph_ctrl.c b/components/esp_hw_support/periph_ctrl.c index 8a226b236f..2d15173e8f 100644 --- a/components/esp_hw_support/periph_ctrl.c +++ b/components/esp_hw_support/periph_ctrl.c @@ -8,6 +8,10 @@ #include "esp_attr.h" #include "esp_private/periph_ctrl.h" +#if SOC_MODEM_CLOCK_IS_INDEPENDENT +#include "esp_private/esp_modem_clock.h" +#endif + static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED; static uint8_t ref_counts[PERIPH_MODULE_MAX] = {0}; @@ -45,35 +49,51 @@ void periph_module_reset(periph_module_t periph) #if CONFIG_ESP32_WIFI_ENABLED IRAM_ATTR void wifi_bt_common_module_enable(void) { +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_enable(PERIPH_PHY_MODULE); +#else portENTER_CRITICAL_SAFE(&periph_spinlock); if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) { periph_ll_wifi_bt_module_enable_clk_clear_rst(); } ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++; portEXIT_CRITICAL_SAFE(&periph_spinlock); +#endif } IRAM_ATTR void wifi_bt_common_module_disable(void) { +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_disable(PERIPH_PHY_MODULE); +#else portENTER_CRITICAL_SAFE(&periph_spinlock); ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]--; if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) { periph_ll_wifi_bt_module_disable_clk_set_rst(); } portEXIT_CRITICAL_SAFE(&periph_spinlock); +#endif } void wifi_module_enable(void) { +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_enable(PERIPH_WIFI_MODULE); +#else portENTER_CRITICAL_SAFE(&periph_spinlock); periph_ll_wifi_module_enable_clk_clear_rst(); portEXIT_CRITICAL_SAFE(&periph_spinlock); +#endif } void wifi_module_disable(void) { +#if SOC_MODEM_CLOCK_IS_INDEPENDENT + modem_clock_module_disable(PERIPH_WIFI_MODULE); +#else portENTER_CRITICAL_SAFE(&periph_spinlock); periph_ll_wifi_module_disable_clk_set_rst(); portEXIT_CRITICAL_SAFE(&periph_spinlock); +#endif } #endif // CONFIG_ESP32_WIFI_ENABLED diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 2fa03c233c..067ef09a91 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -164,22 +164,7 @@ typedef struct { _Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size"); static sleep_config_t s_config = { - .pd_options = { -#if SOC_PM_SUPPORT_RTC_PERIPH_PD - ESP_PD_OPTION_AUTO, -#endif -#if SOC_PM_SUPPORT_RTC_SLOW_MEM_PD - ESP_PD_OPTION_AUTO, -#endif -#if SOC_PM_SUPPORT_RTC_FAST_MEM_PD - ESP_PD_OPTION_AUTO, -#endif - ESP_PD_OPTION_AUTO, -#if SOC_PM_SUPPORT_CPU_PD - ESP_PD_OPTION_AUTO, -#endif - ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO - }, + .pd_options = {[0 ... ESP_PD_DOMAIN_MAX - 1] = ESP_PD_OPTION_AUTO,}, .ccount_ticks_record = 0, .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US, .wakeup_triggers = 0 @@ -1414,7 +1399,7 @@ static uint32_t get_power_down_flags(void) pd_flags |= RTC_SLEEP_PD_CPU; } #endif - if (s_config.pd_options[ESP_PD_DOMAIN_RTC8M] != ESP_PD_OPTION_ON) { + if (s_config.pd_options[ESP_PD_DOMAIN_RC_FAST] != ESP_PD_OPTION_ON) { pd_flags |= RTC_SLEEP_PD_INT_8M; } if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) { diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 1819dec6db..d6bfec15b3 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -205,16 +205,12 @@ static inline void phy_update_wifi_mac_time(bool en_clock_stopped, int64_t now) IRAM_ATTR void esp_phy_common_clock_enable(void) { -#if !CONFIG_IDF_TARGET_ESP32C6 // IDF-5679 wifi_bt_common_module_enable(); -#endif } IRAM_ATTR void esp_phy_common_clock_disable(void) { -#if !CONFIG_IDF_TARGET_ESP32C6 // IDF-5679 wifi_bt_common_module_disable(); -#endif } static inline void phy_digital_regs_store(void) diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index ba9be14df3..22c30c6256 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -20,6 +20,7 @@ #include "soc/i2s_reg.h" #include "esp_cpu.h" #include "hal/wdt_hal.h" +#include "esp_private/esp_modem_clock.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" #include "esp_rom_uart.h" @@ -178,6 +179,7 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { + modem_clock_domain_pmu_state_icg_map_init(); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); #if 0 // TODO: IDF-5658 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 70ebee49d8..a3661e43ac 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -19,6 +19,7 @@ #include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" +#include "hal/modem_syscon_ll.h" #include "esp_private/cache_err_int.h" #include "esp32c6/rom/cache.h" @@ -66,13 +67,12 @@ void IRAM_ATTR esp_restart_noos(void) // Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Moved to module internal // SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - // SYSTEM_WIFIMAC_RST | // TODO: IDF-5679 (esp_wifi) // SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST? // SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet) - // SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | // TODO: IDF-5727 (bt) - // SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); // REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + modem_syscon_ll_reset_all(&MODEM_SYSCON); + // Set Peripheral clk rst SET_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN); SET_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 234d90d294..47ca3a4212 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -111,6 +111,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "sha_hal.c") endif() + if(CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT) + list(APPEND srcs "${target}/modem_clock_hal.c") + endif() + if(${target} STREQUAL "esp32") list(APPEND srcs "sdio_slave_hal.c" diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h index 5d664bbea9..60e402a5ef 100644 --- a/components/hal/esp32c6/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -321,18 +321,6 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) -{ - // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679 - // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) -{ - // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679 - // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - static inline void periph_ll_reset(periph_module_t periph) { DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); @@ -345,18 +333,6 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; } -static inline void periph_ll_wifi_module_enable_clk_clear_rst(void) -{ - // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679 - // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - -static inline void periph_ll_wifi_module_disable_clk_set_rst(void) -{ - // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679 - // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/modem_clock_hal.h b/components/hal/esp32c6/include/hal/modem_clock_hal.h new file mode 100644 index 0000000000..bbd6866fc8 --- /dev/null +++ b/components/hal/esp32c6/include/hal/modem_clock_hal.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "hal/modem_syscon_ll.h" +#include "hal/modem_lpcon_ll.h" +#include "hal/modem_clock_types.h" + +typedef struct { + modem_syscon_dev_t *syscon_dev; + modem_lpcon_dev_t *lpcon_dev; +} modem_clock_hal_context_t; + +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); + +void modem_clock_hal_select_lp_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); + +void modem_clock_hal_deselect_all_lp_timer_lpclk_source(modem_clock_hal_context_t *hal); + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); + +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); + +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); + +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/modem_lpcon_ll.h b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h new file mode 100644 index 0000000000..d6751fe84a --- /dev/null +++ b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h @@ -0,0 +1,227 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C6 MODEM SYSCON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_lpcon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_lp_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->lp_timer_conf.clk_lp_timer_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_lp_timer_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->lp_timer_conf.clk_lp_timer_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->coex_lp_clk_conf.clk_coex_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->coex_lp_clk_conf.clk_coex_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->i2c_mst_clk_conf.clk_i2c_mst_sel_160m = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src) +{ + hw->modem_32k_clk_conf.clk_modem_32k_sel = src; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_wifipwr_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_coex_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_lp_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifipwr_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_coex_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_i2c_mst_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_lp_timer_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_lp_timer_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifipwr_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_coex_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_i2c_mst_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_lp_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/modem_syscon_ll.h b/components/hal/esp32c6/include/hal/modem_syscon_ll.h new file mode 100644 index 0000000000..503472350d --- /dev/null +++ b/components/hal/esp32c6/include/hal/modem_syscon_ll.h @@ -0,0 +1,552 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C6 MODEM SYSCON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_syscon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_mux = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_etm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_mac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscom_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_modem_sec_en = en; + hw->clk_conf.clk_modem_sec_ecb_en = en; + hw->clk_conf.clk_modem_sec_ccm_en = en; + hw->clk_conf.clk_modem_sec_bah_en = en; + hw->clk_conf.clk_modem_sec_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_etm_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zb_apb_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zb_mac_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_modem_sec_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_ble_timer_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_data_dump_fo = 1; +} +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_zb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_fe_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_bt_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_wifi_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifi_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifibb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifibb = 1; + hw->modem_rst_conf.rst_wifibb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifimac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifimac = 1; + hw->modem_rst_conf.rst_wifimac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_fe = 1; + hw->modem_rst_conf.rst_fe = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac_apb = 1; + hw->modem_rst_conf.rst_btmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac = 1; + hw->modem_rst_conf.rst_btmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb_apb = 1; + hw->modem_rst_conf.rst_btbb_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb = 1; + hw->modem_rst_conf.rst_btbb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_etm = 1; + hw->modem_rst_conf.rst_etm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac = 1; + hw->modem_rst_conf.rst_zbmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_ecb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ecb = 1; + hw->modem_rst_conf.rst_modem_ecb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_ccm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ccm = 1; + hw->modem_rst_conf.rst_modem_ccm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_bah(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_bah = 1; + hw->modem_rst_conf.rst_modem_bah = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_sec = 1; + hw->modem_rst_conf.rst_modem_sec = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_ble_timer = 1; + hw->modem_rst_conf.rst_ble_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_data_dump = 1; + hw->modem_rst_conf.rst_data_dump = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.val = 0xffffffff; + hw->modem_rst_conf.val = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_22m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_44m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_160x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifimac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifi_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_20m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_cal_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_anamode_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_anamode_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_anamode_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_22m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_44m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_40x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_80x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_40x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_80x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_160x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifibb_480m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifimac_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_wifi_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_20m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_cal_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_bt_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_bt_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_480m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_anamode_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_anamode_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_anamode_160m_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c new file mode 100644 index 0000000000..7cbe2bf820 --- /dev/null +++ b/components/hal/esp32c6/modem_clock_hal.c @@ -0,0 +1,179 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK (ESP32-C6 specific part) +#include +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/modem_clock_hal.h" +#include "hal/modem_clock_types.h" +#include "hal/assert.h" + +typedef enum { + MODEM_CLOCK_XTAL32K_CODE = 0, + MODEM_CLOCK_RC32K_CODE = 1, + MODEM_CLOCK_EXT32K_CODE = 2 +} modem_clock_32k_clk_src_code_t; + +void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) +{ + HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); + switch (domain) + { + case MODEM_CLOCK_DOMAIN_MODEM_APB: + modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_MODEM_PERIPH: + modem_syscon_ll_set_modem_periph_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_WIFI: + modem_syscon_ll_set_wifi_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_BT: + modem_syscon_ll_set_bt_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_FE: + modem_syscon_ll_set_fe_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_IEEE802154: + modem_syscon_ll_set_ieee802154_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_LP_APB: + modem_lpcon_ll_set_lp_apb_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_I2C_MASTER: + modem_lpcon_ll_set_i2c_master_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_COEX: + modem_lpcon_ll_set_coex_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_WIFIPWR: + modem_lpcon_ll_set_wifipwr_icg_bitmap(hal->lpcon_dev, bitmap); + break; + default: + break; + } +} + +void modem_clock_hal_deselect_all_lp_timer_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_lp_timer_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_lp_timer_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_lp_timer_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_lp_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_lp_timer_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_lp_timer_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_lp_timer_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + break; + } +} + +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + break; + } +} + +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_wifi_lpclk_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_wifi_lpclk_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + break; + } +} diff --git a/components/hal/include/hal/modem_clock_types.h b/components/hal/include/hal/modem_clock_types.h new file mode 100644 index 0000000000..ed435be226 --- /dev/null +++ b/components/hal/include/hal/modem_clock_types.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + MODEM_CLOCK_DOMAIN_MODEM_APB = 0, + MODEM_CLOCK_DOMAIN_MODEM_PERIPH, + MODEM_CLOCK_DOMAIN_WIFI, + MODEM_CLOCK_DOMAIN_BT, + MODEM_CLOCK_DOMAIN_FE, + MODEM_CLOCK_DOMAIN_IEEE802154, + MODEM_CLOCK_DOMAIN_LP_APB, + MODEM_CLOCK_DOMAIN_I2C_MASTER, + MODEM_CLOCK_DOMAIN_COEX, + MODEM_CLOCK_DOMAIN_WIFIPWR, + + MODEM_CLOCK_DOMAIN_MAX +} modem_clock_domain_t; + +typedef enum { + MODEM_CLOCK_LPCLK_SRC_INVALID = -1, + MODEM_CLOCK_LPCLK_SRC_RC_SLOW = 0, + MODEM_CLOCK_LPCLK_SRC_RC_FAST, + MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, + MODEM_CLOCK_LPCLK_SRC_RC32K, + MODEM_CLOCK_LPCLK_SRC_XTAL32K, + MODEM_CLOCK_LPCLK_SRC_EXT32K, + MODEM_CLOCK_LPCLK_SRC_MAX +} modem_clock_lpclk_src_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 30e5a3df62..3c1e3ebb8b 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -719,6 +719,10 @@ config SOC_PM_SUPPORT_RTC_SLOW_MEM_PD bool default y +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_CLK_APLL_SUPPORTED bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 84234e014e..c99948a251 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -366,6 +366,7 @@ #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) #define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1) #define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_APLL_SUPPORTED (1) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index adcf5f6602..1b0a5008c9 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -575,6 +575,10 @@ config SOC_PM_SUPPORT_BT_PD bool default n +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_CLK_RC_FAST_D256_SUPPORTED bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index c3e2f5ef20..edad367a10 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -279,6 +279,7 @@ #define SOC_PM_SUPPORT_CPU_PD (0) #define SOC_PM_SUPPORT_WIFI_PD (0) #define SOC_PM_SUPPORT_BT_PD (0) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) /*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */ #define SOC_CLK_RC_FAST_D256_SUPPORTED (1) diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index cfb7b79d42..871bb7d359 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -819,6 +819,10 @@ config SOC_PM_SUPPORT_BT_PD bool default y +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_CLK_RC_FAST_D256_SUPPORTED bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index dca91106e9..e8b25f27ca 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -366,14 +366,11 @@ /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - #define SOC_PM_SUPPORT_CPU_PD (1) - #define SOC_PM_SUPPORT_WIFI_PD (1) - #define SOC_PM_SUPPORT_BT_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) /*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */ #define SOC_CLK_RC_FAST_D256_SUPPORTED (1) diff --git a/components/soc/esp32c6/include/modem/modem_lpcon_reg.h b/components/soc/esp32c6/include/modem/modem_lpcon_reg.h index edbb585f93..3cddba41bc 100644 --- a/components/soc/esp32c6/include/modem/modem_lpcon_reg.h +++ b/components/soc/esp32c6/include/modem/modem_lpcon_reg.h @@ -1,7 +1,7 @@ -/* +/** * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,373 +11,372 @@ extern "C" { #endif -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_DEBUG_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_DEBUG_ENA (BIT(1)) -#define MODEM_LPCON_CLK_DEBUG_ENA_M (BIT(1)) -#define MODEM_LPCON_CLK_DEBUG_ENA_V 0x1 -#define MODEM_LPCON_CLK_DEBUG_ENA_S 1 -/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S) +#define MODEM_LPCON_CLK_EN_V 0x00000001U #define MODEM_LPCON_CLK_EN_S 0 +/* MODEM_LPCON_CLK_DEBUG_ENA : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_DEBUG_ENA (BIT(1)) +#define MODEM_LPCON_CLK_DEBUG_ENA_M (MODEM_LPCON_CLK_DEBUG_ENA_V << MODEM_LPCON_CLK_DEBUG_ENA_S) +#define MODEM_LPCON_CLK_DEBUG_ENA_V 0x00000001U +#define MODEM_LPCON_CLK_DEBUG_ENA_S 1 -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc) +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0)) -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (BIT(0)) -#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (MODEM_LPCON_CLK_I2C_MST_SEL_160M_V << MODEM_LPCON_CLK_I2C_MST_SEL_160M_S) +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x00000001U #define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0 -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U #define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_V 0x1 -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 +/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S) +#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) -/* MODEM_LPCON_CLK_DC_MEM_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_DC_MEM_FO (BIT(9)) -#define MODEM_LPCON_CLK_DC_MEM_FO_M (BIT(9)) -#define MODEM_LPCON_CLK_DC_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_DC_MEM_FO_S 9 -/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_AGC_MEM_FO (BIT(8)) -#define MODEM_LPCON_CLK_AGC_MEM_FO_M (BIT(8)) -#define MODEM_LPCON_CLK_AGC_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_AGC_MEM_FO_S 8 -/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_PBUS_MEM_FO (BIT(7)) -#define MODEM_LPCON_CLK_PBUS_MEM_FO_M (BIT(7)) -#define MODEM_LPCON_CLK_PBUS_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_PBUS_MEM_FO_S 7 -/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO (BIT(6)) -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M (BIT(6)) -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S 6 -/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO (BIT(5)) -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M (BIT(5)) -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S 5 -/* MODEM_LPCON_CLK_BCMEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_BCMEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_BCMEM_FO_M (BIT(4)) -#define MODEM_LPCON_CLK_BCMEM_FO_V 0x1 -#define MODEM_LPCON_CLK_BCMEM_FO_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_V 0x1 -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c) +/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 +/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S) +#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [4]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_BCMEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_BCMEM_FO_M (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S) +#define MODEM_LPCON_CLK_BCMEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_BCMEM_FO_S 4 +/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [5]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO (BIT(5)) +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S) +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S 5 +/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO (BIT(6)) +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S) +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S 6 +/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [7]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_PBUS_MEM_FO (BIT(7)) +#define MODEM_LPCON_CLK_PBUS_MEM_FO_M (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S) +#define MODEM_LPCON_CLK_PBUS_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_PBUS_MEM_FO_S 7 +/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [8]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_AGC_MEM_FO (BIT(8)) +#define MODEM_LPCON_CLK_AGC_MEM_FO_M (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S) +#define MODEM_LPCON_CLK_AGC_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_AGC_MEM_FO_S 8 +/* MODEM_LPCON_CLK_DC_MEM_FO : R/W; bitpos: [9]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_DC_MEM_FO (BIT(9)) +#define MODEM_LPCON_CLK_DC_MEM_FO_M (MODEM_LPCON_CLK_DC_MEM_FO_V << MODEM_LPCON_CLK_DC_MEM_FO_S) +#define MODEM_LPCON_CLK_DC_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_DC_MEM_FO_S 9 -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU #define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 +/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_V 0x1 -#define MODEM_LPCON_RST_LP_TIMER_S 3 -/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_V 0x1 -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (BIT(1)) -#define MODEM_LPCON_RST_COEX_V 0x1 -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; */ +/*description: */ #define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S) +#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U #define MODEM_LPCON_RST_WIFIPWR_S 0 +/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S) +#define MODEM_LPCON_RST_COEX_V 0x00000001U +#define MODEM_LPCON_RST_COEX_S 1 +/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S) +#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U +#define MODEM_LPCON_RST_I2C_MST_S 2 +/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S) +#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U +#define MODEM_LPCON_RST_LP_TIMER_S 3 -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003 -#define MODEM_LPCON_MODEM_PWR_MEM_RA_M ((MODEM_LPCON_MODEM_PWR_MEM_RA_V)<<(MODEM_LPCON_MODEM_PWR_MEM_RA_S)) -#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x3 -#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18 -/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W ;bitpos:[17:15] ;default: 3'h4 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007 -#define MODEM_LPCON_MODEM_PWR_MEM_WA_M ((MODEM_LPCON_MODEM_PWR_MEM_WA_V)<<(MODEM_LPCON_MODEM_PWR_MEM_WA_S)) -#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x7 -#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15 -/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007 -#define MODEM_LPCON_MODEM_PWR_MEM_WP_M ((MODEM_LPCON_MODEM_PWR_MEM_WP_V)<<(MODEM_LPCON_MODEM_PWR_MEM_WP_S)) -#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x7 -#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12 -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (BIT(11)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (BIT(10)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 -/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (BIT(9)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 -/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (BIT(8)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 -/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7)) -#define MODEM_LPCON_BC_MEM_FORCE_PD_M (BIT(7)) -#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7 -/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6)) -#define MODEM_LPCON_BC_MEM_FORCE_PU_M (BIT(6)) -#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6 -/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (BIT(5)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 -/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (BIT(4)) -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 -/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) -#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (BIT(3)) -#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 -/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) -#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (BIT(2)) -#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 -/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1)) -#define MODEM_LPCON_DC_MEM_FORCE_PD_M (BIT(1)) -#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x1 -#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1 -/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; */ +/*description: */ #define MODEM_LPCON_DC_MEM_FORCE_PU (BIT(0)) -#define MODEM_LPCON_DC_MEM_FORCE_PU_M (BIT(0)) -#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_PU_M (MODEM_LPCON_DC_MEM_FORCE_PU_V << MODEM_LPCON_DC_MEM_FORCE_PU_S) +#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x00000001U #define MODEM_LPCON_DC_MEM_FORCE_PU_S 0 +/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1)) +#define MODEM_LPCON_DC_MEM_FORCE_PD_M (MODEM_LPCON_DC_MEM_FORCE_PD_V << MODEM_LPCON_DC_MEM_FORCE_PD_S) +#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1 +/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */ +/*description: */ +#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 +/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 +/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */ +/*description: */ +#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 +/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */ +/*description: */ +#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 +/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; */ +/*description: */ +#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6)) +#define MODEM_LPCON_BC_MEM_FORCE_PU_M (MODEM_LPCON_BC_MEM_FORCE_PU_V << MODEM_LPCON_BC_MEM_FORCE_PU_S) +#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x00000001U +#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6 +/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; */ +/*description: */ +#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7)) +#define MODEM_LPCON_BC_MEM_FORCE_PD_M (MODEM_LPCON_BC_MEM_FORCE_PD_V << MODEM_LPCON_BC_MEM_FORCE_PD_S) +#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */ +/*description: */ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */ +/*description: */ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */ +/*description: */ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 +/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */ +/*description: */ +#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U +#define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S) +#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U +#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12 +/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 4; */ +/*description: */ +#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U +#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S) +#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U +#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15 +/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */ +/*description: */ +#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U +#define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S) +#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U +#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18 -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) -/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2206240 ; */ -/*description: .*/ -#define MODEM_LPCON_DATE 0x0FFFFFFF -#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) -#define MODEM_LPCON_DATE_V 0xFFFFFFF +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2c) +/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35676736; */ +/*description: */ +#define MODEM_LPCON_DATE 0x0FFFFFFFU +#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S) +#define MODEM_LPCON_DATE_V 0x0FFFFFFFU #define MODEM_LPCON_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/include/modem/modem_lpcon_struct.h b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h index d7fc2ed28d..eafb7933e6 100644 --- a/components/soc/esp32c6/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c6/include/modem/modem_lpcon_struct.h @@ -1,7 +1,7 @@ -/* +/** * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,226 +10,169 @@ extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t reg_clk_en : 1; - uint32_t reg_clk_debug_ena : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t reg_clk_lp_timer_sel_osc_slow : 1; - uint32_t reg_clk_lp_timer_sel_osc_fast : 1; - uint32_t reg_clk_lp_timer_sel_xtal : 1; - uint32_t reg_clk_lp_timer_sel_xtal32k : 1; - uint32_t reg_clk_lp_timer_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } lp_timer_conf; - union { - struct { - uint32_t reg_clk_coex_lp_sel_osc_slow : 1; - uint32_t reg_clk_coex_lp_sel_osc_fast : 1; - uint32_t reg_clk_coex_lp_sel_xtal : 1; - uint32_t reg_clk_coex_lp_sel_xtal32k : 1; - uint32_t reg_clk_coex_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } coex_lp_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t reg_clk_wifipwr_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } wifi_lp_clk_conf; - union { - struct { - uint32_t reg_clk_i2c_mst_sel_160m : 1; - uint32_t reserved1 : 31; - }; - uint32_t val; - } i2c_mst_clk_conf; - union { - struct { - uint32_t reg_clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; - }; - uint32_t val; - } modem_32k_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_en : 1; - uint32_t reg_clk_coex_en : 1; - uint32_t reg_clk_i2c_mst_en : 1; - uint32_t reg_clk_lp_timer_en : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_fo : 1; - uint32_t reg_clk_coex_fo : 1; - uint32_t reg_clk_i2c_mst_fo : 1; - uint32_t reg_clk_lp_timer_fo : 1; - uint32_t reg_clk_bcmem_fo : 1; - uint32_t reg_clk_i2c_mst_mem_fo : 1; - uint32_t reg_clk_chan_freq_mem_fo : 1; - uint32_t reg_clk_pbus_mem_fo : 1; - uint32_t reg_clk_agc_mem_fo : 1; - uint32_t reg_clk_dc_mem_fo : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 16; - uint32_t reg_clk_wifipwr_st_map : 4; - uint32_t reg_clk_coex_st_map : 4; - uint32_t reg_clk_i2c_mst_st_map : 4; - uint32_t reg_clk_lp_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reg_rst_wifipwr : 1; - uint32_t reg_rst_coex : 1; - uint32_t reg_rst_i2c_mst : 1; - uint32_t reg_rst_lp_timer : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } rst_conf; - union { - struct { - uint32_t reg_dc_mem_force_pu : 1; - uint32_t reg_dc_mem_force_pd : 1; - uint32_t reg_agc_mem_force_pu : 1; - uint32_t reg_agc_mem_force_pd : 1; - uint32_t reg_pbus_mem_force_pu : 1; - uint32_t reg_pbus_mem_force_pd : 1; - uint32_t reg_bc_mem_force_pu : 1; - uint32_t reg_bc_mem_force_pd : 1; - uint32_t reg_i2c_mst_mem_force_pu : 1; - uint32_t reg_i2c_mst_mem_force_pd : 1; - uint32_t reg_chan_freq_mem_force_pu : 1; - uint32_t reg_chan_freq_mem_force_pd : 1; - uint32_t reg_modem_pwr_mem_wp : 3; - uint32_t reg_modem_pwr_mem_wa : 3; - uint32_t reg_modem_pwr_mem_ra : 2; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } mem_conf; - union { - struct { - uint32_t reg_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; +typedef union { + struct { + uint32_t clk_en:1; + uint32_t clk_debug_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} modem_lpcon_test_conf_reg_t; + +typedef union { + struct { + uint32_t clk_lp_timer_sel_osc_slow:1; + uint32_t clk_lp_timer_sel_osc_fast:1; + uint32_t clk_lp_timer_sel_xtal:1; + uint32_t clk_lp_timer_sel_xtal32k:1; + uint32_t clk_lp_timer_div_num:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} modem_lpcon_lp_timer_conf_reg_t; + +typedef union { + struct { + uint32_t clk_coex_lp_sel_osc_slow:1; + uint32_t clk_coex_lp_sel_osc_fast:1; + uint32_t clk_coex_lp_sel_xtal:1; + uint32_t clk_coex_lp_sel_xtal32k:1; + uint32_t clk_coex_lp_div_num:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} modem_lpcon_coex_lp_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow:1; + uint32_t clk_wifipwr_lp_sel_osc_fast:1; + uint32_t clk_wifipwr_lp_sel_xtal:1; + uint32_t clk_wifipwr_lp_sel_xtal32k:1; + uint32_t clk_wifipwr_lp_div_num:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} modem_lpcon_wifi_lp_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_i2c_mst_sel_160m:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} modem_lpcon_i2c_mst_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_modem_32k_sel:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} modem_lpcon_modem_32k_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifipwr_en:1; + uint32_t clk_coex_en:1; + uint32_t clk_i2c_mst_en:1; + uint32_t clk_lp_timer_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} modem_lpcon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifipwr_fo:1; + uint32_t clk_coex_fo:1; + uint32_t clk_i2c_mst_fo:1; + uint32_t clk_lp_timer_fo:1; + uint32_t clk_bcmem_fo:1; + uint32_t clk_i2c_mst_mem_fo:1; + uint32_t clk_chan_freq_mem_fo:1; + uint32_t clk_pbus_mem_fo:1; + uint32_t clk_agc_mem_fo:1; + uint32_t clk_dc_mem_fo:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} modem_lpcon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t reserved_0:16; + uint32_t clk_wifipwr_st_map:4; + uint32_t clk_coex_st_map:4; + uint32_t clk_i2c_mst_st_map:4; + uint32_t clk_lp_apb_st_map:4; + }; + uint32_t val; +} modem_lpcon_clk_conf_power_st_reg_t; + +typedef union { + struct { + uint32_t rst_wifipwr:1; + uint32_t rst_coex:1; + uint32_t rst_i2c_mst:1; + uint32_t rst_lp_timer:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} modem_lpcon_rst_conf_reg_t; + +typedef union { + struct { + uint32_t dc_mem_force_pu:1; + uint32_t dc_mem_force_pd:1; + uint32_t agc_mem_force_pu:1; + uint32_t agc_mem_force_pd:1; + uint32_t pbus_mem_force_pu:1; + uint32_t pbus_mem_force_pd:1; + uint32_t bc_mem_force_pu:1; + uint32_t bc_mem_force_pd:1; + uint32_t i2c_mst_mem_force_pu:1; + uint32_t i2c_mst_mem_force_pd:1; + uint32_t chan_freq_mem_force_pu:1; + uint32_t chan_freq_mem_force_pd:1; + uint32_t modem_pwr_mem_wp:3; + uint32_t modem_pwr_mem_wa:3; + uint32_t modem_pwr_mem_ra:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} modem_lpcon_mem_conf_reg_t; + +typedef union { + struct { + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} modem_lpcon_date_reg_t; + + +typedef struct { + volatile modem_lpcon_test_conf_reg_t test_conf; + volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf; + volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf; + volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf; + volatile modem_lpcon_i2c_mst_clk_conf_reg_t i2c_mst_clk_conf; + volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf; + volatile modem_lpcon_clk_conf_reg_t clk_conf; + volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st; + volatile modem_lpcon_rst_conf_reg_t rst_conf; + volatile modem_lpcon_mem_conf_reg_t mem_conf; + volatile modem_lpcon_date_reg_t date; } modem_lpcon_dev_t; extern modem_lpcon_dev_t MODEM_LPCON; +#ifndef __cplusplus +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x30, "Invalid size of modem_lpcon_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/include/modem/modem_syscon_reg.h b/components/soc/esp32c6/include/modem/modem_syscon_reg.h new file mode 100644 index 0000000000..ddfdf32b00 --- /dev/null +++ b/components/soc/esp32c6/include/modem/modem_syscon_reg.h @@ -0,0 +1,612 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + *//*description: */ +#pragma once + +#include +#include "modem/reg_base.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_EN (BIT(0)) +#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) +#define MODEM_SYSCON_CLK_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_EN_S 0 + +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; */ +/*description: */ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 +/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [24]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S) +#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 24 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 + +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_FO_S 22 +/* MODEM_SYSCON_CLK_ZB_APB_FO : R/W; bitpos: [23]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ZB_APB_FO (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_FO_M (MODEM_SYSCON_CLK_ZB_APB_FO_V << MODEM_SYSCON_CLK_ZB_APB_FO_S) +#define MODEM_SYSCON_CLK_ZB_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_APB_FO_S 23 +/* MODEM_SYSCON_CLK_ZB_MAC_FO : R/W; bitpos: [24]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ZB_MAC_FO (BIT(24)) +#define MODEM_SYSCON_CLK_ZB_MAC_FO_M (MODEM_SYSCON_CLK_ZB_MAC_FO_V << MODEM_SYSCON_CLK_ZB_MAC_FO_S) +#define MODEM_SYSCON_CLK_ZB_MAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_MAC_FO_S 24 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [25]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S 25 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [26]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [27]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [28]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S 28 +/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 + +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) +/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 +/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_M (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_M (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 + +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_M (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S) +#define MODEM_SYSCON_RST_WIFIBB_V 0x00000001U +#define MODEM_SYSCON_RST_WIFIBB_S 8 +/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [10]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(10)) +#define MODEM_SYSCON_RST_WIFIMAC_M (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x00000001U +#define MODEM_SYSCON_RST_WIFIMAC_S 10 +/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) +#define MODEM_SYSCON_RST_FE_V 0x00000001U +#define MODEM_SYSCON_RST_FE_S 14 +/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) +#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_S 16 +/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) +#define MODEM_SYSCON_RST_BTBB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_S 18 +/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) +#define MODEM_SYSCON_RST_ETM_V 0x00000001U +#define MODEM_SYSCON_RST_ETM_S 22 +/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) +#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 + +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 +/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/* MODEM_SYSCON_CLK_FE_CAL_160M_EN : R/W; bitpos: [15]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_CAL_160M_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_M (MODEM_SYSCON_CLK_FE_CAL_160M_EN_V << MODEM_SYSCON_CLK_FE_CAL_160M_EN_S) +#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_S 15 +/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_EN_S 16 +/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_EN_S 17 +/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BT_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S) +#define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_EN_S 18 +/* MODEM_SYSCON_CLK_WIFIBB_480M_EN : R/W; bitpos: [19]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_480M_EN (BIT(19)) +#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_M (MODEM_SYSCON_CLK_WIFIBB_480M_EN_V << MODEM_SYSCON_CLK_WIFIBB_480M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_S 19 +/* MODEM_SYSCON_CLK_FE_480M_EN : R/W; bitpos: [20]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_480M_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_480M_EN_M (MODEM_SYSCON_CLK_FE_480M_EN_V << MODEM_SYSCON_CLK_FE_480M_EN_S) +#define MODEM_SYSCON_CLK_FE_480M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_480M_EN_S 20 +/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN : R/W; bitpos: [21]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S 21 +/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN : R/W; bitpos: [22]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN (BIT(22)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S 22 +/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN : R/W; bitpos: [23]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN (BIT(23)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S 23 + +#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [0]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_22M_FO (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S 0 +/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [1]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40M_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [2]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_44M_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S 2 +/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [3]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80M_FO (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S 3 +/* MODEM_SYSCON_CLK_WIFIBB_40X_FO : R/W; bitpos: [4]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40X_FO (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_S 4 +/* MODEM_SYSCON_CLK_WIFIBB_80X_FO : R/W; bitpos: [5]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80X_FO (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_S 5 +/* MODEM_SYSCON_CLK_WIFIBB_40X1_FO : R/W; bitpos: [6]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S 6 +/* MODEM_SYSCON_CLK_WIFIBB_80X1_FO : R/W; bitpos: [7]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S 7 +/* MODEM_SYSCON_CLK_WIFIBB_160X1_FO : R/W; bitpos: [8]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S 8 +/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [9]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 9 +/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [10]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 10 +/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [11]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_20M_FO (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_FO_M (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S) +#define MODEM_SYSCON_CLK_FE_20M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_20M_FO_S 11 +/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [12]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_40M_FO (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_FO_M (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S) +#define MODEM_SYSCON_CLK_FE_40M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_40M_FO_S 12 +/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [13]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_80M_FO (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_FO_M (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S) +#define MODEM_SYSCON_CLK_FE_80M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_80M_FO_S 13 +/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [14]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_160M_FO (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_FO_M (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S) +#define MODEM_SYSCON_CLK_FE_160M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_160M_FO_S 14 +/* MODEM_SYSCON_CLK_FE_CAL_160M_FO : R/W; bitpos: [15]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_CAL_160M_FO (BIT(15)) +#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_M (MODEM_SYSCON_CLK_FE_CAL_160M_FO_V << MODEM_SYSCON_CLK_FE_CAL_160M_FO_S) +#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_S 15 +/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [16]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(16)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_FO_S 16 +/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [17]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(17)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_FO_S 17 +/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_BT_FO (BIT(18)) +#define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S) +#define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_FO_S 18 +/* MODEM_SYSCON_CLK_WIFIBB_480M_FO : R/W; bitpos: [19]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_WIFIBB_480M_FO (BIT(19)) +#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_M (MODEM_SYSCON_CLK_WIFIBB_480M_FO_V << MODEM_SYSCON_CLK_WIFIBB_480M_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_S 19 +/* MODEM_SYSCON_CLK_FE_480M_FO : R/W; bitpos: [20]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_480M_FO (BIT(20)) +#define MODEM_SYSCON_CLK_FE_480M_FO_M (MODEM_SYSCON_CLK_FE_480M_FO_V << MODEM_SYSCON_CLK_FE_480M_FO_S) +#define MODEM_SYSCON_CLK_FE_480M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_480M_FO_S 20 +/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO : R/W; bitpos: [21]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO (BIT(21)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S 21 +/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO : R/W; bitpos: [22]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO (BIT(22)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S 22 +/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO : R/W; bitpos: [23]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO (BIT(23)) +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S) +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S 23 + +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) +/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFFU +#define MODEM_SYSCON_WIFI_BB_CFG_M (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU +#define MODEM_SYSCON_WIFI_BB_CFG_S 0 + +#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S) +#define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WP_S 0 +/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */ +/*description: */ +#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S) +#define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WA_S 3 +/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */ +/*description: */ +#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U +#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S) +#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U +#define MODEM_SYSCON_MODEM_MEM_RA_S 6 + +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35676928; */ +/*description: */ +#define MODEM_SYSCON_DATE 0x0FFFFFFFU +#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) +#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU +#define MODEM_SYSCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/modem/modem_syscon_struct.h b/components/soc/esp32c6/include/modem/modem_syscon_struct.h new file mode 100644 index 0000000000..bb95c39ed9 --- /dev/null +++ b/components/soc/esp32c6/include/modem/modem_syscon_struct.h @@ -0,0 +1,205 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} modem_syscon_test_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:21; + uint32_t clk_data_dump_mux:1; + uint32_t clk_etm_en:1; + uint32_t clk_zb_apb_en:1; + uint32_t clk_zb_mac_en:1; + uint32_t clk_modem_sec_ecb_en:1; + uint32_t clk_modem_sec_ccm_en:1; + uint32_t clk_modem_sec_bah_en:1; + uint32_t clk_modem_sec_apb_en:1; + uint32_t clk_modem_sec_en:1; + uint32_t clk_ble_timer_en:1; + uint32_t clk_data_dump_en:1; + }; + uint32_t val; +} modem_syscon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:22; + uint32_t clk_etm_fo:1; + uint32_t clk_zb_apb_fo:1; + uint32_t clk_zb_mac_fo:1; + uint32_t clk_modem_sec_ecb_fo:1; + uint32_t clk_modem_sec_ccm_fo:1; + uint32_t clk_modem_sec_bah_fo:1; + uint32_t clk_modem_sec_apb_fo:1; + uint32_t clk_modem_sec_fo:1; + uint32_t clk_ble_timer_fo:1; + uint32_t clk_data_dump_fo:1; + }; + uint32_t val; +} modem_syscon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t reserved_0:8; + uint32_t clk_zb_st_map:4; + uint32_t clk_fe_st_map:4; + uint32_t clk_bt_st_map:4; + uint32_t clk_wifi_st_map:4; + uint32_t clk_modem_peri_st_map:4; + uint32_t clk_modem_apb_st_map:4; + }; + uint32_t val; +} modem_syscon_clk_conf_power_st_reg_t; + +typedef union { + struct { + uint32_t reserved_0:8; + uint32_t rst_wifibb:1; + uint32_t reserved_9:1; + uint32_t rst_wifimac:1; + uint32_t reserved_11:3; + uint32_t rst_fe:1; + uint32_t rst_btmac_apb:1; + uint32_t rst_btmac:1; + uint32_t rst_btbb_apb:1; + uint32_t rst_btbb:1; + uint32_t reserved_19:3; + uint32_t rst_etm:1; + uint32_t reserved_23:1; + uint32_t rst_zbmac:1; + uint32_t rst_modem_ecb:1; + uint32_t rst_modem_ccm:1; + uint32_t rst_modem_bah:1; + uint32_t reserved_28:1; + uint32_t rst_modem_sec:1; + uint32_t rst_ble_timer:1; + uint32_t rst_data_dump:1; + }; + uint32_t val; +} modem_syscon_modem_rst_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_22m_en:1; + uint32_t clk_wifibb_40m_en:1; + uint32_t clk_wifibb_44m_en:1; + uint32_t clk_wifibb_80m_en:1; + uint32_t clk_wifibb_40x_en:1; + uint32_t clk_wifibb_80x_en:1; + uint32_t clk_wifibb_40x1_en:1; + uint32_t clk_wifibb_80x1_en:1; + uint32_t clk_wifibb_160x1_en:1; + uint32_t clk_wifimac_en:1; + uint32_t clk_wifi_apb_en:1; + uint32_t clk_fe_20m_en:1; + uint32_t clk_fe_40m_en:1; + uint32_t clk_fe_80m_en:1; + uint32_t clk_fe_160m_en:1; + uint32_t clk_fe_cal_160m_en:1; + uint32_t clk_fe_apb_en:1; + uint32_t clk_bt_apb_en:1; + uint32_t clk_bt_en:1; + uint32_t clk_wifibb_480m_en:1; + uint32_t clk_fe_480m_en:1; + uint32_t clk_fe_anamode_40m_en:1; + uint32_t clk_fe_anamode_80m_en:1; + uint32_t clk_fe_anamode_160m_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} modem_syscon_clk_conf1_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_22m_fo:1; + uint32_t clk_wifibb_40m_fo:1; + uint32_t clk_wifibb_44m_fo:1; + uint32_t clk_wifibb_80m_fo:1; + uint32_t clk_wifibb_40x_fo:1; + uint32_t clk_wifibb_80x_fo:1; + uint32_t clk_wifibb_40x1_fo:1; + uint32_t clk_wifibb_80x1_fo:1; + uint32_t clk_wifibb_160x1_fo:1; + uint32_t clk_wifimac_fo:1; + uint32_t clk_wifi_apb_fo:1; + uint32_t clk_fe_20m_fo:1; + uint32_t clk_fe_40m_fo:1; + uint32_t clk_fe_80m_fo:1; + uint32_t clk_fe_160m_fo:1; + uint32_t clk_fe_cal_160m_fo:1; + uint32_t clk_fe_apb_fo:1; + uint32_t clk_bt_apb_fo:1; + uint32_t clk_bt_fo:1; + uint32_t clk_wifibb_480m_fo:1; + uint32_t clk_fe_480m_fo:1; + uint32_t clk_fe_anamode_40m_fo:1; + uint32_t clk_fe_anamode_80m_fo:1; + uint32_t clk_fe_anamode_160m_fo:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} modem_syscon_clk_conf1_force_on_reg_t; + +typedef union { + struct { + uint32_t wifi_bb_cfg:32; + }; + uint32_t val; +} modem_syscon_wifi_bb_cfg_reg_t; + +typedef union { + struct { + uint32_t modem_mem_wp:3; + uint32_t modem_mem_wa:3; + uint32_t modem_mem_ra:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} modem_syscon_mem_conf_reg_t; + +typedef union { + struct { + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} modem_syscon_date_reg_t; + + +typedef struct { + volatile modem_syscon_test_conf_reg_t test_conf; + volatile modem_syscon_clk_conf_reg_t clk_conf; + volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st; + volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf; + volatile modem_syscon_clk_conf1_reg_t clk_conf1; + volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on; + volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg; + volatile modem_syscon_mem_conf_reg_t mem_conf; + volatile modem_syscon_date_reg_t date; +} modem_syscon_dev_t; + +extern modem_syscon_dev_t MODEM_SYSCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/modem/reg_base.h b/components/soc/esp32c6/include/modem/reg_base.h index 00efdc7d96..4e7b619f92 100644 --- a/components/soc/esp32c6/include/modem/reg_base.h +++ b/components/soc/esp32c6/include/modem/reg_base.h @@ -5,4 +5,5 @@ */ #pragma once +#define DR_REG_MODEM_SYSCON_BASE 0x600A9800 #define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 76f8a7dbf5..085a860374 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -915,10 +915,26 @@ config SOC_PM_SUPPORT_BT_PD bool default y +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32c6/include/soc/periph_defs.h b/components/soc/esp32c6/include/soc/periph_defs.h index 0214b03077..e2b2713aa7 100644 --- a/components/soc/esp32c6/include/soc/periph_defs.h +++ b/components/soc/esp32c6/include/soc/periph_defs.h @@ -27,11 +27,6 @@ typedef enum { PERIPH_TWAI0_MODULE, PERIPH_TWAI1_MODULE, PERIPH_RNG_MODULE, - PERIPH_WIFI_MODULE, - PERIPH_BT_MODULE, - PERIPH_WIFI_BT_COMMON_MODULE, - PERIPH_BT_BASEBAND_MODULE, - PERIPH_BT_LC_MODULE, PERIPH_RSA_MODULE, PERIPH_AES_MODULE, PERIPH_SHA_MODULE, @@ -44,9 +39,19 @@ typedef enum { PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, PERIPH_TEMPSENSOR_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, PERIPH_MODULE_MAX } periph_module_t; +#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + typedef enum { ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 13bc0f22e2..4b78381fb4 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -419,17 +419,17 @@ // TODO: IDF-5351 (Copy from esp32c3, need check) /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - #define SOC_PM_SUPPORT_CPU_PD (1) - #define SOC_PM_SUPPORT_WIFI_PD (1) - #define SOC_PM_SUPPORT_BT_PD (1) +#define SOC_PM_SUPPORT_XTAL32K_PD (1) +#define SOC_PM_SUPPORT_RC32K_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) +#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) diff --git a/components/soc/esp32c6/ld/esp32c6.peripherals.ld b/components/soc/esp32c6/ld/esp32c6.peripherals.ld index 8635a430cb..86b9384b89 100644 --- a/components/soc/esp32c6/ld/esp32c6.peripherals.ld +++ b/components/soc/esp32c6/ld/esp32c6.peripherals.ld @@ -58,6 +58,8 @@ PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( IEEE802154 = 0x600A3000 ); +PROVIDE ( MODEM_SYSCON = 0x600A9800 ); PROVIDE ( MODEM_LPCON = 0x600AF000 ); PROVIDE ( PMU = 0x600B0000 ); @@ -74,4 +76,3 @@ PROVIDE ( LPPERI = 0x600B2800 ); PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( OTP_DEBUG = 0x600B3C00 ); -PROVIDE ( IEEE802154 = 0x600A3000 ); diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 361403d3d4..e4df424186 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -751,6 +751,10 @@ config SOC_PM_SUPPORT_BT_PD bool default y +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 2cc4114bfb..40c064e800 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -403,14 +403,11 @@ // TODO: IDF-6270 (Copy from esp32c6, need check) /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - #define SOC_PM_SUPPORT_CPU_PD (1) - #define SOC_PM_SUPPORT_WIFI_PD (1) - #define SOC_PM_SUPPORT_BT_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) // TODO: IDF-6229 (Copy from esp32c6, need check) /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index ad28130f48..efec18599b 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -767,6 +767,10 @@ config SOC_PM_SUPPORT_BT_PD bool default y +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 9c945a4e4a..1a745d54b0 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -362,12 +362,10 @@ #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) /*-------------------------- Power Management CAPS ----------------------------*/ - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - #define SOC_PM_SUPPORT_CPU_PD (1) - #define SOC_PM_SUPPORT_BT_PD (1) +#define SOC_PM_SUPPORT_RC_FAST_PD (1) /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 469453abce..352f0622dd 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -907,6 +907,10 @@ config SOC_PM_SUPPORT_RTC_SLOW_MEM_PD bool default y +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + config SOC_CLK_APLL_SUPPORTED bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 3915e17c18..5fc78fd97d 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -401,6 +401,7 @@ #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!