mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-02 16:11:41 +01:00
bootloader: move bootloader flash support to isolate folders
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@@ -7,36 +7,14 @@
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "sdkconfig.h"
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#include <stdint.h>
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#include <stdbool.h>
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP8684
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#include "esp32h2/rom/spi_flash.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup spi_flash_apis, spi flash operation related apis
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* @brief spi_flash apis
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*/
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/** @addtogroup spi_flash_apis
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* @{
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*/
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typedef enum {
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ESP_ROM_SPIFLASH_QIO_MODE = 0,
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ESP_ROM_SPIFLASH_QOUT_MODE,
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@@ -69,59 +47,11 @@ typedef struct {
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uint16_t data;
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} esp_rom_spiflash_common_cmd_t;
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/**
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* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
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* Please do not call this function in SDK.
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*
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* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
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*
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* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
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*
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* @return None
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*/
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void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
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/**
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* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
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/**
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* @brief Set SPI Flash pad drivers.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
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* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
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* Values usually read from falsh by rom code, function usually callde by rom code.
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* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
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*
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* @return None
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*/
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void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
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/**
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* @brief Select SPI Flash function for pads.
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* Please do not call this function in SDK.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
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typedef enum {
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ESP_ROM_SPIFLASH_RESULT_OK,
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ESP_ROM_SPIFLASH_RESULT_ERR,
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ESP_ROM_SPIFLASH_RESULT_TIMEOUT
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} esp_rom_spiflash_result_t;
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/**
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* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
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@@ -130,7 +60,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
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* @param uint8_t legacy: always keeping false.
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*
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* @return None
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*/
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@@ -220,18 +150,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
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*/
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esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
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/**
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* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
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* Please do not call this function in SDK.
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*
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* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
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*
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* @return uint16_t 0 : do not send command any more.
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* 1 : go to the next command.
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* n > 1 : skip (n - 1) commands.
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*/
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uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
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/**
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* @brief Unlock SPI write protect.
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* Please do not call this function in SDK.
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@@ -460,14 +378,15 @@ typedef struct {
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esp_rom_spiflash_chip_t chip;
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uint8_t dummy_len_plus[3];
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uint8_t sig_matrix;
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} spiflash_legacy_data_t;
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} esp_rom_spiflash_legacy_data_t;
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/* Flash data defined in ROM*/
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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extern esp_rom_spiflash_chip_t g_rom_flashchip;
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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#else
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extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
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extern esp_rom_spiflash_legacy_data_t *rom_spiflash_legacy_data;
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#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
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#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
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#endif
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