From b10dec96c5db1b6c5a8aaf416deb25749827efeb Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 30 Jan 2024 18:16:20 +0800 Subject: [PATCH] fix(rgb_lcd): relax the check for the data line GPIO so we allow to leave some RGB data line unconnected by set the GPIO to -1 --- components/esp_lcd/rgb/esp_lcd_panel_rgb.c | 23 +++++++++++---------- components/hal/esp32p4/include/hal/lcd_ll.h | 1 + components/hal/esp32s3/include/hal/lcd_ll.h | 1 + 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index 4b0df4336b..cadaedd4cc 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -336,7 +336,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf ret = lcd_rgb_panel_configure_gpio(rgb_panel, rgb_panel_config); ESP_GOTO_ON_ERROR(ret, err, TAG, "configure GPIO failed"); // fill other rgb panel runtime parameters - memcpy(rgb_panel->data_gpio_nums, rgb_panel_config->data_gpio_nums, SOC_LCD_RGB_DATA_WIDTH); + memcpy(rgb_panel->data_gpio_nums, rgb_panel_config->data_gpio_nums, sizeof(rgb_panel->data_gpio_nums)); rgb_panel->timings = rgb_panel_config->timings; rgb_panel->data_width = rgb_panel_config->data_width; rgb_panel->output_bits_per_pixel = fb_bits_per_pixel; // by default, the output bpp is the same as the frame buffer bpp @@ -783,8 +783,10 @@ static esp_err_t rgb_panel_invert_color(esp_lcd_panel_t *panel, bool invert_colo int panel_id = rgb_panel->panel_id; // inverting the data line by GPIO matrix for (int i = 0; i < rgb_panel->data_width; i++) { - esp_rom_gpio_connect_out_signal(rgb_panel->data_gpio_nums[i], lcd_periph_signals.panels[panel_id].data_sigs[i], - invert_color_data, false); + if (rgb_panel->data_gpio_nums[i] >= 0) { + esp_rom_gpio_connect_out_signal(rgb_panel->data_gpio_nums[i], lcd_periph_signals.panels[panel_id].data_sigs[i], + invert_color_data, false); + } } return ESP_OK; } @@ -836,9 +838,6 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_ // Hsync and Vsync are required in HV mode valid_gpio = valid_gpio && (panel_config->hsync_gpio_num >= 0) && (panel_config->vsync_gpio_num >= 0); } - for (size_t i = 0; i < panel_config->data_width; i++) { - valid_gpio = valid_gpio && (panel_config->data_gpio_nums[i] >= 0); - } if (!valid_gpio) { return ESP_ERR_INVALID_ARG; } @@ -846,10 +845,12 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_ lcd_ll_set_data_wire_width(panel->hal.dev, panel_config->data_width); // connect peripheral signals via GPIO matrix for (size_t i = 0; i < panel_config->data_width; i++) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->data_gpio_nums[i]], PIN_FUNC_GPIO); - gpio_set_direction(panel_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i], - lcd_periph_signals.panels[panel_id].data_sigs[i], false, false); + if (panel_config->data_gpio_nums[i] >= 0) { + gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->data_gpio_nums[i]], PIN_FUNC_GPIO); + gpio_set_direction(panel_config->data_gpio_nums[i], GPIO_MODE_OUTPUT); + esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i], + lcd_periph_signals.panels[panel_id].data_sigs[i], false, false); + } } if (panel_config->hsync_gpio_num >= 0) { gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->hsync_gpio_num], PIN_FUNC_GPIO); @@ -965,7 +966,7 @@ static IRAM_ATTR bool lcd_rgb_panel_eof_handler(gdma_channel_handle_t dma_chan, // If we restart GDMA, many pixels already have been transferred to the LCD peripheral. // Looks like that has 16 pixels of FIFO plus one holding register. -#define LCD_FIFO_PRESERVE_SIZE_PX (GDMA_LL_L2FIFO_BASE_SIZE + 1) +#define LCD_FIFO_PRESERVE_SIZE_PX (LCD_LL_FIFO_DEPTH + 1) static esp_err_t lcd_rgb_panel_create_trans_link(esp_rgb_panel_t *panel) { diff --git a/components/hal/esp32p4/include/hal/lcd_ll.h b/components/hal/esp32p4/include/hal/lcd_ll.h index 58bfeb34ec..bdd3ef12a9 100644 --- a/components/hal/esp32p4/include/hal/lcd_ll.h +++ b/components/hal/esp32p4/include/hal/lcd_ll.h @@ -28,6 +28,7 @@ extern "C" { #define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width #define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width +#define LCD_LL_FIFO_DEPTH 8 // Async FIFO depth /** * @brief LCD data byte swizzle mode diff --git a/components/hal/esp32s3/include/hal/lcd_ll.h b/components/hal/esp32s3/include/hal/lcd_ll.h index 284d9c3258..7e46542a37 100644 --- a/components/hal/esp32s3/include/hal/lcd_ll.h +++ b/components/hal/esp32s3/include/hal/lcd_ll.h @@ -28,6 +28,7 @@ extern "C" { #define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width #define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width +#define LCD_LL_FIFO_DEPTH 16 // Async FIFO depth /** * @brief LCD data byte swizzle mode