diff --git a/components/hal/esp32/include/hal/dac_ll.h b/components/hal/esp32/include/hal/dac_ll.h
index 7eb4955705..dce5fa62e5 100644
--- a/components/hal/esp32/include/hal/dac_ll.h
+++ b/components/hal/esp32/include/hal/dac_ll.h
@@ -65,10 +65,10 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
 {
     if (channel == DAC_CHANNEL_1) {
         SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     } else if (channel == DAC_CHANNEL_2) {
         SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     }
 }
 
diff --git a/components/hal/esp32/include/hal/mcpwm_ll.h b/components/hal/esp32/include/hal/mcpwm_ll.h
index 15f70c2f98..619add398d 100644
--- a/components/hal/esp32/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32/include/hal/mcpwm_ll.h
@@ -85,7 +85,7 @@ static inline mcpwm_intr_t mcpwm_ll_get_intr(mcpwm_dev_t *mcpwm)
  * @param mcpwm Address of the MCPWM peripheral registers.
  * @param intr Bitwise ORed interrupts to clear.
  */
-static inline void mcpwm_ll_clear_intr(mcpwm_dev_t* mcpwm, mcpwm_intr_t intr)
+static inline void mcpwm_ll_clear_intr(mcpwm_dev_t *mcpwm, mcpwm_intr_t intr)
 {
     mcpwm->int_clr.val = intr;
 }
@@ -100,9 +100,9 @@ static inline void mcpwm_ll_clear_intr(mcpwm_dev_t* mcpwm, mcpwm_intr_t intr)
  * @param timer The timer to set the prescale, 0-2.
  * @param prescale Prescale factor, 0-255.
  */
-static inline void mcpwm_ll_timer_set_prescale(mcpwm_dev_t* mcpwm, int timer, uint32_t prescale)
+static inline void mcpwm_ll_timer_set_prescale(mcpwm_dev_t *mcpwm, int timer, uint32_t prescale)
 {
-    mcpwm->timer[timer].period.prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer].period, prescale, prescale);
 }
 
 
@@ -155,8 +155,7 @@ static inline void mcpwm_ll_timer_stop(mcpwm_dev_t *mcpwm, int timer)
  */
 static inline void mcpwm_ll_timer_set_period(mcpwm_dev_t *mcpwm, int timer, uint32_t period)
 {
-
-    mcpwm->timer[timer].period.period = period - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer].period, period, period - 1);
     mcpwm->timer[timer].period.upmethod = 0;
 }
 
@@ -169,7 +168,7 @@ static inline void mcpwm_ll_timer_set_period(mcpwm_dev_t *mcpwm, int timer, uint
  */
 static inline uint32_t mcpwm_ll_timer_get_period(mcpwm_dev_t *mcpwm, int timer)
 {
-    return mcpwm->timer[timer].period.period + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer].period, period) + 1;
 }
 
 /********************* Sync *******************/
@@ -264,7 +263,7 @@ static inline void mcpwm_ll_operator_set_compare_upmethod(mcpwm_dev_t *mcpwm, in
  */
 static inline uint32_t mcpwm_ll_operator_get_compare(mcpwm_dev_t *mcpwm, int op, int cmp_n)
 {
-    return (mcpwm->channel[op].cmpr_value[cmp_n].cmpr_val);
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->channel[op].cmpr_value[cmp_n], cmpr_val);
 }
 
 /**
@@ -277,7 +276,7 @@ static inline uint32_t mcpwm_ll_operator_get_compare(mcpwm_dev_t *mcpwm, int op,
  */
 static inline void mcpwm_ll_operator_set_compare(mcpwm_dev_t *mcpwm, int op, int cmp_n, uint32_t compare)
 {
-    mcpwm->channel[op].cmpr_value[cmp_n].cmpr_val = compare;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->channel[op].cmpr_value[cmp_n], cmpr_val, compare);
 }
 
 /********************* Generator *******************/
@@ -325,7 +324,7 @@ static inline void mcpwm_ll_gen_set_period_action(mcpwm_dev_t *mcpwm, int op, in
  * @param down_action The action to take when the counter is counting down.
  */
 static inline void mcpwm_ll_gen_set_cmp_action(mcpwm_dev_t *mcpwm, int op, int gen,
-               int cmp_n, mcpwm_output_action_t up_action, mcpwm_output_action_t down_action)
+        int cmp_n, mcpwm_output_action_t up_action, mcpwm_output_action_t down_action)
 {
     if (cmp_n == 0) {
         mcpwm->channel[op].generator[gen].utea = up_action;
@@ -473,7 +472,7 @@ static inline void mcpwm_ll_fault_set_oneshot_action(mcpwm_dev_t *mcpwm, int op,
  * @param down_action   Action to take when fault happens when counting down.
  */
 static inline void mcpwm_ll_fault_set_cyc_action(mcpwm_dev_t *mcpwm, int op, int gen,
-                  mcpwm_output_action_t up_action, mcpwm_output_action_t down_action)
+        mcpwm_output_action_t up_action, mcpwm_output_action_t down_action)
 {
     mcpwm->channel[op].tz_cfg1.cbcpulse = BIT(0);    //immediately
     if (gen == 0) {
@@ -509,7 +508,7 @@ static inline void mcpwm_ll_deadtime_init(mcpwm_dev_t *mcpwm, int op)
  * @param mode  Dead zone mode to use.
  */
 static inline void mcpwm_ll_set_deadtime_mode(mcpwm_dev_t *mcpwm,
-    int op, mcpwm_deadtime_type_t mode)
+        int op, mcpwm_deadtime_type_t mode)
 {
 #define MCPWM_LL_DEADTIME_REG_MASK (MCPWM_DT0_DEB_MODE_M | MCPWM_DT0_A_OUTSWAP_M | MCPWM_DT0_B_OUTSWAP_M | \
     MCPWM_DT0_RED_INSEL_M | MCPWM_DT0_FED_INSEL_M | MCPWM_DT0_RED_OUTINVERT_M | MCPWM_DT0_FED_OUTINVERT_M | \
@@ -541,7 +540,7 @@ static inline void mcpwm_ll_set_deadtime_mode(mcpwm_dev_t *mcpwm,
  */
 static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int op, uint32_t fed)
 {
-    mcpwm->channel[op].db_fed_cfg.fed = fed;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->channel[op].db_fed_cfg, fed, fed);
 }
 
 /**
@@ -553,7 +552,7 @@ static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int o
  */
 static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int op, uint32_t red)
 {
-    mcpwm->channel[op].db_red_cfg.red = red;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->channel[op].db_red_cfg, red, red);
 }
 
 /**
@@ -688,7 +687,7 @@ static inline mcpwm_capture_on_edge_t mcpwm_ll_get_captured_edge(mcpwm_dev_t *mc
     } else {   //2
         edge = mcpwm->cap_status.cap2_edge;
     }
-    return (edge? MCPWM_NEG_EDGE: MCPWM_POS_EDGE);
+    return (edge ? MCPWM_NEG_EDGE : MCPWM_POS_EDGE);
 }
 
 STATIC_HAL_REG_CHECK(MCPWM, MCPWM_NEG_EDGE, BIT(0));
@@ -702,7 +701,7 @@ STATIC_HAL_REG_CHECK(MCPWM, MCPWM_POS_EDGE, BIT(1));
  * @param cap_edge  The edge to capture, bitwise.
  */
 static inline void mcpwm_ll_capture_select_edge(mcpwm_dev_t *mcpwm, int cap_sig,
-                                  mcpwm_capture_on_edge_t cap_edge)
+        mcpwm_capture_on_edge_t cap_edge)
 {
     mcpwm->cap_cfg_ch[cap_sig].mode = cap_edge;
 }
@@ -716,7 +715,7 @@ static inline void mcpwm_ll_capture_select_edge(mcpwm_dev_t *mcpwm, int cap_sig,
  */
 static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int cap_sig, uint32_t prescale)
 {
-    mcpwm->cap_cfg_ch[cap_sig].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->cap_cfg_ch[cap_sig], prescale, prescale);
 }
 
 /**
@@ -727,7 +726,7 @@ static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int cap_sig
  */
 static inline mcpwm_intr_t mcpwm_ll_get_cap_intr_def(int bit)
 {
-    return BIT(bit+MCPWM_CAP0_INT_RAW_S);
+    return BIT(bit + MCPWM_CAP0_INT_RAW_S);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h
index 676ce21ad3..6653057472 100644
--- a/components/hal/esp32/include/hal/rmt_ll.h
+++ b/components/hal/esp32/include/hal/rmt_ll.h
@@ -122,23 +122,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
 static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
@@ -149,12 +149,12 @@ static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b
 
 static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf0.idle_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
 }
 
 static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->conf_ch[channel].conf0.idle_thres;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
 }
 
 static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
@@ -184,7 +184,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -313,14 +313,14 @@ static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
 
 static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    dev->carrier_duty_ch[channel].high = high_ticks;
-    dev->carrier_duty_ch[channel].low = low_ticks;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks);
 }
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->carrier_duty_ch[channel].high;
-    *low_ticks = dev->carrier_duty_ch[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32/include/hal/sigmadelta_ll.h b/components/hal/esp32/include/hal/sigmadelta_ll.h
index c8f1f80723..000cd31da4 100644
--- a/components/hal/esp32/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32/include/hal/sigmadelta_ll.h
@@ -25,6 +25,7 @@
 #include "soc/sigmadelta_periph.h"
 #include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
+#include "hal/hal_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -54,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -66,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/hal/esp32/include/hal/timer_ll.h
index 4ff9c68866..d3f1941f55 100644
--- a/components/hal/esp32/include/hal/timer_ll.h
+++ b/components/hal/esp32/include/hal/timer_ll.h
@@ -23,6 +23,7 @@ extern "C" {
 
 #include <stdlib.h>
 #include "hal/timer_types.h"
+#include "hal/hal_defs.h"
 #include "soc/timer_periph.h"
 #include "soc/timer_group_struct.h"
 
@@ -52,7 +53,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     }
     int timer_en = hw->hw_timer[timer_num].config.enable;
     hw->hw_timer[timer_num].config.enable = 0;
-    hw->hw_timer[timer_num].config.divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
     hw->hw_timer[timer_num].config.enable = timer_en;
 }
 
@@ -67,7 +68,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h
index 0291724234..fa4d7689e4 100644
--- a/components/hal/esp32/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32/include/hal/touch_sensor_ll.h
@@ -295,9 +295,9 @@ static inline void touch_ll_set_threshold(touch_pad_t touch_num, uint16_t thresh
 {
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
     if (tp_wrap & 0x1) {
-        SENS.touch_thresh[tp_wrap / 2].l_thresh = threshold;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh, threshold);
     } else {
-        SENS.touch_thresh[tp_wrap / 2].h_thresh = threshold;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh, threshold);
     }
 }
 
@@ -312,8 +312,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint16_t *thres
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
     if (threshold) {
         *threshold = (tp_wrap & 0x1 ) ?
-                     SENS.touch_thresh[tp_wrap / 2].l_thresh :
-                     SENS.touch_thresh[tp_wrap / 2].h_thresh;
+                     HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh) :
+                     HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh);
     }
 }
 
@@ -493,7 +493,8 @@ static inline void touch_ll_intr_clear(void)
 static inline uint32_t touch_ll_read_raw_data(touch_pad_t touch_num)
 {
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
-    return ((tp_wrap & 0x1) ? SENS.touch_meas[tp_wrap / 2].l_val : SENS.touch_meas[tp_wrap / 2].h_val);
+    return ((tp_wrap & 0x1) ? HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_meas[tp_wrap / 2], l_val) :
+                              HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_meas[tp_wrap / 2], h_val));
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/twai_ll.h b/components/hal/esp32/include/hal/twai_ll.h
index 869759258a..40f1b38373 100644
--- a/components/hal/esp32/include/hal/twai_ll.h
+++ b/components/hal/esp32/include/hal/twai_ll.h
@@ -579,8 +579,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = __builtin_bswap32(code);
     uint32_t mask_swapped = __builtin_bswap32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -615,7 +615,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -795,8 +795,8 @@ static inline void twai_ll_save_reg(twai_dev_t *hw, twai_ll_reg_save_t *reg_save
     reg_save->bus_timing_1_reg = (uint8_t) hw->bus_timing_1_reg.val;
     reg_save->error_warning_limit_reg = (uint8_t) hw->error_warning_limit_reg.val;
     for (int i = 0; i < 4; i++) {
-        reg_save->acr_reg[i] = hw->acceptance_filter.acr[i].byte;
-        reg_save->amr_reg[i] = hw->acceptance_filter.amr[i].byte;
+        reg_save->acr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte);
+        reg_save->amr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte);
     }
     reg_save->rx_error_counter_reg = (uint8_t) hw->rx_error_counter_reg.val;
     reg_save->tx_error_counter_reg = (uint8_t) hw->tx_error_counter_reg.val;
@@ -822,8 +822,8 @@ static inline void twai_ll_restore_reg(twai_dev_t *hw, twai_ll_reg_save_t *reg_s
     hw->bus_timing_1_reg.val = reg_save->bus_timing_1_reg;
     hw->error_warning_limit_reg.val = reg_save->error_warning_limit_reg;
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = reg_save->acr_reg[i];
-        hw->acceptance_filter.amr[i].byte = reg_save->amr_reg[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, reg_save->acr_reg[i]);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, reg_save->amr_reg[i]);
     }
     hw->rx_error_counter_reg.val = reg_save->rx_error_counter_reg;
     hw->tx_error_counter_reg.val = reg_save->tx_error_counter_reg;
diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h
index 41facaf158..af1ef16e2d 100644
--- a/components/hal/esp32c3/include/hal/i2c_ll.h
+++ b/components/hal/esp32c3/include/hal/i2c_ll.h
@@ -576,7 +576,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i< len; i++) {
-        hw->fifo_data.data = ptr[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]);
     }
 }
 
diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h
index 731d74c363..ad867fe4ea 100644
--- a/components/hal/esp32c3/include/hal/rmt_ll.h
+++ b/components/hal/esp32c3/include/hal/rmt_ll.h
@@ -138,22 +138,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->tx_conf[channel].div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->rx_conf[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt);
 }
 
 static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt);
 }
 
 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -230,7 +230,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->rx_conf[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -413,32 +413,26 @@ static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
 
 static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
-    // We take care of the "read-modify-write" procedure by ourselves.
-    typeof(dev->tx_carrier[0]) reg;
-    reg.high = high_ticks;
-    reg.low = low_ticks;
-    dev->tx_carrier[channel].val = reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_carrier[channel], high, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_carrier[channel], low, low_ticks);
 }
 
 static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    typeof(dev->rx_carrier[0]) reg;
-    reg.high_thres = high_ticks;
-    reg.low_thres = low_ticks;
-    dev->rx_carrier[channel].val = reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_carrier[channel], high_thres, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_carrier[channel], low_thres, low_ticks);
 }
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->tx_carrier[channel].high;
-    *low_ticks = dev->tx_carrier[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], low);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->rx_carrier[channel].high_thres;
-    *low_ticks = dev->rx_carrier[channel].low_thres;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], high_thres);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], low_thres);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32c3/include/hal/sigmadelta_ll.h b/components/hal/esp32c3/include/hal/sigmadelta_ll.h
index 0a559dfb52..43afda1a97 100644
--- a/components/hal/esp32c3/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32c3/include/hal/sigmadelta_ll.h
@@ -25,6 +25,7 @@
 #include "soc/sigmadelta_periph.h"
 #include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
+#include "hal/hal_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -54,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -66,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h
index b17667e7de..105d33dd5d 100644
--- a/components/hal/esp32c3/include/hal/timer_ll.h
+++ b/components/hal/esp32c3/include/hal/timer_ll.h
@@ -25,6 +25,7 @@ extern "C" {
 #include "hal/timer_types.h"
 #include "soc/timer_periph.h"
 #include "soc/timer_group_struct.h"
+#include "hal/hal_defs.h"
 
 _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
 _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
@@ -50,7 +51,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
 {
     int timer_en = hw->hw_timer[timer_num].config.enable;
     hw->hw_timer[timer_num].config.enable = 0;
-    hw->hw_timer[timer_num].config.divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
     hw->hw_timer[timer_num].config.enable = timer_en;
 }
 
@@ -65,7 +66,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
     if (d == 0) {
         d = 65536;
     }
diff --git a/components/hal/esp32c3/include/hal/twai_ll.h b/components/hal/esp32c3/include/hal/twai_ll.h
index 68df4cf7e2..41fa40817d 100644
--- a/components/hal/esp32c3/include/hal/twai_ll.h
+++ b/components/hal/esp32c3/include/hal/twai_ll.h
@@ -487,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = __builtin_bswap32(code);
     uint32_t mask_swapped = __builtin_bswap32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -523,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/dac_ll.h b/components/hal/esp32s2/include/hal/dac_ll.h
index deb50ce35f..c2e7ca05e5 100644
--- a/components/hal/esp32s2/include/hal/dac_ll.h
+++ b/components/hal/esp32s2/include/hal/dac_ll.h
@@ -77,10 +77,10 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
 {
     if (channel == DAC_CHANNEL_1) {
         SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     } else if (channel == DAC_CHANNEL_2) {
         SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h
index 608b72e455..e9533c04d8 100644
--- a/components/hal/esp32s2/include/hal/rmt_ll.h
+++ b/components/hal/esp32s2/include/hal/rmt_ll.h
@@ -20,6 +20,7 @@ extern "C" {
 #include <stdbool.h>
 #include "soc/soc_caps.h"
 #include "soc/rmt_struct.h"
+#include "hal/hal_defs.h"
 
 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
@@ -123,23 +124,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
 static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
@@ -150,12 +151,12 @@ static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b
 
 static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf0.idle_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
 }
 
 static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->conf_ch[channel].conf0.idle_thres;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
 }
 
 static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
@@ -217,7 +218,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -386,32 +387,26 @@ static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
 
 static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
-    // We take care of the "read-modify-write" procedure by ourselves.
-    typeof(dev->carrier_duty_ch[0]) reg;
-    reg.high = high_ticks;
-    reg.low = low_ticks;
-    dev->carrier_duty_ch[channel].val = reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks);
 }
 
 static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    typeof(dev->ch_rx_carrier_rm[0]) reg;
-    reg.carrier_high_thres_ch = high_ticks;
-    reg.carrier_low_thres_ch = low_ticks;
-    dev->ch_rx_carrier_rm[channel].val = reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch, low_ticks);
 }
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->carrier_duty_ch[channel].high;
-    *low_ticks = dev->carrier_duty_ch[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->ch_rx_carrier_rm[channel].carrier_high_thres_ch;
-    *low_ticks = dev->ch_rx_carrier_rm[channel].carrier_low_thres_ch;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32s2/include/hal/sigmadelta_ll.h b/components/hal/esp32s2/include/hal/sigmadelta_ll.h
index e0124b0df2..a230129ace 100644
--- a/components/hal/esp32s2/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32s2/include/hal/sigmadelta_ll.h
@@ -25,6 +25,7 @@
 #include "soc/sigmadelta_periph.h"
 #include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
+#include "hal/hal_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -54,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -66,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/hal/esp32s2/include/hal/timer_ll.h
index 1849064381..38739cec31 100644
--- a/components/hal/esp32s2/include/hal/timer_ll.h
+++ b/components/hal/esp32s2/include/hal/timer_ll.h
@@ -25,6 +25,7 @@ extern "C" {
 #include "hal/timer_types.h"
 #include "soc/timer_periph.h"
 #include "soc/timer_group_struct.h"
+#include "hal/hal_defs.h"
 
 _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
 _Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
@@ -50,7 +51,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     }
     int timer_en = hw->hw_timer[timer_num].config.enable;
     hw->hw_timer[timer_num].config.enable = 0;
-    hw->hw_timer[timer_num].config.divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
     hw->hw_timer[timer_num].config.enable = timer_en;
 }
 
@@ -65,7 +66,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
     if (d == 0) {
         d = 65536;
     }
diff --git a/components/hal/esp32s2/include/hal/twai_ll.h b/components/hal/esp32s2/include/hal/twai_ll.h
index 0dd352757c..235aab8ffc 100644
--- a/components/hal/esp32s2/include/hal/twai_ll.h
+++ b/components/hal/esp32s2/include/hal/twai_ll.h
@@ -487,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = __builtin_bswap32(code);
     uint32_t mask_swapped = __builtin_bswap32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -523,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }