From b194636859f3f89ef44b48126e34cc268bc0115a Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Wed, 4 Jun 2025 15:15:33 +0800 Subject: [PATCH] feat(spi_flash): Add spi flash suspend support on esp32c5, esp32c61 --- .../hal/esp32c5/include/hal/spimem_flash_ll.h | 15 +- .../esp32c61/include/hal/spimem_flash_ll.h | 15 +- components/hal/include/hal/spi_flash_hal.h | 2 + components/hal/spi_flash_hal.c | 1 + components/hal/spi_flash_hal_iram.c | 7 +- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c5/include/soc/soc_caps.h | 1 + .../soc/esp32c5/register/soc/spi1_mem_reg.h | 14 +- .../esp32c5/register/soc/spi1_mem_struct.h | 21 +- .../soc/esp32c5/register/soc/spi_mem_c_reg.h | 114 +- .../esp32c5/register/soc/spi_mem_c_reg_eco2.h | 3988 ----------------- .../esp32c5/register/soc/spi_mem_c_struct.h | 261 +- .../register/soc/spi_mem_c_struct_eco2.h | 2982 ------------ .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 + .../soc/esp32c61/include/soc/soc_caps.h | 1 + components/spi_flash/Kconfig | 12 + components/spi_flash/esp_flash_spi_init.c | 15 +- 17 files changed, 300 insertions(+), 7157 deletions(-) delete mode 100644 components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h delete mode 100644 components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h index f6f1b4e1fa..390aa8d7b6 100644 --- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -216,7 +216,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 } /** - * Configure the delay after Suspend/Resume + * Configure the delay after Suspend * * @param dev Beginning address of the peripheral registers. * @param dly_val delay time @@ -224,10 +224,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val) { dev->ctrl1.cs_hold_dly_res = dly_val; - dev->sus_status.flash_per_dly_128 = 1; dev->sus_status.flash_pes_dly_128 = 1; } +/** + * Configure the delay after Resume + * + * @param dev Beginning address of the peripheral registers. + * @param dly_val delay time + */ +static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val) +{ + dev->ctrl1.cs_hold_dly_per = dly_val; + dev->sus_status.flash_per_dly_128 = 1; +} + /** * Configure the cs hold delay time(used to set the minimum CS high time tSHSL) * diff --git a/components/hal/esp32c61/include/hal/spimem_flash_ll.h b/components/hal/esp32c61/include/hal/spimem_flash_ll.h index 3fb325e2d1..2174d97944 100644 --- a/components/hal/esp32c61/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c61/include/hal/spimem_flash_ll.h @@ -215,7 +215,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 } /** - * Configure the delay after Suspend/Resume + * Configure the delay after Suspend * * @param dev Beginning address of the peripheral registers. * @param dly_val delay time @@ -223,10 +223,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val) { dev->ctrl1.cs_hold_dly_res = dly_val; - dev->sus_status.flash_per_dly_128 = 1; dev->sus_status.flash_pes_dly_128 = 1; } +/** + * Configure the delay after Resume + * + * @param dev Beginning address of the peripheral registers. + * @param dly_val delay time + */ +static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val) +{ + dev->ctrl1.cs_hold_dly_per = dly_val; + dev->sus_status.flash_per_dly_128 = 1; +} + /** * Configure the cs hold delay time(used to set the minimum CS high time tSHSL) * diff --git a/components/hal/include/hal/spi_flash_hal.h b/components/hal/include/hal/spi_flash_hal.h index a0f0ee1746..e21a42fec2 100644 --- a/components/hal/include/hal/spi_flash_hal.h +++ b/components/hal/include/hal/spi_flash_hal.h @@ -57,6 +57,7 @@ typedef struct { #define SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR BIT(0) ///< Slice data according to DTR mode, the address and length must be even (A0=0). int freq_mhz; /// Flash clock frequency. uint8_t tsus_val; ///< Tsus value of suspend (us) + uint8_t trs_val; ///< Trs value of suspend (us) bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay. } spi_flash_hal_context_t; ESP_STATIC_ASSERT(sizeof(spi_flash_hal_context_t) == 48, "size of spi_flash_hal_context_t incorrect. Please check data compatibility with the ROM"); @@ -94,6 +95,7 @@ typedef struct { int freq_mhz; ///< SPI flash clock speed (MHZ). int clock_src_freq; ///< SPI flash clock source (MHZ). uint8_t tsus_val; ///< Tsus value of suspend (us). + uint8_t trs_val; ///< Trs value of suspend (us) bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay. } spi_flash_hal_config_t; diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c index 46a63c773f..de457e1d1b 100644 --- a/components/hal/spi_flash_hal.c +++ b/components/hal/spi_flash_hal.c @@ -131,6 +131,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_ data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND; data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME; data_out->tsus_val = cfg->tsus_val; + data_out->trs_val = cfg->trs_val; data_out->auto_waiti_pes = cfg->auto_waiti_pes; } diff --git a/components/hal/spi_flash_hal_iram.c b/components/hal/spi_flash_hal_iram.c index e4f62e956c..611756b72e 100644 --- a/components/hal/spi_flash_hal_iram.c +++ b/components/hal/spi_flash_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -154,6 +154,11 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host) // tsus = ceil(ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); spimem_flash_ll_set_sus_delay(dev, tsus); +#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + // trs = ceil(ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); + uint32_t trs = (ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->trs_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); + spimem_flash_ll_set_rs_delay(dev, trs); +#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR // tshsl2 = ceil(SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() * 0.001); uint32_t tshsl2 = (SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() / 1000) + ((SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz()) % 1000 != 0); spimem_flash_set_cs_hold_delay(dev, tshsl2); diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 8d4f1df11e..31b5bae58d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1207,6 +1207,10 @@ config SOC_SPI_MEM_SUPPORT_TIMING_TUNING bool default y +config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + bool + default y + config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index e10357be40..68514f9d99 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -475,6 +475,7 @@ #define SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) +#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 diff --git a/components/soc/esp32c5/register/soc/spi1_mem_reg.h b/components/soc/esp32c5/register/soc/spi1_mem_reg.h index d5116a49c6..d153011d6d 100644 --- a/components/soc/esp32c5/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32c5/register/soc/spi1_mem_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -328,13 +328,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 /** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ #define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S) #define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ +#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S) +#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_S 12 /** SPI_MEM_CTRL2_REG(i) register * SPI1 control2 register. diff --git a/components/soc/esp32c5/register/soc/spi1_mem_struct.h b/components/soc/esp32c5/register/soc/spi1_mem_struct.h index d1b4d26a97..67702ddf29 100644 --- a/components/soc/esp32c5/register/soc/spi1_mem_struct.h +++ b/components/soc/esp32c5/register/soc/spi1_mem_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -338,11 +338,16 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ + uint32_t cs_hold_dly_per:10; + uint32_t reserved_22:10; }; uint32_t val; } spi_mem_ctrl1_reg_t; @@ -367,16 +372,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -1222,7 +1227,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774400; + /** date : R/W; bitpos: [27:0]; default: 37786176; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_reg.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h index 40b9b2fef8..857e106ccf 100644 --- a/components/soc/esp32c5/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -205,29 +205,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) #define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) #define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) #define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 /** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -488,10 +480,13 @@ extern "C" { /** SPI_MEM_RD_STATUS_REG register * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c) /** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE 0x000000FFU #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) @@ -499,6 +494,7 @@ extern "C" { #define SPI_MEM_WB_MODE_S 16 /** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_BITLEN 0x00000007U #define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) @@ -506,6 +502,7 @@ extern "C" { #define SPI_MEM_WB_MODE_BITLEN_S 24 /** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_EN (BIT(27)) #define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) @@ -937,14 +934,16 @@ extern "C" { */ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) /** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_L 0x000000FFU #define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) #define SPI_MEM_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_SCLKCNT_L_S 0 /** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_H 0x000000FFU #define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) @@ -952,7 +951,8 @@ extern "C" { #define SPI_MEM_SCLKCNT_H_S 8 /** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_N 0x000000FFU #define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) @@ -961,6 +961,7 @@ extern "C" { /** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) @@ -971,27 +972,27 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [12]; default: 0; +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. */ -#define SPI_MEM_FLASH_LOCK_EN (BIT(12)) +#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) #define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) #define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U -#define SPI_MEM_FLASH_LOCK_EN_S 12 -/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [13]; default: 0; +#define SPI_MEM_FLASH_LOCK_EN_S 19 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. */ -#define SPI_MEM_SRAM_LOCK_EN (BIT(13)) +#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) #define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) #define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U -#define SPI_MEM_SRAM_LOCK_EN_S 13 +#define SPI_MEM_SRAM_LOCK_EN_S 20 /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register @@ -1593,7 +1594,7 @@ extern "C" { #define SPI_SMEM_HYPERBUS_CA_S 30 /** SPI_FMEM_PMS0_ATTR_REG register - * MSPI flash PMS section 0 attribute register + * SPI1 flash PMS section 0 attribute register */ #define SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) /** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1621,7 +1622,7 @@ extern "C" { #define SPI_FMEM_PMS0_ECC_S 2 /** SPI_FMEM_PMS1_ATTR_REG register - * MSPI flash PMS section 1 attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) /** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1649,7 +1650,7 @@ extern "C" { #define SPI_FMEM_PMS1_ECC_S 2 /** SPI_FMEM_PMS2_ATTR_REG register - * MSPI flash PMS section 2 attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) /** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1677,7 +1678,7 @@ extern "C" { #define SPI_FMEM_PMS2_ECC_S 2 /** SPI_FMEM_PMS3_ATTR_REG register - * MSPI flash PMS section 3 attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10c) /** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1805,7 +1806,7 @@ extern "C" { #define SPI_FMEM_PMS3_SIZE_S 0 /** SPI_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) /** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1833,7 +1834,7 @@ extern "C" { #define SPI_SMEM_PMS0_ECC_S 2 /** SPI_SMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 start address register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) /** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1861,7 +1862,7 @@ extern "C" { #define SPI_SMEM_PMS1_ECC_S 2 /** SPI_SMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 start address register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) /** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1889,7 +1890,7 @@ extern "C" { #define SPI_SMEM_PMS2_ECC_S 2 /** SPI_SMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 start address register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13c) /** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -2669,7 +2670,7 @@ extern "C" { #define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) #define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U #define SPI_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; +/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1; * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. */ @@ -2677,7 +2678,7 @@ extern "C" { #define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) #define SPI_SMEM_DQS0_270_SEL_V 0x00000003U #define SPI_SMEM_DQS0_270_SEL_S 7 -/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; +/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1; * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, * 2'd2: 1.5ns 2'd3: 2.0ns. */ @@ -2685,6 +2686,22 @@ extern "C" { #define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) #define SPI_SMEM_DQS0_90_SEL_V 0x00000003U #define SPI_SMEM_DQS0_90_SEL_S 9 +/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_270_SEL 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S) +#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_S 11 +/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_90_SEL 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S) +#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_S 13 /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register @@ -3309,6 +3326,13 @@ extern "C" { #define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) #define SPI_CLK_EN_V 0x00000001U #define SPI_CLK_EN_S 0 +/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ +#define SPI_MSPI_CLK_FORCE_ON (BIT(1)) +#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S) +#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U +#define SPI_MSPI_CLK_FORCE_ON_S 1 /** SPI_MEM_NAND_FLASH_EN_REG register * NAND FLASH control register @@ -3755,14 +3779,14 @@ extern "C" { #define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) #define SPI_MMU_MEM_FORCE_ON_V 0x00000001U #define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 1; +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ #define SPI_MMU_MEM_FORCE_PD (BIT(1)) #define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) #define SPI_MMU_MEM_FORCE_PD_V 0x00000001U #define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; * Set this bit to force mmu-memory powerup, in this case, the power should also be * controlled by rtc. */ @@ -3770,7 +3794,7 @@ extern "C" { #define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) #define SPI_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MMU_PAGE_SIZE : HRO; bitpos: [4:3]; default: 0; +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ #define SPI_MMU_PAGE_SIZE 0x00000003U @@ -3786,6 +3810,7 @@ extern "C" { #define SPI_MEM_AUX_CTRL_S 16 /** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RDN_ENA (BIT(30)) #define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) @@ -3793,6 +3818,7 @@ extern "C" { #define SPI_MEM_RDN_ENA_S 30 /** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RDN_RESULT (BIT(31)) #define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) @@ -3894,7 +3920,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; * SPI0 register version. */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h deleted file mode 100644 index e247e8d6ef..0000000000 --- a/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h +++ /dev/null @@ -1,3988 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI_MEM_CMD_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) -/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ -#define SPI_MEM_MST_ST 0x0000000FU -#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) -#define SPI_MEM_MST_ST_V 0x0000000FU -#define SPI_MEM_MST_ST_S 0 -/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ -#define SPI_MEM_SLV_ST 0x0000000FU -#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) -#define SPI_MEM_SLV_ST_V 0x0000000FU -#define SPI_MEM_SLV_ST_S 4 -/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) -#define SPI_MEM_USR_V 0x00000001U -#define SPI_MEM_USR_S 18 - -/** SPI_MEM_CTRL_REG register - * SPI0 control register. - */ -#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 -/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 -/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ -#define SPI_MEM_FDUMMY_RIN (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) -#define SPI_MEM_FDUMMY_RIN_V 0x00000001U -#define SPI_MEM_FDUMMY_RIN_S 2 -/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ -#define SPI_MEM_FDUMMY_WOUT (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) -#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) -#define SPI_MEM_FDOUT_OCT_V 0x00000001U -#define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) -#define SPI_MEM_FDIN_OCT_V 0x00000001U -#define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) -#define SPI_MEM_FADDR_OCT_V 0x00000001U -#define SPI_MEM_FADDR_OCT_S 6 -/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) -#define SPI_MEM_FCMD_QUAD_V 0x00000001U -#define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) -#define SPI_MEM_FCMD_OCT_V 0x00000001U -#define SPI_MEM_FCMD_OCT_S 9 -/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) -#define SPI_MEM_FASTRD_MODE_V 0x00000001U -#define SPI_MEM_FASTRD_MODE_S 13 -/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) -#define SPI_MEM_FREAD_DUAL_V 0x00000001U -#define SPI_MEM_FREAD_DUAL_S 14 -/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) -#define SPI_MEM_Q_POL_V 0x00000001U -#define SPI_MEM_Q_POL_S 18 -/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) -#define SPI_MEM_D_POL_V 0x00000001U -#define SPI_MEM_D_POL_S 19 -/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) -#define SPI_MEM_FREAD_QUAD_V 0x00000001U -#define SPI_MEM_FREAD_QUAD_S 20 -/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) -#define SPI_MEM_WP_REG_V 0x00000001U -#define SPI_MEM_WP_REG_S 21 -/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) -#define SPI_MEM_FREAD_DIO_V 0x00000001U -#define SPI_MEM_FREAD_DIO_S 23 -/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) -#define SPI_MEM_FREAD_QIO_V 0x00000001U -#define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ -#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) -#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ -#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) -#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 - -/** SPI_MEM_CTRL1_REG register - * SPI0 control1 register. - */ -#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) -/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ -#define SPI_MEM_CLK_MODE 0x00000003U -#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) -#define SPI_MEM_CLK_MODE_V 0x00000003U -#define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) -#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) -#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) -#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) -#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 -/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ -#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) -#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U -#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ -#define SPI_MEM_AR_SPLICE_EN (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) -#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ -#define SPI_MEM_AW_SPLICE_EN (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) -#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AW_SPLICE_EN_S 26 -/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ -#define SPI_MEM_RAM0_EN (BIT(27)) -#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) -#define SPI_MEM_RAM0_EN_V 0x00000001U -#define SPI_MEM_RAM0_EN_S 27 -/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ -#define SPI_MEM_DUAL_RAM_EN (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) -#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U -#define SPI_MEM_DUAL_RAM_EN_S 28 -/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ -#define SPI_MEM_FAST_WRITE_EN (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) -#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U -#define SPI_MEM_FAST_WRITE_EN_S 29 -/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) -#define SPI_MEM_RXFIFO_RST_V 0x00000001U -#define SPI_MEM_RXFIFO_RST_S 30 -/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ -#define SPI_MEM_TXFIFO_RST (BIT(31)) -#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) -#define SPI_MEM_TXFIFO_RST_V 0x00000001U -#define SPI_MEM_TXFIFO_RST_S 31 - -/** SPI_MEM_CTRL2_REG register - * SPI0 control2 register. - */ -#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) -/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ -#define SPI_MEM_CS_SETUP_TIME 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) -#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_S 0 -/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ -#define SPI_MEM_CS_HOLD_TIME 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) -#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 -/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ -#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) -#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_MEM_SPLIT_TRANS_EN_S 24 -/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ -#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) -#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_S 25 -/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) -#define SPI_MEM_SYNC_RESET_V 0x00000001U -#define SPI_MEM_SYNC_RESET_S 31 - -/** SPI_MEM_CLOCK_REG register - * SPI clock division control register. - */ -#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) -/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to SPI_MEM_CLKCNT_N. - */ -#define SPI_MEM_CLKCNT_L 0x000000FFU -#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) -#define SPI_MEM_CLKCNT_L_V 0x000000FFU -#define SPI_MEM_CLKCNT_L_S 0 -/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). - */ -#define SPI_MEM_CLKCNT_H 0x000000FFU -#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) -#define SPI_MEM_CLKCNT_H_V 0x000000FFU -#define SPI_MEM_CLKCNT_H_S 8 -/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(SPI_MEM_CLKCNT_N+1) - */ -#define SPI_MEM_CLKCNT_N 0x000000FFU -#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) -#define SPI_MEM_CLKCNT_N_V 0x000000FFU -#define SPI_MEM_CLKCNT_N_S 16 -/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 - -/** SPI_MEM_USER_REG register - * SPI0 user register. - */ -#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) -/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) -#define SPI_MEM_CS_HOLD_V 0x00000001U -#define SPI_MEM_CS_HOLD_S 6 -/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) -#define SPI_MEM_CS_SETUP_V 0x00000001U -#define SPI_MEM_CS_SETUP_S 7 -/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) -#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U -#define SPI_MEM_CK_OUT_EDGE_S 9 -/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U -#define SPI_MEM_USR_DUMMY_IDLE_S 26 -/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) -#define SPI_MEM_USR_DUMMY_V 0x00000001U -#define SPI_MEM_USR_DUMMY_S 29 - -/** SPI_MEM_USER1_REG register - * SPI0 user1 register. - */ -#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) -/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ -#define SPI_MEM_USR_DBYTELEN 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_S 6 -/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_S 26 - -/** SPI_MEM_USER2_REG register - * SPI0 user2 register. - */ -#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) -/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) -#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_S 0 -/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 - -/** SPI_MEM_RD_STATUS_REG register - * SPI0 read control register. - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_BASE + 0x2c) -/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE 0x000000FFU -#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) -#define SPI_MEM_WB_MODE_V 0x000000FFU -#define SPI_MEM_WB_MODE_S 16 -/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE_BITLEN 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) -#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_S 24 -/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE_EN (BIT(27)) -#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) -#define SPI_MEM_WB_MODE_EN_V 0x00000001U -#define SPI_MEM_WB_MODE_EN_S 27 - -/** SPI_MEM_MISC_REG register - * SPI0 misc register - */ -#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) -/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) -#define SPI_MEM_FSUB_PIN_V 0x00000001U -#define SPI_MEM_FSUB_PIN_S 7 -/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) -#define SPI_MEM_SSUB_PIN_V 0x00000001U -#define SPI_MEM_SSUB_PIN_S 8 -/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) -#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U -#define SPI_MEM_CK_IDLE_EDGE_S 9 -/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 - -/** SPI_MEM_CACHE_FCTRL_REG register - * SPI0 bit mode control register. - */ -#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) -/** SPI_MEM_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_AXI_REQ_EN (BIT(0)) -#define SPI_MEM_AXI_REQ_EN_M (SPI_MEM_AXI_REQ_EN_V << SPI_MEM_AXI_REQ_EN_S) -#define SPI_MEM_AXI_REQ_EN_V 0x00000001U -#define SPI_MEM_AXI_REQ_EN_S 0 -/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 -/** SPI_MEM_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (SPI_MEM_CACHE_FLASH_USR_CMD_V << SPI_MEM_CACHE_FLASH_USR_CMD_S) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x00000001U -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 -/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) -#define SPI_MEM_FDIN_DUAL_V 0x00000001U -#define SPI_MEM_FDIN_DUAL_S 3 -/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) -#define SPI_MEM_FDOUT_DUAL_V 0x00000001U -#define SPI_MEM_FDOUT_DUAL_S 4 -/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) -#define SPI_MEM_FADDR_DUAL_V 0x00000001U -#define SPI_MEM_FADDR_DUAL_S 5 -/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) -#define SPI_MEM_FDIN_QUAD_V 0x00000001U -#define SPI_MEM_FDIN_QUAD_S 6 -/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) -#define SPI_MEM_FDOUT_QUAD_V 0x00000001U -#define SPI_MEM_FDOUT_QUAD_S 7 -/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) -#define SPI_MEM_FADDR_QUAD_V 0x00000001U -#define SPI_MEM_FADDR_QUAD_S 8 -/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ -#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U -#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 -/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ -#define SPI_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) -#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U -#define SPI_CLOSE_AXI_INF_EN_S 31 - -/** SPI_MEM_CACHE_SCTRL_REG register - * SPI0 external RAM control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_CACHE_SCTRL_REG (DR_REG_SPI_BASE + 0x40) -/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) -#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_DIO_S 1 -/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) -#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_QIO_S 2 -/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; - * reserved - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) -#define SPI_MEM_SRAM_OCT_V 0x00000001U -#define SPI_MEM_SRAM_OCT_S 21 -/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 - -/** SPI_MEM_SRAM_CMD_REG register - * SPI0 external RAM mode control register - */ -#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) -/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLK_MODE 0x00000003U -#define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) -#define SPI_MEM_SCLK_MODE_V 0x00000003U -#define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SWB_MODE 0x000000FFU -#define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) -#define SPI_MEM_SWB_MODE_V 0x000000FFU -#define SPI_MEM_SWB_MODE_S 2 -/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) -#define SPI_MEM_SDIN_DUAL_V 0x00000001U -#define SPI_MEM_SDIN_DUAL_S 10 -/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) -#define SPI_MEM_SDOUT_DUAL_V 0x00000001U -#define SPI_MEM_SDOUT_DUAL_S 11 -/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) -#define SPI_MEM_SADDR_DUAL_V 0x00000001U -#define SPI_MEM_SADDR_DUAL_S 12 -/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) -#define SPI_MEM_SDIN_QUAD_V 0x00000001U -#define SPI_MEM_SDIN_QUAD_S 14 -/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) -#define SPI_MEM_SDOUT_QUAD_V 0x00000001U -#define SPI_MEM_SDOUT_QUAD_S 15 -/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) -#define SPI_MEM_SADDR_QUAD_V 0x00000001U -#define SPI_MEM_SADDR_QUAD_S 16 -/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) -#define SPI_MEM_SCMD_QUAD_V 0x00000001U -#define SPI_MEM_SCMD_QUAD_S 17 -/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) -#define SPI_MEM_SDIN_OCT_V 0x00000001U -#define SPI_MEM_SDIN_OCT_S 18 -/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) -#define SPI_MEM_SDOUT_OCT_V 0x00000001U -#define SPI_MEM_SDOUT_OCT_S 19 -/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) -#define SPI_MEM_SADDR_OCT_V 0x00000001U -#define SPI_MEM_SADDR_OCT_S 20 -/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (SPI_MEM_SCMD_OCT_V << SPI_MEM_SCMD_OCT_S) -#define SPI_MEM_SCMD_OCT_V 0x00000001U -#define SPI_MEM_SCMD_OCT_S 21 -/** SPI_MEM_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDUMMY_RIN (BIT(22)) -#define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) -#define SPI_MEM_SDUMMY_RIN_V 0x00000001U -#define SPI_MEM_SDUMMY_RIN_S 22 -/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDUMMY_WOUT (BIT(23)) -#define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) -#define SPI_MEM_SDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_SDUMMY_WOUT_S 23 -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_MEM_SDIN_HEX : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_HEX (BIT(26)) -#define SPI_MEM_SDIN_HEX_M (SPI_MEM_SDIN_HEX_V << SPI_MEM_SDIN_HEX_S) -#define SPI_MEM_SDIN_HEX_V 0x00000001U -#define SPI_MEM_SDIN_HEX_S 26 -/** SPI_MEM_SDOUT_HEX : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_HEX (BIT(27)) -#define SPI_MEM_SDOUT_HEX_M (SPI_MEM_SDOUT_HEX_V << SPI_MEM_SDOUT_HEX_S) -#define SPI_MEM_SDOUT_HEX_V 0x00000001U -#define SPI_MEM_SDOUT_HEX_S 27 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ -#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ -#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 - -/** SPI_MEM_SRAM_DRD_CMD_REG register - * SPI0 external RAM DDR read command control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_DRD_CMD_REG (DR_REG_SPI_BASE + 0x48) -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 - -/** SPI_MEM_SRAM_DWR_CMD_REG register - * SPI0 external RAM DDR write command control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_DWR_CMD_REG (DR_REG_SPI_BASE + 0x4c) -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 - -/** SPI_MEM_SRAM_CLK_REG register - * SPI0 external RAM clock control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_CLK_REG (DR_REG_SPI_BASE + 0x50) -/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_L 0x000000FFU -#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) -#define SPI_MEM_SCLKCNT_L_V 0x000000FFU -#define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_H 0x000000FFU -#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) -#define SPI_MEM_SCLKCNT_H_V 0x000000FFU -#define SPI_MEM_SCLKCNT_H_S 8 -/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(SPI_MEM_SCLKCNT_N+1) - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_N 0x000000FFU -#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) -#define SPI_MEM_SCLKCNT_N_V 0x000000FFU -#define SPI_MEM_SCLKCNT_N_S 16 -/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk - * is divided from system clock. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x00000001U -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 - -/** SPI_MEM_FSM_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ -#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU -#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU -#define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ -#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) -#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) -#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U -#define SPI_MEM_FLASH_LOCK_EN_S 19 -/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ -#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) -#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) -#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U -#define SPI_MEM_SRAM_LOCK_EN_S 20 - -/** SPI_MEM_INT_ENA_REG register - * SPI0 interrupt enable register - */ -#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) -/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) -#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 -/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) -#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ENA_S 5 -/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) -#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 - -/** SPI_MEM_INT_CLR_REG register - * SPI0 interrupt clear register - */ -#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) -/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) -#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 -/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) -#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_CLR_S 5 -/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) -#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 - -/** SPI_MEM_INT_RAW_REG register - * SPI0 interrupt raw register - */ -#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) -/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ -#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) -#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 -/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ -#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) -#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_RAW_S 5 -/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ -#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) -#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 - -/** SPI_MEM_INT_ST_REG register - * SPI0 interrupt status register - */ -#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) -/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) -#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ST_S 3 -/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) -#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ST_S 5 -/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) -#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ST_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 - -/** SPI_MEM_DDR_REG register - * SPI0 flash DDR mode control register - */ -#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) -/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) -#define SPI_FMEM_DDR_EN_V 0x00000001U -#define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) -#define SPI_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) -#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) -#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) -#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ -#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) -#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ -#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) -#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ -#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) -#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) -#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) -#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) -#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) -#define SPI_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ -#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) -#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ -#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) -#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) -#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_FMEM_HYPERBUS_CA_S 30 - -/** SPI_SMEM_DDR_REG register - * SPI0 external RAM DDR mode control register - */ -#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) -/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) -#define SPI_SMEM_DDR_EN_V 0x00000001U -#define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) -#define SPI_SMEM_VAR_DUMMY_V 0x00000001U -#define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) -#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) -#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) -#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ -#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) -#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) -#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) -#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) -#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) -#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) -#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) -#define SPI_SMEM_DQS_CA_IN_V 0x00000001U -#define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ -#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) -#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ -#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) -#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) -#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_SMEM_HYPERBUS_CA_S 30 - -/** SPI_FMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 attribute register - */ -#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) -/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) -#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_RD_ATTR_S 0 -/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) -#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_WR_ATTR_S 1 -/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and - * SPI_FMEM_PMS0_SIZE_REG. - */ -#define SPI_FMEM_PMS0_ECC (BIT(2)) -#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) -#define SPI_FMEM_PMS0_ECC_V 0x00000001U -#define SPI_FMEM_PMS0_ECC_S 2 - -/** SPI_FMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 attribute register - */ -#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) -/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) -#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_RD_ATTR_S 0 -/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) -#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_WR_ATTR_S 1 -/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and - * SPI_FMEM_PMS1_SIZE_REG. - */ -#define SPI_FMEM_PMS1_ECC (BIT(2)) -#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) -#define SPI_FMEM_PMS1_ECC_V 0x00000001U -#define SPI_FMEM_PMS1_ECC_S 2 - -/** SPI_FMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 attribute register - */ -#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) -/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) -#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_RD_ATTR_S 0 -/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) -#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_WR_ATTR_S 1 -/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and - * SPI_FMEM_PMS2_SIZE_REG. - */ -#define SPI_FMEM_PMS2_ECC (BIT(2)) -#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) -#define SPI_FMEM_PMS2_ECC_V 0x00000001U -#define SPI_FMEM_PMS2_ECC_S 2 - -/** SPI_FMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 attribute register - */ -#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) -/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) -#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_RD_ATTR_S 0 -/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) -#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_WR_ATTR_S 1 -/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and - * SPI_FMEM_PMS3_SIZE_REG. - */ -#define SPI_FMEM_PMS3_ECC (BIT(2)) -#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) -#define SPI_FMEM_PMS3_ECC_V 0x00000001U -#define SPI_FMEM_PMS3_ECC_S 2 - -/** SPI_FMEM_PMS0_ADDR_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 0 start address value - */ -#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_S 0 - -/** SPI_FMEM_PMS1_ADDR_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 1 start address value - */ -#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_S 0 - -/** SPI_FMEM_PMS2_ADDR_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 2 start address value - */ -#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_S 0 - -/** SPI_FMEM_PMS3_ADDR_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 3 start address value - */ -#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_S 0 - -/** SPI_FMEM_PMS0_SIZE_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, - * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) - */ -#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_S 0 - -/** SPI_FMEM_PMS1_SIZE_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, - * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) - */ -#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_S 0 - -/** SPI_FMEM_PMS2_SIZE_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, - * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) - */ -#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_S 0 - -/** SPI_FMEM_PMS3_SIZE_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, - * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) - */ -#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_S 0 - -/** SPI_SMEM_PMS0_ATTR_REG register - * SPI1 external RAM PMS section 0 attribute register - */ -#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) -/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) -#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_RD_ATTR_S 0 -/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) -#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_WR_ATTR_S 1 -/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and - * SPI_SMEM_PMS0_SIZE_REG. - */ -#define SPI_SMEM_PMS0_ECC (BIT(2)) -#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) -#define SPI_SMEM_PMS0_ECC_V 0x00000001U -#define SPI_SMEM_PMS0_ECC_S 2 - -/** SPI_SMEM_PMS1_ATTR_REG register - * SPI1 external RAM PMS section 1 attribute register - */ -#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) -/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) -#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_RD_ATTR_S 0 -/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) -#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_WR_ATTR_S 1 -/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and - * SPI_SMEM_PMS1_SIZE_REG. - */ -#define SPI_SMEM_PMS1_ECC (BIT(2)) -#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) -#define SPI_SMEM_PMS1_ECC_V 0x00000001U -#define SPI_SMEM_PMS1_ECC_S 2 - -/** SPI_SMEM_PMS2_ATTR_REG register - * SPI1 external RAM PMS section 2 attribute register - */ -#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) -/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) -#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_RD_ATTR_S 0 -/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) -#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_WR_ATTR_S 1 -/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and - * SPI_SMEM_PMS2_SIZE_REG. - */ -#define SPI_SMEM_PMS2_ECC (BIT(2)) -#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) -#define SPI_SMEM_PMS2_ECC_V 0x00000001U -#define SPI_SMEM_PMS2_ECC_S 2 - -/** SPI_SMEM_PMS3_ATTR_REG register - * SPI1 external RAM PMS section 3 attribute register - */ -#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) -/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) -#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_RD_ATTR_S 0 -/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) -#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_WR_ATTR_S 1 -/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and - * SPI_SMEM_PMS3_SIZE_REG. - */ -#define SPI_SMEM_PMS3_ECC (BIT(2)) -#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) -#define SPI_SMEM_PMS3_ECC_V 0x00000001U -#define SPI_SMEM_PMS3_ECC_S 2 - -/** SPI_SMEM_PMS0_ADDR_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 0 start address value - */ -#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_S 0 - -/** SPI_SMEM_PMS1_ADDR_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 1 start address value - */ -#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_S 0 - -/** SPI_SMEM_PMS2_ADDR_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 2 start address value - */ -#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_S 0 - -/** SPI_SMEM_PMS3_ADDR_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 3 start address value - */ -#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_S 0 - -/** SPI_SMEM_PMS0_SIZE_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, - * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) - */ -#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_S 0 - -/** SPI_SMEM_PMS1_SIZE_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, - * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) - */ -#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_S 0 - -/** SPI_SMEM_PMS2_SIZE_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, - * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) - */ -#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_S 0 - -/** SPI_SMEM_PMS3_SIZE_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, - * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) - */ -#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_S 0 - -/** SPI_MEM_PMS_REJECT_REG register - * SPI1 access reject register - */ -#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x160) -/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ -#define SPI_MEM_PM_EN (BIT(27)) -#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) -#define SPI_MEM_PM_EN_V 0x00000001U -#define SPI_MEM_PM_EN_S 27 -/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_LD (BIT(28)) -#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) -#define SPI_MEM_PMS_LD_V 0x00000001U -#define SPI_MEM_PMS_LD_S 28 -/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_ST (BIT(29)) -#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) -#define SPI_MEM_PMS_ST_V 0x00000001U -#define SPI_MEM_PMS_ST_S 29 -/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) -#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U -#define SPI_MEM_PMS_MULTI_HIT_S 30 -/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_IVD (BIT(31)) -#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) -#define SPI_MEM_PMS_IVD_V 0x00000001U -#define SPI_MEM_PMS_IVD_S 31 - -/** SPI_MEM_PMS_REJECT_ADDR_REG register - * SPI1 access reject addr register - */ -#define SPI_MEM_PMS_REJECT_ADDR_REG (DR_REG_SPI_BASE + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_REJECT_ADDR_S 0 - -/** SPI_MEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) -/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_CNT 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) -#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) -#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ -#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) -#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_FMEM_ECC_ERR_INT_EN_S 17 -/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ -#define SPI_FMEM_PAGE_SIZE 0x00000003U -#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) -#define SPI_FMEM_PAGE_SIZE_V 0x00000003U -#define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) -#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) -#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 21 -/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) -#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) -#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 22 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ -#define SPI_MEM_ECC_ERR_BITS 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) -#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_S 25 - -/** SPI_MEM_ECC_ERR_ADDR_REG register - * MSPI ECC error address register - */ -#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_S 0 - -/** SPI_MEM_AXI_ERR_ADDR_REG register - * SPI0 AXI request error address. - */ -#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ -#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_S 0 - -/** SPI_SMEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ -#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) -#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ -#define SPI_SMEM_PAGE_SIZE 0x00000003U -#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) -#define SPI_SMEM_PAGE_SIZE_V 0x00000003U -#define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ -#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) -#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_SMEM_ECC_ADDR_EN_S 20 - -/** SPI_SMEM_AXI_ADDR_CTRL_REG register - * SPI0 AXI address control register - */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) -/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ -#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) -#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U -#define SPI_MEM_ALL_FIFO_EMPTY_S 26 -/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) -#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) -#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_RDATA_AFIFO_REMPTY_S 27 -/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) -#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) -#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U -#define SPI_RADDR_AFIFO_REMPTY_S 28 -/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) -#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) -#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_WDATA_AFIFO_REMPTY_S 29 -/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) -#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) -#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U -#define SPI_WBLEN_AFIFO_REMPTY_S 30 -/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 - -/** SPI_MEM_AXI_ERR_RESP_EN_REG register - * SPI0 AXI error response enable register - */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) -#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) -#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 -/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 -/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) -#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) -#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 -/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 -/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 -/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 - -/** SPI_MEM_TIMING_CALI_REG register - * SPI0 flash timing calibration register - */ -#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) -/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) -#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_MEM_TIMING_CLK_ENA_S 0 -/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) -#define SPI_MEM_TIMING_CALI_V 0x00000001U -#define SPI_MEM_TIMING_CALI_S 1 -/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ -#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) -#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_MEM_DLL_TIMING_CALI_S 5 -/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ -#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) -#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U -#define SPI_MEM_TIMING_CALI_UPDATE_S 6 - -/** SPI_MEM_DIN_MODE_REG register - * MSPI flash input timing delay mode control register - */ -#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) -/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN0_MODE 0x00000007U -#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) -#define SPI_MEM_DIN0_MODE_V 0x00000007U -#define SPI_MEM_DIN0_MODE_S 0 -/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN1_MODE 0x00000007U -#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) -#define SPI_MEM_DIN1_MODE_V 0x00000007U -#define SPI_MEM_DIN1_MODE_S 3 -/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN2_MODE 0x00000007U -#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) -#define SPI_MEM_DIN2_MODE_V 0x00000007U -#define SPI_MEM_DIN2_MODE_S 6 -/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN3_MODE 0x00000007U -#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) -#define SPI_MEM_DIN3_MODE_V 0x00000007U -#define SPI_MEM_DIN3_MODE_S 9 -/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN4_MODE 0x00000007U -#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) -#define SPI_MEM_DIN4_MODE_V 0x00000007U -#define SPI_MEM_DIN4_MODE_S 12 -/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN5_MODE 0x00000007U -#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) -#define SPI_MEM_DIN5_MODE_V 0x00000007U -#define SPI_MEM_DIN5_MODE_S 15 -/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN6_MODE 0x00000007U -#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) -#define SPI_MEM_DIN6_MODE_V 0x00000007U -#define SPI_MEM_DIN6_MODE_S 18 -/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN7_MODE 0x00000007U -#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) -#define SPI_MEM_DIN7_MODE_V 0x00000007U -#define SPI_MEM_DIN7_MODE_S 21 -/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DINS_MODE 0x00000007U -#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) -#define SPI_MEM_DINS_MODE_V 0x00000007U -#define SPI_MEM_DINS_MODE_S 24 - -/** SPI_MEM_DIN_NUM_REG register - * MSPI flash input timing delay number control register - */ -#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) -/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN0_NUM 0x00000003U -#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) -#define SPI_MEM_DIN0_NUM_V 0x00000003U -#define SPI_MEM_DIN0_NUM_S 0 -/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN1_NUM 0x00000003U -#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) -#define SPI_MEM_DIN1_NUM_V 0x00000003U -#define SPI_MEM_DIN1_NUM_S 2 -/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN2_NUM 0x00000003U -#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) -#define SPI_MEM_DIN2_NUM_V 0x00000003U -#define SPI_MEM_DIN2_NUM_S 4 -/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN3_NUM 0x00000003U -#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) -#define SPI_MEM_DIN3_NUM_V 0x00000003U -#define SPI_MEM_DIN3_NUM_S 6 -/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN4_NUM 0x00000003U -#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) -#define SPI_MEM_DIN4_NUM_V 0x00000003U -#define SPI_MEM_DIN4_NUM_S 8 -/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN5_NUM 0x00000003U -#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) -#define SPI_MEM_DIN5_NUM_V 0x00000003U -#define SPI_MEM_DIN5_NUM_S 10 -/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN6_NUM 0x00000003U -#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) -#define SPI_MEM_DIN6_NUM_V 0x00000003U -#define SPI_MEM_DIN6_NUM_S 12 -/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN7_NUM 0x00000003U -#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) -#define SPI_MEM_DIN7_NUM_V 0x00000003U -#define SPI_MEM_DIN7_NUM_S 14 -/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DINS_NUM 0x00000003U -#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) -#define SPI_MEM_DINS_NUM_V 0x00000003U -#define SPI_MEM_DINS_NUM_S 16 - -/** SPI_MEM_DOUT_MODE_REG register - * MSPI flash output timing adjustment control register - */ -#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) -/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) -#define SPI_MEM_DOUT0_MODE_V 0x00000001U -#define SPI_MEM_DOUT0_MODE_S 0 -/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) -#define SPI_MEM_DOUT1_MODE_V 0x00000001U -#define SPI_MEM_DOUT1_MODE_S 1 -/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) -#define SPI_MEM_DOUT2_MODE_V 0x00000001U -#define SPI_MEM_DOUT2_MODE_S 2 -/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) -#define SPI_MEM_DOUT3_MODE_V 0x00000001U -#define SPI_MEM_DOUT3_MODE_S 3 -/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) -#define SPI_MEM_DOUT4_MODE_V 0x00000001U -#define SPI_MEM_DOUT4_MODE_S 4 -/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) -#define SPI_MEM_DOUT5_MODE_V 0x00000001U -#define SPI_MEM_DOUT5_MODE_S 5 -/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) -#define SPI_MEM_DOUT6_MODE_V 0x00000001U -#define SPI_MEM_DOUT6_MODE_S 6 -/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) -#define SPI_MEM_DOUT7_MODE_V 0x00000001U -#define SPI_MEM_DOUT7_MODE_S 7 -/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) -#define SPI_MEM_DOUTS_MODE_V 0x00000001U -#define SPI_MEM_DOUTS_MODE_S 8 - -/** SPI_SMEM_TIMING_CALI_REG register - * MSPI external RAM timing calibration register - */ -#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) -#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ -#define SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) -#define SPI_SMEM_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ -#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) -#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_270_SEL 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) -#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_S 7 -/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_90_SEL 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) -#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_S 9 -/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS1_270_SEL 0x00000003U -#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S) -#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U -#define SPI_SMEM_DQS1_270_SEL_S 11 -/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS1_90_SEL 0x00000003U -#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S) -#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U -#define SPI_SMEM_DQS1_90_SEL_S 13 - -/** SPI_SMEM_DIN_MODE_REG register - * MSPI external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) -/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN0_MODE 0x00000007U -#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) -#define SPI_SMEM_DIN0_MODE_V 0x00000007U -#define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN1_MODE 0x00000007U -#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) -#define SPI_SMEM_DIN1_MODE_V 0x00000007U -#define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN2_MODE 0x00000007U -#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) -#define SPI_SMEM_DIN2_MODE_V 0x00000007U -#define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN3_MODE 0x00000007U -#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) -#define SPI_SMEM_DIN3_MODE_V 0x00000007U -#define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN4_MODE 0x00000007U -#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) -#define SPI_SMEM_DIN4_MODE_V 0x00000007U -#define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN5_MODE 0x00000007U -#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) -#define SPI_SMEM_DIN5_MODE_V 0x00000007U -#define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN6_MODE 0x00000007U -#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) -#define SPI_SMEM_DIN6_MODE_V 0x00000007U -#define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN7_MODE 0x00000007U -#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) -#define SPI_SMEM_DIN7_MODE_V 0x00000007U -#define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_MODE 0x00000007U -#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) -#define SPI_SMEM_DINS_MODE_V 0x00000007U -#define SPI_SMEM_DINS_MODE_S 24 - -/** SPI_SMEM_DIN_NUM_REG register - * MSPI external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) -/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN0_NUM 0x00000003U -#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) -#define SPI_SMEM_DIN0_NUM_V 0x00000003U -#define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN1_NUM 0x00000003U -#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) -#define SPI_SMEM_DIN1_NUM_V 0x00000003U -#define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN2_NUM 0x00000003U -#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) -#define SPI_SMEM_DIN2_NUM_V 0x00000003U -#define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN3_NUM 0x00000003U -#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) -#define SPI_SMEM_DIN3_NUM_V 0x00000003U -#define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN4_NUM 0x00000003U -#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) -#define SPI_SMEM_DIN4_NUM_V 0x00000003U -#define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN5_NUM 0x00000003U -#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) -#define SPI_SMEM_DIN5_NUM_V 0x00000003U -#define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN6_NUM 0x00000003U -#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) -#define SPI_SMEM_DIN6_NUM_V 0x00000003U -#define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN7_NUM 0x00000003U -#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) -#define SPI_SMEM_DIN7_NUM_V 0x00000003U -#define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_NUM 0x00000003U -#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) -#define SPI_SMEM_DINS_NUM_V 0x00000003U -#define SPI_SMEM_DINS_NUM_S 16 - -/** SPI_SMEM_DOUT_MODE_REG register - * MSPI external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) -/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) -#define SPI_SMEM_DOUT0_MODE_V 0x00000001U -#define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) -#define SPI_SMEM_DOUT1_MODE_V 0x00000001U -#define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) -#define SPI_SMEM_DOUT2_MODE_V 0x00000001U -#define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) -#define SPI_SMEM_DOUT3_MODE_V 0x00000001U -#define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) -#define SPI_SMEM_DOUT4_MODE_V 0x00000001U -#define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) -#define SPI_SMEM_DOUT5_MODE_V 0x00000001U -#define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) -#define SPI_SMEM_DOUT6_MODE_V 0x00000001U -#define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) -#define SPI_SMEM_DOUT7_MODE_V 0x00000001U -#define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) -#define SPI_SMEM_DOUTS_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_MODE_S 8 - -/** SPI_SMEM_AC_REG register - * MSPI external RAM ECC and SPI CS timing control register - */ -#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) -/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ -#define SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) -#define SPI_SMEM_CS_SETUP_V 0x00000001U -#define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) -#define SPI_SMEM_CS_HOLD_V 0x00000001U -#define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ -#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) -#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ -#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) -#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ -#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) -#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ -#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) -#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ -#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) -#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) -#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_SMEM_SPLIT_TRANS_EN_S 31 - -/** SPI_SMEM_DIN_HEX_MODE_REG register - * MSPI 16x external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1a4) -/** SPI_SMEM_DIN08_MODE : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN08_MODE 0x00000007U -#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) -#define SPI_SMEM_DIN08_MODE_V 0x00000007U -#define SPI_SMEM_DIN08_MODE_S 0 -/** SPI_SMEM_DIN09_MODE : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN09_MODE 0x00000007U -#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) -#define SPI_SMEM_DIN09_MODE_V 0x00000007U -#define SPI_SMEM_DIN09_MODE_S 3 -/** SPI_SMEM_DIN10_MODE : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN10_MODE 0x00000007U -#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) -#define SPI_SMEM_DIN10_MODE_V 0x00000007U -#define SPI_SMEM_DIN10_MODE_S 6 -/** SPI_SMEM_DIN11_MODE : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN11_MODE 0x00000007U -#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) -#define SPI_SMEM_DIN11_MODE_V 0x00000007U -#define SPI_SMEM_DIN11_MODE_S 9 -/** SPI_SMEM_DIN12_MODE : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN12_MODE 0x00000007U -#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) -#define SPI_SMEM_DIN12_MODE_V 0x00000007U -#define SPI_SMEM_DIN12_MODE_S 12 -/** SPI_SMEM_DIN13_MODE : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN13_MODE 0x00000007U -#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) -#define SPI_SMEM_DIN13_MODE_V 0x00000007U -#define SPI_SMEM_DIN13_MODE_S 15 -/** SPI_SMEM_DIN14_MODE : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN14_MODE 0x00000007U -#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) -#define SPI_SMEM_DIN14_MODE_V 0x00000007U -#define SPI_SMEM_DIN14_MODE_S 18 -/** SPI_SMEM_DIN15_MODE : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN15_MODE 0x00000007U -#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) -#define SPI_SMEM_DIN15_MODE_V 0x00000007U -#define SPI_SMEM_DIN15_MODE_S 21 -/** SPI_SMEM_DINS_HEX_MODE : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_HEX_MODE 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) -#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_S 24 - -/** SPI_SMEM_DIN_HEX_NUM_REG register - * MSPI 16x external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_SPI_BASE + 0x1a8) -/** SPI_SMEM_DIN08_NUM : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN08_NUM 0x00000003U -#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) -#define SPI_SMEM_DIN08_NUM_V 0x00000003U -#define SPI_SMEM_DIN08_NUM_S 0 -/** SPI_SMEM_DIN09_NUM : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN09_NUM 0x00000003U -#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) -#define SPI_SMEM_DIN09_NUM_V 0x00000003U -#define SPI_SMEM_DIN09_NUM_S 2 -/** SPI_SMEM_DIN10_NUM : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN10_NUM 0x00000003U -#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) -#define SPI_SMEM_DIN10_NUM_V 0x00000003U -#define SPI_SMEM_DIN10_NUM_S 4 -/** SPI_SMEM_DIN11_NUM : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN11_NUM 0x00000003U -#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) -#define SPI_SMEM_DIN11_NUM_V 0x00000003U -#define SPI_SMEM_DIN11_NUM_S 6 -/** SPI_SMEM_DIN12_NUM : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN12_NUM 0x00000003U -#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) -#define SPI_SMEM_DIN12_NUM_V 0x00000003U -#define SPI_SMEM_DIN12_NUM_S 8 -/** SPI_SMEM_DIN13_NUM : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN13_NUM 0x00000003U -#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) -#define SPI_SMEM_DIN13_NUM_V 0x00000003U -#define SPI_SMEM_DIN13_NUM_S 10 -/** SPI_SMEM_DIN14_NUM : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN14_NUM 0x00000003U -#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) -#define SPI_SMEM_DIN14_NUM_V 0x00000003U -#define SPI_SMEM_DIN14_NUM_S 12 -/** SPI_SMEM_DIN15_NUM : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN15_NUM 0x00000003U -#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) -#define SPI_SMEM_DIN15_NUM_V 0x00000003U -#define SPI_SMEM_DIN15_NUM_S 14 -/** SPI_SMEM_DINS_HEX_NUM : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_HEX_NUM 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) -#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_S 16 - -/** SPI_SMEM_DOUT_HEX_MODE_REG register - * MSPI 16x external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1ac) -/** SPI_SMEM_DOUT08_MODE : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT08_MODE (BIT(0)) -#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) -#define SPI_SMEM_DOUT08_MODE_V 0x00000001U -#define SPI_SMEM_DOUT08_MODE_S 0 -/** SPI_SMEM_DOUT09_MODE : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT09_MODE (BIT(1)) -#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) -#define SPI_SMEM_DOUT09_MODE_V 0x00000001U -#define SPI_SMEM_DOUT09_MODE_S 1 -/** SPI_SMEM_DOUT10_MODE : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT10_MODE (BIT(2)) -#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) -#define SPI_SMEM_DOUT10_MODE_V 0x00000001U -#define SPI_SMEM_DOUT10_MODE_S 2 -/** SPI_SMEM_DOUT11_MODE : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT11_MODE (BIT(3)) -#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) -#define SPI_SMEM_DOUT11_MODE_V 0x00000001U -#define SPI_SMEM_DOUT11_MODE_S 3 -/** SPI_SMEM_DOUT12_MODE : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT12_MODE (BIT(4)) -#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) -#define SPI_SMEM_DOUT12_MODE_V 0x00000001U -#define SPI_SMEM_DOUT12_MODE_S 4 -/** SPI_SMEM_DOUT13_MODE : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT13_MODE (BIT(5)) -#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) -#define SPI_SMEM_DOUT13_MODE_V 0x00000001U -#define SPI_SMEM_DOUT13_MODE_S 5 -/** SPI_SMEM_DOUT14_MODE : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT14_MODE (BIT(6)) -#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) -#define SPI_SMEM_DOUT14_MODE_V 0x00000001U -#define SPI_SMEM_DOUT14_MODE_S 6 -/** SPI_SMEM_DOUT15_MODE : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT15_MODE (BIT(7)) -#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) -#define SPI_SMEM_DOUT15_MODE_V 0x00000001U -#define SPI_SMEM_DOUT15_MODE_S 7 -/** SPI_SMEM_DOUTS_HEX_MODE : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) -#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_HEX_MODE_S 8 - -/** SPI_MEM_CLOCK_GATE_REG register - * SPI0 clock gate register - */ -#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) -/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ -#define SPI_CLK_EN (BIT(0)) -#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_CLK_EN_V 0x00000001U -#define SPI_CLK_EN_S 0 -/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1; - * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. - */ -#define SPI_MSPI_CLK_FORCE_ON (BIT(1)) -#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S) -#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U -#define SPI_MSPI_CLK_FORCE_ON_S 1 - -/** SPI_MEM_NAND_FLASH_EN_REG register - * NAND FLASH control register - */ -#define SPI_MEM_NAND_FLASH_EN_REG (DR_REG_SPI_BASE + 0x204) -/** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ -#define SPI_MEM_NAND_FLASH_EN (BIT(0)) -#define SPI_MEM_NAND_FLASH_EN_M (SPI_MEM_NAND_FLASH_EN_V << SPI_MEM_NAND_FLASH_EN_S) -#define SPI_MEM_NAND_FLASH_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_EN_S 0 -/** SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M (SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V << SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S) -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 -/** SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V << SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 -/** SPI_MEM_NAND_FLASH_LUT_EN : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) -#define SPI_MEM_NAND_FLASH_LUT_EN_M (SPI_MEM_NAND_FLASH_LUT_EN_V << SPI_MEM_NAND_FLASH_LUT_EN_S) -#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 -/** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to - * execute page execute. 1: write end 0: write in a page size. - */ -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND (BIT(18)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S 18 - -/** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG (DR_REG_SPI_BASE + 0x208) -/** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_M (SPI_MEM_NAND_FLASH_SR_ADDR0_V << SPI_MEM_NAND_FLASH_SR_ADDR0_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 -/** SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_M (SPI_MEM_NAND_FLASH_SR_ADDR1_V << SPI_MEM_NAND_FLASH_SR_ADDR1_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 -/** SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_M (SPI_MEM_NAND_FLASH_SR_ADDR2_V << SPI_MEM_NAND_FLASH_SR_ADDR2_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 -/** SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR3_M (SPI_MEM_NAND_FLASH_SR_ADDR3_V << SPI_MEM_NAND_FLASH_SR_ADDR3_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR3_S 24 - -/** SPI_MEM_NAND_FLASH_SR_DIN0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0_REG (DR_REG_SPI_BASE + 0x20c) -/** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_M (SPI_MEM_NAND_FLASH_SR_DIN0_V << SPI_MEM_NAND_FLASH_SR_DIN0_S) -#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 -/** SPI_MEM_NAND_FLASH_SR_DIN1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_M (SPI_MEM_NAND_FLASH_SR_DIN1_V << SPI_MEM_NAND_FLASH_SR_DIN1_S) -#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 -/** SPI_MEM_NAND_FLASH_SR_DIN2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_M (SPI_MEM_NAND_FLASH_SR_DIN2_V << SPI_MEM_NAND_FLASH_SR_DIN2_S) -#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 -/** SPI_MEM_NAND_FLASH_SR_DIN3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN3_M (SPI_MEM_NAND_FLASH_SR_DIN3_V << SPI_MEM_NAND_FLASH_SR_DIN3_S) -#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN3_S 24 - -/** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG (DR_REG_SPI_BASE + 0x210) -/** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_M (SPI_MEM_NAND_FLASH_CFG_DATA0_V << SPI_MEM_NAND_FLASH_CFG_DATA0_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA1_M (SPI_MEM_NAND_FLASH_CFG_DATA1_V << SPI_MEM_NAND_FLASH_CFG_DATA1_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA1_S 16 - -/** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG (DR_REG_SPI_BASE + 0x214) -/** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_M (SPI_MEM_NAND_FLASH_CFG_DATA2_V << SPI_MEM_NAND_FLASH_CFG_DATA2_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA3_M (SPI_MEM_NAND_FLASH_CFG_DATA3_V << SPI_MEM_NAND_FLASH_CFG_DATA3_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA3_S 16 - -/** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG (DR_REG_SPI_BASE + 0x218) -/** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_M (SPI_MEM_NAND_FLASH_CFG_DATA4_V << SPI_MEM_NAND_FLASH_CFG_DATA4_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA5_M (SPI_MEM_NAND_FLASH_CFG_DATA5_V << SPI_MEM_NAND_FLASH_CFG_DATA5_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA5_S 16 - -/** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register - * MSPI NAND FLASH CMD LUT control register - */ -#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG (DR_REG_SPI_BASE + 0x240) -/** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M (SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V << SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 -/** SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M (SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V << SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 -/** SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M (SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V << SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 -/** SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M (SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V << SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 -/** SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M (SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V << SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 -/** SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0 (BIT(30)) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V << SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S 30 - -/** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG (DR_REG_SPI_BASE + 0x280) -/** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V << SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 -/** SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (SPI_MEM_NAND_FLASH_SR_CHK_EN0_V << SPI_MEM_NAND_FLASH_SR_CHK_EN0_S) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 -/** SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ -#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M (SPI_MEM_NAND_FLASH_DIN_INDEX0_V << SPI_MEM_NAND_FLASH_DIN_INDEX0_S) -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 -/** SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M (SPI_MEM_NAND_FLASH_ADDR_INDEX0_V << SPI_MEM_NAND_FLASH_ADDR_INDEX0_S) -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 -/** SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V << SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 -/** SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ -#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M (SPI_MEM_NAND_FLASH_CMD_INDEX0_V << SPI_MEM_NAND_FLASH_CMD_INDEX0_S) -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_S 11 - -/** SPI_MEM_XTS_PLAIN_BASE_REG register - * The base address of the memory that stores plaintext in Manual Encryption - */ -#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) -/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ -#define SPI_XTS_PLAIN 0xFFFFFFFFU -#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) -#define SPI_XTS_PLAIN_V 0xFFFFFFFFU -#define SPI_XTS_PLAIN_S 0 - -/** SPI_MEM_XTS_LINESIZE_REG register - * Manual Encryption Line-Size register - */ -#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) -/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ -#define SPI_XTS_LINESIZE 0x00000003U -#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) -#define SPI_XTS_LINESIZE_V 0x00000003U -#define SPI_XTS_LINESIZE_S 0 - -/** SPI_MEM_XTS_DESTINATION_REG register - * Manual Encryption destination register - */ -#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) -/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ -#define SPI_XTS_DESTINATION (BIT(0)) -#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) -#define SPI_XTS_DESTINATION_V 0x00000001U -#define SPI_XTS_DESTINATION_S 0 - -/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) -/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ -#define SPI_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_S 0 - -/** SPI_MEM_XTS_TRIGGER_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ -#define SPI_XTS_TRIGGER (BIT(0)) -#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) -#define SPI_XTS_TRIGGER_V 0x00000001U -#define SPI_XTS_TRIGGER_S 0 - -/** SPI_MEM_XTS_RELEASE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) -/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ -#define SPI_XTS_RELEASE (BIT(0)) -#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) -#define SPI_XTS_RELEASE_V 0x00000001U -#define SPI_XTS_RELEASE_S 0 - -/** SPI_MEM_XTS_DESTROY_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) -/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ -#define SPI_XTS_DESTROY (BIT(0)) -#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) -#define SPI_XTS_DESTROY_V 0x00000001U -#define SPI_XTS_DESTROY_S 0 - -/** SPI_MEM_XTS_STATE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) -/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ -#define SPI_XTS_STATE 0x00000003U -#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) -#define SPI_XTS_STATE_V 0x00000003U -#define SPI_XTS_STATE_S 0 - -/** SPI_MEM_XTS_DATE_REG register - * Manual Encryption version register - */ -#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) -/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ -#define SPI_XTS_DATE 0x3FFFFFFFU -#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) -#define SPI_XTS_DATE_V 0x3FFFFFFFU -#define SPI_XTS_DATE_S 0 - -/** SPI_MEM_MMU_ITEM_CONTENT_REG register - * MSPI-MMU item content register - */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) -/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ -#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) -#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_S 0 - -/** SPI_MEM_MMU_ITEM_INDEX_REG register - * MSPI-MMU item index register - */ -#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) -/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ -#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) -#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_S 0 - -/** SPI_MEM_MMU_POWER_CTRL_REG register - * MSPI MMU power control register - */ -#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) -/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ -#define SPI_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) -#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U -#define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * Set this bit to force mmu-memory powerdown - */ -#define SPI_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) -#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ -#define SPI_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) -#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ -#define SPI_MMU_PAGE_SIZE 0x00000003U -#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) -#define SPI_MMU_PAGE_SIZE_V 0x00000003U -#define SPI_MMU_PAGE_SIZE_S 3 -/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ -#define SPI_MEM_AUX_CTRL 0x00003FFFU -#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) -#define SPI_MEM_AUX_CTRL_V 0x00003FFFU -#define SPI_MEM_AUX_CTRL_S 16 -/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_RDN_ENA (BIT(30)) -#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) -#define SPI_MEM_RDN_ENA_V 0x00000001U -#define SPI_MEM_RDN_ENA_S 30 -/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_RDN_RESULT (BIT(31)) -#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) -#define SPI_MEM_RDN_RESULT_V 0x00000001U -#define SPI_MEM_RDN_RESULT_S 31 - -/** SPI_MEM_DPA_CTRL_REG register - * SPI memory cryption DPA register - */ -#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) -/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ -#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) -#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_S 0 -/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ -#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) -#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U -#define SPI_CRYPT_CALC_D_DPA_EN_S 3 -/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ -#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) -#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U -#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 - -/** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register - * SPI memory cryption PSEUDO register - */ -#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_SPI_BASE + 0x38c) -/** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ -#define SPI_MEM_MODE_PSEUDO 0x00000003U -#define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) -#define SPI_MEM_MODE_PSEUDO_V 0x00000003U -#define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be performed. - */ -#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) -#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_S 2 -/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be performed. - */ -#define SPI_MEM_PSEUDO_BASE 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) -#define SPI_MEM_PSEUDO_BASE_V 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_S 5 -/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be performed randomly between 0 & - * 2**(inc+1). - */ -#define SPI_MEM_PSEUDO_INC 0x00000003U -#define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) -#define SPI_MEM_PSEUDO_INC_V 0x00000003U -#define SPI_MEM_PSEUDO_INC_S 9 - -/** SPI_MEM_REGISTERRND_ECO_HIGH_REG register - * MSPI ECO high register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_SPI_BASE + 0x3f0) -/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; - * ECO high register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_HIGH_M (SPI_MEM_REGISTERRND_ECO_HIGH_V << SPI_MEM_REGISTERRND_ECO_HIGH_S) -#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 - -/** SPI_MEM_REGISTERRND_ECO_LOW_REG register - * MSPI ECO low register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_SPI_BASE + 0x3f4) -/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; - * ECO low register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_LOW_M (SPI_MEM_REGISTERRND_ECO_LOW_V << SPI_MEM_REGISTERRND_ECO_LOW_S) -#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 - -/** SPI_MEM_DATE_REG register - * SPI0 version control register - */ -#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; - * SPI0 register version. - */ -#define SPI_MEM_DATE 0x0FFFFFFFU -#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) -#define SPI_MEM_DATE_V 0x0FFFFFFFU -#define SPI_MEM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_struct.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h index 9d10a730c5..09eac698aa 100644 --- a/components/soc/esp32c5/register/soc/spi_mem_c_struct.h +++ b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,7 @@ typedef union { uint32_t mem_slv_st:4; uint32_t reserved_8:10; /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_AXI_REQ_EN is cleared. An operation + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ @@ -47,8 +47,8 @@ typedef union { struct { /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ uint32_t mem_axi_err_addr:29; uint32_t reserved_29:3; @@ -108,8 +108,8 @@ typedef union { uint32_t mem_fcmd_oct:1; uint32_t reserved_10:3; /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_FREAD_QIO, spi_mem_c_FREAD_DIO, spi_mem_c_FREAD_QOUT - * and spi_mem_c_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ uint32_t mem_fastrd_mode:1; /** mem_fread_dual : R/W; bitpos: [14]; default: 0; @@ -170,25 +170,20 @@ typedef union { * SPI clock is always on. */ uint32_t mem_clk_mode:2; - uint32_t reserved_2:19; - /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + uint32_t reserved_2:20; + /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_ECC_ERR_ADDR_REG. + * in SPI_MEM_ECC_ERR_ADDR_REG. */ uint32_t mem_rresp_ecc_err_en:1; /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; @@ -200,9 +195,9 @@ typedef union { */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -238,16 +233,16 @@ typedef union { struct { /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_CS_SETUP bit. + * SPI_MEM_CS_SETUP bit. */ uint32_t mem_cs_setup_time:5; /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_CS_HOLD bit. + * SPI_MEM_CS_HOLD bit. */ uint32_t mem_cs_hold_time:5; /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * spi_mem_c_CS_HOLD_TIME + spi_mem_c_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ uint32_t mem_ecc_cs_hold_time:3; @@ -270,7 +265,7 @@ typedef union { uint32_t mem_split_trans_en:1; /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t mem_cs_hold_delay:6; @@ -424,7 +419,7 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -471,16 +466,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -499,18 +494,18 @@ typedef union { typedef union { struct { /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk - * frequency is system/(spi_mem_c_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; @@ -534,7 +529,11 @@ typedef union { * Register clock gate enable signal. 1: Enable. 0: Disable. */ uint32_t clk_en:1; - uint32_t reserved_1:31; + /** mspi_clk_force_on : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ + uint32_t mspi_clk_force_on:1; + uint32_t reserved_2:30; }; uint32_t val; } spi_mem_c_clock_gate_reg_t; @@ -557,7 +556,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -933,7 +932,7 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -998,7 +997,7 @@ typedef union { */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * spi_smem_c_CS_HOLD_TIME + spi_smem_c_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; @@ -1015,7 +1014,7 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (spi_smem_c_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; @@ -1037,19 +1036,19 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - /** mem_flash_lock_en : R/W; bitpos: [12]; default: 0; + uint32_t mem_lock_delay_time:12; + /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. */ uint32_t mem_flash_lock_en:1; - /** mem_sram_lock_en : R/W; bitpos: [13]; default: 0; + /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. */ uint32_t mem_sram_lock_en:1; - uint32_t reserved_14:18; + uint32_t reserved_21:11; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -1063,48 +1062,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_ena:1; /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_ena:1; /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_ECC_ERR_INT interrupt. + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_ena:1; /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_ena:1; /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_ena:1; /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_ena:1; /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_ena:1; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_ena:1; /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_ena:1; /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_ena:1; }; @@ -1118,48 +1117,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_clr:1; /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_clr:1; /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_ECC_ERR_INT interrupt. + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_clr:1; /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_clr:1; /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_clr:1; /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_clr:1; /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_clr:1; /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_clr:1; /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_clr:1; /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_clr:1; }; @@ -1173,67 +1172,67 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t mem_slv_st_end_int_raw:1; /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ uint32_t mem_mst_st_end_int_raw:1; /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_ECC_ERR_INT interrupt. When spi_fmem_c_ECC_ERR_INT_EN is set - * and spi_smem_c_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_ECC_ERR_INT_NUM. When - * spi_fmem_c_ECC_ERR_INT_EN is cleared and spi_smem_c_ECC_ERR_INT_EN is set, this bit is + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and - * spi_smem_c_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and spi_smem_c_ECC_ERR_INT_EN + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ uint32_t mem_ecc_err_int_raw:1; /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ uint32_t mem_pms_reject_int_raw:1; /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_raddr_err_int_raw:1; /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ uint32_t mem_axi_wr_flash_err_int_raw:1; /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. */ uint32_t mem_dqs0_afifo_ovf_int_raw:1; /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS is overflow. */ uint32_t mem_dqs1_afifo_ovf_int_raw:1; /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is * underflow. */ uint32_t mem_bus_fifo1_udf_int_raw:1; /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is * underflow. */ uint32_t mem_bus_fifo0_udf_int_raw:1; @@ -1248,48 +1247,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_st:1; /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_st:1; /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_ECC_ERR_INT interrupt. + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_st:1; /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_st:1; /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_st:1; /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_st:1; /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_st:1; /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_st:1; /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_st:1; /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_st:1; }; @@ -1313,8 +1312,8 @@ typedef union { uint32_t fmem_pmsn_wr_attr:1; /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers spi_fmem_c_PMSn_ADDR_REG and - * spi_fmem_c_PMSn_SIZE_REG. + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; uint32_t reserved_3:29; @@ -1342,8 +1341,8 @@ typedef union { typedef union { struct { /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section n address region is (spi_fmem_c_PMSn_ADDR_S, - * spi_fmem_c_PMSn_ADDR_S + spi_fmem_c_PMSn_SIZE) + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) */ uint32_t fmem_pmsn_size:17; uint32_t reserved_17:15; @@ -1366,8 +1365,8 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers spi_smem_c_PMSn_ADDR_REG and - * spi_smem_c_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; uint32_t reserved_3:29; @@ -1395,8 +1394,8 @@ typedef union { typedef union { struct { /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (spi_smem_c_PMSn_ADDR_S, - * spi_smem_c_PMSn_ADDR_S + spi_smem_c_PMSn_SIZE) + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) */ uint32_t smem_pmsn_size:17; uint32_t reserved_17:15; @@ -1416,22 +1415,22 @@ typedef union { uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; @@ -1445,7 +1444,7 @@ typedef union { struct { /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_reject_addr:29; uint32_t reserved_29:3; @@ -1463,11 +1462,11 @@ typedef union { uint32_t reserved_0:5; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; @@ -1492,9 +1491,9 @@ typedef union { uint32_t mem_usr_ecc_addr_en:1; uint32_t reserved_23:1; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_ECC_ERR_BITS and spi_mem_c_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_ECC_ERR_BITS and - * spi_mem_c_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; @@ -1513,7 +1512,7 @@ typedef union { struct { /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_addr:29; uint32_t reserved_29:3; @@ -1895,17 +1894,27 @@ typedef union { */ uint32_t smem_dll_timing_cali:1; uint32_t reserved_6:1; - /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; + /** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1; * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. */ uint32_t smem_dqs0_270_sel:2; - /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; + /** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1; * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, * 2'd2: 1.5ns 2'd3: 2.0ns. */ uint32_t smem_dqs0_90_sel:2; - uint32_t reserved_11:21; + /** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_270_sel:2; + /** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_90_sel:2; + uint32_t reserved_15:17; }; uint32_t val; } spi_smem_c_timing_cali_reg_t; @@ -2330,8 +2339,8 @@ typedef union { */ uint32_t mem_nand_flash_seq_hd_index:15; /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. spi_mem_c_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to spi_mem_c_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. */ uint32_t mem_nand_flash_seq_usr_trig:1; /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; @@ -2339,7 +2348,7 @@ typedef union { */ uint32_t mem_nand_flash_lut_en:1; /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; - * Used with spi_mem_c_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to * execute page execute. 1: write end 0: write in a page size. */ uint32_t mem_nand_flash_seq_usr_wend:1; @@ -2384,22 +2393,22 @@ typedef union { struct { /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din0:8; /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din1:8; /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din2:8; /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din3:8; }; @@ -2492,7 +2501,7 @@ typedef union { /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the spi_mem_c_NAND_FLASH_CMD_LUT0_REG's + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's * field. The number of CMD LUT entries can be defined by the user, but cannot exceed * 16 ) */ @@ -2518,12 +2527,12 @@ typedef union { uint32_t mem_nand_flash_sr_chk_en0:1; /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * spi_mem_c_NAND_FLASH_CFG_DATA + * SPI_MEM_NAND_FLASH_CFG_DATA */ uint32_t mem_nand_flash_din_index0:4; /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * spi_mem_c_NAND_FLASH_SR_ADDR + * SPI_MEM_NAND_FLASH_SR_ADDR */ uint32_t mem_nand_flash_addr_index0:4; /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; @@ -2534,7 +2543,7 @@ typedef union { /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in * CMD LUT.(Note these registers are described to indicate the - * spi_mem_c_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined * by the user, but cannot exceed 16 ) */ uint32_t mem_nand_flash_cmd_index0:4; @@ -2730,16 +2739,16 @@ typedef union { * Set this bit to enable mmu-memory clock force on */ uint32_t mmu_mem_force_on:1; - /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ uint32_t mmu_mem_force_pd:1; - /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 0; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; * Set this bit to force mmu-memory powerup, in this case, the power should also be * controlled by rtc. */ uint32_t mmu_mem_force_pu:1; - /** mmu_page_size : HRO; bitpos: [4:3]; default: 0; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ uint32_t mmu_page_size:2; @@ -2859,7 +2868,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36774400; + /** mem_date : R/W; bitpos: [27:0]; default: 37822512; * SPI0 register version. */ uint32_t mem_date:28; diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h deleted file mode 100644 index 220deaf10b..0000000000 --- a/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h +++ /dev/null @@ -1,2982 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Status and state control register */ -/** Type of mem_cmd register - * SPI0 FSM status register - */ -typedef union { - struct { - /** mem_mst_st : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ - uint32_t mem_mst_st:4; - /** mem_slv_st : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ - uint32_t mem_slv_st:4; - uint32_t reserved_8:10; - /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - uint32_t mem_usr:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_cmd_reg_t; - -/** Type of mem_axi_err_addr register - * SPI0 AXI request error address. - */ -typedef union { - struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ - uint32_t mem_axi_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_axi_err_addr_reg_t; - - -/** Group: Flash Control and configuration registers */ -/** Type of mem_ctrl register - * SPI0 control register. - */ -typedef union { - struct { - /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ - uint32_t mem_wdummy_dqs_always_out:1; - /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t mem_wdummy_always_out:1; - /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ - uint32_t mem_fdummy_rin:1; - /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ - uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ - uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ - uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ - uint32_t mem_faddr_oct:1; - uint32_t reserved_7:1; - /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_oct:1; - uint32_t reserved_10:3; - /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ - uint32_t mem_fastrd_mode:1; - /** mem_fread_dual : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_dual:1; - uint32_t reserved_15:3; - /** mem_q_pol : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ - uint32_t mem_q_pol:1; - /** mem_d_pol : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ - uint32_t mem_d_pol:1; - /** mem_fread_quad : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_quad:1; - /** mem_wp_reg : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ - uint32_t mem_wp_reg:1; - uint32_t reserved_22:1; - /** mem_fread_dio : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_dio:1; - /** mem_fread_qio : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_qio:1; - uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ - uint32_t mem_dqs_ie_always_on:1; - /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ - uint32_t mem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_ctrl_reg_t; - -/** Type of mem_ctrl1 register - * SPI0 control1 register. - */ -typedef union { - struct { - /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ - uint32_t mem_clk_mode:2; - uint32_t reserved_2:20; - /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t aw_size0_1_support_en:1; - /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ - uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ - uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ - uint32_t mem_aw_splice_en:1; - /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ - uint32_t mem_ram0_en:1; - /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ - uint32_t mem_dual_ram_en:1; - /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ - uint32_t mem_fast_write_en:1; - /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_rxfifo_rst:1; - /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_txfifo_rst:1; - }; - uint32_t val; -} spi_mem_ctrl1_reg_t; - -/** Type of mem_ctrl2 register - * SPI0 control2 register. - */ -typedef union { - struct { - /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ - uint32_t mem_cs_setup_time:5; - /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ - uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ - uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ - uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ - uint32_t mem_ecc_16to18_byte_en:1; - uint32_t reserved_15:9; - /** mem_split_trans_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ - uint32_t mem_split_trans_en:1; - /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ - uint32_t mem_cs_hold_delay:6; - /** mem_sync_reset : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ - uint32_t mem_sync_reset:1; - }; - uint32_t val; -} spi_mem_ctrl2_reg_t; - -/** Type of mem_misc register - * SPI0 misc register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ - uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ - uint32_t mem_ssub_pin:1; - /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ - uint32_t mem_ck_idle_edge:1; - /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ - uint32_t mem_cs_keep_active:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_misc_reg_t; - -/** Type of mem_cache_fctrl register - * SPI0 bit mode control register. - */ -typedef union { - struct { - /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_axi_req_en:1; - /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_usr_addr_4byte:1; - /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_flash_usr_cmd:1; - /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdin_dual:1; - /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdout_dual:1; - /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_faddr_dual:1; - /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdin_quad:1; - /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdout_quad:1; - /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_faddr_quad:1; - uint32_t reserved_9:21; - /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ - uint32_t same_aw_ar_addr_chk_en:1; - /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ - uint32_t close_axi_inf_en:1; - }; - uint32_t val; -} spi_mem_cache_fctrl_reg_t; - -/** Type of mem_ddr register - * SPI0 flash DDR mode control register - */ -typedef union { - struct { - /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t fmem_ddr_en:1; - /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t fmem_var_dummy:1; - /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_rdat_swp:1; - /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_wdat_swp:1; - /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t fmem_ddr_cmd_dis:1; - /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ - uint32_t fmem_outminbytelen:7; - /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ - uint32_t fmem_tx_ddr_msk_en:1; - /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ - uint32_t fmem_rx_ddr_msk_en:1; - /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t fmem_usr_ddr_dqs_thd:7; - /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t fmem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t fmem_clk_diff_en:1; - uint32_t reserved_25:1; - /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t fmem_dqs_ca_in:1; - /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t fmem_hyperbus_dummy_2x:1; - /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ - uint32_t fmem_clk_diff_inv:1; - /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ - uint32_t fmem_octa_ram_addr:1; - /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t fmem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_ddr_reg_t; - - -/** Group: Clock control and configuration registers */ -/** Type of mem_clock register - * SPI clock division control register. - */ -typedef union { - struct { - /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to SPI_MEM_CLKCNT_N. - */ - uint32_t mem_clkcnt_l:8; - /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). - */ - uint32_t mem_clkcnt_h:8; - /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(SPI_MEM_CLKCNT_N+1) - */ - uint32_t mem_clkcnt_n:8; - uint32_t reserved_24:7; - /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ - uint32_t mem_clk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_clock_reg_t; - -/** Type of mem_sram_clk register - * SPI0 external RAM clock control register - */ -typedef union { - struct { - /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_l:8; - /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_h:8; - /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(SPI_MEM_SCLKCNT_N+1) - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_n:8; - uint32_t reserved_24:7; - /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk - * is divided from system clock. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_sram_clk_reg_t; - -/** Type of mem_clock_gate register - * SPI0 clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ - uint32_t clk_en:1; - /** mspi_clk_force_on : HRO; bitpos: [1]; default: 1; - * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. - */ - uint32_t mspi_clk_force_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_clock_gate_reg_t; - - -/** Group: Flash User-defined control registers */ -/** Type of mem_user register - * SPI0 user register. - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** mem_cs_hold : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t mem_cs_hold:1; - /** mem_cs_setup : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ - uint32_t mem_cs_setup:1; - uint32_t reserved_8:1; - /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ - uint32_t mem_ck_out_edge:1; - uint32_t reserved_10:16; - /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ - uint32_t mem_usr_dummy_idle:1; - uint32_t reserved_27:2; - /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ - uint32_t mem_usr_dummy:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_user_reg_t; - -/** Type of mem_user1 register - * SPI0 user1 register. - */ -typedef union { - struct { - /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ - uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ - uint32_t mem_usr_dbytelen:6; - uint32_t reserved_12:14; - /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ - uint32_t mem_usr_addr_bitlen:6; - }; - uint32_t val; -} spi_mem_user1_reg_t; - -/** Type of mem_user2 register - * SPI0 user2 register. - */ -typedef union { - struct { - /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ - uint32_t mem_usr_command_value:16; - uint32_t reserved_16:12; - /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ - uint32_t mem_usr_command_bitlen:4; - }; - uint32_t val; -} spi_mem_user2_reg_t; - -/** Type of mem_rd_status register - * SPI0 read control register. - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode:8; - /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode_bitlen:3; - /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode_en:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_rd_status_reg_t; - - -/** Group: External RAM Control and configuration registers */ -/** Type of mem_cache_sctrl register - * SPI0 external RAM control register - */ -typedef union { - struct { - /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_usr_saddr_4byte:1; - /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_sram_dio:1; - /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_sram_qio:1; - /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_wr_sram_dummy:1; - /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_rd_sram_dummy:1; - /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rcmd:1; - /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_rdummy_cyclelen:6; - uint32_t reserved_12:2; - /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_addr_bitlen:6; - /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wcmd:1; - /** mem_sram_oct : R/W; bitpos: [21]; default: 0; - * reserved - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_oct:1; - /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_wdummy_cyclelen:6; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_cache_sctrl_reg_t; - -/** Type of mem_sram_cmd register - * SPI0 external RAM mode control register - */ -typedef union { - struct { - /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclk_mode:2; - /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_swb_mode:8; - /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_dual:1; - /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_dual:1; - /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_dual:1; - uint32_t reserved_13:1; - /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_quad:1; - /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_quad:1; - /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_quad:1; - /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_scmd_quad:1; - /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_oct:1; - /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_oct:1; - /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_oct:1; - /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_scmd_oct:1; - /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdummy_rin:1; - /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdummy_wout:1; - /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ - uint32_t smem_wdummy_dqs_always_out:1; - /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t smem_wdummy_always_out:1; - /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_hex:1; - /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_hex:1; - uint32_t reserved_28:2; - /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ - uint32_t smem_dqs_ie_always_on:1; - /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ - uint32_t smem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_sram_cmd_reg_t; - -/** Type of mem_sram_drd_cmd register - * SPI0 external RAM DDR read command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rd_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_drd_cmd_reg_t; - -/** Type of mem_sram_dwr_cmd register - * SPI0 external RAM DDR write command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wr_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_dwr_cmd_reg_t; - -/** Type of smem_ddr register - * SPI0 external RAM DDR mode control register - */ -typedef union { - struct { - /** smem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t smem_ddr_en:1; - /** smem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t smem_var_dummy:1; - /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_rdat_swp:1; - /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_wdat_swp:1; - /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t smem_ddr_cmd_dis:1; - /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ - uint32_t smem_outminbytelen:7; - /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ - uint32_t smem_tx_ddr_msk_en:1; - /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ - uint32_t smem_rx_ddr_msk_en:1; - /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t smem_usr_ddr_dqs_thd:7; - /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t smem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t smem_clk_diff_en:1; - uint32_t reserved_25:1; - /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t smem_dqs_ca_in:1; - /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t smem_hyperbus_dummy_2x:1; - /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ - uint32_t smem_clk_diff_inv:1; - /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ - uint32_t smem_octa_ram_addr:1; - /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t smem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_smem_ddr_reg_t; - -/** Type of smem_ac register - * MSPI external RAM ECC and SPI CS timing control register - */ -typedef union { - struct { - /** smem_cs_setup : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ - uint32_t smem_cs_setup:1; - /** smem_cs_hold : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t smem_cs_hold:1; - /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ - uint32_t smem_cs_setup_time:5; - /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ - uint32_t smem_cs_hold_time:5; - /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ - uint32_t smem_ecc_cs_hold_time:3; - /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ - uint32_t smem_ecc_skip_page_corner:1; - /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ - uint32_t smem_ecc_16to18_byte_en:1; - uint32_t reserved_17:8; - /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ - uint32_t smem_cs_hold_delay:6; - /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ - uint32_t smem_split_trans_en:1; - }; - uint32_t val; -} spi_smem_ac_reg_t; - - -/** Group: State control register */ -/** Type of mem_fsm register - * SPI0 FSM status register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ - uint32_t mem_lock_delay_time:12; - /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_flash_lock_en:1; - /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_sram_lock_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_mem_fsm_reg_t; - - -/** Group: Interrupt registers */ -/** Type of mem_int_ena register - * SPI0 interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_ena:1; - /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_ena:1; - /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_ena:1; - /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_ena:1; - /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_ena:1; - /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_ena:1; - /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_ena:1; - }; - uint32_t val; -} spi_mem_int_ena_reg_t; - -/** Type of mem_int_clr register - * SPI0 interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_clr:1; - /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_clr:1; - /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_clr:1; - /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_clr:1; - /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_clr:1; - /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_clr:1; - /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_clr:1; - }; - uint32_t val; -} spi_mem_int_clr_reg_t; - -/** Type of mem_int_raw register - * SPI0 interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ - uint32_t mem_slv_st_end_int_raw:1; - /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ - uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ - uint32_t mem_ecc_err_int_raw:1; - /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ - uint32_t mem_pms_reject_int_raw:1; - /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ - uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ - uint32_t mem_dqs0_afifo_ovf_int_raw:1; - /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ - uint32_t mem_dqs1_afifo_ovf_int_raw:1; - /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo1_udf_int_raw:1; - /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo0_udf_int_raw:1; - }; - uint32_t val; -} spi_mem_int_raw_reg_t; - -/** Type of mem_int_st register - * SPI0 interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_st:1; - /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_st:1; - /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_st:1; - /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_st:1; - /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_st:1; - /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_st:1; - /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_st:1; - }; - uint32_t val; -} spi_mem_int_st_reg_t; - - -/** Group: PMS control and configuration registers */ -/** Type of fmem_pmsn_attr register - * SPI1 flash PMS section n attribute register - */ -typedef union { - struct { - /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_rd_attr:1; - /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_wr_attr:1; - /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and - * SPI_FMEM_PMSn_SIZE_REG. - */ - uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_fmem_pmsn_attr_reg_t; - -/** Type of fmem_pmsn_addr register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section n start address value - */ - uint32_t fmem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_fmem_pmsn_addr_reg_t; - -/** Type of fmem_pmsn_size register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, - * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) - */ - uint32_t fmem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_fmem_pmsn_size_reg_t; - -/** Type of smem_pmsn_attr register - * SPI1 external RAM PMS section n attribute register - */ -typedef union { - struct { - /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_rd_attr:1; - /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_wr_attr:1; - /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and - * SPI_SMEM_PMSn_SIZE_REG. - */ - uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_smem_pmsn_attr_reg_t; - -/** Type of smem_pmsn_addr register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section n start address value - */ - uint32_t smem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_smem_pmsn_addr_reg_t; - -/** Type of smem_pmsn_size register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, - * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) - */ - uint32_t smem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_smem_pmsn_size_reg_t; - -/** Type of mem_pms_reject register - * SPI1 access reject register - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** mem_pm_en : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ - uint32_t mem_pm_en:1; - /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ld:1; - /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_st:1; - /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_multi_hit:1; - /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ivd:1; - }; - uint32_t val; -} spi_mem_pms_reject_reg_t; - -/** Type of mem_pms_reject_addr register - * SPI1 access reject addr register - */ -typedef union { - struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_reject_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_pms_reject_addr_reg_t; - - -/** Group: MSPI ECC registers */ -/** Type of mem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_cnt:6; - /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t fmem_ecc_err_int_num:6; - /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ - uint32_t fmem_ecc_err_int_en:1; - /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ - uint32_t fmem_page_size:2; - uint32_t reserved_20:1; - /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ - uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ - uint32_t mem_usr_ecc_addr_en:1; - uint32_t reserved_23:1; - /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ - uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ - uint32_t mem_ecc_err_bits:7; - }; - uint32_t val; -} spi_mem_ecc_ctrl_reg_t; - -/** Type of mem_ecc_err_addr register - * MSPI ECC error address register - */ -typedef union { - struct { - /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_ecc_err_addr_reg_t; - -/** Type of smem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:17; - /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ - uint32_t smem_ecc_err_int_en:1; - /** smem_page_size : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ - uint32_t smem_page_size:2; - /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ - uint32_t smem_ecc_addr_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_smem_ecc_ctrl_reg_t; - - -/** Group: Status and state control registers */ -/** Type of smem_axi_addr_ctrl register - * SPI0 AXI address control register - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ - uint32_t mem_all_fifo_empty:1; - /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t rdata_afifo_rempty:1; - /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t raddr_afifo_rempty:1; - /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wdata_afifo_rempty:1; - /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wblen_afifo_rempty:1; - /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ - uint32_t all_axi_trans_afifo_empty:1; - }; - uint32_t val; -} spi_smem_axi_addr_ctrl_reg_t; - -/** Type of mem_axi_err_resp_en register - * SPI0 AXI error response enable register - */ -typedef union { - struct { - /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_wstrb:1; - /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_vld:1; - /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_gid:1; - /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_ecc:1; - /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ - uint32_t mem_ar_resp_en_mmu_sens:1; - /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ - uint32_t mem_ar_resp_en_axi_size:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} spi_mem_axi_err_resp_en_reg_t; - - -/** Group: Flash timing registers */ -/** Type of mem_timing_cali register - * SPI0 flash timing calibration register - */ -typedef union { - struct { - /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t mem_timing_clk_ena:1; - /** mem_timing_cali : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ - uint32_t mem_timing_cali:1; - /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ - uint32_t mem_dll_timing_cali:1; - /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ - uint32_t mem_timing_cali_update:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} spi_mem_timing_cali_reg_t; - -/** Type of mem_din_mode register - * MSPI flash input timing delay mode control register - */ -typedef union { - struct { - /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din0_mode:3; - /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din1_mode:3; - /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din2_mode:3; - /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din3_mode:3; - /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din4_mode:3; - /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din5_mode:3; - /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din6_mode:3; - /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din7_mode:3; - /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_mem_din_mode_reg_t; - -/** Type of mem_din_num register - * MSPI flash input timing delay number control register - */ -typedef union { - struct { - /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din0_num:2; - /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din1_num:2; - /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din2_num:2; - /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din3_num:2; - /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din4_num:2; - /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din5_num:2; - /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din6_num:2; - /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din7_num:2; - /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_mem_din_num_reg_t; - -/** Type of mem_dout_mode register - * MSPI flash output timing adjustment control register - */ -typedef union { - struct { - /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout0_mode:1; - /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout1_mode:1; - /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout2_mode:1; - /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout3_mode:1; - /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout4_mode:1; - /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout5_mode:1; - /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout6_mode:1; - /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout7_mode:1; - /** mem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_mem_dout_mode_reg_t; - - -/** Group: External RAM timing registers */ -/** Type of smem_timing_cali register - * MSPI external RAM timing calibration register - */ -typedef union { - struct { - /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t smem_timing_clk_ena:1; - /** smem_timing_cali : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ - uint32_t smem_timing_cali:1; - /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t smem_extra_dummy_cyclelen:3; - /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ - uint32_t smem_dll_timing_cali:1; - uint32_t reserved_6:1; - /** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_270_sel:2; - /** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_90_sel:2; - /** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs1_270_sel:2; - /** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs1_90_sel:2; - uint32_t reserved_15:17; - }; - uint32_t val; -} spi_smem_timing_cali_reg_t; - -/** Type of smem_din_mode register - * MSPI external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din0_mode:3; - /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din1_mode:3; - /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din2_mode:3; - /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din3_mode:3; - /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din4_mode:3; - /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din5_mode:3; - /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din6_mode:3; - /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din7_mode:3; - /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_mode_reg_t; - -/** Type of smem_din_num register - * MSPI external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din0_num:2; - /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din1_num:2; - /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din2_num:2; - /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din3_num:2; - /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din4_num:2; - /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din5_num:2; - /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din6_num:2; - /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din7_num:2; - /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_num_reg_t; - -/** Type of smem_dout_mode register - * MSPI external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout0_mode:1; - /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout1_mode:1; - /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout2_mode:1; - /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout3_mode:1; - /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout4_mode:1; - /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout5_mode:1; - /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout6_mode:1; - /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout7_mode:1; - /** smem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_mode_reg_t; - -/** Type of smem_din_hex_mode register - * MSPI 16x external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din08_mode : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din08_mode:3; - /** smem_din09_mode : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din09_mode:3; - /** smem_din10_mode : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din10_mode:3; - /** smem_din11_mode : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din11_mode:3; - /** smem_din12_mode : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din12_mode:3; - /** smem_din13_mode : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din13_mode:3; - /** smem_din14_mode : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din14_mode:3; - /** smem_din15_mode : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din15_mode:3; - /** smem_dins_hex_mode : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_hex_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_hex_mode_reg_t; - -/** Type of smem_din_hex_num register - * MSPI 16x external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din08_num : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din08_num:2; - /** smem_din09_num : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din09_num:2; - /** smem_din10_num : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din10_num:2; - /** smem_din11_num : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din11_num:2; - /** smem_din12_num : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din12_num:2; - /** smem_din13_num : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din13_num:2; - /** smem_din14_num : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din14_num:2; - /** smem_din15_num : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din15_num:2; - /** smem_dins_hex_num : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_hex_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_hex_num_reg_t; - -/** Type of smem_dout_hex_mode register - * MSPI 16x external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout08_mode : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout08_mode:1; - /** smem_dout09_mode : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout09_mode:1; - /** smem_dout10_mode : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout10_mode:1; - /** smem_dout11_mode : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout11_mode:1; - /** smem_dout12_mode : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout12_mode:1; - /** smem_dout13_mode : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout13_mode:1; - /** smem_dout14_mode : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout14_mode:1; - /** smem_dout15_mode : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout15_mode:1; - /** smem_douts_hex_mode : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_hex_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_hex_mode_reg_t; - - -/** Group: NAND FLASH control and status registers */ -/** Type of mem_nand_flash_en register - * NAND FLASH control register - */ -typedef union { - struct { - /** mem_nand_flash_en : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ - uint32_t mem_nand_flash_en:1; - /** mem_nand_flash_seq_hd_index : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ - uint32_t mem_nand_flash_seq_hd_index:15; - /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ - uint32_t mem_nand_flash_seq_usr_trig:1; - /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_lut_en:1; - /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to - * execute page execute. 1: write end 0: write in a page size. - */ - uint32_t mem_nand_flash_seq_usr_wend:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_nand_flash_en_reg_t; - -/** Type of mem_nand_flash_sr_addr0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_addr0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr0:8; - /** mem_nand_flash_sr_addr1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr1:8; - /** mem_nand_flash_sr_addr2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr2:8; - /** mem_nand_flash_sr_addr3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_addr0_reg_t; - -/** Type of mem_nand_flash_sr_din0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din0:8; - /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din1:8; - /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din2:8; - /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_din0_reg_t; - -/** Type of mem_nand_flash_cfg_data0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data0:16; - /** mem_nand_flash_cfg_data1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data1:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data0_reg_t; - -/** Type of mem_nand_flash_cfg_data1 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data2:16; - /** mem_nand_flash_cfg_data3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data3:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data1_reg_t; - -/** Type of mem_nand_flash_cfg_data2 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data4:16; - /** mem_nand_flash_cfg_data5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data5:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data2_reg_t; - -/** Type of mem_nand_flash_cmd_lut0 register - * MSPI NAND FLASH CMD LUT control register - */ -typedef union { - struct { - /** mem_nand_flash_lut_cmd_value0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_value0:16; - /** mem_nand_flash_lut_sfsm_st_en0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ - uint32_t mem_nand_flash_lut_sfsm_st_en0:4; - /** mem_nand_flash_lut_cmd_len0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_len0:4; - /** mem_nand_flash_lut_addr_len0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_addr_len0:4; - /** mem_nand_flash_lut_data_len0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_data_len0:2; - /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ - uint32_t mem_nand_flash_lut_bus_en0:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_nand_flash_cmd_lut0_reg_t; - -/** Type of mem_nand_flash_spi_seq0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_seq_tail_flg0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ - uint32_t mem_nand_flash_seq_tail_flg0:1; - /** mem_nand_flash_sr_chk_en0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_sr_chk_en0:1; - /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ - uint32_t mem_nand_flash_din_index0:4; - /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ - uint32_t mem_nand_flash_addr_index0:4; - /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ - uint32_t mem_nand_flash_req_or_cfg0:1; - /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ - uint32_t mem_nand_flash_cmd_index0:4; - uint32_t reserved_15:17; - }; - uint32_t val; -} spi_mem_nand_flash_spi_seq0_reg_t; - - -/** Group: Manual Encryption plaintext Memory */ -/** Type of mem_xts_plain_base register - * The base address of the memory that stores plaintext in Manual Encryption - */ -typedef union { - struct { - /** xts_plain : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ - uint32_t xts_plain:32; - }; - uint32_t val; -} spi_mem_xts_plain_base_reg_t; - - -/** Group: Manual Encryption configuration registers */ -/** Type of mem_xts_linesize register - * Manual Encryption Line-Size register - */ -typedef union { - struct { - /** xts_linesize : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ - uint32_t xts_linesize:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_linesize_reg_t; - -/** Type of mem_xts_destination register - * Manual Encryption destination register - */ -typedef union { - struct { - /** xts_destination : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ - uint32_t xts_destination:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destination_reg_t; - -/** Type of mem_xts_physical_address register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ - uint32_t xts_physical_address:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_physical_address_reg_t; - - -/** Group: Manual Encryption control and status registers */ -/** Type of mem_xts_trigger register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_trigger : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ - uint32_t xts_trigger:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_trigger_reg_t; - -/** Type of mem_xts_release register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_release : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ - uint32_t xts_release:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_release_reg_t; - -/** Type of mem_xts_destroy register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_destroy : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ - uint32_t xts_destroy:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destroy_reg_t; - -/** Type of mem_xts_state register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_state : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ - uint32_t xts_state:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_state_reg_t; - - -/** Group: Manual Encryption version control register */ -/** Type of mem_xts_date register - * Manual Encryption version register - */ -typedef union { - struct { - /** xts_date : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ - uint32_t xts_date:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_date_reg_t; - - -/** Group: MMU access registers */ -/** Type of mem_mmu_item_content register - * MSPI-MMU item content register - */ -typedef union { - struct { - /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ - uint32_t mmu_item_content:32; - }; - uint32_t val; -} spi_mem_mmu_item_content_reg_t; - -/** Type of mem_mmu_item_index register - * MSPI-MMU item index register - */ -typedef union { - struct { - /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ - uint32_t mmu_item_index:32; - }; - uint32_t val; -} spi_mem_mmu_item_index_reg_t; - - -/** Group: MMU power control and configuration registers */ -/** Type of mem_mmu_power_ctrl register - * MSPI MMU power control register - */ -typedef union { - struct { - /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ - uint32_t mmu_mem_force_on:1; - /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Set this bit to force mmu-memory powerdown - */ - uint32_t mmu_mem_force_pd:1; - /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ - uint32_t mmu_mem_force_pu:1; - /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ - uint32_t mmu_page_size:2; - uint32_t reserved_5:11; - /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ - uint32_t mem_aux_ctrl:14; - /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_rdn_ena:1; - /** mem_rdn_result : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_rdn_result:1; - }; - uint32_t val; -} spi_mem_mmu_power_ctrl_reg_t; - - -/** Group: External mem cryption DPA registers */ -/** Type of mem_dpa_ctrl register - * SPI memory cryption DPA register - */ -typedef union { - struct { - /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ - uint32_t crypt_security_level:3; - /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ - uint32_t crypt_calc_d_dpa_en:1; - /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ - uint32_t crypt_dpa_select_register:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} spi_mem_dpa_ctrl_reg_t; - - -/** Group: External mem cryption PSEUDO registers */ -/** Type of mem_xts_pseudo_round_conf register - * SPI memory cryption PSEUDO register - */ -typedef union { - struct { - /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ - uint32_t mem_mode_pseudo:2; - /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be performed. - */ - uint32_t mem_pseudo_rng_cnt:3; - /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be performed. - */ - uint32_t mem_pseudo_base:4; - /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be performed randomly between 0 & - * 2**(inc+1). - */ - uint32_t mem_pseudo_inc:2; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_xts_pseudo_round_conf_reg_t; - - -/** Group: ECO registers */ -/** Type of mem_registerrnd_eco_high register - * MSPI ECO high register - */ -typedef union { - struct { - /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; - * ECO high register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_registerrnd_eco_high:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_high_reg_t; - -/** Type of mem_registerrnd_eco_low register - * MSPI ECO low register - */ -typedef union { - struct { - /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; - * ECO low register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_registerrnd_eco_low:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_low_reg_t; - - -/** Group: Version control register */ -/** Type of mem_date register - * SPI0 version control register - */ -typedef union { - struct { - /** mem_date : R/W; bitpos: [27:0]; default: 37822512; - * SPI0 register version. - */ - uint32_t mem_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_date_reg_t; - - -typedef struct { - volatile spi_mem_cmd_reg_t mem_cmd; - uint32_t reserved_004; - volatile spi_mem_ctrl_reg_t mem_ctrl; - volatile spi_mem_ctrl1_reg_t mem_ctrl1; - volatile spi_mem_ctrl2_reg_t mem_ctrl2; - volatile spi_mem_clock_reg_t mem_clock; - volatile spi_mem_user_reg_t mem_user; - volatile spi_mem_user1_reg_t mem_user1; - volatile spi_mem_user2_reg_t mem_user2; - uint32_t reserved_024[2]; - volatile spi_mem_rd_status_reg_t mem_rd_status; - uint32_t reserved_030; - volatile spi_mem_misc_reg_t mem_misc; - uint32_t reserved_038; - volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; - volatile spi_mem_cache_sctrl_reg_t mem_cache_sctrl; - volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; - volatile spi_mem_sram_drd_cmd_reg_t mem_sram_drd_cmd; - volatile spi_mem_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; - volatile spi_mem_sram_clk_reg_t mem_sram_clk; - volatile spi_mem_fsm_reg_t mem_fsm; - uint32_t reserved_058[26]; - volatile spi_mem_int_ena_reg_t mem_int_ena; - volatile spi_mem_int_clr_reg_t mem_int_clr; - volatile spi_mem_int_raw_reg_t mem_int_raw; - volatile spi_mem_int_st_reg_t mem_int_st; - uint32_t reserved_0d0; - volatile spi_mem_ddr_reg_t mem_ddr; - volatile spi_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; - volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; - volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; - volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; - volatile spi_mem_pms_reject_reg_t mem_pms_reject; - volatile spi_mem_pms_reject_addr_reg_t mem_pms_reject_addr; - volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; - volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; - volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; - volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; - volatile spi_mem_timing_cali_reg_t mem_timing_cali; - volatile spi_mem_din_mode_reg_t mem_din_mode; - volatile spi_mem_din_num_reg_t mem_din_num; - volatile spi_mem_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_din_mode_reg_t smem_din_mode; - volatile spi_smem_din_num_reg_t smem_din_num; - volatile spi_smem_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_ac_reg_t smem_ac; - volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; - volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; - volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; - uint32_t reserved_1b0[20]; - volatile spi_mem_clock_gate_reg_t mem_clock_gate; - volatile spi_mem_nand_flash_en_reg_t mem_nand_flash_en; - volatile spi_mem_nand_flash_sr_addr0_reg_t mem_nand_flash_sr_addr0; - volatile spi_mem_nand_flash_sr_din0_reg_t mem_nand_flash_sr_din0; - volatile spi_mem_nand_flash_cfg_data0_reg_t mem_nand_flash_cfg_data0; - volatile spi_mem_nand_flash_cfg_data1_reg_t mem_nand_flash_cfg_data1; - volatile spi_mem_nand_flash_cfg_data2_reg_t mem_nand_flash_cfg_data2; - uint32_t reserved_21c[9]; - volatile spi_mem_nand_flash_cmd_lut0_reg_t mem_nand_flash_cmd_lut0; - uint32_t reserved_244[15]; - volatile spi_mem_nand_flash_spi_seq0_reg_t mem_nand_flash_spi_seq0; - uint32_t reserved_284[31]; - volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; - uint32_t reserved_304[15]; - volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; - volatile spi_mem_xts_destination_reg_t mem_xts_destination; - volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; - volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; - volatile spi_mem_xts_release_reg_t mem_xts_release; - volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; - volatile spi_mem_xts_state_reg_t mem_xts_state; - volatile spi_mem_xts_date_reg_t mem_xts_date; - uint32_t reserved_360[7]; - volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; - volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; - volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; - volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; - volatile spi_mem_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; - uint32_t reserved_390[24]; - volatile spi_mem_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; - volatile spi_mem_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; - uint32_t reserved_3f8; - volatile spi_mem_date_reg_t mem_date; -} spi_dev_t; - -extern spi_dev_t SPIMEM0; - -#ifndef __cplusplus -_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 123eae8110..fe30fd945e 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -807,6 +807,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + bool + default y + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 489c91b559..36c0a8067d 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -344,6 +344,7 @@ #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 79ffd1833d..724a5a4819 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -109,6 +109,18 @@ menu "Main Flash configuration" This config is used for setting Tsus parameter. Tsus means CS# high to next command after suspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet. + config SPI_FLASH_SUSPEND_TRS_VAL_US + int "SPI flash tRS value (refer to chapter AC CHARACTERISTICS)" + default 50 + range 20 200 + depends on SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + help + This config is used for setting Trs parameter. Trs means CS Latency Between Resume And Next Suspend. + You can refer to the chapter of AC CHARACTERISTICS of flash datasheet. + For high-performance scenarios, some flash chips allow this set value to be smaller than the + given value in the datasheet without causing errors in the flash state machine. + When you have any related needs, please contact espressif business team. + config SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND bool "Enable XMC-C series flash chip suspend feature anyway" default n diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 65e6759a3f..d16506d391 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -129,6 +129,9 @@ esp_flash_t *esp_flash_default_chip = NULL; .cs_setup = 1,\ } #define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US +#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR +#define TRS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US +#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND #endif // Other target @@ -396,6 +399,16 @@ esp_err_t esp_flash_init_default_chip(void) return ESP_ERR_INVALID_ARG; } cfg.tsus_val = TSUS_VAL_SUSPEND; + + #if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + if (TRS_VAL_SUSPEND > 400 || TRS_VAL_SUSPEND < 20) { + // Assume that the TRS value cannot larger than 400 (because the performance might be really bad) + // And value cannot smaller than 20 (never see that small tsus value, might be wrong) + return ESP_ERR_INVALID_ARG; + } + cfg.trs_val = TRS_VAL_SUSPEND; + #endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + #endif // CONFIG_SPI_FLASH_AUTO_SUSPEND #if CONFIG_SPI_FLASH_AUTO_CHECK_SUSPEND_STATUS