From b1990352bbba1007b87fff222139fdff7f12b972 Mon Sep 17 00:00:00 2001
From: Li Shuai <lishuai@espressif.com>
Date: Fri, 24 Apr 2020 09:51:58 +0800
Subject: [PATCH] added psram stack check in backtrace

---
 components/esp32/include/esp_panic.h | 27 ++++++++++++++++++++++++++-
 components/spi_flash/cache_utils.c   |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/components/esp32/include/esp_panic.h b/components/esp32/include/esp_panic.h
index b9e192f046..8db2836ee3 100644
--- a/components/esp32/include/esp_panic.h
+++ b/components/esp32/include/esp_panic.h
@@ -20,6 +20,7 @@ extern "C"
 #ifndef __ASSEMBLER__
 
 #include "esp_err.h"
+#include "soc/soc.h"
 
 
 /**
@@ -61,12 +62,36 @@ esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
  */
 void esp_clear_watchpoint(int no);
 
+/**
+ * @brief Checks stack pointer in dram
+ */
+inline static bool esp_stack_ptr_in_dram(uint32_t sp)
+{
+    //Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
+    return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
+}
+
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+/**
+ * @brief Checks stack pointer in external ram
+ */
+inline static bool esp_stack_ptr_in_extram(uint32_t sp)
+{
+    //Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned.
+    return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0));
+}
+#endif
+
 /**
  * @brief Checks stack pointer
  */
 static inline bool esp_stack_ptr_is_sane(uint32_t sp)
 {
-	return !(sp < 0x3ffae010UL || sp > 0x3ffffff0UL || ((sp & 0xf) != 0));
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+    return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp));
+#else
+    return esp_stack_ptr_in_dram(sp);
+#endif
 }
 #endif
 
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index 56038de379..c3010f0f2a 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -92,6 +92,8 @@ void IRAM_ATTR spi_flash_op_block_func(void* arg)
 
 void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
 {
+    assert(esp_ptr_in_dram((const void *)get_sp()));
+
     spi_flash_op_lock();
 
     const uint32_t cpuid = xPortGetCoreID();