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change(cache): use bus id to get cache vaddr bus

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This commit is contained in:
armando
2025-07-15 14:16:50 +08:00
committed by Armando (Dou Yiwen)
parent 84ae601fef
commit b25bde3378
13 changed files with 67 additions and 107 deletions
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19
components/hal/esp32/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -100,7 +100,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -131,20 +130,18 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
* @param enable 1: enable; 0: disable * @param enable 1: enable; 0: disable
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
(void) mask; (void) mask;
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
uint32_t bus_mask = 0; uint32_t bus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
@@ -200,18 +197,16 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
* @param enable 1: enable; 0: disable * @param enable 1: enable; 0: disable
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
(void) mask; (void) mask;
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
uint32_t bus_mask = 0; uint32_t bus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0); bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);

11
components/hal/esp32c2/include/hal/cache_ll.h
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@@ -220,7 +220,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -238,15 +237,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -262,13 +260,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

7
components/hal/esp32c3/include/hal/cache_ll.h
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@@ -223,7 +223,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -247,9 +246,8 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -269,9 +267,8 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

13
components/hal/esp32c5/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -217,7 +217,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -234,15 +233,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -258,13 +256,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

13
components/hal/esp32c6/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -198,7 +198,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -215,15 +214,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -239,13 +237,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

13
components/hal/esp32c61/include/hal/cache_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -216,7 +216,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -233,15 +232,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -257,13 +255,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

13
components/hal/esp32h2/include/hal/cache_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -198,7 +198,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -215,15 +214,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -239,13 +237,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

11
components/hal/esp32h21/include/hal/cache_ll.h
View File

@@ -186,7 +186,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -203,15 +202,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -227,13 +225,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);

27
components/hal/esp32h4/include/hal/cache_ll.h
View File

@@ -213,8 +213,6 @@ static inline void cache_ll_l1_enable_dcache(uint32_t cache_id, bool data_autolo
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{ {
HAL_ASSERT(cache_level == 1 || cache_level == 2);
if (cache_level == 1) { if (cache_level == 1) {
switch (type) { switch (type) {
case CACHE_TYPE_INSTRUCTION: case CACHE_TYPE_INSTRUCTION:
@@ -276,8 +274,6 @@ static inline void cache_ll_l1_suspend_dcache(uint32_t cache_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{ {
HAL_ASSERT(cache_level == 1 || cache_level == 2);
if (cache_level == 1) { if (cache_level == 1) {
switch (type) { switch (type) {
case CACHE_TYPE_INSTRUCTION: case CACHE_TYPE_INSTRUCTION:
@@ -708,16 +704,15 @@ static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t
* External virtual address can only be accessed when the involved cache buses are enabled. * External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside. * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
* *
* @param bus_id bus ID * @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start * @param vaddr_start virtual address start
* @param len vaddr length * @param len vaddr length
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t bus_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(bus_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
@@ -734,20 +729,19 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t bus_id, uint32_t vad
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0);
} else { } else {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS1 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS1 : 0);
@@ -755,7 +749,7 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
REG_CLR_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); REG_CLR_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (cache_id == 1) { if (bus_id == 1) {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
} else { } else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0);
@@ -766,18 +760,17 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0);
} else { } else {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS1 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS1 : 0);
@@ -785,7 +778,7 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
REG_SET_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); REG_SET_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (cache_id == 1) { if (bus_id == 1) {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
} else { } else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0);

11
components/hal/esp32p4/include/hal/cache_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -1006,7 +1006,7 @@ static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t
* @param len vaddr length * @param len vaddr length
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t bus_id, uint32_t vaddr_start, uint32_t len)
{ {
return (cache_bus_mask_t)(CACHE_LL_DEFAULT_IBUS_MASK | CACHE_LL_DEFAULT_DBUS_MASK); return (cache_bus_mask_t)(CACHE_LL_DEFAULT_IBUS_MASK | CACHE_LL_DEFAULT_DBUS_MASK);
} }
@@ -1018,7 +1018,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
//not used, for compatibility //not used, for compatibility
} }
@@ -1030,7 +1030,7 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
//not used, for compatibility //not used, for compatibility
} }
@@ -1038,14 +1038,13 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
/** /**
* @brief Get the buses of a particular cache that are mapped to a virtual address range * @brief Get the buses of a particular cache that are mapped to a virtual address range
* *
* @param cache_id cache ID * @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start * @param vaddr_start virtual address start
* @param len vaddr length * @param len vaddr length
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline cache_bus_mask_t cache_ll_l2_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l2_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
(void)cache_id;
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;

16
components/hal/esp32s2/include/hal/cache_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -461,8 +461,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
(void)cache_id;
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) { if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
@@ -502,15 +500,15 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
/** /**
* Enable the Cache Buses * Enable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be enabled * @param mask To know which buses should be enabled
*/ */
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
(void)cache_id; (void)bus_id;
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
@@ -528,13 +526,13 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
/** /**
* Disable the Cache Buses * Disable the Cache Buses
* *
* @param cache_id cache ID (when l1 cache is per core) * @param bus_id bus ID
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
(void)cache_id; (void)bus_id;
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);

18
components/hal/esp32s3/include/hal/cache_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -558,8 +558,6 @@ __attribute__((always_inline))
#endif #endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0; cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1; uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) { if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
@@ -582,14 +580,13 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
#if !BOOTLOADER_BUILD #if !BOOTLOADER_BUILD
__attribute__((always_inline)) __attribute__((always_inline))
#endif #endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else { } else {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
@@ -597,7 +594,7 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (cache_id == 1) { if (bus_id == 1) {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
} else { } else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);
@@ -643,14 +640,13 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
* @param mask To know which buses should be disabled * @param mask To know which buses should be disabled
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
if (cache_id == 0) { if (bus_id == 0) {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
} else { } else {
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0); ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
@@ -658,7 +654,7 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (cache_id == 1) { if (bus_id == 1) {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
} else { } else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0); dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);

2
components/hal/include/hal/cache_types.h
View File

@@ -23,7 +23,7 @@ typedef enum {
* *
* @note * @note
* These enumurations are abstract concepts. Virtual address reside in one of these buses. * These enumurations are abstract concepts. Virtual address reside in one of these buses.
* Therefore, use `cache_ll_l1_get_bus(cache_id, vaddr_start, len)` to convert your vaddr into buses first * Therefore, use `cache_ll_l1_get_bus(bus_id, vaddr_start, len)` to convert your vaddr into buses first
*/ */
typedef enum { typedef enum {
CACHE_BUS_IBUS0 = BIT(0), CACHE_BUS_IBUS0 = BIT(0),