mirror of
https://github.com/espressif/esp-idf.git
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esp32s2: add CP_DMA driver
This commit is contained in:
morris
@@ -1,5 +1,6 @@
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set(srcs "adc_hal.c"
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"brownout_hal.c"
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"cp_dma_hal.c"
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"rtc_clk.c"
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"rtc_clk_init.c"
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"rtc_init.c"
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218
components/soc/src/esp32s2/cp_dma_hal.c
Normal file
218
components/soc/src/esp32s2/cp_dma_hal.c
Normal file
@@ -0,0 +1,218 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "hal/cp_dma_hal.h"
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#include "hal/cp_dma_ll.h"
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#include "soc/cp_dma_caps.h"
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#define MCP_DESCRIPTOR_BUFFER_OWNER_DMA (1)
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#define MCP_DESCRIPTOR_BUFFER_OWNER_CPU (0)
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void cp_dma_hal_init(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *tx_descriptors[], uint32_t tx_desc_num, cp_dma_descriptor_t *rx_descriptors[], uint32_t rx_desc_num)
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{
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hal->dev = &CP_DMA;
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cp_dma_ll_enable_clock(hal->dev, true);
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cp_dma_ll_reset_in_link(hal->dev);
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cp_dma_ll_reset_out_link(hal->dev);
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cp_dma_ll_reset_cmd_fifo(hal->dev);
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cp_dma_ll_reset_fifo(hal->dev);
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cp_dma_ll_enable_intr(hal->dev, UINT32_MAX, false);
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cp_dma_ll_clear_intr_status(hal->dev, UINT32_MAX);
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cp_dma_ll_enable_owner_check(hal->dev, true);
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// circle TX descriptors
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for (int i = 0; i < tx_desc_num; i++) {
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tx_descriptors[i]->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_CPU;
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tx_descriptors[i]->next = tx_descriptors[i + 1];
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}
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tx_descriptors[tx_desc_num - 1]->next = tx_descriptors[0];
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// circle RX descriptors
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for (int i = 0; i < rx_desc_num; i++) {
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rx_descriptors[i]->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_CPU;
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rx_descriptors[i]->next = rx_descriptors[i + 1];
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}
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rx_descriptors[rx_desc_num - 1]->next = rx_descriptors[0];
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// set the start of each descriptor chain
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hal->tx_desc = tx_descriptors[0];
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hal->rx_desc = rx_descriptors[0];
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/* set base address of the first descriptor */
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cp_dma_ll_tx_set_descriptor_base_addr(hal->dev, (uint32_t)hal->tx_desc);
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cp_dma_ll_rx_set_descriptor_base_addr(hal->dev, (uint32_t)hal->rx_desc);
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hal->next_rx_desc_to_check = rx_descriptors[0];
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}
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void cp_dma_hal_deinit(cp_dma_hal_context_t *hal)
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{
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cp_dma_ll_enable_clock(hal->dev, false);
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hal->dev = NULL;
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hal->tx_desc = NULL;
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hal->rx_desc = NULL;
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}
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void cp_dma_hal_start(cp_dma_hal_context_t *hal)
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{
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// enable DMA engine
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cp_dma_ll_start_rx(hal->dev, true);
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cp_dma_ll_start_tx(hal->dev, true);
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// enable RX EOF interrupt
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cp_dma_ll_enable_intr(hal->dev, CP_DMA_LL_EVENT_RX_EOF, true);
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}
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void cp_dma_hal_stop(cp_dma_hal_context_t *hal)
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{
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// disable interrupt
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cp_dma_ll_enable_intr(hal->dev, CP_DMA_LL_EVENT_RX_EOF, false);
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cp_dma_ll_enable_intr(hal->dev, CP_DMA_LL_EVENT_TX_EOF, false);
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// disable DMA
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cp_dma_ll_start_rx(hal->dev, false);
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cp_dma_ll_start_tx(hal->dev, false);
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}
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uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal)
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{
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return cp_dma_ll_get_intr_status(hal->dev);
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}
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void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask)
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{
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cp_dma_ll_clear_intr_status(hal->dev, mask);
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}
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int cp_dma_hal_prepare_transmit(cp_dma_hal_context_t *hal, void *buffer, size_t len, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc)
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{
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uint32_t prepared_length = 0;
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uint8_t *buf = (uint8_t *)buffer;
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cp_dma_descriptor_t *desc = hal->tx_desc; // descriptor iterator
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cp_dma_descriptor_t *start = desc;
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cp_dma_descriptor_t *end = desc;
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while (len > SOC_CP_DMA_MAX_BUFFER_SIZE) {
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if (desc->dw0.owner != MCP_DESCRIPTOR_BUFFER_OWNER_DMA) {
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desc->dw0.eof = 0; // not the end of the transaction
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desc->dw0.size = SOC_CP_DMA_MAX_BUFFER_SIZE;
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desc->dw0.length = SOC_CP_DMA_MAX_BUFFER_SIZE;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += SOC_CP_DMA_MAX_BUFFER_SIZE;
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len -= SOC_CP_DMA_MAX_BUFFER_SIZE;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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if (len) {
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if (desc->dw0.owner != MCP_DESCRIPTOR_BUFFER_OWNER_DMA) {
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end = desc; // the last descriptor used
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desc->dw0.eof = 1; // end of the transaction
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desc->dw0.size = len;
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desc->dw0.length = len;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += len;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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*start_desc = start;
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*end_desc = end;
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_exit:
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return prepared_length;
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}
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int cp_dma_hal_prepare_receive(cp_dma_hal_context_t *hal, void *buffer, size_t size, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc)
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{
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uint32_t prepared_length = 0;
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uint8_t *buf = (uint8_t *)buffer;
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cp_dma_descriptor_t *desc = hal->rx_desc; // descriptor iterator
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cp_dma_descriptor_t *start = desc;
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cp_dma_descriptor_t *end = desc;
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while (size > SOC_CP_DMA_MAX_BUFFER_SIZE) {
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if (desc->dw0.owner != MCP_DESCRIPTOR_BUFFER_OWNER_DMA) {
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desc->dw0.size = SOC_CP_DMA_MAX_BUFFER_SIZE;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += SOC_CP_DMA_MAX_BUFFER_SIZE;
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size -= SOC_CP_DMA_MAX_BUFFER_SIZE;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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if (size) {
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if (desc->dw0.owner != MCP_DESCRIPTOR_BUFFER_OWNER_DMA) {
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end = desc; // the last descriptor used
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desc->dw0.size = size;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += size;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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*start_desc = start;
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*end_desc = end;
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_exit:
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return prepared_length;
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}
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void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc)
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{
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// Give descriptor owner to DMA
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cp_dma_descriptor_t *desc = start_desc;
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while (desc != end_desc) {
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desc->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_DMA;
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desc = desc->next;
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}
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desc->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_DMA;
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hal->tx_desc = end_desc->next; // update the next available descriptor in HAL
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cp_dma_ll_restart_tx(hal->dev);
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}
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void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc)
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{
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// Give descriptor owner to DMA
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cp_dma_descriptor_t *desc = start_desc;
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while (desc != end_desc) {
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desc->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_DMA;
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desc = desc->next;
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}
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desc->dw0.owner = MCP_DESCRIPTOR_BUFFER_OWNER_DMA;
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hal->rx_desc = end_desc->next; // update the next available descriptor in HAL
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cp_dma_ll_restart_rx(hal->dev);
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}
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bool cp_dma_hal_get_next_rx_descriptor(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *eof_desc, cp_dma_descriptor_t **next_desc)
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{
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cp_dma_descriptor_t *next = hal->next_rx_desc_to_check;
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// additional check, to avoid potential interrupt got triggered by mistake
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if (next->dw0.owner == MCP_DESCRIPTOR_BUFFER_OWNER_CPU) {
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hal->next_rx_desc_to_check = hal->next_rx_desc_to_check->next;
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*next_desc = next;
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// return if we need to continue
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return eof_desc == next ? false : true;
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} else {
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*next_desc = NULL;
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return false;
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}
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}
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155
components/soc/src/esp32s2/include/hal/cp_dma_hal.h
Normal file
155
components/soc/src/esp32s2/include/hal/cp_dma_hal.h
Normal file
@@ -0,0 +1,155 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The HAL is not public api, don't use in application code.
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* See readme.md in soc/README.md
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******************************************************************************/
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// CP DMA HAL usages:
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// 1. Initialize HAL layer by cp_dma_hal_init, pass in the allocated descriptors for TX and RX
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// 2. Enable DMA and interrupt by cp_dma_hal_start
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// 3. Prepare descriptors used for TX and RX
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// 4. Restart the DMA engine in case it's not in working
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stddef.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/cp_dma_struct.h"
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typedef struct cp_dma_descriptor {
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struct {
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uint32_t size : 12; /*!< buffer size */
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uint32_t length : 12; /*!< specify number of valid bytes in the buffer */
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uint32_t reversed24_27 : 4; /*!< reserved */
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uint32_t err : 1; /*!< specify whether a received buffer contains error */
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uint32_t reserved29 : 1; /*!< reserved */
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uint32_t eof : 1; /*!< if this dma link is the last one, you shoule set this bit 1 */
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uint32_t owner : 1; /*!< specify the owner of buffer that this descriptor points to, 1=DMA, 0=CPU. DMA will clear it after use. */
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} dw0; /*!< descriptor word 0 */
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void *buffer; /*!< pointer to the buffer */
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struct cp_dma_descriptor *next; /*!< pointer to the next descriptor or NULL if this descriptor is the last one */
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} cp_dma_descriptor_t;
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_Static_assert(sizeof(cp_dma_descriptor_t) == 12, "cp_dma_descriptor_t should occupy 12 bytes in memory");
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/**
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* @brief HAL context
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*
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* @note `tx_desc` and `rx_desc` are internal state of the HAL, will be modified during the operations.
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* Upper layer of HAL should keep the buffer address themselves and make sure the buffers are freed when the HAL is no longer used.
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*
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*/
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typedef struct {
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cp_dma_dev_t *dev;
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cp_dma_descriptor_t *tx_desc;
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cp_dma_descriptor_t *rx_desc;
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cp_dma_descriptor_t *next_rx_desc_to_check;
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} cp_dma_hal_context_t;
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/**
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* @brief Initialize HAL layer context
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*
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* @param hal HAL layer context, memroy should be allocated at driver layer
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* @param tx_descriptors out link descriptor pool
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* @param tx_desc_num number of out link descriptors
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* @param rx_descriptors in line descriptor pool
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* @param rx_desc_num number of in link descriptors
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*/
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void cp_dma_hal_init(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *tx_descriptors[], uint32_t tx_desc_num, cp_dma_descriptor_t *rx_descriptors[], uint32_t rx_desc_num);
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/**
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* @brief Deinitialize HAL layer context
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*/
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void cp_dma_hal_deinit(cp_dma_hal_context_t *hal);
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/**
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* @brief Start mem2mem DMA state machine
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*/
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void cp_dma_hal_start(cp_dma_hal_context_t *hal);
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/**
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* @brief Stop mem2mem DMA state machine
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*/
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void cp_dma_hal_stop(cp_dma_hal_context_t *hal);
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/**
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* @brief Get interrupt status word
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*
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* @return uint32_t Interrupt status
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*/
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uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal) IRAM_ATTR;
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/**
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* @brief Clear interrupt mask
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*
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* @param mask interrupt mask
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*/
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void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask) IRAM_ATTR;
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/**
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* @brief Get next RX descriptor that needs recycling
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*
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* @param eof_desc EOF descriptor for this iteration
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* @param[out] next_desc Next descriptor needs to check
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* @return Whether to continue
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*/
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bool cp_dma_hal_get_next_rx_descriptor(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *eof_desc, cp_dma_descriptor_t **next_desc);
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/**
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* @brief Prepare buffer to be transmitted
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*
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* @param hal HAL layer context
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* @param buffer buffer address
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* @param len buffer size
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* @param[out] start_desc The first descriptor that carry the TX transaction
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* @param[out] end_desc The last descriptor that carry the TX transaction
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* @return Number of bytes has been parepared to transmit
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*/
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int cp_dma_hal_prepare_transmit(cp_dma_hal_context_t *hal, void *buffer, size_t len, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc);
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|
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/**
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* @brief Prepare buffer to receive
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*
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* @param hal HAL layer context
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* @param buffer buffer address
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* @param size buffer size
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* @param[out] start_desc The first descriptor that carries the RX transaction
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* @param[out] end_desc The last descriptor that carries the RX transaction
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* @return Number of bytes has been parepared to receive
|
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*/
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int cp_dma_hal_prepare_receive(cp_dma_hal_context_t *hal, void *buffer, size_t size, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc);
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|
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/**@{*/
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/**
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* @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW engine
|
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*
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* @param hal HAL layer context
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* @param start_desc The first descriptor that carries one transaction
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* @param end_desc The last descriptor that carries one transaction
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*/
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void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc);
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void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc);
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/**@}*/
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#ifdef __cplusplus
|
||||
}
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#endif
|
||||
159
components/soc/src/esp32s2/include/hal/cp_dma_ll.h
Normal file
159
components/soc/src/esp32s2/include/hal/cp_dma_ll.h
Normal file
@@ -0,0 +1,159 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/cp_dma_struct.h"
|
||||
|
||||
#define CP_DMA_LL_EVENT_RX_DONE (1 << 0)
|
||||
#define CP_DMA_LL_EVENT_RX_EOF (1 << 1)
|
||||
#define CP_DMA_LL_EVENT_TX_DONE (1 << 2)
|
||||
#define CP_DMA_LL_EVENT_TX_EOF (1 << 3)
|
||||
#define CP_DMA_LL_EVENT_RX_DESC_ERR (1 << 4)
|
||||
#define CP_DMA_LL_EVENT_TX_DESC_ERR (1 << 5)
|
||||
#define CP_DMA_LL_EVENT_RX_DESC_EMPTY (1 << 6)
|
||||
#define CP_DMA_LL_EVENT_TX_TOTAL_EOF (1 << 7)
|
||||
#define CP_DMA_LL_EVENT_ALL (0xFF)
|
||||
|
||||
/**
|
||||
* Copy DMA firstly reads data to be transferred from internal RAM,
|
||||
* stores the data into DMA FIFO via an outlink,
|
||||
* and then writes the data to the destination internal RAM via an inlink.
|
||||
*/
|
||||
|
||||
static inline void cp_dma_ll_reset_in_link(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_conf.dma_in_rst = 1;
|
||||
dev->dma_conf.dma_in_rst = 0;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_reset_out_link(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_conf.dma_out_rst = 1;
|
||||
dev->dma_conf.dma_out_rst = 0;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_reset_fifo(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_conf.dma_fifo_rst = 1;
|
||||
dev->dma_conf.dma_fifo_rst = 0;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_reset_cmd_fifo(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_conf.dma_cmdfifo_rst = 1;
|
||||
dev->dma_conf.dma_cmdfifo_rst = 0;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_enable_owner_check(cp_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->dma_conf.dma_check_owner = enable;
|
||||
dev->dma_conf.dma_out_auto_wrback = 1;
|
||||
dev->dma_conf.dma_out_owner = 0;
|
||||
dev->dma_conf.dma_in_owner = 0;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_enable_clock(cp_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->dma_conf.dma_clk_en = enable;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_enable_intr(cp_dma_dev_t *dev, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->dma_int_ena.val |= mask;
|
||||
} else {
|
||||
dev->dma_int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) uint32_t cp_dma_ll_get_intr_status(cp_dma_dev_t *dev)
|
||||
{
|
||||
return dev->dma_int_st.val;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void cp_dma_ll_clear_intr_status(cp_dma_dev_t *dev, uint32_t mask)
|
||||
{
|
||||
dev->dma_int_clr.val = mask;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_tx_set_descriptor_base_addr(cp_dma_dev_t *dev, uint32_t address)
|
||||
{
|
||||
dev->dma_out_link.dma_outlink_addr = address;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_rx_set_descriptor_base_addr(cp_dma_dev_t *dev, uint32_t address)
|
||||
{
|
||||
dev->dma_in_link.dma_inlink_addr = address;
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_start_tx(cp_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->dma_out_link.dma_outlink_start = 1; // cleared automatically by HW
|
||||
} else {
|
||||
dev->dma_out_link.dma_outlink_stop = 1; // cleared automatically by HW
|
||||
}
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_start_rx(cp_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->dma_in_link.dma_inlink_start = 1; // cleared automatically by HW
|
||||
} else {
|
||||
dev->dma_in_link.dma_inlink_stop = 1; // cleared automatically by HW
|
||||
}
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_restart_tx(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_out_link.dma_outlink_restart = 1; // cleared automatically by HW
|
||||
}
|
||||
|
||||
static inline void cp_dma_ll_restart_rx(cp_dma_dev_t *dev)
|
||||
{
|
||||
dev->dma_in_link.dma_inlink_restart = 1; // cleared automatically by HW
|
||||
}
|
||||
|
||||
// get the address of last rx descriptor
|
||||
static inline uint32_t cp_dma_ll_get_rx_eof_descriptor_address(cp_dma_dev_t *dev)
|
||||
{
|
||||
return dev->dma_in_eof_des_addr.dma_in_suc_eof_des_addr;
|
||||
}
|
||||
|
||||
// get the address of last tx descriptor
|
||||
static inline uint32_t cp_dma_ll_get_tx_eof_descriptor_address(cp_dma_dev_t *dev)
|
||||
{
|
||||
return dev->dma_out_eof_des_addr.dma_out_eof_des_addr;
|
||||
}
|
||||
|
||||
static inline uint32_t cp_dma_ll_get_tx_status(cp_dma_dev_t *dev)
|
||||
{
|
||||
return dev->dma_out_st.val;
|
||||
}
|
||||
|
||||
static inline uint32_t cp_dma_ll_get_rx_status(cp_dma_dev_t *dev)
|
||||
{
|
||||
return dev->dma_in_st.val;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user