From b3d8db3ae2285ea74b0ed63b2b4b55add76b2e59 Mon Sep 17 00:00:00 2001 From: songruojing Date: Mon, 4 Jul 2022 14:17:54 +0800 Subject: [PATCH] bootloader, esp_system: esp32c2 console uart to support 26MHz xtal Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h --- components/bootloader_support/src/bootloader_console.c | 2 +- components/esp_system/port/cpu_start.c | 5 +++-- components/soc/esp32c2/include/soc/soc.h | 1 - components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32s2/include/soc/soc.h | 1 - components/soc/esp32s3/include/soc/soc.h | 1 - 7 files changed, 4 insertions(+), 8 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 83cc7893a0..85e4aa8027 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -90,7 +90,7 @@ void bootloader_console_init(void) // Set configured UART console baud rate uint32_t clock_hz = rtc_clk_apb_freq_get(); #if ESP_ROM_UART_CLK_IS_XTAL - clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM + clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM #endif esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); } diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 1e660d5427..d0de1f862a 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -21,6 +21,7 @@ #include "esp_rom_efuse.h" #include "esp_rom_uart.h" #include "esp_rom_sys.h" +#include "esp_rom_caps.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 @@ -516,8 +517,8 @@ void IRAM_ATTR call_start_cpu0(void) #ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed #ifdef CONFIG_ESP_CONSOLE_UART uint32_t clock_hz = esp_clk_apb_freq(); -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 - clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM +#if ESP_ROM_UART_CLK_IS_XTAL + clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM #endif esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index b4ff43d342..83afaa5fab 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -142,7 +142,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 40*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 40*1000000 ) diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 547b7fe815..a4131b79b8 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -135,7 +135,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 40*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #if CONFIG_IDF_ENV_FPGA diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 98c5f62c92..d83bca8e50 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -135,7 +135,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 32*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 32*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #if CONFIG_IDF_ENV_FPGA diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 55112b84e9..fe25297917 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -142,7 +142,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define REF_CLK_FREQ ( 1000000 ) diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 0405dc4405..ab0db41ae3 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -152,7 +152,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM (40*1000000) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM (40*1000000) #define EFUSE_CLK_FREQ_ROM (20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ (80*1000000)